[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / iceland_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "drmP.h"
#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_2_4_d.h"
#include "oss/oss_2_4_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * iceland_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void iceland_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_cntl = RREG32(mmIH_CNTL);
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	WREG32(mmIH_CNTL, ih_cntl);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * iceland_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	u32 ih_cntl = RREG32(mmIH_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	WREG32(mmIH_CNTL, ih_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * iceland_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int iceland_ih_irq_init(struct amdgpu_device *adev)
{
	int ret = 0;
	int rb_bufsz;
	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
	u64 wptr_off;

	/* disable irqs */
	iceland_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

	/* set the writeback address whether it's enabled or not */
	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	/* Default settings for IH_CNTL (disabled at first) */
	ih_cntl = RREG32(mmIH_CNTL);
	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

	if (adev->irq.msi_enabled)
		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
	WREG32(mmIH_CNTL, ih_cntl);

	pci_set_master(adev->pdev);

	/* enable interrupts */
	iceland_ih_enable_interrupts(adev);

	return ret;
}

/**
 * iceland_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void iceland_ih_irq_disable(struct amdgpu_device *adev)
{
	iceland_ih_disable_interrupts(adev);

	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * iceland_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
{
	u32 wptr, tmp;

	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);

	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
		/* When a ring buffer overflow happen start parsing interrupt
		 * from the last not overwritten vector (wptr + 16). Hopefully
		 * this should allow us to catchup.
		 */
		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
		tmp = RREG32(mmIH_RB_CNTL);
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
		WREG32(mmIH_RB_CNTL, tmp);
	}
	return (wptr & adev->irq.ih.ptr_mask);
}

/**
 * iceland_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void iceland_ih_decode_iv(struct amdgpu_device *adev,
				 struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = adev->irq.ih.rptr >> 2;
	uint32_t dw[4];

	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);

	entry->src_id = dw[0] & 0xff;
	entry->src_data = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vm_id = (dw[2] >> 8) & 0xff;
	entry->pas_id = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	adev->irq.ih.rptr += 16;
}

/**
 * iceland_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 *
 * Set the IH ring buffer rptr.
 */
static void iceland_ih_set_rptr(struct amdgpu_device *adev)
{
	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}

static int iceland_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	ret = amdgpu_irq_add_domain(adev);
	if (ret)
		return ret;

	iceland_ih_set_interrupt_funcs(adev);

	return 0;
}

static int iceland_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
	if (r)
		return r;

	r = amdgpu_irq_init(adev);

	return r;
}

static int iceland_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini(adev);
	amdgpu_ih_ring_fini(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}

static int iceland_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = iceland_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int iceland_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	iceland_ih_irq_disable(adev);

	return 0;
}

static int iceland_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return iceland_ih_hw_fini(adev);
}

static int iceland_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return iceland_ih_hw_init(adev);
}

static bool iceland_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
		return false;

	return true;
}

static int iceland_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS);
		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static void iceland_ih_print_status(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	dev_info(adev->dev, "ICELAND IH registers\n");
	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
		RREG32(mmSRBM_STATUS));
	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
		RREG32(mmSRBM_STATUS2));
	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
		 RREG32(mmINTERRUPT_CNTL));
	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
		 RREG32(mmINTERRUPT_CNTL2));
	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
		 RREG32(mmIH_CNTL));
	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
		 RREG32(mmIH_RB_CNTL));
	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
		 RREG32(mmIH_RB_BASE));
	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
		 RREG32(mmIH_RB_WPTR_ADDR_LO));
	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
		 RREG32(mmIH_RB_WPTR_ADDR_HI));
	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
		 RREG32(mmIH_RB_RPTR));
	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
		 RREG32(mmIH_RB_WPTR));
}

static int iceland_ih_soft_reset(void *handle)
{
	u32 srbm_soft_reset = 0;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
						SOFT_RESET_IH, 1);

	if (srbm_soft_reset) {
		iceland_ih_print_status((void *)adev);

		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);

		iceland_ih_print_status((void *)adev);
	}

	return 0;
}

static int iceland_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int iceland_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

const struct amd_ip_funcs iceland_ih_ip_funcs = {
	.early_init = iceland_ih_early_init,
	.late_init = NULL,
	.sw_init = iceland_ih_sw_init,
	.sw_fini = iceland_ih_sw_fini,
	.hw_init = iceland_ih_hw_init,
	.hw_fini = iceland_ih_hw_fini,
	.suspend = iceland_ih_suspend,
	.resume = iceland_ih_resume,
	.is_idle = iceland_ih_is_idle,
	.wait_for_idle = iceland_ih_wait_for_idle,
	.soft_reset = iceland_ih_soft_reset,
	.print_status = iceland_ih_print_status,
	.set_clockgating_state = iceland_ih_set_clockgating_state,
	.set_powergating_state = iceland_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs iceland_ih_funcs = {
	.get_wptr = iceland_ih_get_wptr,
	.decode_iv = iceland_ih_decode_iv,
	.set_rptr = iceland_ih_set_rptr
};

static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	if (adev->irq.ih_funcs == NULL)
		adev->irq.ih_funcs = &iceland_ih_funcs;
}
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "drmP.h"
	24	#include "amdgpu.h"
	25	#include "amdgpu_ih.h"
	26	#include "vid.h"
	27
	28	#include "oss/oss_2_4_d.h"
	29	#include "oss/oss_2_4_sh_mask.h"
	30
	31	#include "bif/bif_5_1_d.h"
	32	#include "bif/bif_5_1_sh_mask.h"
	33
	34	/*
	35	* Interrupts
	36	* Starting with r6xx, interrupts are handled via a ring buffer.
	37	* Ring buffers are areas of GPU accessible memory that the GPU
	38	* writes interrupt vectors into and the host reads vectors out of.
	39	* There is a rptr (read pointer) that determines where the
	40	* host is currently reading, and a wptr (write pointer)
	41	* which determines where the GPU has written. When the
	42	* pointers are equal, the ring is idle. When the GPU
	43	* writes vectors to the ring buffer, it increments the
	44	* wptr. When there is an interrupt, the host then starts
	45	* fetching commands and processing them until the pointers are
	46	* equal again at which point it updates the rptr.
	47	*/
	48
	49	static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	50
	51	/**
	52	* iceland_ih_enable_interrupts - Enable the interrupt ring buffer
	53	*
	54	* @adev: amdgpu_device pointer
	55	*
	56	* Enable the interrupt ring buffer (VI).
	57	*/
	58	static void iceland_ih_enable_interrupts(struct amdgpu_device *adev)
	59	{
	60	u32 ih_cntl = RREG32(mmIH_CNTL);
	61	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	62
	63	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
	64	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
65	WREG32(mmIH_CNTL, ih_cntl);
66	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67	adev->irq.ih.enabled = true;
68	}
69
70	/**
71	* iceland_ih_disable_interrupts - Disable the interrupt ring buffer
72	*
73	* @adev: amdgpu_device pointer
74	*
75	* Disable the interrupt ring buffer (VI).
76	*/
77	static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
78	{
79	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80	u32 ih_cntl = RREG32(mmIH_CNTL);
81
82	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
83	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
84	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
85	WREG32(mmIH_CNTL, ih_cntl);
86	/* set rptr, wptr to 0 */
87	WREG32(mmIH_RB_RPTR, 0);
88	WREG32(mmIH_RB_WPTR, 0);
89	adev->irq.ih.enabled = false;
90	adev->irq.ih.rptr = 0;
91	}
92
93	/**
94	* iceland_ih_irq_init - init and enable the interrupt ring
95	*
96	* @adev: amdgpu_device pointer
97	*
98	* Allocate a ring buffer for the interrupt controller,
99	* enable the RLC, disable interrupts, enable the IH
100	* ring buffer and enable it (VI).
101	* Called at device load and reume.
102	* Returns 0 for success, errors for failure.
103	*/
104	static int iceland_ih_irq_init(struct amdgpu_device *adev)
105	{
106	int ret = 0;
107	int rb_bufsz;
108	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
109	u64 wptr_off;
110
111	/* disable irqs */
112	iceland_ih_disable_interrupts(adev);
113
114	/* setup interrupt control */
115	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
116	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
117	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
118	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
119	*/
120	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
121	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
122	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
123	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
124
125	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
126	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
127
128	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
129	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
130	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
131	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
132
133	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
134	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
135
136	/* set the writeback address whether it's enabled or not */
137	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
138	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
139	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
140
141	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
142
143	/* set rptr, wptr to 0 */
144	WREG32(mmIH_RB_RPTR, 0);
145	WREG32(mmIH_RB_WPTR, 0);
146
147	/* Default settings for IH_CNTL (disabled at first) */
148	ih_cntl = RREG32(mmIH_CNTL);
149	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
150
151	if (adev->irq.msi_enabled)
152	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
153	WREG32(mmIH_CNTL, ih_cntl);
154
155	pci_set_master(adev->pdev);
156
157	/* enable interrupts */
158	iceland_ih_enable_interrupts(adev);
159
160	return ret;
161	}
162
163	/**
164	* iceland_ih_irq_disable - disable interrupts
165	*
166	* @adev: amdgpu_device pointer
167	*
168	* Disable interrupts on the hw (VI).
169	*/
170	static void iceland_ih_irq_disable(struct amdgpu_device *adev)
171	{
172	iceland_ih_disable_interrupts(adev);
173
174	/* Wait and acknowledge irq */
175	mdelay(1);
176	}
177
178	/**
179	* iceland_ih_get_wptr - get the IH ring buffer wptr
180	*
181	* @adev: amdgpu_device pointer
182	*
183	* Get the IH ring buffer wptr from either the register
184	* or the writeback memory buffer (VI). Also check for
185	* ring buffer overflow and deal with it.
186	* Used by cz_irq_process(VI).
187	* Returns the value of the wptr.
188	*/
189	static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
190	{
191	u32 wptr, tmp;
192
193	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
194
195	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
196	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
197	/* When a ring buffer overflow happen start parsing interrupt
198	* from the last not overwritten vector (wptr + 16). Hopefully
199	* this should allow us to catchup.
200	*/
201	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
202	wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
203	adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
204	tmp = RREG32(mmIH_RB_CNTL);
205	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
206	WREG32(mmIH_RB_CNTL, tmp);
207	}
208	return (wptr & adev->irq.ih.ptr_mask);
209	}
210
211	/**
212	* iceland_ih_decode_iv - decode an interrupt vector
213	*
214	* @adev: amdgpu_device pointer
215	*
216	* Decodes the interrupt vector at the current rptr
217	* position and also advance the position.
218	*/
219	static void iceland_ih_decode_iv(struct amdgpu_device *adev,
220	struct amdgpu_iv_entry *entry)
221	{
222	/* wptr/rptr are in bytes! */
223	u32 ring_index = adev->irq.ih.rptr >> 2;
224	uint32_t dw[4];
225
226	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
227	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
228	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
229	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
230
231	entry->src_id = dw[0] & 0xff;
232	entry->src_data = dw[1] & 0xfffffff;
233	entry->ring_id = dw[2] & 0xff;
234	entry->vm_id = (dw[2] >> 8) & 0xff;
235	entry->pas_id = (dw[2] >> 16) & 0xffff;
236
237	/* wptr/rptr are in bytes! */
238	adev->irq.ih.rptr += 16;
239	}
240
241	/**
242	* iceland_ih_set_rptr - set the IH ring buffer rptr
243	*
244	* @adev: amdgpu_device pointer
245	*
246	* Set the IH ring buffer rptr.
247	*/
248	static void iceland_ih_set_rptr(struct amdgpu_device *adev)
249	{
250	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
251	}
252
5fc3aeeb	253	static int iceland_ih_early_init(void *handle)
aaa36a97	254	{
5fc3aeeb	255	struct amdgpu_device adev = (struct amdgpu_device )handle;
5f232365 AD	256	int ret;
	257
	258	ret = amdgpu_irq_add_domain(adev);
	259	if (ret)
	260	return ret;
5fc3aeeb	261
aaa36a97	262	iceland_ih_set_interrupt_funcs(adev);
5f232365	263
aaa36a97 AD	264	return 0;
	265	}
	266
5fc3aeeb	267	static int iceland_ih_sw_init(void *handle)
aaa36a97 AD	268	{
aaa36a97 AD	269	int r;
5fc3aeeb	270	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	271
	272	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
	273	if (r)
	274	return r;
	275
	276	r = amdgpu_irq_init(adev);
	277
	278	return r;
	279	}
	280
5fc3aeeb	281	static int iceland_ih_sw_fini(void *handle)
aaa36a97	282	{
5fc3aeeb	283	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	284
aaa36a97 AD	285	amdgpu_irq_fini(adev);
aaa36a97 AD	286	amdgpu_ih_ring_fini(adev);
5f232365	287	amdgpu_irq_remove_domain(adev);
aaa36a97 AD	288
	289	return 0;
	290	}
	291
5fc3aeeb	292	static int iceland_ih_hw_init(void *handle)
aaa36a97 AD	293	{
aaa36a97 AD	294	int r;
5fc3aeeb	295	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	296
	297	r = iceland_ih_irq_init(adev);
	298	if (r)
	299	return r;
	300
	301	return 0;
	302	}
	303
5fc3aeeb	304	static int iceland_ih_hw_fini(void *handle)
aaa36a97	305	{
5fc3aeeb	306	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	307
aaa36a97 AD	308	iceland_ih_irq_disable(adev);
	309
	310	return 0;
	311	}
	312
5fc3aeeb	313	static int iceland_ih_suspend(void *handle)
aaa36a97	314	{
5fc3aeeb	315	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	316
aaa36a97 AD	317	return iceland_ih_hw_fini(adev);
	318	}
	319
5fc3aeeb	320	static int iceland_ih_resume(void *handle)
aaa36a97	321	{
5fc3aeeb	322	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	323
aaa36a97 AD	324	return iceland_ih_hw_init(adev);
	325	}
	326
5fc3aeeb	327	static bool iceland_ih_is_idle(void *handle)
aaa36a97	328	{
5fc3aeeb	329	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	330	u32 tmp = RREG32(mmSRBM_STATUS);
	331
	332	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	333	return false;
	334
	335	return true;
	336	}
	337
5fc3aeeb	338	static int iceland_ih_wait_for_idle(void *handle)
aaa36a97 AD	339	{
	340	unsigned i;
	341	u32 tmp;
5fc3aeeb	342	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	343
	344	for (i = 0; i < adev->usec_timeout; i++) {
	345	/* read MC_STATUS */
	346	tmp = RREG32(mmSRBM_STATUS);
	347	if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	348	return 0;
	349	udelay(1);
	350	}
	351	return -ETIMEDOUT;
	352	}
	353
5fc3aeeb	354	static void iceland_ih_print_status(void *handle)
aaa36a97	355	{
5fc3aeeb	356	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	357
aaa36a97 AD	358	dev_info(adev->dev, "ICELAND IH registers\n");
	359	dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
	360	RREG32(mmSRBM_STATUS));
	361	dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
	362	RREG32(mmSRBM_STATUS2));
	363	dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
	364	RREG32(mmINTERRUPT_CNTL));
	365	dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
	366	RREG32(mmINTERRUPT_CNTL2));
	367	dev_info(adev->dev, " IH_CNTL=0x%08X\n",
	368	RREG32(mmIH_CNTL));
	369	dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
	370	RREG32(mmIH_RB_CNTL));
	371	dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
	372	RREG32(mmIH_RB_BASE));
	373	dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
	374	RREG32(mmIH_RB_WPTR_ADDR_LO));
	375	dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
	376	RREG32(mmIH_RB_WPTR_ADDR_HI));
	377	dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
	378	RREG32(mmIH_RB_RPTR));
	379	dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
	380	RREG32(mmIH_RB_WPTR));
	381	}
	382
5fc3aeeb	383	static int iceland_ih_soft_reset(void *handle)
aaa36a97 AD	384	{
aaa36a97 AD	385	u32 srbm_soft_reset = 0;
5fc3aeeb	386	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	387	u32 tmp = RREG32(mmSRBM_STATUS);
	388
	389	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	390	srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
	391	SOFT_RESET_IH, 1);
	392
	393	if (srbm_soft_reset) {
5fc3aeeb	394	iceland_ih_print_status((void *)adev);
aaa36a97 AD	395
	396	tmp = RREG32(mmSRBM_SOFT_RESET);
	397	tmp \|= srbm_soft_reset;
	398	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	399	WREG32(mmSRBM_SOFT_RESET, tmp);
	400	tmp = RREG32(mmSRBM_SOFT_RESET);
	401
	402	udelay(50);
	403
	404	tmp &= ~srbm_soft_reset;
	405	WREG32(mmSRBM_SOFT_RESET, tmp);
	406	tmp = RREG32(mmSRBM_SOFT_RESET);
	407
	408	/* Wait a little for things to settle down */
	409	udelay(50);
	410
5fc3aeeb	411	iceland_ih_print_status((void *)adev);
aaa36a97 AD	412	}
	413
	414	return 0;
	415	}
	416
5fc3aeeb	417	static int iceland_ih_set_clockgating_state(void *handle,
5fc3aeeb	418	enum amd_clockgating_state state)
aaa36a97	419	{
aaa36a97 AD	420	return 0;
	421	}
	422
5fc3aeeb	423	static int iceland_ih_set_powergating_state(void *handle,
5fc3aeeb	424	enum amd_powergating_state state)
aaa36a97	425	{
aaa36a97 AD	426	return 0;
	427	}
	428
5fc3aeeb	429	const struct amd_ip_funcs iceland_ih_ip_funcs = {
aaa36a97 AD	430	.early_init = iceland_ih_early_init,
	431	.late_init = NULL,
	432	.sw_init = iceland_ih_sw_init,
	433	.sw_fini = iceland_ih_sw_fini,
	434	.hw_init = iceland_ih_hw_init,
	435	.hw_fini = iceland_ih_hw_fini,
	436	.suspend = iceland_ih_suspend,
	437	.resume = iceland_ih_resume,
	438	.is_idle = iceland_ih_is_idle,
	439	.wait_for_idle = iceland_ih_wait_for_idle,
	440	.soft_reset = iceland_ih_soft_reset,
	441	.print_status = iceland_ih_print_status,
	442	.set_clockgating_state = iceland_ih_set_clockgating_state,
	443	.set_powergating_state = iceland_ih_set_powergating_state,
	444	};
	445
	446	static const struct amdgpu_ih_funcs iceland_ih_funcs = {
	447	.get_wptr = iceland_ih_get_wptr,
	448	.decode_iv = iceland_ih_decode_iv,
	449	.set_rptr = iceland_ih_set_rptr
	450	};
	451
	452	static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	453	{
	454	if (adev->irq.ih_funcs == NULL)
	455	adev->irq.ih_funcs = &iceland_ih_funcs;
	456	}
	457