[linux-block.git] / drivers / gpu / drm / amd / amdgpu / hdp_v6_0.c

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "hdp_v6_0.h"

#include "hdp/hdp_6_0_0_offset.h"
#include "hdp/hdp_6_0_0_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>

#define regHDP_CLK_CNTL_V6_1	0xd5
#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0

static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
				struct amdgpu_ring *ring)
{
	if (!ring || !ring->funcs->emit_wreg)
		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
	else
		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
}

static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
					 bool enable)
{
	uint32_t hdp_clk_cntl;
	uint32_t hdp_mem_pwr_cntl;

	if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
				AMD_CG_SUPPORT_HDP_DS |
				AMD_CG_SUPPORT_HDP_SD)))
		return;

	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
		hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);
	else
		hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

	/* Before doing clock/power mode switch,
	 * forced on IPH & RC clock */
	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
				     RC_MEM_CLK_SOFT_OVERRIDE, 1);
	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
		WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
	else
		WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);

	/* disable clock and power gating before any changing */
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 ATOMIC_MEM_POWER_CTRL_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 ATOMIC_MEM_POWER_LS_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 ATOMIC_MEM_POWER_DS_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 ATOMIC_MEM_POWER_SD_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 RC_MEM_POWER_CTRL_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 RC_MEM_POWER_LS_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 RC_MEM_POWER_DS_EN, 0);
	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
					 RC_MEM_POWER_SD_EN, 0);
	WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);

	/* Already disabled above. The actions below are for "enabled" only */
	if (enable) {
		/* only one clock gating mode (LS/DS/SD) can be enabled */
		if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
							 HDP_MEM_POWER_CTRL,
							 ATOMIC_MEM_POWER_SD_EN, 1);
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
							 HDP_MEM_POWER_CTRL,
							 RC_MEM_POWER_SD_EN, 1);
		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
							 HDP_MEM_POWER_CTRL,
							 ATOMIC_MEM_POWER_LS_EN, 1);
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
							 HDP_MEM_POWER_CTRL,
							 RC_MEM_POWER_LS_EN, 1);
		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
							 HDP_MEM_POWER_CTRL,
							 ATOMIC_MEM_POWER_DS_EN, 1);
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
							 HDP_MEM_POWER_CTRL,
							 RC_MEM_POWER_DS_EN, 1);
		}

		/* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
		 * be set for SRAM LS/DS/SD */
		if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
				      AMD_CG_SUPPORT_HDP_SD)) {
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
							 ATOMIC_MEM_POWER_CTRL_EN, 1);
			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
							 RC_MEM_POWER_CTRL_EN, 1);
			WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
		}
	}

	/* disable IPH & RC clock override after clock/power mode changing */
	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
				     RC_MEM_CLK_SOFT_OVERRIDE, 0);
	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
		WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
	else
		WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
}

static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
					    u64 *flags)
{
	uint32_t tmp;

	/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
	tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
	if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
		*flags |= AMD_CG_SUPPORT_HDP_LS;
	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
		*flags |= AMD_CG_SUPPORT_HDP_DS;
	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
		*flags |= AMD_CG_SUPPORT_HDP_SD;
}

const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
	.flush_hdp = hdp_v6_0_flush_hdp,
	.update_clock_gating = hdp_v6_0_update_clock_gating,
	.get_clock_gating_state = hdp_v6_0_get_clockgating_state,
};
Commit	Line	Data
563fcfbf LG	1	/*
	2	* Copyright 2020 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "amdgpu_atombios.h"
	25	#include "hdp_v6_0.h"
	26
	27	#include "hdp/hdp_6_0_0_offset.h"
	28	#include "hdp/hdp_6_0_0_sh_mask.h"
	29	#include <uapi/linux/kfd_ioctl.h>
	30
f56c1941 LY	31	#define regHDP_CLK_CNTL_V6_1 0xd5
	32	#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
	33
563fcfbf LG	34	static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
	35	struct amdgpu_ring *ring)
	36	{
	37	if (!ring \|\| !ring->funcs->emit_wreg)
	38	WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
	39	else
	40	amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
	41	}
	42
	43	static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
d386f645	44	bool enable)
563fcfbf	45	{
f56c1941	46	uint32_t hdp_clk_cntl;
d386f645	47	uint32_t hdp_mem_pwr_cntl;
563fcfbf	48
d386f645 EQ	49	if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS \|
	50	AMD_CG_SUPPORT_HDP_DS \|
	51	AMD_CG_SUPPORT_HDP_SD)))
563fcfbf LG	52	return;
563fcfbf LG	53
4e8303cf	54	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
f56c1941 LY	55	hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);
	56	else
	57	hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
d386f645	58	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
563fcfbf	59
d386f645 EQ	60	/* Before doing clock/power mode switch,
	61	* forced on IPH & RC clock */
	62	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
	63	RC_MEM_CLK_SOFT_OVERRIDE, 1);
4e8303cf	64	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
f56c1941 LY	65	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
	66	else
	67	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
d386f645 EQ	68
	69	/* disable clock and power gating before any changing */
	70	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	71	ATOMIC_MEM_POWER_CTRL_EN, 0);
	72	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	73	ATOMIC_MEM_POWER_LS_EN, 0);
	74	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	75	ATOMIC_MEM_POWER_DS_EN, 0);
	76	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	77	ATOMIC_MEM_POWER_SD_EN, 0);
	78	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	79	RC_MEM_POWER_CTRL_EN, 0);
	80	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	81	RC_MEM_POWER_LS_EN, 0);
	82	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	83	RC_MEM_POWER_DS_EN, 0);
	84	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	85	RC_MEM_POWER_SD_EN, 0);
	86	WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
	87
	88	/* Already disabled above. The actions below are for "enabled" only */
563fcfbf	89	if (enable) {
d386f645 EQ	90	/* only one clock gating mode (LS/DS/SD) can be enabled */
	91	if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
	92	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
	93	HDP_MEM_POWER_CTRL,
	94	ATOMIC_MEM_POWER_SD_EN, 1);
	95	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
	96	HDP_MEM_POWER_CTRL,
	97	RC_MEM_POWER_SD_EN, 1);
	98	} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
	99	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
	100	HDP_MEM_POWER_CTRL,
	101	ATOMIC_MEM_POWER_LS_EN, 1);
	102	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
	103	HDP_MEM_POWER_CTRL,
	104	RC_MEM_POWER_LS_EN, 1);
	105	} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
	106	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
	107	HDP_MEM_POWER_CTRL,
	108	ATOMIC_MEM_POWER_DS_EN, 1);
	109	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
	110	HDP_MEM_POWER_CTRL,
	111	RC_MEM_POWER_DS_EN, 1);
	112	}
	113
	114	/* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
	115	* be set for SRAM LS/DS/SD */
	116	if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS \| AMD_CG_SUPPORT_HDP_DS \|
	117	AMD_CG_SUPPORT_HDP_SD)) {
	118	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	119	ATOMIC_MEM_POWER_CTRL_EN, 1);
	120	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
	121	RC_MEM_POWER_CTRL_EN, 1);
	122	WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
	123	}
563fcfbf LG	124	}
563fcfbf LG	125
d386f645 EQ	126	/* disable IPH & RC clock override after clock/power mode changing */
	127	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
	128	RC_MEM_CLK_SOFT_OVERRIDE, 0);
4e8303cf	129	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
f56c1941 LY	130	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
	131	else
	132	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
563fcfbf LG	133	}
	134
	135	static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
	136	u64 *flags)
	137	{
	138	uint32_t tmp;
	139
563fcfbf LG	140	/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
	141	tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
	142	if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
	143	*flags \|= AMD_CG_SUPPORT_HDP_LS;
	144	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
	145	*flags \|= AMD_CG_SUPPORT_HDP_DS;
	146	else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
	147	*flags \|= AMD_CG_SUPPORT_HDP_SD;
	148	}
	149
	150	const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
	151	.flush_hdp = hdp_v6_0_flush_hdp,
	152	.update_clock_gating = hdp_v6_0_update_clock_gating,
	153	.get_clock_gating_state = hdp_v6_0_get_clockgating_state,
	154	};