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Merge remote-tracking branch 'asoc/topic/pcm5102a' into asoc-next
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gmc_v9_0.c
CommitLineData
e60f8db5
AX		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "gmc_v9_0.h"
8d6a5230 26#include "amdgpu_atomfirmware.h"
e60f8db5 27
75199b8c
FX		 28#include "hdp/hdp_4_0_offset.h"
29#include "hdp/hdp_4_0_sh_mask.h"
cde5c34f 30#include "gc/gc_9_0_sh_mask.h"
135d4b10
FX		 31#include "dce/dce_12_0_offset.h"
32#include "dce/dce_12_0_sh_mask.h"
fb960bd2 33#include "vega10_enum.h"
65417d9f 34#include "mmhub/mmhub_1_0_offset.h"
6ce68225 35#include "athub/athub_1_0_offset.h"
e60f8db5 36
946a4d5b 37#include "soc15.h"
e60f8db5 38#include "soc15_common.h"
90c7a935 39#include "umc/umc_6_0_sh_mask.h"
e60f8db5 40
e60f8db5
AX		 41#include "gfxhub_v1_0.h"
42#include "mmhub_v1_0.h"
43
44#define mmDF_CS_AON0_DramBaseAddress0 0x0044
45#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
46//DF_CS_AON0_DramBaseAddress0
47#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
48#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
49#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
50#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
51#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
52#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
53#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
54#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
55#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
56#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
57
58/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
59#define AMDGPU_NUM_OF_VMIDS 8
60
61static const u32 golden_settings_vega10_hdp[] =
62{
63 0xf64, 0x0fffffff, 0x00000000,
64 0xf65, 0x0fffffff, 0x00000000,
65 0xf66, 0x0fffffff, 0x00000000,
66 0xf67, 0x0fffffff, 0x00000000,
67 0xf68, 0x0fffffff, 0x00000000,
68 0xf6a, 0x0fffffff, 0x00000000,
69 0xf6b, 0x0fffffff, 0x00000000,
70 0xf6c, 0x0fffffff, 0x00000000,
71 0xf6d, 0x0fffffff, 0x00000000,
72 0xf6e, 0x0fffffff, 0x00000000,
73};
74
946a4d5b 75static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
5c583018 76{
946a4d5b
SL		 77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
78 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
5c583018
EQ		 79};
80
946a4d5b 81static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
5c583018 82{
946a4d5b
SL		 83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
84 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
5c583018
EQ		 85};
86
02bab923
DP		 87/* Ecc related register addresses, (BASE + reg offset) */
88/* Universal Memory Controller caps (may be fused). */
89/* UMCCH:UmcLocalCap */
90#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
91#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
92#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
93#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
94#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
95#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
96#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
97#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
98#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
99#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
100#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
101#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
102#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
103#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
104#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
105#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
106
107/* Universal Memory Controller Channel config. */
108/* UMCCH:UMC_CONFIG */
109#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
110#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
111#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
112#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
113#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
114#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
115#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
116#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
117#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
118#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
119#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
120#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
121#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
122#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
123#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
124#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
125
126/* Universal Memory Controller Channel Ecc config. */
127/* UMCCH:EccCtrl */
128#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
129#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
130#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
131#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
132#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
133#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
134#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
135#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
136#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
137#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
138#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
139#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
140#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
141#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
142#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
143#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
144
145static const uint32_t ecc_umclocalcap_addrs[] = {
146 UMCLOCALCAPS_ADDR0,
147 UMCLOCALCAPS_ADDR1,
148 UMCLOCALCAPS_ADDR2,
149 UMCLOCALCAPS_ADDR3,
150 UMCLOCALCAPS_ADDR4,
151 UMCLOCALCAPS_ADDR5,
152 UMCLOCALCAPS_ADDR6,
153 UMCLOCALCAPS_ADDR7,
154 UMCLOCALCAPS_ADDR8,
155 UMCLOCALCAPS_ADDR9,
156 UMCLOCALCAPS_ADDR10,
157 UMCLOCALCAPS_ADDR11,
158 UMCLOCALCAPS_ADDR12,
159 UMCLOCALCAPS_ADDR13,
160 UMCLOCALCAPS_ADDR14,
161 UMCLOCALCAPS_ADDR15,
162};
163
164static const uint32_t ecc_umcch_umc_config_addrs[] = {
165 UMCCH_UMC_CONFIG_ADDR0,
166 UMCCH_UMC_CONFIG_ADDR1,
167 UMCCH_UMC_CONFIG_ADDR2,
168 UMCCH_UMC_CONFIG_ADDR3,
169 UMCCH_UMC_CONFIG_ADDR4,
170 UMCCH_UMC_CONFIG_ADDR5,
171 UMCCH_UMC_CONFIG_ADDR6,
172 UMCCH_UMC_CONFIG_ADDR7,
173 UMCCH_UMC_CONFIG_ADDR8,
174 UMCCH_UMC_CONFIG_ADDR9,
175 UMCCH_UMC_CONFIG_ADDR10,
176 UMCCH_UMC_CONFIG_ADDR11,
177 UMCCH_UMC_CONFIG_ADDR12,
178 UMCCH_UMC_CONFIG_ADDR13,
179 UMCCH_UMC_CONFIG_ADDR14,
180 UMCCH_UMC_CONFIG_ADDR15,
181};
182
183static const uint32_t ecc_umcch_eccctrl_addrs[] = {
184 UMCCH_ECCCTRL_ADDR0,
185 UMCCH_ECCCTRL_ADDR1,
186 UMCCH_ECCCTRL_ADDR2,
187 UMCCH_ECCCTRL_ADDR3,
188 UMCCH_ECCCTRL_ADDR4,
189 UMCCH_ECCCTRL_ADDR5,
190 UMCCH_ECCCTRL_ADDR6,
191 UMCCH_ECCCTRL_ADDR7,
192 UMCCH_ECCCTRL_ADDR8,
193 UMCCH_ECCCTRL_ADDR9,
194 UMCCH_ECCCTRL_ADDR10,
195 UMCCH_ECCCTRL_ADDR11,
196 UMCCH_ECCCTRL_ADDR12,
197 UMCCH_ECCCTRL_ADDR13,
198 UMCCH_ECCCTRL_ADDR14,
199 UMCCH_ECCCTRL_ADDR15,
200};
201
e60f8db5
AX		 202static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
203 struct amdgpu_irq_src *src,
204 unsigned type,
205 enum amdgpu_interrupt_state state)
206{
207 struct amdgpu_vmhub *hub;
ae6d1416 208 u32 tmp, reg, bits, i, j;
e60f8db5 209
11250164
CK		 210 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
211 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
212 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
216 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
217
e60f8db5
AX		 218 switch (state) {
219 case AMDGPU_IRQ_STATE_DISABLE:
ae6d1416
TSD		 220 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
221 hub = &adev->vmhub[j];
222 for (i = 0; i < 16; i++) {
223 reg = hub->vm_context0_cntl + i;
224 tmp = RREG32(reg);
225 tmp &= ~bits;
226 WREG32(reg, tmp);
227 }
e60f8db5
AX		 228 }
229 break;
230 case AMDGPU_IRQ_STATE_ENABLE:
ae6d1416
TSD		 231 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
232 hub = &adev->vmhub[j];
233 for (i = 0; i < 16; i++) {
234 reg = hub->vm_context0_cntl + i;
235 tmp = RREG32(reg);
236 tmp |= bits;
237 WREG32(reg, tmp);
238 }
e60f8db5 239 }
e60f8db5
AX		 240 default:
241 break;
242 }
243
244 return 0;
245}
246
247static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
248 struct amdgpu_irq_src *source,
249 struct amdgpu_iv_entry *entry)
250{
c4f46f22 251 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
4d6cbde3 252 uint32_t status = 0;
e60f8db5
AX		 253 u64 addr;
254
255 addr = (u64)entry->src_data[0] << 12;
256 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
257
79a0c465 258 if (!amdgpu_sriov_vf(adev)) {
5a9b8e8a
CK		 259 status = RREG32(hub->vm_l2_pro_fault_status);
260 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
4d6cbde3 261 }
e60f8db5 262
4d6cbde3
FK		 263 if (printk_ratelimit()) {
264 dev_err(adev->dev,
c4f46f22
CK		 265 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pas_id:%u)\n",
266 entry->vmid_src ? "mmhub" : "gfxhub",
267 entry->src_id, entry->ring_id, entry->vmid,
4d6cbde3
FK		 268 entry->pas_id);
269 dev_err(adev->dev, " at page 0x%016llx from %d\n",
270 addr, entry->client_id);
271 if (!amdgpu_sriov_vf(adev))
272 dev_err(adev->dev,
273 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
274 status);
79a0c465 275 }
e60f8db5
AX		 276
277 return 0;
278}
279
280static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
281 .set = gmc_v9_0_vm_fault_interrupt_state,
282 .process = gmc_v9_0_process_interrupt,
283};
284
285static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
286{
287 adev->mc.vm_fault.num_types = 1;
288 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
289}
290
c4f46f22 291static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
03f89feb
CK		 292{
293 u32 req = 0;
294
c4f46f22 295 /* invalidate using legacy mode on vmid*/
03f89feb 296 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
c4f46f22 297 PER_VMID_INVALIDATE_REQ, 1 << vmid);
03f89feb
CK		 298 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
299 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
305 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
306
307 return req;
308}
309
e60f8db5
AX		 310/*
311 * GART
312 * VMID 0 is the physical GPU addresses as used by the kernel.
313 * VMIDs 1-15 are used for userspace clients and are handled
314 * by the amdgpu vm/hsa code.
315 */
316
317/**
318 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
319 *
320 * @adev: amdgpu_device pointer
321 * @vmid: vm instance to flush
322 *
323 * Flush the TLB for the requested page table.
324 */
325static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
326 uint32_t vmid)
327{
328 /* Use register 17 for GART */
329 const unsigned eng = 17;
330 unsigned i, j;
331
332 /* flush hdp cache */
bf383fb6 333 adev->nbio_funcs->hdp_flush(adev);
e60f8db5
AX		 334
335 spin_lock(&adev->mc.invalidate_lock);
336
337 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
338 struct amdgpu_vmhub *hub = &adev->vmhub[i];
03f89feb 339 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
e60f8db5 340
c7a7266b 341 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
e60f8db5
AX		 342
343 /* Busy wait for ACK.*/
344 for (j = 0; j < 100; j++) {
c7a7266b 345 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 346 tmp &= 1 << vmid;
347 if (tmp)
348 break;
349 cpu_relax();
350 }
351 if (j < 100)
352 continue;
353
354 /* Wait for ACK with a delay.*/
355 for (j = 0; j < adev->usec_timeout; j++) {
c7a7266b 356 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
e60f8db5
AX		 357 tmp &= 1 << vmid;
358 if (tmp)
359 break;
360 udelay(1);
361 }
362 if (j < adev->usec_timeout)
363 continue;
364
365 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
366 }
367
368 spin_unlock(&adev->mc.invalidate_lock);
369}
370
371/**
372 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
373 *
374 * @adev: amdgpu_device pointer
375 * @cpu_pt_addr: cpu address of the page table
376 * @gpu_page_idx: entry in the page table to update
377 * @addr: dst addr to write into pte/pde
378 * @flags: access flags
379 *
380 * Update the page tables using the CPU.
381 */
382static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
383 void *cpu_pt_addr,
384 uint32_t gpu_page_idx,
385 uint64_t addr,
386 uint64_t flags)
387{
388 void __iomem *ptr = (void *)cpu_pt_addr;
389 uint64_t value;
390
391 /*
392 * PTE format on VEGA 10:
393 * 63:59 reserved
394 * 58:57 mtype
395 * 56 F
396 * 55 L
397 * 54 P
398 * 53 SW
399 * 52 T
400 * 50:48 reserved
401 * 47:12 4k physical page base address
402 * 11:7 fragment
403 * 6 write
404 * 5 read
405 * 4 exe
406 * 3 Z
407 * 2 snooped
408 * 1 system
409 * 0 valid
410 *
411 * PDE format on VEGA 10:
412 * 63:59 block fragment size
413 * 58:55 reserved
414 * 54 P
415 * 53:48 reserved
416 * 47:6 physical base address of PD or PTE
417 * 5:3 reserved
418 * 2 C
419 * 1 system
420 * 0 valid
421 */
422
423 /*
424 * The following is for PTE only. GART does not have PDEs.
425 */
426 value = addr & 0x0000FFFFFFFFF000ULL;
427 value |= flags;
428 writeq(value, ptr + (gpu_page_idx * 8));
429 return 0;
430}
431
432static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
433 uint32_t flags)
434
435{
436 uint64_t pte_flag = 0;
437
438 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
439 pte_flag |= AMDGPU_PTE_EXECUTABLE;
440 if (flags & AMDGPU_VM_PAGE_READABLE)
441 pte_flag |= AMDGPU_PTE_READABLE;
442 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
443 pte_flag |= AMDGPU_PTE_WRITEABLE;
444
445 switch (flags & AMDGPU_VM_MTYPE_MASK) {
446 case AMDGPU_VM_MTYPE_DEFAULT:
447 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
448 break;
449 case AMDGPU_VM_MTYPE_NC:
450 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
451 break;
452 case AMDGPU_VM_MTYPE_WC:
453 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
454 break;
455 case AMDGPU_VM_MTYPE_CC:
456 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
457 break;
458 case AMDGPU_VM_MTYPE_UC:
459 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
460 break;
461 default:
462 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
463 break;
464 }
465
466 if (flags & AMDGPU_VM_PAGE_PRT)
467 pte_flag |= AMDGPU_PTE_PRT;
468
469 return pte_flag;
470}
471
3de676d8
CK		 472static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
473 uint64_t *addr, uint64_t *flags)
e60f8db5 474{
3de676d8
CK		 475 if (!(*flags & AMDGPU_PDE_PTE))
476 *addr = adev->vm_manager.vram_base_offset + *addr -
477 adev->mc.vram_start;
478 BUG_ON(*addr & 0xFFFF00000000003FULL);
6a42fd6f
CK		 479
480 if (!adev->mc.translate_further)
481 return;
482
483 if (level == AMDGPU_VM_PDB1) {
484 /* Set the block fragment size */
485 if (!(*flags & AMDGPU_PDE_PTE))
486 *flags |= AMDGPU_PDE_BFS(0x9);
487
488 } else if (level == AMDGPU_VM_PDB0) {
489 if (*flags & AMDGPU_PDE_PTE)
490 *flags &= ~AMDGPU_PDE_PTE;
491 else
492 *flags |= AMDGPU_PTE_TF;
493 }
e60f8db5
AX		 494}
495
f75e237c
CK		 496static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
497 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
498 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
03f89feb 499 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
b1166325
CK		 500 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
501 .get_vm_pde = gmc_v9_0_get_vm_pde
e60f8db5
AX		 502};
503
f75e237c 504static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
e60f8db5 505{
f75e237c
CK		 506 if (adev->gart.gart_funcs == NULL)
507 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
e60f8db5
AX		 508}
509
510static int gmc_v9_0_early_init(void *handle)
511{
512 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
513
514 gmc_v9_0_set_gart_funcs(adev);
e60f8db5
AX		 515 gmc_v9_0_set_irq_funcs(adev);
516
a7ea6548
AD		 517 adev->mc.shared_aperture_start = 0x2000000000000000ULL;
518 adev->mc.shared_aperture_end =
519 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
520 adev->mc.private_aperture_start =
521 adev->mc.shared_aperture_end + 1;
522 adev->mc.private_aperture_end =
523 adev->mc.private_aperture_start + (4ULL << 30) - 1;
524
e60f8db5
AX		 525 return 0;
526}
527
02bab923
DP		 528static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
529{
530 uint32_t reg_val;
531 uint32_t reg_addr;
532 uint32_t field_val;
533 size_t i;
534 uint32_t fv2;
535 size_t lost_sheep;
536
537 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
538
539 lost_sheep = 0;
540 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
541 reg_addr = ecc_umclocalcap_addrs[i];
542 DRM_DEBUG("ecc: "
543 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
544 i, reg_addr);
545 reg_val = RREG32(reg_addr);
546 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
547 EccDis);
548 DRM_DEBUG("ecc: "
549 "reg_val: 0x%08x, "
550 "EccDis: 0x%08x, ",
551 reg_val, field_val);
552 if (field_val) {
553 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
554 ++lost_sheep;
555 }
556 }
557
558 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
559 reg_addr = ecc_umcch_umc_config_addrs[i];
560 DRM_DEBUG("ecc: "
561 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
562 i, reg_addr);
563 reg_val = RREG32(reg_addr);
564 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
565 DramReady);
566 DRM_DEBUG("ecc: "
567 "reg_val: 0x%08x, "
568 "DramReady: 0x%08x\n",
569 reg_val, field_val);
570
571 if (!field_val) {
572 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
573 ++lost_sheep;
574 }
575 }
576
577 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
578 reg_addr = ecc_umcch_eccctrl_addrs[i];
579 DRM_DEBUG("ecc: "
580 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
581 i, reg_addr);
582 reg_val = RREG32(reg_addr);
583 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
584 WrEccEn);
585 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
586 RdEccEn);
587 DRM_DEBUG("ecc: "
588 "reg_val: 0x%08x, "
589 "WrEccEn: 0x%08x, "
590 "RdEccEn: 0x%08x\n",
591 reg_val, field_val, fv2);
592
593 if (!field_val) {
5a16008f 594 DRM_DEBUG("ecc: WrEccEn is not set\n");
02bab923
DP		 595 ++lost_sheep;
596 }
597 if (!fv2) {
5a16008f 598 DRM_DEBUG("ecc: RdEccEn is not set\n");
02bab923
DP		 599 ++lost_sheep;
600 }
601 }
602
603 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
604 return lost_sheep == 0;
605}
606
e60f8db5
AX		 607static int gmc_v9_0_late_init(void *handle)
608{
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c5066129 610 /*
611 * The latest engine allocation on gfx9 is:
612 * Engine 0, 1: idle
613 * Engine 2, 3: firmware
614 * Engine 4~13: amdgpu ring, subject to change when ring number changes
615 * Engine 14~15: idle
616 * Engine 16: kfd tlb invalidation
617 * Engine 17: Gart flushes
618 */
619 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
4789c463 620 unsigned i;
02bab923 621 int r;
4789c463
CK		 622
623 for(i = 0; i < adev->num_rings; ++i) {
624 struct amdgpu_ring *ring = adev->rings[i];
625 unsigned vmhub = ring->funcs->vmhub;
626
627 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
775f55f1
TSD		 628 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
629 ring->idx, ring->name, ring->vm_inv_eng,
630 ring->funcs->vmhub);
4789c463
CK		 631 }
632
c5066129 633 /* Engine 16 is used for KFD and 17 for GART flushes */
4789c463 634 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
c5066129 635 BUG_ON(vm_inv_eng[i] > 16);
4789c463 636
fd430a70 637 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
5ba4fa35
AD		 638 r = gmc_v9_0_ecc_available(adev);
639 if (r == 1) {
640 DRM_INFO("ECC is active.\n");
641 } else if (r == 0) {
642 DRM_INFO("ECC is not present.\n");
643 } else {
644 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
645 return r;
646 }
02bab923
DP		 647 }
648
e60f8db5
AX		 649 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
650}
651
652static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
653 struct amdgpu_mc *mc)
654{
eeb2487d
ML		 655 u64 base = 0;
656 if (!amdgpu_sriov_vf(adev))
657 base = mmhub_v1_0_get_fb_location(adev);
2543e28a
AD		 658 amdgpu_device_vram_location(adev, &adev->mc, base);
659 amdgpu_device_gart_location(adev, mc);
bc099ee9
CZ		 660 /* base offset of vram pages */
661 if (adev->flags & AMD_IS_APU)
662 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
663 else
664 adev->vm_manager.vram_base_offset = 0;
e60f8db5
AX		 665}
666
667/**
668 * gmc_v9_0_mc_init - initialize the memory controller driver params
669 *
670 * @adev: amdgpu_device pointer
671 *
672 * Look up the amount of vram, vram width, and decide how to place
673 * vram and gart within the GPU's physical address space.
674 * Returns 0 for success.
675 */
676static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
677{
678 u32 tmp;
679 int chansize, numchan;
d6895ad3 680 int r;
e60f8db5 681
8d6a5230
AD		 682 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
683 if (!adev->mc.vram_width) {
684 /* hbm memory channel size */
82d0ece9
TSD		 685 if (adev->flags & AMD_IS_APU)
686 chansize = 64;
687 else
688 chansize = 128;
8d6a5230
AD		 689
690 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
691 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
692 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
693 switch (tmp) {
694 case 0:
695 default:
696 numchan = 1;
697 break;
698 case 1:
699 numchan = 2;
700 break;
701 case 2:
702 numchan = 0;
703 break;
704 case 3:
705 numchan = 4;
706 break;
707 case 4:
708 numchan = 0;
709 break;
710 case 5:
711 numchan = 8;
712 break;
713 case 6:
714 numchan = 0;
715 break;
716 case 7:
717 numchan = 16;
718 break;
719 case 8:
720 numchan = 2;
721 break;
722 }
723 adev->mc.vram_width = numchan * chansize;
e60f8db5 724 }
e60f8db5 725
e60f8db5
AX		 726 /* size in MB on si */
727 adev->mc.mc_vram_size =
bf383fb6 728 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
e60f8db5 729 adev->mc.real_vram_size = adev->mc.mc_vram_size;
d6895ad3
CK		 730
731 if (!(adev->flags & AMD_IS_APU)) {
732 r = amdgpu_device_resize_fb_bar(adev);
733 if (r)
734 return r;
735 }
736 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
737 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
e60f8db5
AX		 738
739 /* In case the PCI BAR is larger than the actual amount of vram */
d6895ad3 740 adev->mc.visible_vram_size = adev->mc.aper_size;
e60f8db5
AX		 741 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
742 adev->mc.visible_vram_size = adev->mc.real_vram_size;
743
c3db7b5a
AD		 744 /* set the gart size */
745 if (amdgpu_gart_size == -1) {
746 switch (adev->asic_type) {
747 case CHIP_VEGA10: /* all engines support GPUVM */
748 default:
749 adev->mc.gart_size = 256ULL << 20;
750 break;
751 case CHIP_RAVEN: /* DCE SG support */
752 adev->mc.gart_size = 1024ULL << 20;
753 break;
754 }
755 } else {
756 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
757 }
758
e60f8db5
AX		 759 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
760
761 return 0;
762}
763
764static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
765{
766 int r;
767
768 if (adev->gart.robj) {
769 WARN(1, "VEGA10 PCIE GART already initialized\n");
770 return 0;
771 }
772 /* Initialize common gart structure */
773 r = amdgpu_gart_init(adev);
774 if (r)
775 return r;
776 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
777 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
778 AMDGPU_PTE_EXECUTABLE;
779 return amdgpu_gart_table_vram_alloc(adev);
780}
781
e60f8db5
AX		 782static int gmc_v9_0_sw_init(void *handle)
783{
784 int r;
785 int dma_bits;
786 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
787
0c8c0847 788 gfxhub_v1_0_init(adev);
77f6c763 789 mmhub_v1_0_init(adev);
0c8c0847 790
e60f8db5
AX		 791 spin_lock_init(&adev->mc.invalidate_lock);
792
fd66560b
HZ		 793 switch (adev->asic_type) {
794 case CHIP_RAVEN:
e60f8db5 795 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
6a42fd6f 796 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
f3368128 797 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
6a42fd6f
CK		 798 } else {
799 /* vm_size is 128TB + 512GB for legacy 3-level page support */
800 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
801 adev->mc.translate_further =
802 adev->vm_manager.num_level > 1;
803 }
fd66560b
HZ		 804 break;
805 case CHIP_VEGA10:
e60f8db5
AX		 806 /* XXX Don't know how to get VRAM type yet. */
807 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
36b32a68
ZJ		 808 /*
809 * To fulfill 4-level page support,
810 * vm size is 256TB (48bit), maximum size of Vega10,
811 * block size 512 (9bit)
812 */
f3368128 813 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
fd66560b
HZ		 814 break;
815 default:
816 break;
e60f8db5
AX		 817 }
818
819 /* This interrupt is VMC page fault.*/
820 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
821 &adev->mc.vm_fault);
d7c434d3
FK		 822 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
823 &adev->mc.vm_fault);
e60f8db5
AX		 824
825 if (r)
826 return r;
827
e60f8db5
AX		 828 /* Set the internal MC address mask
829 * This is the max address of the GPU's
830 * internal address space.
831 */
832 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
833
916910ad
HR		 834 /*
835 * It needs to reserve 8M stolen memory for vega10
836 * TODO: Figure out how to avoid that...
837 */
838 adev->mc.stolen_size = 8 * 1024 * 1024;
839
e60f8db5
AX		 840 /* set DMA mask + need_dma32 flags.
841 * PCIE - can handle 44-bits.
842 * IGP - can handle 44-bits
843 * PCI - dma32 for legacy pci gart, 44 bits on vega10
844 */
845 adev->need_dma32 = false;
846 dma_bits = adev->need_dma32 ? 32 : 44;
847 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
848 if (r) {
849 adev->need_dma32 = true;
850 dma_bits = 32;
851 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
852 }
853 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
854 if (r) {
855 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
856 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
857 }
858
859 r = gmc_v9_0_mc_init(adev);
860 if (r)
861 return r;
862
863 /* Memory manager */
864 r = amdgpu_bo_init(adev);
865 if (r)
866 return r;
867
868 r = gmc_v9_0_gart_init(adev);
869 if (r)
870 return r;
871
05ec3eda
CK		 872 /*
873 * number of VMs
874 * VMID 0 is reserved for System
875 * amdgpu graphics/compute will use VMIDs 1-7
876 * amdkfd will use VMIDs 8-15
877 */
878 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
879 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
880
05ec3eda
CK		 881 amdgpu_vm_manager_init(adev);
882
883 return 0;
e60f8db5
AX		 884}
885
886/**
c79ee7d8 887 * gmc_v9_0_gart_fini - vm fini callback
e60f8db5
AX		 888 *
889 * @adev: amdgpu_device pointer
890 *
891 * Tears down the driver GART/VM setup (CIK).
892 */
893static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
894{
895 amdgpu_gart_table_vram_free(adev);
896 amdgpu_gart_fini(adev);
897}
898
899static int gmc_v9_0_sw_fini(void *handle)
900{
901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
902
f59548c8 903 amdgpu_gem_force_release(adev);
05ec3eda 904 amdgpu_vm_manager_fini(adev);
e60f8db5 905 gmc_v9_0_gart_fini(adev);
e60f8db5
AX		 906 amdgpu_bo_fini(adev);
907
908 return 0;
909}
910
911static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
912{
946a4d5b 913
e60f8db5
AX		 914 switch (adev->asic_type) {
915 case CHIP_VEGA10:
946a4d5b 916 soc15_program_register_sequence(adev,
5c583018 917 golden_settings_mmhub_1_0_0,
c47b41a7 918 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
946a4d5b 919 soc15_program_register_sequence(adev,
5c583018 920 golden_settings_athub_1_0_0,
c47b41a7 921 ARRAY_SIZE(golden_settings_athub_1_0_0));
e60f8db5 922 break;
e4f3abaa 923 case CHIP_RAVEN:
946a4d5b 924 soc15_program_register_sequence(adev,
5c583018 925 golden_settings_athub_1_0_0,
c47b41a7 926 ARRAY_SIZE(golden_settings_athub_1_0_0));
e4f3abaa 927 break;
e60f8db5
AX		 928 default:
929 break;
930 }
931}
932
933/**
934 * gmc_v9_0_gart_enable - gart enable
935 *
936 * @adev: amdgpu_device pointer
937 */
938static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
939{
940 int r;
941 bool value;
942 u32 tmp;
943
9c3f2b54
AD		 944 amdgpu_device_program_register_sequence(adev,
945 golden_settings_vega10_hdp,
946 ARRAY_SIZE(golden_settings_vega10_hdp));
e60f8db5
AX		 947
948 if (adev->gart.robj == NULL) {
949 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
950 return -EINVAL;
951 }
ce1b1b66
ML		 952 r = amdgpu_gart_table_vram_pin(adev);
953 if (r)
954 return r;
e60f8db5 955
2fcd43ce
HZ		 956 switch (adev->asic_type) {
957 case CHIP_RAVEN:
958 mmhub_v1_0_initialize_power_gating(adev);
f8386b35 959 mmhub_v1_0_update_power_gating(adev, true);
2fcd43ce
HZ		 960 break;
961 default:
962 break;
963 }
964
e60f8db5
AX		 965 r = gfxhub_v1_0_gart_enable(adev);
966 if (r)
967 return r;
968
969 r = mmhub_v1_0_gart_enable(adev);
970 if (r)
971 return r;
972
846347c9 973 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
e60f8db5 974
b9509c80
HR		 975 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
976 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
e60f8db5 977
1d4e0a8c 978 /* After HDP is initialized, flush HDP.*/
bf383fb6 979 adev->nbio_funcs->hdp_flush(adev);
1d4e0a8c 980
e60f8db5
AX		 981 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
982 value = false;
983 else
984 value = true;
985
986 gfxhub_v1_0_set_fault_enable_default(adev, value);
987 mmhub_v1_0_set_fault_enable_default(adev, value);
e60f8db5
AX		 988 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
989
990 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
6f02a696 991 (unsigned)(adev->mc.gart_size >> 20),
e60f8db5
AX		 992 (unsigned long long)adev->gart.table_addr);
993 adev->gart.ready = true;
994 return 0;
995}
996
997static int gmc_v9_0_hw_init(void *handle)
998{
999 int r;
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002 /* The sequence of these two function calls matters.*/
1003 gmc_v9_0_init_golden_registers(adev);
1004
edca2d05 1005 if (adev->mode_info.num_crtc) {
edca2d05 1006 /* Lockout access through VGA aperture*/
4d9c333a 1007 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
edca2d05
AD		 1008
1009 /* disable VGA render */
4d9c333a 1010 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
edca2d05
AD		 1011 }
1012
e60f8db5
AX		 1013 r = gmc_v9_0_gart_enable(adev);
1014
1015 return r;
1016}
1017
1018/**
1019 * gmc_v9_0_gart_disable - gart disable
1020 *
1021 * @adev: amdgpu_device pointer
1022 *
1023 * This disables all VM page table.
1024 */
1025static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1026{
1027 gfxhub_v1_0_gart_disable(adev);
1028 mmhub_v1_0_gart_disable(adev);
ce1b1b66 1029 amdgpu_gart_table_vram_unpin(adev);
e60f8db5
AX		 1030}
1031
1032static int gmc_v9_0_hw_fini(void *handle)
1033{
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
5dd696ae
TH		 1036 if (amdgpu_sriov_vf(adev)) {
1037 /* full access mode, so don't touch any GMC register */
1038 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1039 return 0;
1040 }
1041
e60f8db5
AX		 1042 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1043 gmc_v9_0_gart_disable(adev);
1044
1045 return 0;
1046}
1047
1048static int gmc_v9_0_suspend(void *handle)
1049{
1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
f053cd47 1052 return gmc_v9_0_hw_fini(adev);
e60f8db5
AX		 1053}
1054
1055static int gmc_v9_0_resume(void *handle)
1056{
1057 int r;
1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060 r = gmc_v9_0_hw_init(adev);
1061 if (r)
1062 return r;
1063
620f774f 1064 amdgpu_vmid_reset_all(adev);
e60f8db5 1065
32601d48 1066 return 0;
e60f8db5
AX		 1067}
1068
1069static bool gmc_v9_0_is_idle(void *handle)
1070{
1071 /* MC is always ready in GMC v9.*/
1072 return true;
1073}
1074
1075static int gmc_v9_0_wait_for_idle(void *handle)
1076{
1077 /* There is no need to wait for MC idle in GMC v9.*/
1078 return 0;
1079}
1080
1081static int gmc_v9_0_soft_reset(void *handle)
1082{
1083 /* XXX for emulation.*/
1084 return 0;
1085}
1086
1087static int gmc_v9_0_set_clockgating_state(void *handle,
1088 enum amd_clockgating_state state)
1089{
d5583d4f
HR		 1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1091
1092 return mmhub_v1_0_set_clockgating(adev, state);
e60f8db5
AX		 1093}
1094
13052be5
HR		 1095static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1096{
1097 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1098
1099 mmhub_v1_0_get_clockgating(adev, flags);
1100}
1101
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AX		 1102static int gmc_v9_0_set_powergating_state(void *handle,
1103 enum amd_powergating_state state)
1104{
1105 return 0;
1106}
1107
1108const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1109 .name = "gmc_v9_0",
1110 .early_init = gmc_v9_0_early_init,
1111 .late_init = gmc_v9_0_late_init,
1112 .sw_init = gmc_v9_0_sw_init,
1113 .sw_fini = gmc_v9_0_sw_fini,
1114 .hw_init = gmc_v9_0_hw_init,
1115 .hw_fini = gmc_v9_0_hw_fini,
1116 .suspend = gmc_v9_0_suspend,
1117 .resume = gmc_v9_0_resume,
1118 .is_idle = gmc_v9_0_is_idle,
1119 .wait_for_idle = gmc_v9_0_wait_for_idle,
1120 .soft_reset = gmc_v9_0_soft_reset,
1121 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1122 .set_powergating_state = gmc_v9_0_set_powergating_state,
13052be5 1123 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
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AX		 1124};
1125
1126const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1127{
1128 .type = AMD_IP_BLOCK_TYPE_GMC,
1129 .major = 9,
1130 .minor = 0,
1131 .rev = 0,
1132 .funcs = &gmc_v9_0_ip_funcs,
1133};
Linux 6.x block layer and io_uring tree(s)