projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v8_0.h"
27#include "amdgpu_ucode.h"
28
29#include "gmc/gmc_8_1_d.h"
30#include "gmc/gmc_8_1_sh_mask.h"
31
32#include "bif/bif_5_0_d.h"
33#include "bif/bif_5_0_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "vid.h"
39#include "vi.h"
40
81c59f54 41
aaa36a97
AD		 42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
44
c65444fe 45MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
aaa36a97
AD		 46
47static const u32 golden_settings_tonga_a11[] =
48{
49 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
50 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
51 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
52 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
53 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
54 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
55 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
56};
57
58static const u32 tonga_mgcg_cgcg_init[] =
59{
60 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
61};
62
127a2628
DZ		 63static const u32 golden_settings_fiji_a10[] =
64{
65 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
66 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
67 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
68 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
69};
70
71static const u32 fiji_mgcg_cgcg_init[] =
72{
73 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
74};
75
aaa36a97
AD		 76static const u32 cz_mgcg_cgcg_init[] =
77{
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
79};
80
aade2f04
SL		 81static const u32 stoney_mgcg_cgcg_init[] =
82{
83 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
84};
85
86
aaa36a97
AD		 87static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
88{
89 switch (adev->asic_type) {
127a2628
DZ		 90 case CHIP_FIJI:
91 amdgpu_program_register_sequence(adev,
92 fiji_mgcg_cgcg_init,
93 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
94 amdgpu_program_register_sequence(adev,
95 golden_settings_fiji_a10,
96 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
97 break;
aaa36a97
AD		 98 case CHIP_TONGA:
99 amdgpu_program_register_sequence(adev,
100 tonga_mgcg_cgcg_init,
101 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
102 amdgpu_program_register_sequence(adev,
103 golden_settings_tonga_a11,
104 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
105 break;
106 case CHIP_CARRIZO:
107 amdgpu_program_register_sequence(adev,
108 cz_mgcg_cgcg_init,
109 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
110 break;
aade2f04
SL		 111 case CHIP_STONEY:
112 amdgpu_program_register_sequence(adev,
113 stoney_mgcg_cgcg_init,
114 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
115 break;
aaa36a97
AD		 116 default:
117 break;
118 }
119}
120
121/**
122 * gmc8_mc_wait_for_idle - wait for MC idle callback.
123 *
124 * @adev: amdgpu_device pointer
125 *
126 * Wait for the MC (memory controller) to be idle.
127 * (evergreen+).
128 * Returns 0 if the MC is idle, -1 if not.
129 */
130int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
131{
132 unsigned i;
133 u32 tmp;
134
135 for (i = 0; i < adev->usec_timeout; i++) {
136 /* read MC_STATUS */
137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
138 SRBM_STATUS__MCB_BUSY_MASK |
139 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
140 SRBM_STATUS__MCC_BUSY_MASK |
141 SRBM_STATUS__MCD_BUSY_MASK |
142 SRBM_STATUS__VMC1_BUSY_MASK);
143 if (!tmp)
144 return 0;
145 udelay(1);
146 }
147 return -1;
148}
149
150void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
151 struct amdgpu_mode_mc_save *save)
152{
153 u32 blackout;
154
155 if (adev->mode_info.num_crtc)
156 amdgpu_display_stop_mc_access(adev, save);
157
158 amdgpu_asic_wait_for_mc_idle(adev);
159
160 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
161 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
162 /* Block CPU access */
163 WREG32(mmBIF_FB_EN, 0);
164 /* blackout the MC */
165 blackout = REG_SET_FIELD(blackout,
166 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
167 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
168 }
169 /* wait for the MC to settle */
170 udelay(100);
171}
172
173void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
174 struct amdgpu_mode_mc_save *save)
175{
176 u32 tmp;
177
178 /* unblackout the MC */
179 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
180 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
182 /* allow CPU access */
183 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
184 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
185 WREG32(mmBIF_FB_EN, tmp);
186
187 if (adev->mode_info.num_crtc)
188 amdgpu_display_resume_mc_access(adev, save);
189}
190
191/**
192 * gmc_v8_0_init_microcode - load ucode images from disk
193 *
194 * @adev: amdgpu_device pointer
195 *
196 * Use the firmware interface to load the ucode images into
197 * the driver (not loaded into hw).
198 * Returns 0 on success, error on failure.
199 */
200static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
201{
202 const char *chip_name;
203 char fw_name[30];
204 int err;
205
206 DRM_DEBUG("\n");
207
208 switch (adev->asic_type) {
aaa36a97
AD		 209 case CHIP_TONGA:
210 chip_name = "tonga";
211 break;
127a2628 212 case CHIP_FIJI:
aaa36a97 213 case CHIP_CARRIZO:
aade2f04 214 case CHIP_STONEY:
aaa36a97
AD		 215 return 0;
216 default: BUG();
217 }
218
c65444fe 219 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
aaa36a97
AD		 220 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
221 if (err)
222 goto out;
223 err = amdgpu_ucode_validate(adev->mc.fw);
224
225out:
226 if (err) {
227 printk(KERN_ERR
228 "mc: Failed to load firmware \"%s\"\n",
229 fw_name);
230 release_firmware(adev->mc.fw);
231 adev->mc.fw = NULL;
232 }
233 return err;
234}
235
236/**
237 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
238 *
239 * @adev: amdgpu_device pointer
240 *
241 * Load the GDDR MC ucode into the hw (CIK).
242 * Returns 0 on success, error on failure.
243 */
244static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
245{
246 const struct mc_firmware_header_v1_0 *hdr;
247 const __le32 *fw_data = NULL;
248 const __le32 *io_mc_regs = NULL;
249 u32 running, blackout = 0;
250 int i, ucode_size, regs_size;
251
252 if (!adev->mc.fw)
253 return -EINVAL;
254
255 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
256 amdgpu_ucode_print_mc_hdr(&hdr->header);
257
258 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
259 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
260 io_mc_regs = (const __le32 *)
261 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
262 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
263 fw_data = (const __le32 *)
264 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
265
266 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
267
268 if (running == 0) {
269 if (running) {
270 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
271 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
272 }
273
274 /* reset the engine and set to writable */
275 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
276 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
277
278 /* load mc io regs */
279 for (i = 0; i < regs_size; i++) {
280 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
281 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
282 }
283 /* load the MC ucode */
284 for (i = 0; i < ucode_size; i++)
285 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
286
287 /* put the engine back into the active state */
288 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
289 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
290 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
291
292 /* wait for training to complete */
293 for (i = 0; i < adev->usec_timeout; i++) {
294 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
295 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
296 break;
297 udelay(1);
298 }
299 for (i = 0; i < adev->usec_timeout; i++) {
300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
301 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
302 break;
303 udelay(1);
304 }
305
306 if (running)
307 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
308 }
309
310 return 0;
311}
312
313static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
314 struct amdgpu_mc *mc)
315{
316 if (mc->mc_vram_size > 0xFFC0000000ULL) {
317 /* leave room for at least 1024M GTT */
318 dev_warn(adev->dev, "limiting VRAM\n");
319 mc->real_vram_size = 0xFFC0000000ULL;
320 mc->mc_vram_size = 0xFFC0000000ULL;
321 }
322 amdgpu_vram_location(adev, &adev->mc, 0);
323 adev->mc.gtt_base_align = 0;
324 amdgpu_gtt_location(adev, mc);
325}
326
327/**
328 * gmc_v8_0_mc_program - program the GPU memory controller
329 *
330 * @adev: amdgpu_device pointer
331 *
332 * Set the location of vram, gart, and AGP in the GPU's
333 * physical address space (CIK).
334 */
335static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
336{
337 struct amdgpu_mode_mc_save save;
338 u32 tmp;
339 int i, j;
340
341 /* Initialize HDP */
342 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
343 WREG32((0xb05 + j), 0x00000000);
344 WREG32((0xb06 + j), 0x00000000);
345 WREG32((0xb07 + j), 0x00000000);
346 WREG32((0xb08 + j), 0x00000000);
347 WREG32((0xb09 + j), 0x00000000);
348 }
349 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
350
351 if (adev->mode_info.num_crtc)
352 amdgpu_display_set_vga_render_state(adev, false);
353
354 gmc_v8_0_mc_stop(adev, &save);
355 if (amdgpu_asic_wait_for_mc_idle(adev)) {
356 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
357 }
358 /* Update configuration */
359 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
360 adev->mc.vram_start >> 12);
361 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
362 adev->mc.vram_end >> 12);
363 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
364 adev->vram_scratch.gpu_addr >> 12);
365 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
366 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
367 WREG32(mmMC_VM_FB_LOCATION, tmp);
368 /* XXX double check these! */
369 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
370 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
371 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
372 WREG32(mmMC_VM_AGP_BASE, 0);
373 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
374 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
375 if (amdgpu_asic_wait_for_mc_idle(adev)) {
376 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
377 }
378 gmc_v8_0_mc_resume(adev, &save);
379
380 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
381
382 tmp = RREG32(mmHDP_MISC_CNTL);
383 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
384 WREG32(mmHDP_MISC_CNTL, tmp);
385
386 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
387 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
388}
389
390/**
391 * gmc_v8_0_mc_init - initialize the memory controller driver params
392 *
393 * @adev: amdgpu_device pointer
394 *
395 * Look up the amount of vram, vram width, and decide how to place
396 * vram and gart within the GPU's physical address space (CIK).
397 * Returns 0 for success.
398 */
399static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
400{
401 u32 tmp;
402 int chansize, numchan;
403
404 /* Get VRAM informations */
405 tmp = RREG32(mmMC_ARB_RAMCFG);
406 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
407 chansize = 64;
408 } else {
409 chansize = 32;
410 }
411 tmp = RREG32(mmMC_SHARED_CHMAP);
412 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
413 case 0:
414 default:
415 numchan = 1;
416 break;
417 case 1:
418 numchan = 2;
419 break;
420 case 2:
421 numchan = 4;
422 break;
423 case 3:
424 numchan = 8;
425 break;
426 case 4:
427 numchan = 3;
428 break;
429 case 5:
430 numchan = 6;
431 break;
432 case 6:
433 numchan = 10;
434 break;
435 case 7:
436 numchan = 12;
437 break;
438 case 8:
439 numchan = 16;
440 break;
441 }
442 adev->mc.vram_width = numchan * chansize;
443 /* Could aper size report 0 ? */
444 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
445 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
446 /* size in MB on si */
447 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
448 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
449 adev->mc.visible_vram_size = adev->mc.aper_size;
450
a1493cd5
AD		 451 /* In case the PCI BAR is larger than the actual amount of vram */
452 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
453 adev->mc.visible_vram_size = adev->mc.real_vram_size;
454
aaa36a97
AD		 455 /* unless the user had overridden it, set the gart
456 * size equal to the 1024 or vram, whichever is larger.
457 */
458 if (amdgpu_gart_size == -1)
459 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
460 else
461 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
462
463 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
464
465 return 0;
466}
467
468/*
469 * GART
470 * VMID 0 is the physical GPU addresses as used by the kernel.
471 * VMIDs 1-15 are used for userspace clients and are handled
472 * by the amdgpu vm/hsa code.
473 */
474
475/**
476 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
477 *
478 * @adev: amdgpu_device pointer
479 * @vmid: vm instance to flush
480 *
481 * Flush the TLB for the requested page table (CIK).
482 */
483static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
484 uint32_t vmid)
485{
486 /* flush hdp cache */
487 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
488
489 /* bits 0-15 are the VM contexts0-15 */
490 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
491}
492
493/**
494 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
495 *
496 * @adev: amdgpu_device pointer
497 * @cpu_pt_addr: cpu address of the page table
498 * @gpu_page_idx: entry in the page table to update
499 * @addr: dst addr to write into pte/pde
500 * @flags: access flags
501 *
502 * Update the page tables using the CPU.
503 */
504static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
505 void *cpu_pt_addr,
506 uint32_t gpu_page_idx,
507 uint64_t addr,
508 uint32_t flags)
509{
510 void __iomem *ptr = (void *)cpu_pt_addr;
511 uint64_t value;
512
513 /*
514 * PTE format on VI:
515 * 63:40 reserved
516 * 39:12 4k physical page base address
517 * 11:7 fragment
518 * 6 write
519 * 5 read
520 * 4 exe
521 * 3 reserved
522 * 2 snooped
523 * 1 system
524 * 0 valid
525 *
526 * PDE format on VI:
527 * 63:59 block fragment size
528 * 58:40 reserved
529 * 39:1 physical base address of PTE
530 * bits 5:1 must be 0.
531 * 0 valid
532 */
533 value = addr & 0x000000FFFFFFF000ULL;
534 value |= flags;
535 writeq(value, ptr + (gpu_page_idx * 8));
536
537 return 0;
538}
539
d9c13156
CK		 540/**
541 * gmc_v8_0_set_fault_enable_default - update VM fault handling
542 *
543 * @adev: amdgpu_device pointer
544 * @value: true redirects VM faults to the default page
545 */
546static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
547 bool value)
548{
549 u32 tmp;
550
551 tmp = RREG32(mmVM_CONTEXT1_CNTL);
552 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
553 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
554 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
555 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
556 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
557 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
558 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
559 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
561 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
562 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
563 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
564 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
565 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
566 WREG32(mmVM_CONTEXT1_CNTL, tmp);
567}
568
aaa36a97
AD		 569/**
570 * gmc_v8_0_gart_enable - gart enable
571 *
572 * @adev: amdgpu_device pointer
573 *
574 * This sets up the TLBs, programs the page tables for VMID0,
575 * sets up the hw for VMIDs 1-15 which are allocated on
576 * demand, and sets up the global locations for the LDS, GDS,
577 * and GPUVM for FSA64 clients (CIK).
578 * Returns 0 for success, errors for failure.
579 */
580static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
581{
582 int r, i;
583 u32 tmp;
584
585 if (adev->gart.robj == NULL) {
586 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
587 return -EINVAL;
588 }
589 r = amdgpu_gart_table_vram_pin(adev);
590 if (r)
591 return r;
592 /* Setup TLB control */
593 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
594 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
595 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
596 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
597 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
598 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
599 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
600 /* Setup L2 cache */
601 tmp = RREG32(mmVM_L2_CNTL);
602 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
603 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
604 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
605 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
606 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
607 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
a80b3047 608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
aaa36a97
AD		 609 WREG32(mmVM_L2_CNTL, tmp);
610 tmp = RREG32(mmVM_L2_CNTL2);
611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
613 WREG32(mmVM_L2_CNTL2, tmp);
614 tmp = RREG32(mmVM_L2_CNTL3);
615 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
616 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
618 WREG32(mmVM_L2_CNTL3, tmp);
619 /* XXX: set to enable PTE/PDE in system memory */
620 tmp = RREG32(mmVM_L2_CNTL4);
621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
633 WREG32(mmVM_L2_CNTL4, tmp);
634 /* setup context0 */
635 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
9c97b5ab 636 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
aaa36a97
AD		 637 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
638 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
639 (u32)(adev->dummy_page.addr >> 12));
640 WREG32(mmVM_CONTEXT0_CNTL2, 0);
641 tmp = RREG32(mmVM_CONTEXT0_CNTL);
642 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
643 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
644 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
645 WREG32(mmVM_CONTEXT0_CNTL, tmp);
646
647 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
648 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
649 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
650
651 /* empty context1-15 */
652 /* FIXME start with 4G, once using 2 level pt switch to full
653 * vm size space
654 */
655 /* set vm size, must be a multiple of 4 */
656 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
25a595e4 657 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
aaa36a97
AD		 658 for (i = 1; i < 16; i++) {
659 if (i < 8)
660 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
661 adev->gart.table_addr >> 12);
662 else
663 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
664 adev->gart.table_addr >> 12);
665 }
666
667 /* enable context1-15 */
668 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
669 (u32)(adev->dummy_page.addr >> 12));
670 WREG32(mmVM_CONTEXT1_CNTL2, 4);
671 tmp = RREG32(mmVM_CONTEXT1_CNTL);
672 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
673 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
aaa36a97 674 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 675 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 676 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 677 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 678 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97
AD		 680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
682 amdgpu_vm_block_size - 9);
683 WREG32(mmVM_CONTEXT1_CNTL, tmp);
d9c13156
CK		 684 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
685 gmc_v8_0_set_fault_enable_default(adev, false);
686 else
687 gmc_v8_0_set_fault_enable_default(adev, true);
aaa36a97
AD		 688
689 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
690 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
691 (unsigned)(adev->mc.gtt_size >> 20),
692 (unsigned long long)adev->gart.table_addr);
693 adev->gart.ready = true;
694 return 0;
695}
696
697static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
698{
699 int r;
700
701 if (adev->gart.robj) {
702 WARN(1, "R600 PCIE GART already initialized\n");
703 return 0;
704 }
705 /* Initialize common gart structure */
706 r = amdgpu_gart_init(adev);
707 if (r)
708 return r;
709 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
710 return amdgpu_gart_table_vram_alloc(adev);
711}
712
713/**
714 * gmc_v8_0_gart_disable - gart disable
715 *
716 * @adev: amdgpu_device pointer
717 *
718 * This disables all VM page table (CIK).
719 */
720static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
721{
722 u32 tmp;
723
724 /* Disable all tables */
725 WREG32(mmVM_CONTEXT0_CNTL, 0);
726 WREG32(mmVM_CONTEXT1_CNTL, 0);
727 /* Setup TLB control */
728 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
729 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
730 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
731 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
732 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
733 /* Setup L2 cache */
734 tmp = RREG32(mmVM_L2_CNTL);
735 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
736 WREG32(mmVM_L2_CNTL, tmp);
737 WREG32(mmVM_L2_CNTL2, 0);
738 amdgpu_gart_table_vram_unpin(adev);
739}
740
741/**
742 * gmc_v8_0_gart_fini - vm fini callback
743 *
744 * @adev: amdgpu_device pointer
745 *
746 * Tears down the driver GART/VM setup (CIK).
747 */
748static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
749{
750 amdgpu_gart_table_vram_free(adev);
751 amdgpu_gart_fini(adev);
752}
753
754/*
755 * vm
756 * VMID 0 is the physical GPU addresses as used by the kernel.
757 * VMIDs 1-15 are used for userspace clients and are handled
758 * by the amdgpu vm/hsa code.
759 */
760/**
761 * gmc_v8_0_vm_init - cik vm init callback
762 *
763 * @adev: amdgpu_device pointer
764 *
765 * Inits cik specific vm parameters (number of VMs, base of vram for
766 * VMIDs 1-15) (CIK).
767 * Returns 0 for success.
768 */
769static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
770{
771 /*
772 * number of VMs
773 * VMID 0 is reserved for System
774 * amdgpu graphics/compute will use VMIDs 1-7
775 * amdkfd will use VMIDs 8-15
776 */
777 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
778
779 /* base offset of vram pages */
2f7d10b3 780 if (adev->flags & AMD_IS_APU) {
aaa36a97
AD		 781 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
782 tmp <<= 22;
783 adev->vm_manager.vram_base_offset = tmp;
784 } else
785 adev->vm_manager.vram_base_offset = 0;
786
787 return 0;
788}
789
790/**
791 * gmc_v8_0_vm_fini - cik vm fini callback
792 *
793 * @adev: amdgpu_device pointer
794 *
795 * Tear down any asic specific VM setup (CIK).
796 */
797static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
798{
799}
800
801/**
802 * gmc_v8_0_vm_decode_fault - print human readable fault info
803 *
804 * @adev: amdgpu_device pointer
805 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
806 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
807 *
808 * Print human readable fault information (CIK).
809 */
810static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
811 u32 status, u32 addr, u32 mc_client)
812{
813 u32 mc_id;
814 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
815 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
816 PROTECTIONS);
817 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
818 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
819
820 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
821 MEMORY_CLIENT_ID);
822
823 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
824 protections, vmid, addr,
825 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
826 MEMORY_CLIENT_RW) ?
827 "write" : "read", block, mc_client, mc_id);
828}
829
81c59f54
KW		 830static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
831{
832 switch (mc_seq_vram_type) {
833 case MC_SEQ_MISC0__MT__GDDR1:
834 return AMDGPU_VRAM_TYPE_GDDR1;
835 case MC_SEQ_MISC0__MT__DDR2:
836 return AMDGPU_VRAM_TYPE_DDR2;
837 case MC_SEQ_MISC0__MT__GDDR3:
838 return AMDGPU_VRAM_TYPE_GDDR3;
839 case MC_SEQ_MISC0__MT__GDDR4:
840 return AMDGPU_VRAM_TYPE_GDDR4;
841 case MC_SEQ_MISC0__MT__GDDR5:
842 return AMDGPU_VRAM_TYPE_GDDR5;
843 case MC_SEQ_MISC0__MT__HBM:
844 return AMDGPU_VRAM_TYPE_HBM;
845 case MC_SEQ_MISC0__MT__DDR3:
846 return AMDGPU_VRAM_TYPE_DDR3;
847 default:
848 return AMDGPU_VRAM_TYPE_UNKNOWN;
849 }
850}
851
5fc3aeeb 852static int gmc_v8_0_early_init(void *handle)
aaa36a97 853{
5fc3aeeb 854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
855
aaa36a97
AD		 856 gmc_v8_0_set_gart_funcs(adev);
857 gmc_v8_0_set_irq_funcs(adev);
858
2f7d10b3 859 if (adev->flags & AMD_IS_APU) {
81c59f54 860 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
aaa36a97
AD		 861 } else {
862 u32 tmp = RREG32(mmMC_SEQ_MISC0);
81c59f54
KW		 863 tmp &= MC_SEQ_MISC0__MT__MASK;
864 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
aaa36a97
AD		 865 }
866
867 return 0;
868}
869
140b519f
CK		 870static int gmc_v8_0_late_init(void *handle)
871{
872 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
873
874 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
875}
876
5fc3aeeb 877static int gmc_v8_0_sw_init(void *handle)
aaa36a97
AD		 878{
879 int r;
880 int dma_bits;
5fc3aeeb 881 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 882
883 r = amdgpu_gem_init(adev);
884 if (r)
885 return r;
886
887 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
888 if (r)
889 return r;
890
891 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
892 if (r)
893 return r;
894
895 /* Adjust VM size here.
896 * Currently set to 4GB ((1 << 20) 4k pages).
897 * Max GPUVM size for cayman and SI is 40 bits.
898 */
899 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
900
901 /* Set the internal MC address mask
902 * This is the max address of the GPU's
903 * internal address space.
904 */
905 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
906
907 /* set DMA mask + need_dma32 flags.
908 * PCIE - can handle 40-bits.
909 * IGP - can handle 40-bits
910 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
911 */
912 adev->need_dma32 = false;
913 dma_bits = adev->need_dma32 ? 32 : 40;
914 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
915 if (r) {
916 adev->need_dma32 = true;
917 dma_bits = 32;
918 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
919 }
920 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
921 if (r) {
922 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
923 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
924 }
925
926 r = gmc_v8_0_init_microcode(adev);
927 if (r) {
928 DRM_ERROR("Failed to load mc firmware!\n");
929 return r;
930 }
931
932 r = gmc_v8_0_mc_init(adev);
933 if (r)
934 return r;
935
936 /* Memory manager */
937 r = amdgpu_bo_init(adev);
938 if (r)
939 return r;
940
941 r = gmc_v8_0_gart_init(adev);
942 if (r)
943 return r;
944
945 if (!adev->vm_manager.enabled) {
946 r = gmc_v8_0_vm_init(adev);
947 if (r) {
948 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
949 return r;
950 }
951 adev->vm_manager.enabled = true;
952 }
953
954 return r;
955}
956
5fc3aeeb 957static int gmc_v8_0_sw_fini(void *handle)
aaa36a97 958{
5fc3aeeb 959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 960
961 if (adev->vm_manager.enabled) {
ea89f8c9 962 amdgpu_vm_manager_fini(adev);
aaa36a97
AD		 963 gmc_v8_0_vm_fini(adev);
964 adev->vm_manager.enabled = false;
965 }
966 gmc_v8_0_gart_fini(adev);
967 amdgpu_gem_fini(adev);
968 amdgpu_bo_fini(adev);
969
970 return 0;
971}
972
5fc3aeeb 973static int gmc_v8_0_hw_init(void *handle)
aaa36a97
AD		 974{
975 int r;
5fc3aeeb 976 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 977
978 gmc_v8_0_init_golden_registers(adev);
979
980 gmc_v8_0_mc_program(adev);
981
8878d854 982 if (adev->asic_type == CHIP_TONGA) {
aaa36a97
AD		 983 r = gmc_v8_0_mc_load_microcode(adev);
984 if (r) {
985 DRM_ERROR("Failed to load MC firmware!\n");
986 return r;
987 }
988 }
989
990 r = gmc_v8_0_gart_enable(adev);
991 if (r)
992 return r;
993
994 return r;
995}
996
5fc3aeeb 997static int gmc_v8_0_hw_fini(void *handle)
aaa36a97 998{
5fc3aeeb 999 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1000
140b519f 1001 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
aaa36a97
AD		 1002 gmc_v8_0_gart_disable(adev);
1003
1004 return 0;
1005}
1006
5fc3aeeb 1007static int gmc_v8_0_suspend(void *handle)
aaa36a97 1008{
5fc3aeeb 1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1010
1011 if (adev->vm_manager.enabled) {
aaa36a97
AD		 1012 gmc_v8_0_vm_fini(adev);
1013 adev->vm_manager.enabled = false;
1014 }
1015 gmc_v8_0_hw_fini(adev);
1016
1017 return 0;
1018}
1019
5fc3aeeb 1020static int gmc_v8_0_resume(void *handle)
aaa36a97
AD		 1021{
1022 int r;
5fc3aeeb 1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1024
1025 r = gmc_v8_0_hw_init(adev);
1026 if (r)
1027 return r;
1028
1029 if (!adev->vm_manager.enabled) {
1030 r = gmc_v8_0_vm_init(adev);
1031 if (r) {
1032 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1033 return r;
1034 }
1035 adev->vm_manager.enabled = true;
1036 }
1037
1038 return r;
1039}
1040
5fc3aeeb 1041static bool gmc_v8_0_is_idle(void *handle)
aaa36a97 1042{
5fc3aeeb 1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1044 u32 tmp = RREG32(mmSRBM_STATUS);
1045
1046 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1047 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1048 return false;
1049
1050 return true;
1051}
1052
5fc3aeeb 1053static int gmc_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 1054{
1055 unsigned i;
1056 u32 tmp;
5fc3aeeb 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1058
1059 for (i = 0; i < adev->usec_timeout; i++) {
1060 /* read MC_STATUS */
1061 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1062 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1063 SRBM_STATUS__MCC_BUSY_MASK |
1064 SRBM_STATUS__MCD_BUSY_MASK |
1065 SRBM_STATUS__VMC_BUSY_MASK |
1066 SRBM_STATUS__VMC1_BUSY_MASK);
1067 if (!tmp)
1068 return 0;
1069 udelay(1);
1070 }
1071 return -ETIMEDOUT;
1072
1073}
1074
5fc3aeeb 1075static void gmc_v8_0_print_status(void *handle)
aaa36a97
AD		 1076{
1077 int i, j;
5fc3aeeb 1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1079
1080 dev_info(adev->dev, "GMC 8.x registers\n");
1081 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1082 RREG32(mmSRBM_STATUS));
1083 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1084 RREG32(mmSRBM_STATUS2));
1085
1086 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1087 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1088 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1089 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1090 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1091 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1092 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1093 RREG32(mmVM_L2_CNTL));
1094 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1095 RREG32(mmVM_L2_CNTL2));
1096 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1097 RREG32(mmVM_L2_CNTL3));
1098 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
1099 RREG32(mmVM_L2_CNTL4));
1100 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1101 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1102 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1103 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1104 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1105 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1106 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1107 RREG32(mmVM_CONTEXT0_CNTL2));
1108 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1109 RREG32(mmVM_CONTEXT0_CNTL));
1110 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1111 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1112 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1113 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1114 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1115 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1116 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1117 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1118 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1119 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1120 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1121 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1122 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1123 RREG32(mmVM_CONTEXT1_CNTL2));
1124 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1125 RREG32(mmVM_CONTEXT1_CNTL));
1126 for (i = 0; i < 16; i++) {
1127 if (i < 8)
1128 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1129 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1130 else
1131 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1132 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1133 }
1134 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1135 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1136 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1137 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1138 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1139 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1140 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1141 RREG32(mmMC_VM_FB_LOCATION));
1142 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1143 RREG32(mmMC_VM_AGP_BASE));
1144 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1145 RREG32(mmMC_VM_AGP_TOP));
1146 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1147 RREG32(mmMC_VM_AGP_BOT));
1148
1149 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1150 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1151 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1152 RREG32(mmHDP_NONSURFACE_BASE));
1153 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1154 RREG32(mmHDP_NONSURFACE_INFO));
1155 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1156 RREG32(mmHDP_NONSURFACE_SIZE));
1157 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1158 RREG32(mmHDP_MISC_CNTL));
1159 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1160 RREG32(mmHDP_HOST_PATH_CNTL));
1161
1162 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1163 dev_info(adev->dev, " %d:\n", i);
1164 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1165 0xb05 + j, RREG32(0xb05 + j));
1166 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1167 0xb06 + j, RREG32(0xb06 + j));
1168 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1169 0xb07 + j, RREG32(0xb07 + j));
1170 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1171 0xb08 + j, RREG32(0xb08 + j));
1172 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1173 0xb09 + j, RREG32(0xb09 + j));
1174 }
1175
1176 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1177 RREG32(mmBIF_FB_EN));
1178}
1179
5fc3aeeb 1180static int gmc_v8_0_soft_reset(void *handle)
aaa36a97
AD		 1181{
1182 struct amdgpu_mode_mc_save save;
1183 u32 srbm_soft_reset = 0;
5fc3aeeb 1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1185 u32 tmp = RREG32(mmSRBM_STATUS);
1186
1187 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1188 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1189 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1190
1191 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1192 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
2f7d10b3 1193 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 1194 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1195 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1196 }
1197
1198 if (srbm_soft_reset) {
5fc3aeeb 1199 gmc_v8_0_print_status((void *)adev);
aaa36a97
AD		 1200
1201 gmc_v8_0_mc_stop(adev, &save);
1202 if (gmc_v8_0_wait_for_idle(adev)) {
1203 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1204 }
1205
1206
1207 tmp = RREG32(mmSRBM_SOFT_RESET);
1208 tmp |= srbm_soft_reset;
1209 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1210 WREG32(mmSRBM_SOFT_RESET, tmp);
1211 tmp = RREG32(mmSRBM_SOFT_RESET);
1212
1213 udelay(50);
1214
1215 tmp &= ~srbm_soft_reset;
1216 WREG32(mmSRBM_SOFT_RESET, tmp);
1217 tmp = RREG32(mmSRBM_SOFT_RESET);
1218
1219 /* Wait a little for things to settle down */
1220 udelay(50);
1221
1222 gmc_v8_0_mc_resume(adev, &save);
1223 udelay(50);
1224
5fc3aeeb 1225 gmc_v8_0_print_status((void *)adev);
aaa36a97
AD		 1226 }
1227
1228 return 0;
1229}
1230
1231static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1232 struct amdgpu_irq_src *src,
1233 unsigned type,
1234 enum amdgpu_interrupt_state state)
1235{
1236 u32 tmp;
1237 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1238 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1239 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1240 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1241 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1242 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1243 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1244
1245 switch (state) {
1246 case AMDGPU_IRQ_STATE_DISABLE:
1247 /* system context */
1248 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1249 tmp &= ~bits;
1250 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1251 /* VMs */
1252 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1253 tmp &= ~bits;
1254 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1255 break;
1256 case AMDGPU_IRQ_STATE_ENABLE:
1257 /* system context */
1258 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1259 tmp |= bits;
1260 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1261 /* VMs */
1262 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1263 tmp |= bits;
1264 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1265 break;
1266 default:
1267 break;
1268 }
1269
1270 return 0;
1271}
1272
1273static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1274 struct amdgpu_irq_src *source,
1275 struct amdgpu_iv_entry *entry)
1276{
1277 u32 addr, status, mc_client;
1278
1279 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1280 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1281 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
ce0c6bcd
CK		 1282 /* reset addr and status */
1283 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1284
1285 if (!addr && !status)
1286 return 0;
1287
d9c13156
CK		 1288 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1289 gmc_v8_0_set_fault_enable_default(adev, false);
1290
aaa36a97
AD		 1291 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1292 entry->src_id, entry->src_data);
1293 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1294 addr);
1295 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1296 status);
1297 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
aaa36a97
AD		 1298
1299 return 0;
1300}
1301
a0d69786
EH		 1302static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1303 bool enable)
1304{
1305 uint32_t data;
1306
1307 if (enable) {
1308 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1309 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1310 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1311
1312 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1313 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1314 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1315
1316 data = RREG32(mmMC_HUB_MISC_VM_CG);
1317 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1318 WREG32(mmMC_HUB_MISC_VM_CG, data);
1319
1320 data = RREG32(mmMC_XPB_CLK_GAT);
1321 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1322 WREG32(mmMC_XPB_CLK_GAT, data);
1323
1324 data = RREG32(mmATC_MISC_CG);
1325 data |= ATC_MISC_CG__ENABLE_MASK;
1326 WREG32(mmATC_MISC_CG, data);
1327
1328 data = RREG32(mmMC_CITF_MISC_WR_CG);
1329 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1330 WREG32(mmMC_CITF_MISC_WR_CG, data);
1331
1332 data = RREG32(mmMC_CITF_MISC_RD_CG);
1333 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1334 WREG32(mmMC_CITF_MISC_RD_CG, data);
1335
1336 data = RREG32(mmMC_CITF_MISC_VM_CG);
1337 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1338 WREG32(mmMC_CITF_MISC_VM_CG, data);
1339
1340 data = RREG32(mmVM_L2_CG);
1341 data |= VM_L2_CG__ENABLE_MASK;
1342 WREG32(mmVM_L2_CG, data);
1343 } else {
1344 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1345 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1346 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1347
1348 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1349 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1350 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1351
1352 data = RREG32(mmMC_HUB_MISC_VM_CG);
1353 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1354 WREG32(mmMC_HUB_MISC_VM_CG, data);
1355
1356 data = RREG32(mmMC_XPB_CLK_GAT);
1357 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1358 WREG32(mmMC_XPB_CLK_GAT, data);
1359
1360 data = RREG32(mmATC_MISC_CG);
1361 data &= ~ATC_MISC_CG__ENABLE_MASK;
1362 WREG32(mmATC_MISC_CG, data);
1363
1364 data = RREG32(mmMC_CITF_MISC_WR_CG);
1365 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1366 WREG32(mmMC_CITF_MISC_WR_CG, data);
1367
1368 data = RREG32(mmMC_CITF_MISC_RD_CG);
1369 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1370 WREG32(mmMC_CITF_MISC_RD_CG, data);
1371
1372 data = RREG32(mmMC_CITF_MISC_VM_CG);
1373 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1374 WREG32(mmMC_CITF_MISC_VM_CG, data);
1375
1376 data = RREG32(mmVM_L2_CG);
1377 data &= ~VM_L2_CG__ENABLE_MASK;
1378 WREG32(mmVM_L2_CG, data);
1379 }
1380}
1381
1382static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1383 bool enable)
1384{
1385 uint32_t data;
1386
1387 if (enable) {
1388 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1389 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1390 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1391
1392 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1393 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1394 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1395
1396 data = RREG32(mmMC_HUB_MISC_VM_CG);
1397 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1398 WREG32(mmMC_HUB_MISC_VM_CG, data);
1399
1400 data = RREG32(mmMC_XPB_CLK_GAT);
1401 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1402 WREG32(mmMC_XPB_CLK_GAT, data);
1403
1404 data = RREG32(mmATC_MISC_CG);
1405 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1406 WREG32(mmATC_MISC_CG, data);
1407
1408 data = RREG32(mmMC_CITF_MISC_WR_CG);
1409 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1410 WREG32(mmMC_CITF_MISC_WR_CG, data);
1411
1412 data = RREG32(mmMC_CITF_MISC_RD_CG);
1413 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1414 WREG32(mmMC_CITF_MISC_RD_CG, data);
1415
1416 data = RREG32(mmMC_CITF_MISC_VM_CG);
1417 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1418 WREG32(mmMC_CITF_MISC_VM_CG, data);
1419
1420 data = RREG32(mmVM_L2_CG);
1421 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1422 WREG32(mmVM_L2_CG, data);
1423 } else {
1424 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1425 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1426 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1427
1428 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1429 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1430 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1431
1432 data = RREG32(mmMC_HUB_MISC_VM_CG);
1433 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1434 WREG32(mmMC_HUB_MISC_VM_CG, data);
1435
1436 data = RREG32(mmMC_XPB_CLK_GAT);
1437 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1438 WREG32(mmMC_XPB_CLK_GAT, data);
1439
1440 data = RREG32(mmATC_MISC_CG);
1441 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1442 WREG32(mmATC_MISC_CG, data);
1443
1444 data = RREG32(mmMC_CITF_MISC_WR_CG);
1445 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1446 WREG32(mmMC_CITF_MISC_WR_CG, data);
1447
1448 data = RREG32(mmMC_CITF_MISC_RD_CG);
1449 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1450 WREG32(mmMC_CITF_MISC_RD_CG, data);
1451
1452 data = RREG32(mmMC_CITF_MISC_VM_CG);
1453 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1454 WREG32(mmMC_CITF_MISC_VM_CG, data);
1455
1456 data = RREG32(mmVM_L2_CG);
1457 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1458 WREG32(mmVM_L2_CG, data);
1459 }
1460}
1461
5fc3aeeb 1462static int gmc_v8_0_set_clockgating_state(void *handle,
1463 enum amd_clockgating_state state)
aaa36a97 1464{
a0d69786
EH		 1465 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1466
1467 switch (adev->asic_type) {
1468 case CHIP_FIJI:
1469 fiji_update_mc_medium_grain_clock_gating(adev,
1470 state == AMD_CG_STATE_GATE ? true : false);
1471 fiji_update_mc_light_sleep(adev,
1472 state == AMD_CG_STATE_GATE ? true : false);
1473 break;
1474 default:
1475 break;
1476 }
aaa36a97
AD		 1477 return 0;
1478}
1479
5fc3aeeb 1480static int gmc_v8_0_set_powergating_state(void *handle,
1481 enum amd_powergating_state state)
aaa36a97
AD		 1482{
1483 return 0;
1484}
1485
5fc3aeeb 1486const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
aaa36a97 1487 .early_init = gmc_v8_0_early_init,
140b519f 1488 .late_init = gmc_v8_0_late_init,
aaa36a97
AD		 1489 .sw_init = gmc_v8_0_sw_init,
1490 .sw_fini = gmc_v8_0_sw_fini,
1491 .hw_init = gmc_v8_0_hw_init,
1492 .hw_fini = gmc_v8_0_hw_fini,
1493 .suspend = gmc_v8_0_suspend,
1494 .resume = gmc_v8_0_resume,
1495 .is_idle = gmc_v8_0_is_idle,
1496 .wait_for_idle = gmc_v8_0_wait_for_idle,
1497 .soft_reset = gmc_v8_0_soft_reset,
1498 .print_status = gmc_v8_0_print_status,
1499 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1500 .set_powergating_state = gmc_v8_0_set_powergating_state,
1501};
1502
1503static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1504 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1505 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1506};
1507
1508static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1509 .set = gmc_v8_0_vm_fault_interrupt_state,
1510 .process = gmc_v8_0_process_interrupt,
1511};
1512
1513static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1514{
1515 if (adev->gart.gart_funcs == NULL)
1516 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1517}
1518
1519static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1520{
1521 adev->mc.vm_fault.num_types = 1;
1522 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1523}
Linux 6.x block layer and io_uring tree(s)