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drm/amd/amdgpu: Tidy up static int dce_v6_0_get_num_crtc()
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gmc_v6_0.c
CommitLineData
df70502e
KW		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v6_0.h"
27#include "amdgpu_ucode.h"
72518269
TSD		 28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
df70502e
KW		 38
39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static int gmc_v6_0_wait_for_idle(void *handle);
42
43MODULE_FIRMWARE("radeon/tahiti_mc.bin");
44MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
45MODULE_FIRMWARE("radeon/verde_mc.bin");
46MODULE_FIRMWARE("radeon/oland_mc.bin");
f1d877be 47MODULE_FIRMWARE("radeon/si58_mc.bin");
df70502e 48
72518269
TSD		 49#define MC_SEQ_MISC0__MT__MASK 0xf0000000
50#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
51#define MC_SEQ_MISC0__MT__DDR2 0x20000000
52#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
53#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
54#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
55#define MC_SEQ_MISC0__MT__HBM 0x60000000
56#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
57
58
df70502e
KW		 59static const u32 crtc_offsets[6] =
60{
61 SI_CRTC0_REGISTER_OFFSET,
62 SI_CRTC1_REGISTER_OFFSET,
63 SI_CRTC2_REGISTER_OFFSET,
64 SI_CRTC3_REGISTER_OFFSET,
65 SI_CRTC4_REGISTER_OFFSET,
66 SI_CRTC5_REGISTER_OFFSET
67};
68
69static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
70 struct amdgpu_mode_mc_save *save)
71{
72 u32 blackout;
73
74 if (adev->mode_info.num_crtc)
75 amdgpu_display_stop_mc_access(adev, save);
76
77 gmc_v6_0_wait_for_idle((void *)adev);
78
72518269
TSD		 79 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
80 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
df70502e 81 /* Block CPU access */
72518269 82 WREG32(mmBIF_FB_EN, 0);
df70502e
KW		 83 /* blackout the MC */
84 blackout = REG_SET_FIELD(blackout,
72518269
TSD		 85 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
86 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
df70502e
KW		 87 }
88 /* wait for the MC to settle */
89 udelay(100);
90
91}
92
93static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
94 struct amdgpu_mode_mc_save *save)
95{
96 u32 tmp;
97
98 /* unblackout the MC */
72518269
TSD		 99 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
100 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
df70502e 102 /* allow CPU access */
72518269
TSD		 103 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
104 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
105 WREG32(mmBIF_FB_EN, tmp);
df70502e
KW		 106
107 if (adev->mode_info.num_crtc)
108 amdgpu_display_resume_mc_access(adev, save);
109
110}
111
112static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
113{
114 const char *chip_name;
115 char fw_name[30];
116 int err;
f1d877be 117 bool is_58_fw = false;
df70502e
KW		 118
119 DRM_DEBUG("\n");
120
121 switch (adev->asic_type) {
122 case CHIP_TAHITI:
123 chip_name = "tahiti";
124 break;
125 case CHIP_PITCAIRN:
126 chip_name = "pitcairn";
127 break;
128 case CHIP_VERDE:
129 chip_name = "verde";
130 break;
131 case CHIP_OLAND:
132 chip_name = "oland";
133 break;
134 case CHIP_HAINAN:
135 chip_name = "hainan";
136 break;
137 default: BUG();
138 }
139
f1d877be
AD		 140 /* this memory configuration requires special firmware */
141 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
142 is_58_fw = true;
143
144 if (is_58_fw)
145 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
146 else
147 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
df70502e
KW		 148 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
149 if (err)
150 goto out;
151
152 err = amdgpu_ucode_validate(adev->mc.fw);
153
154out:
155 if (err) {
075719c3 156 dev_err(adev->dev,
df70502e
KW		 157 "si_mc: Failed to load firmware \"%s\"\n",
158 fw_name);
159 release_firmware(adev->mc.fw);
160 adev->mc.fw = NULL;
161 }
162 return err;
163}
164
165static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
166{
167 const __le32 *new_fw_data = NULL;
168 u32 running;
169 const __le32 *new_io_mc_regs = NULL;
170 int i, regs_size, ucode_size;
171 const struct mc_firmware_header_v1_0 *hdr;
172
173 if (!adev->mc.fw)
174 return -EINVAL;
175
176 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
177
178 amdgpu_ucode_print_mc_hdr(&hdr->header);
179
180 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
181 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
182 new_io_mc_regs = (const __le32 *)
183 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
184 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
185 new_fw_data = (const __le32 *)
186 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
187
72518269 188 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
df70502e
KW		 189
190 if (running == 0) {
191
192 /* reset the engine and set to writable */
72518269
TSD		 193 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
df70502e
KW		 195
196 /* load mc io regs */
197 for (i = 0; i < regs_size; i++) {
72518269
TSD		 198 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
199 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
df70502e
KW		 200 }
201 /* load the MC ucode */
202 for (i = 0; i < ucode_size; i++) {
72518269 203 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
df70502e
KW		 204 }
205
206 /* put the engine back into the active state */
72518269
TSD		 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
209 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
df70502e
KW		 210
211 /* wait for training to complete */
212 for (i = 0; i < adev->usec_timeout; i++) {
72518269 213 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
df70502e
KW		 214 break;
215 udelay(1);
216 }
217 for (i = 0; i < adev->usec_timeout; i++) {
72518269 218 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
df70502e
KW		 219 break;
220 udelay(1);
221 }
222
223 }
224
225 return 0;
226}
227
228static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
229 struct amdgpu_mc *mc)
230{
231 if (mc->mc_vram_size > 0xFFC0000000ULL) {
232 dev_warn(adev->dev, "limiting VRAM\n");
233 mc->real_vram_size = 0xFFC0000000ULL;
234 mc->mc_vram_size = 0xFFC0000000ULL;
235 }
236 amdgpu_vram_location(adev, &adev->mc, 0);
237 adev->mc.gtt_base_align = 0;
238 amdgpu_gtt_location(adev, mc);
239}
240
241static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
242{
243 struct amdgpu_mode_mc_save save;
244 u32 tmp;
245 int i, j;
246
247 /* Initialize HDP */
248 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
249 WREG32((0xb05 + j), 0x00000000);
250 WREG32((0xb06 + j), 0x00000000);
251 WREG32((0xb07 + j), 0x00000000);
252 WREG32((0xb08 + j), 0x00000000);
253 WREG32((0xb09 + j), 0x00000000);
254 }
72518269 255 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
df70502e 256
57bcd0a6
AD		 257 if (adev->mode_info.num_crtc)
258 amdgpu_display_set_vga_render_state(adev, false);
259
df70502e
KW		 260 gmc_v6_0_mc_stop(adev, &save);
261
262 if (gmc_v6_0_wait_for_idle((void *)adev)) {
263 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
264 }
265
72518269 266 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
df70502e 267 /* Update configuration */
72518269 268 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
df70502e 269 adev->mc.vram_start >> 12);
72518269 270 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
df70502e 271 adev->mc.vram_end >> 12);
72518269 272 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
df70502e
KW		 273 adev->vram_scratch.gpu_addr >> 12);
274 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
275 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
72518269 276 WREG32(mmMC_VM_FB_LOCATION, tmp);
df70502e 277 /* XXX double check these! */
72518269
TSD		 278 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
279 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
280 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
281 WREG32(mmMC_VM_AGP_BASE, 0);
282 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
283 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
df70502e
KW		 284
285 if (gmc_v6_0_wait_for_idle((void *)adev)) {
286 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
287 }
288 gmc_v6_0_mc_resume(adev, &save);
df70502e
KW		 289}
290
291static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
292{
293
294 u32 tmp;
295 int chansize, numchan;
296
72518269
TSD		 297 tmp = RREG32(mmMC_ARB_RAMCFG);
298 if (tmp & (1 << 11)) {
df70502e 299 chansize = 16;
72518269 300 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
df70502e
KW		 301 chansize = 64;
302 } else {
303 chansize = 32;
304 }
72518269
TSD		 305 tmp = RREG32(mmMC_SHARED_CHMAP);
306 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
df70502e
KW		 307 case 0:
308 default:
309 numchan = 1;
310 break;
311 case 1:
312 numchan = 2;
313 break;
314 case 2:
315 numchan = 4;
316 break;
317 case 3:
318 numchan = 8;
319 break;
320 case 4:
321 numchan = 3;
322 break;
323 case 5:
324 numchan = 6;
325 break;
326 case 6:
327 numchan = 10;
328 break;
329 case 7:
330 numchan = 12;
331 break;
332 case 8:
333 numchan = 16;
334 break;
335 }
336 adev->mc.vram_width = numchan * chansize;
337 /* Could aper size report 0 ? */
338 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
339 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
340 /* size in MB on si */
72518269
TSD		 341 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
342 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
df70502e
KW		 343 adev->mc.visible_vram_size = adev->mc.aper_size;
344
345 /* unless the user had overridden it, set the gart
346 * size equal to the 1024 or vram, whichever is larger.
347 */
348 if (amdgpu_gart_size == -1)
55ed8caf
CZ		 349 adev->mc.gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
350 adev->mc.mc_vram_size);
df70502e
KW		 351 else
352 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
353
354 gmc_v6_0_vram_gtt_location(adev, &adev->mc);
355
356 return 0;
357}
358
359static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
360 uint32_t vmid)
361{
72518269 362 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
df70502e 363
72518269 364 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
df70502e
KW		 365}
366
367static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
368 void *cpu_pt_addr,
369 uint32_t gpu_page_idx,
370 uint64_t addr,
6b777607 371 uint64_t flags)
df70502e
KW		 372{
373 void __iomem *ptr = (void *)cpu_pt_addr;
374 uint64_t value;
375
376 value = addr & 0xFFFFFFFFFFFFF000ULL;
377 value |= flags;
378 writeq(value, ptr + (gpu_page_idx * 8));
379
380 return 0;
381}
382
5463545b
AX		 383static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
384 uint32_t flags)
385{
386 uint64_t pte_flag = 0;
387
388 if (flags & AMDGPU_VM_PAGE_READABLE)
389 pte_flag |= AMDGPU_PTE_READABLE;
390 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
391 pte_flag |= AMDGPU_PTE_WRITEABLE;
392 if (flags & AMDGPU_VM_PAGE_PRT)
393 pte_flag |= AMDGPU_PTE_PRT;
394
395 return pte_flag;
396}
397
df70502e
KW		 398static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
399 bool value)
400{
401 u32 tmp;
402
72518269
TSD		 403 tmp = RREG32(mmVM_CONTEXT1_CNTL);
404 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
405 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
406 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
407 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
408 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
409 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
410 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
411 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
412 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
413 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
414 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
415 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
416 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 417}
418
f7c35abe
CK		 419 /**
420 + * gmc_v8_0_set_prt - set PRT VM fault
421 + *
422 + * @adev: amdgpu_device pointer
423 + * @enable: enable/disable VM fault handling for PRT
424 +*/
425static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
426{
427 u32 tmp;
428
429 if (enable && !adev->mc.prt_warning) {
430 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
431 adev->mc.prt_warning = true;
432 }
433
434 tmp = RREG32(mmVM_PRT_CNTL);
435 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
436 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
437 enable);
438 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
439 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
440 enable);
441 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
442 L2_CACHE_STORE_INVALID_ENTRIES,
443 enable);
444 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
445 L1_TLB_STORE_INVALID_ENTRIES,
446 enable);
447 WREG32(mmVM_PRT_CNTL, tmp);
448
449 if (enable) {
450 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
451 uint32_t high = adev->vm_manager.max_pfn;
452
453 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
454 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
455 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
456 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
457 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
458 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
459 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
460 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
461 } else {
462 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
463 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
464 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
465 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
466 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
467 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
468 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
469 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
470 }
471}
472
df70502e
KW		 473static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
474{
475 int r, i;
476
477 if (adev->gart.robj == NULL) {
478 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
479 return -EINVAL;
480 }
481 r = amdgpu_gart_table_vram_pin(adev);
482 if (r)
483 return r;
484 /* Setup TLB control */
72518269 485 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
df70502e 486 (0xA << 7) |
72518269
TSD		 487 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
488 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
489 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
490 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
491 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
df70502e 492 /* Setup L2 cache */
72518269
TSD		 493 WREG32(mmVM_L2_CNTL,
494 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
495 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
496 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
497 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
498 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
499 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
500 WREG32(mmVM_L2_CNTL2,
501 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
502 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
503 WREG32(mmVM_L2_CNTL3,
504 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
505 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
506 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
df70502e 507 /* setup context0 */
72518269
TSD		 508 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
509 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
510 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
511 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
df70502e 512 (u32)(adev->dummy_page.addr >> 12));
72518269
TSD		 513 WREG32(mmVM_CONTEXT0_CNTL2, 0);
514 WREG32(mmVM_CONTEXT0_CNTL,
515 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
516 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
517 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
df70502e
KW		 518
519 WREG32(0x575, 0);
520 WREG32(0x576, 0);
521 WREG32(0x577, 0);
522
523 /* empty context1-15 */
524 /* set vm size, must be a multiple of 4 */
72518269
TSD		 525 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
526 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
df70502e
KW		 527 /* Assign the pt base to something valid for now; the pts used for
528 * the VMs are determined by the application and setup and assigned
529 * on the fly in the vm part of radeon_gart.c
530 */
531 for (i = 1; i < 16; i++) {
532 if (i < 8)
72518269 533 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
df70502e
KW		 534 adev->gart.table_addr >> 12);
535 else
72518269 536 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
df70502e
KW		 537 adev->gart.table_addr >> 12);
538 }
539
540 /* enable context1-15 */
72518269 541 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
df70502e 542 (u32)(adev->dummy_page.addr >> 12));
72518269
TSD		 543 WREG32(mmVM_CONTEXT1_CNTL2, 4);
544 WREG32(mmVM_CONTEXT1_CNTL,
545 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
546 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
36b32a68
ZJ		 547 ((adev->vm_manager.block_size - 9)
548 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
a8447647
FC		 549 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
550 gmc_v6_0_set_fault_enable_default(adev, false);
551 else
552 gmc_v6_0_set_fault_enable_default(adev, true);
df70502e
KW		 553
554 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
075719c3 555 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
df70502e
KW		 556 (unsigned)(adev->mc.gtt_size >> 20),
557 (unsigned long long)adev->gart.table_addr);
558 adev->gart.ready = true;
559 return 0;
560}
561
562static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
563{
564 int r;
565
566 if (adev->gart.robj) {
075719c3 567 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
df70502e
KW		 568 return 0;
569 }
570 r = amdgpu_gart_init(adev);
571 if (r)
572 return r;
573 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
4b98e0c4 574 adev->gart.gart_pte_flags = 0;
df70502e
KW		 575 return amdgpu_gart_table_vram_alloc(adev);
576}
577
578static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
579{
580 /*unsigned i;
581
582 for (i = 1; i < 16; ++i) {
583 uint32_t reg;
584 if (i < 8)
585 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
586 else
587 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
588 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
589 }*/
590
591 /* Disable all tables */
72518269
TSD		 592 WREG32(mmVM_CONTEXT0_CNTL, 0);
593 WREG32(mmVM_CONTEXT1_CNTL, 0);
df70502e 594 /* Setup TLB control */
72518269
TSD		 595 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
596 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
597 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
df70502e 598 /* Setup L2 cache */
72518269
TSD		 599 WREG32(mmVM_L2_CNTL,
600 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
601 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
602 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
603 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
604 WREG32(mmVM_L2_CNTL2, 0);
605 WREG32(mmVM_L2_CNTL3,
606 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
607 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
df70502e
KW		 608 amdgpu_gart_table_vram_unpin(adev);
609}
610
611static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
612{
613 amdgpu_gart_table_vram_free(adev);
614 amdgpu_gart_fini(adev);
615}
616
df70502e
KW		 617static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
618 u32 status, u32 addr, u32 mc_client)
619{
620 u32 mc_id;
72518269
TSD		 621 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
622 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
623 PROTECTIONS);
df70502e
KW		 624 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
625 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
626
72518269
TSD		 627 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
628 MEMORY_CLIENT_ID);
df70502e 629
075719c3 630 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
df70502e 631 protections, vmid, addr,
72518269
TSD		 632 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
633 MEMORY_CLIENT_RW) ?
df70502e
KW		 634 "write" : "read", block, mc_client, mc_id);
635}
636
637/*
638static const u32 mc_cg_registers[] = {
639 MC_HUB_MISC_HUB_CG,
640 MC_HUB_MISC_SIP_CG,
641 MC_HUB_MISC_VM_CG,
642 MC_XPB_CLK_GAT,
643 ATC_MISC_CG,
644 MC_CITF_MISC_WR_CG,
645 MC_CITF_MISC_RD_CG,
646 MC_CITF_MISC_VM_CG,
647 VM_L2_CG,
648};
649
650static const u32 mc_cg_ls_en[] = {
651 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
652 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
653 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
654 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
655 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
656 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
657 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
658 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
659 VM_L2_CG__MEM_LS_ENABLE_MASK,
660};
661
662static const u32 mc_cg_en[] = {
663 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
664 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
665 MC_HUB_MISC_VM_CG__ENABLE_MASK,
666 MC_XPB_CLK_GAT__ENABLE_MASK,
667 ATC_MISC_CG__ENABLE_MASK,
668 MC_CITF_MISC_WR_CG__ENABLE_MASK,
669 MC_CITF_MISC_RD_CG__ENABLE_MASK,
670 MC_CITF_MISC_VM_CG__ENABLE_MASK,
671 VM_L2_CG__ENABLE_MASK,
672};
673
674static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
675 bool enable)
676{
677 int i;
678 u32 orig, data;
679
680 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
681 orig = data = RREG32(mc_cg_registers[i]);
682 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
683 data |= mc_cg_ls_en[i];
684 else
685 data &= ~mc_cg_ls_en[i];
686 if (data != orig)
687 WREG32(mc_cg_registers[i], data);
688 }
689}
690
691static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
692 bool enable)
693{
694 int i;
695 u32 orig, data;
696
697 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
698 orig = data = RREG32(mc_cg_registers[i]);
699 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
700 data |= mc_cg_en[i];
701 else
702 data &= ~mc_cg_en[i];
703 if (data != orig)
704 WREG32(mc_cg_registers[i], data);
705 }
706}
707
708static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
709 bool enable)
710{
711 u32 orig, data;
712
713 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
714
715 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
716 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
717 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
718 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
719 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
720 } else {
721 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
722 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
723 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
724 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
725 }
726
727 if (orig != data)
728 WREG32_PCIE(ixPCIE_CNTL2, data);
729}
730
731static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
732 bool enable)
733{
734 u32 orig, data;
735
72518269 736 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
df70502e
KW		 737
738 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
739 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
740 else
741 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
742
743 if (orig != data)
72518269 744 WREG32(mmHDP_HOST_PATH_CNTL, data);
df70502e
KW		 745}
746
747static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
748 bool enable)
749{
750 u32 orig, data;
751
72518269 752 orig = data = RREG32(mmHDP_MEM_POWER_LS);
df70502e
KW		 753
754 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
755 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
756 else
757 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
758
759 if (orig != data)
72518269 760 WREG32(mmHDP_MEM_POWER_LS, data);
df70502e
KW		 761}
762*/
763
764static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
765{
766 switch (mc_seq_vram_type) {
767 case MC_SEQ_MISC0__MT__GDDR1:
768 return AMDGPU_VRAM_TYPE_GDDR1;
769 case MC_SEQ_MISC0__MT__DDR2:
770 return AMDGPU_VRAM_TYPE_DDR2;
771 case MC_SEQ_MISC0__MT__GDDR3:
772 return AMDGPU_VRAM_TYPE_GDDR3;
773 case MC_SEQ_MISC0__MT__GDDR4:
774 return AMDGPU_VRAM_TYPE_GDDR4;
775 case MC_SEQ_MISC0__MT__GDDR5:
776 return AMDGPU_VRAM_TYPE_GDDR5;
777 case MC_SEQ_MISC0__MT__DDR3:
778 return AMDGPU_VRAM_TYPE_DDR3;
779 default:
780 return AMDGPU_VRAM_TYPE_UNKNOWN;
781 }
782}
783
784static int gmc_v6_0_early_init(void *handle)
785{
786 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
787
788 gmc_v6_0_set_gart_funcs(adev);
789 gmc_v6_0_set_irq_funcs(adev);
790
791 if (adev->flags & AMD_IS_APU) {
792 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
793 } else {
72518269 794 u32 tmp = RREG32(mmMC_SEQ_MISC0);
df70502e
KW		 795 tmp &= MC_SEQ_MISC0__MT__MASK;
796 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
797 }
798
799 return 0;
800}
801
802static int gmc_v6_0_late_init(void *handle)
803{
804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
805
a8447647
FC		 806 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
807 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
808 else
809 return 0;
df70502e
KW		 810}
811
812static int gmc_v6_0_sw_init(void *handle)
813{
814 int r;
815 int dma_bits;
816 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
817
d766e6a3 818 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
df70502e
KW		 819 if (r)
820 return r;
821
d766e6a3 822 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
df70502e
KW		 823 if (r)
824 return r;
825
bab4fee7 826 amdgpu_vm_adjust_size(adev, 64);
36b32a68
ZJ		 827 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
828
df70502e
KW		 829 adev->mc.mc_mask = 0xffffffffffULL;
830
831 adev->need_dma32 = false;
832 dma_bits = adev->need_dma32 ? 32 : 40;
833 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
834 if (r) {
835 adev->need_dma32 = true;
836 dma_bits = 32;
075719c3 837 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
df70502e
KW		 838 }
839 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
840 if (r) {
841 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
075719c3 842 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
df70502e
KW		 843 }
844
845 r = gmc_v6_0_init_microcode(adev);
846 if (r) {
075719c3 847 dev_err(adev->dev, "Failed to load mc firmware!\n");
df70502e
KW		 848 return r;
849 }
850
df70502e
KW		 851 r = gmc_v6_0_mc_init(adev);
852 if (r)
853 return r;
854
855 r = amdgpu_bo_init(adev);
856 if (r)
857 return r;
858
859 r = gmc_v6_0_gart_init(adev);
860 if (r)
861 return r;
862
05ec3eda
CK		 863 /*
864 * number of VMs
865 * VMID 0 is reserved for System
866 * amdgpu graphics/compute will use VMIDs 1-7
867 * amdkfd will use VMIDs 8-15
868 */
869 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
870 adev->vm_manager.num_level = 1;
871 amdgpu_vm_manager_init(adev);
872
873 /* base offset of vram pages */
874 if (adev->flags & AMD_IS_APU) {
875 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
876
877 tmp <<= 22;
878 adev->vm_manager.vram_base_offset = tmp;
879 } else {
880 adev->vm_manager.vram_base_offset = 0;
df70502e
KW		 881 }
882
05ec3eda 883 return 0;
df70502e
KW		 884}
885
886static int gmc_v6_0_sw_fini(void *handle)
887{
888 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
889
05ec3eda 890 amdgpu_vm_manager_fini(adev);
df70502e
KW		 891 gmc_v6_0_gart_fini(adev);
892 amdgpu_gem_force_release(adev);
893 amdgpu_bo_fini(adev);
894
895 return 0;
896}
897
898static int gmc_v6_0_hw_init(void *handle)
899{
900 int r;
901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
902
903 gmc_v6_0_mc_program(adev);
904
905 if (!(adev->flags & AMD_IS_APU)) {
906 r = gmc_v6_0_mc_load_microcode(adev);
907 if (r) {
075719c3 908 dev_err(adev->dev, "Failed to load MC firmware!\n");
df70502e
KW		 909 return r;
910 }
911 }
912
913 r = gmc_v6_0_gart_enable(adev);
914 if (r)
915 return r;
916
917 return r;
918}
919
920static int gmc_v6_0_hw_fini(void *handle)
921{
922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
923
924 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
925 gmc_v6_0_gart_disable(adev);
926
927 return 0;
928}
929
930static int gmc_v6_0_suspend(void *handle)
931{
932 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
933
df70502e
KW		 934 gmc_v6_0_hw_fini(adev);
935
936 return 0;
937}
938
939static int gmc_v6_0_resume(void *handle)
940{
941 int r;
942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
943
944 r = gmc_v6_0_hw_init(adev);
945 if (r)
946 return r;
947
32601d48 948 amdgpu_vm_reset_all_ids(adev);
df70502e 949
32601d48 950 return 0;
df70502e
KW		 951}
952
953static bool gmc_v6_0_is_idle(void *handle)
954{
955 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
72518269 956 u32 tmp = RREG32(mmSRBM_STATUS);
df70502e
KW		 957
958 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
959 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
960 return false;
961
962 return true;
963}
964
965static int gmc_v6_0_wait_for_idle(void *handle)
966{
967 unsigned i;
968 u32 tmp;
969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
970
971 for (i = 0; i < adev->usec_timeout; i++) {
72518269 972 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
df70502e
KW		 973 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
974 SRBM_STATUS__MCC_BUSY_MASK |
975 SRBM_STATUS__MCD_BUSY_MASK |
976 SRBM_STATUS__VMC_BUSY_MASK);
977 if (!tmp)
978 return 0;
979 udelay(1);
980 }
981 return -ETIMEDOUT;
982
983}
984
985static int gmc_v6_0_soft_reset(void *handle)
986{
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
988 struct amdgpu_mode_mc_save save;
989 u32 srbm_soft_reset = 0;
72518269 990 u32 tmp = RREG32(mmSRBM_STATUS);
df70502e
KW		 991
992 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
993 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
72518269 994 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
df70502e
KW		 995
996 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
997 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
998 if (!(adev->flags & AMD_IS_APU))
999 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
72518269 1000 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
df70502e
KW		 1001 }
1002
1003 if (srbm_soft_reset) {
1004 gmc_v6_0_mc_stop(adev, &save);
1005 if (gmc_v6_0_wait_for_idle(adev)) {
1006 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1007 }
1008
1009
72518269 1010 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 1011 tmp |= srbm_soft_reset;
1012 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
72518269
TSD		 1013 WREG32(mmSRBM_SOFT_RESET, tmp);
1014 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 1015
1016 udelay(50);
1017
1018 tmp &= ~srbm_soft_reset;
72518269
TSD		 1019 WREG32(mmSRBM_SOFT_RESET, tmp);
1020 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 1021
1022 udelay(50);
1023
1024 gmc_v6_0_mc_resume(adev, &save);
1025 udelay(50);
1026 }
1027
1028 return 0;
1029}
1030
1031static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1032 struct amdgpu_irq_src *src,
1033 unsigned type,
1034 enum amdgpu_interrupt_state state)
1035{
1036 u32 tmp;
1037 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1038 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1039 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1040 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1041 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1042 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1043
1044 switch (state) {
1045 case AMDGPU_IRQ_STATE_DISABLE:
72518269 1046 tmp = RREG32(mmVM_CONTEXT0_CNTL);
df70502e 1047 tmp &= ~bits;
72518269
TSD		 1048 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1049 tmp = RREG32(mmVM_CONTEXT1_CNTL);
df70502e 1050 tmp &= ~bits;
72518269 1051 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 1052 break;
1053 case AMDGPU_IRQ_STATE_ENABLE:
72518269 1054 tmp = RREG32(mmVM_CONTEXT0_CNTL);
df70502e 1055 tmp |= bits;
72518269
TSD		 1056 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1057 tmp = RREG32(mmVM_CONTEXT1_CNTL);
df70502e 1058 tmp |= bits;
72518269 1059 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 1060 break;
1061 default:
1062 break;
1063 }
1064
1065 return 0;
1066}
1067
1068static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1069 struct amdgpu_irq_src *source,
1070 struct amdgpu_iv_entry *entry)
1071{
1072 u32 addr, status;
1073
72518269
TSD		 1074 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1075 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1076 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
df70502e
KW		 1077
1078 if (!addr && !status)
1079 return 0;
1080
1081 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1082 gmc_v6_0_set_fault_enable_default(adev, false);
1083
01615881
EC		 1084 if (printk_ratelimit()) {
1085 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
7ccf5aa8 1086 entry->src_id, entry->src_data[0]);
01615881
EC		 1087 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1088 addr);
1089 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1090 status);
1091 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1092 }
df70502e
KW		 1093
1094 return 0;
1095}
1096
1097static int gmc_v6_0_set_clockgating_state(void *handle,
1098 enum amd_clockgating_state state)
1099{
1100 return 0;
1101}
1102
1103static int gmc_v6_0_set_powergating_state(void *handle,
1104 enum amd_powergating_state state)
1105{
1106 return 0;
1107}
1108
a1255107 1109static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
df70502e
KW		 1110 .name = "gmc_v6_0",
1111 .early_init = gmc_v6_0_early_init,
1112 .late_init = gmc_v6_0_late_init,
1113 .sw_init = gmc_v6_0_sw_init,
1114 .sw_fini = gmc_v6_0_sw_fini,
1115 .hw_init = gmc_v6_0_hw_init,
1116 .hw_fini = gmc_v6_0_hw_fini,
1117 .suspend = gmc_v6_0_suspend,
1118 .resume = gmc_v6_0_resume,
1119 .is_idle = gmc_v6_0_is_idle,
1120 .wait_for_idle = gmc_v6_0_wait_for_idle,
1121 .soft_reset = gmc_v6_0_soft_reset,
1122 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1123 .set_powergating_state = gmc_v6_0_set_powergating_state,
1124};
1125
1126static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1127 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1128 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
f7c35abe 1129 .set_prt = gmc_v6_0_set_prt,
5463545b 1130 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
df70502e
KW		 1131};
1132
1133static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1134 .set = gmc_v6_0_vm_fault_interrupt_state,
1135 .process = gmc_v6_0_process_interrupt,
1136};
1137
1138static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1139{
1140 if (adev->gart.gart_funcs == NULL)
1141 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1142}
1143
1144static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1145{
1146 adev->mc.vm_fault.num_types = 1;
1147 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1148}
1149
a1255107
AD		 1150const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1151{
1152 .type = AMD_IP_BLOCK_TYPE_GMC,
1153 .major = 6,
1154 .minor = 0,
1155 .rev = 0,
1156 .funcs = &gmc_v6_0_ip_funcs,
1157};
Linux 6.x block layer and io_uring tree(s)