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drm/amd/amdgpu: Port GMC v6 driver to new SI headers (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gmc_v6_0.c
CommitLineData
df70502e
KW		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v6_0.h"
27#include "amdgpu_ucode.h"
72518269
TSD		 28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
df70502e
KW		 38
39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static int gmc_v6_0_wait_for_idle(void *handle);
42
43MODULE_FIRMWARE("radeon/tahiti_mc.bin");
44MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
45MODULE_FIRMWARE("radeon/verde_mc.bin");
46MODULE_FIRMWARE("radeon/oland_mc.bin");
47
72518269
TSD		 48#define MC_SEQ_MISC0__MT__MASK 0xf0000000
49#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
50#define MC_SEQ_MISC0__MT__DDR2 0x20000000
51#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
52#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
53#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
54#define MC_SEQ_MISC0__MT__HBM 0x60000000
55#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
56
57
df70502e
KW		 58static const u32 crtc_offsets[6] =
59{
60 SI_CRTC0_REGISTER_OFFSET,
61 SI_CRTC1_REGISTER_OFFSET,
62 SI_CRTC2_REGISTER_OFFSET,
63 SI_CRTC3_REGISTER_OFFSET,
64 SI_CRTC4_REGISTER_OFFSET,
65 SI_CRTC5_REGISTER_OFFSET
66};
67
68static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
69 struct amdgpu_mode_mc_save *save)
70{
71 u32 blackout;
72
73 if (adev->mode_info.num_crtc)
74 amdgpu_display_stop_mc_access(adev, save);
75
76 gmc_v6_0_wait_for_idle((void *)adev);
77
72518269
TSD		 78 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
79 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
df70502e 80 /* Block CPU access */
72518269 81 WREG32(mmBIF_FB_EN, 0);
df70502e
KW		 82 /* blackout the MC */
83 blackout = REG_SET_FIELD(blackout,
72518269
TSD		 84 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
85 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
df70502e
KW		 86 }
87 /* wait for the MC to settle */
88 udelay(100);
89
90}
91
92static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
93 struct amdgpu_mode_mc_save *save)
94{
95 u32 tmp;
96
97 /* unblackout the MC */
72518269
TSD		 98 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
99 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
100 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
df70502e 101 /* allow CPU access */
72518269
TSD		 102 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
103 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
104 WREG32(mmBIF_FB_EN, tmp);
df70502e
KW		 105
106 if (adev->mode_info.num_crtc)
107 amdgpu_display_resume_mc_access(adev, save);
108
109}
110
111static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
112{
113 const char *chip_name;
114 char fw_name[30];
115 int err;
116
117 DRM_DEBUG("\n");
118
119 switch (adev->asic_type) {
120 case CHIP_TAHITI:
121 chip_name = "tahiti";
122 break;
123 case CHIP_PITCAIRN:
124 chip_name = "pitcairn";
125 break;
126 case CHIP_VERDE:
127 chip_name = "verde";
128 break;
129 case CHIP_OLAND:
130 chip_name = "oland";
131 break;
132 case CHIP_HAINAN:
133 chip_name = "hainan";
134 break;
135 default: BUG();
136 }
137
138 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
139 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
140 if (err)
141 goto out;
142
143 err = amdgpu_ucode_validate(adev->mc.fw);
144
145out:
146 if (err) {
075719c3 147 dev_err(adev->dev,
df70502e
KW		 148 "si_mc: Failed to load firmware \"%s\"\n",
149 fw_name);
150 release_firmware(adev->mc.fw);
151 adev->mc.fw = NULL;
152 }
153 return err;
154}
155
156static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
157{
158 const __le32 *new_fw_data = NULL;
159 u32 running;
160 const __le32 *new_io_mc_regs = NULL;
161 int i, regs_size, ucode_size;
162 const struct mc_firmware_header_v1_0 *hdr;
163
164 if (!adev->mc.fw)
165 return -EINVAL;
166
167 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
168
169 amdgpu_ucode_print_mc_hdr(&hdr->header);
170
171 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
172 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
173 new_io_mc_regs = (const __le32 *)
174 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
175 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
176 new_fw_data = (const __le32 *)
177 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
178
72518269 179 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
df70502e
KW		 180
181 if (running == 0) {
182
183 /* reset the engine and set to writable */
72518269
TSD		 184 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
df70502e
KW		 186
187 /* load mc io regs */
188 for (i = 0; i < regs_size; i++) {
72518269
TSD		 189 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
190 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
df70502e
KW		 191 }
192 /* load the MC ucode */
193 for (i = 0; i < ucode_size; i++) {
72518269 194 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
df70502e
KW		 195 }
196
197 /* put the engine back into the active state */
72518269
TSD		 198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
df70502e
KW		 201
202 /* wait for training to complete */
203 for (i = 0; i < adev->usec_timeout; i++) {
72518269 204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
df70502e
KW		 205 break;
206 udelay(1);
207 }
208 for (i = 0; i < adev->usec_timeout; i++) {
72518269 209 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
df70502e
KW		 210 break;
211 udelay(1);
212 }
213
214 }
215
216 return 0;
217}
218
219static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
220 struct amdgpu_mc *mc)
221{
222 if (mc->mc_vram_size > 0xFFC0000000ULL) {
223 dev_warn(adev->dev, "limiting VRAM\n");
224 mc->real_vram_size = 0xFFC0000000ULL;
225 mc->mc_vram_size = 0xFFC0000000ULL;
226 }
227 amdgpu_vram_location(adev, &adev->mc, 0);
228 adev->mc.gtt_base_align = 0;
229 amdgpu_gtt_location(adev, mc);
230}
231
232static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
233{
234 struct amdgpu_mode_mc_save save;
235 u32 tmp;
236 int i, j;
237
238 /* Initialize HDP */
239 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
240 WREG32((0xb05 + j), 0x00000000);
241 WREG32((0xb06 + j), 0x00000000);
242 WREG32((0xb07 + j), 0x00000000);
243 WREG32((0xb08 + j), 0x00000000);
244 WREG32((0xb09 + j), 0x00000000);
245 }
72518269 246 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
df70502e
KW		 247
248 gmc_v6_0_mc_stop(adev, &save);
249
250 if (gmc_v6_0_wait_for_idle((void *)adev)) {
251 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
252 }
253
72518269 254 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
df70502e 255 /* Update configuration */
72518269 256 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
df70502e 257 adev->mc.vram_start >> 12);
72518269 258 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
df70502e 259 adev->mc.vram_end >> 12);
72518269 260 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
df70502e
KW		 261 adev->vram_scratch.gpu_addr >> 12);
262 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
263 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
72518269 264 WREG32(mmMC_VM_FB_LOCATION, tmp);
df70502e 265 /* XXX double check these! */
72518269
TSD		 266 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
267 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
268 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
269 WREG32(mmMC_VM_AGP_BASE, 0);
270 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
271 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
df70502e
KW		 272
273 if (gmc_v6_0_wait_for_idle((void *)adev)) {
274 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
275 }
276 gmc_v6_0_mc_resume(adev, &save);
277 amdgpu_display_set_vga_render_state(adev, false);
278}
279
280static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
281{
282
283 u32 tmp;
284 int chansize, numchan;
285
72518269
TSD		 286 tmp = RREG32(mmMC_ARB_RAMCFG);
287 if (tmp & (1 << 11)) {
df70502e 288 chansize = 16;
72518269 289 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
df70502e
KW		 290 chansize = 64;
291 } else {
292 chansize = 32;
293 }
72518269
TSD		 294 tmp = RREG32(mmMC_SHARED_CHMAP);
295 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
df70502e
KW		 296 case 0:
297 default:
298 numchan = 1;
299 break;
300 case 1:
301 numchan = 2;
302 break;
303 case 2:
304 numchan = 4;
305 break;
306 case 3:
307 numchan = 8;
308 break;
309 case 4:
310 numchan = 3;
311 break;
312 case 5:
313 numchan = 6;
314 break;
315 case 6:
316 numchan = 10;
317 break;
318 case 7:
319 numchan = 12;
320 break;
321 case 8:
322 numchan = 16;
323 break;
324 }
325 adev->mc.vram_width = numchan * chansize;
326 /* Could aper size report 0 ? */
327 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
328 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
329 /* size in MB on si */
72518269
TSD		 330 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
331 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
df70502e
KW		 332 adev->mc.visible_vram_size = adev->mc.aper_size;
333
334 /* unless the user had overridden it, set the gart
335 * size equal to the 1024 or vram, whichever is larger.
336 */
337 if (amdgpu_gart_size == -1)
338 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
339 else
340 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
341
342 gmc_v6_0_vram_gtt_location(adev, &adev->mc);
343
344 return 0;
345}
346
347static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
348 uint32_t vmid)
349{
72518269 350 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
df70502e 351
72518269 352 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
df70502e
KW		 353}
354
355static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
356 void *cpu_pt_addr,
357 uint32_t gpu_page_idx,
358 uint64_t addr,
359 uint32_t flags)
360{
361 void __iomem *ptr = (void *)cpu_pt_addr;
362 uint64_t value;
363
364 value = addr & 0xFFFFFFFFFFFFF000ULL;
365 value |= flags;
366 writeq(value, ptr + (gpu_page_idx * 8));
367
368 return 0;
369}
370
371static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
372 bool value)
373{
374 u32 tmp;
375
72518269
TSD		 376 tmp = RREG32(mmVM_CONTEXT1_CNTL);
377 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
378 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
379 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
380 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
381 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
382 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
383 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
384 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
385 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
386 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
387 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
388 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
389 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 390}
391
392static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
393{
394 int r, i;
395
396 if (adev->gart.robj == NULL) {
397 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
398 return -EINVAL;
399 }
400 r = amdgpu_gart_table_vram_pin(adev);
401 if (r)
402 return r;
403 /* Setup TLB control */
72518269 404 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
df70502e 405 (0xA << 7) |
72518269
TSD		 406 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
407 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
408 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
409 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
410 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
df70502e 411 /* Setup L2 cache */
72518269
TSD		 412 WREG32(mmVM_L2_CNTL,
413 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
414 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
415 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
416 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
417 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
418 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
419 WREG32(mmVM_L2_CNTL2,
420 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
421 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
422 WREG32(mmVM_L2_CNTL3,
423 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
424 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
425 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
df70502e 426 /* setup context0 */
72518269
TSD		 427 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
428 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
429 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
430 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
df70502e 431 (u32)(adev->dummy_page.addr >> 12));
72518269
TSD		 432 WREG32(mmVM_CONTEXT0_CNTL2, 0);
433 WREG32(mmVM_CONTEXT0_CNTL,
434 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
435 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
436 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
df70502e
KW		 437
438 WREG32(0x575, 0);
439 WREG32(0x576, 0);
440 WREG32(0x577, 0);
441
442 /* empty context1-15 */
443 /* set vm size, must be a multiple of 4 */
72518269
TSD		 444 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
445 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
df70502e
KW		 446 /* Assign the pt base to something valid for now; the pts used for
447 * the VMs are determined by the application and setup and assigned
448 * on the fly in the vm part of radeon_gart.c
449 */
450 for (i = 1; i < 16; i++) {
451 if (i < 8)
72518269 452 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
df70502e
KW		 453 adev->gart.table_addr >> 12);
454 else
72518269 455 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
df70502e
KW		 456 adev->gart.table_addr >> 12);
457 }
458
459 /* enable context1-15 */
72518269 460 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
df70502e 461 (u32)(adev->dummy_page.addr >> 12));
72518269
TSD		 462 WREG32(mmVM_CONTEXT1_CNTL2, 4);
463 WREG32(mmVM_CONTEXT1_CNTL,
464 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
465 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
466 ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) |
467 VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
468 VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
469 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
470 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
471 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
472 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
473 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
476 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
477 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
df70502e
KW		 479
480 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
075719c3 481 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
df70502e
KW		 482 (unsigned)(adev->mc.gtt_size >> 20),
483 (unsigned long long)adev->gart.table_addr);
484 adev->gart.ready = true;
485 return 0;
486}
487
488static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
489{
490 int r;
491
492 if (adev->gart.robj) {
075719c3 493 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
df70502e
KW		 494 return 0;
495 }
496 r = amdgpu_gart_init(adev);
497 if (r)
498 return r;
499 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
500 return amdgpu_gart_table_vram_alloc(adev);
501}
502
503static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
504{
505 /*unsigned i;
506
507 for (i = 1; i < 16; ++i) {
508 uint32_t reg;
509 if (i < 8)
510 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
511 else
512 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
513 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
514 }*/
515
516 /* Disable all tables */
72518269
TSD		 517 WREG32(mmVM_CONTEXT0_CNTL, 0);
518 WREG32(mmVM_CONTEXT1_CNTL, 0);
df70502e 519 /* Setup TLB control */
72518269
TSD		 520 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
521 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
522 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
df70502e 523 /* Setup L2 cache */
72518269
TSD		 524 WREG32(mmVM_L2_CNTL,
525 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
526 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
527 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
528 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
529 WREG32(mmVM_L2_CNTL2, 0);
530 WREG32(mmVM_L2_CNTL3,
531 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
532 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
df70502e
KW		 533 amdgpu_gart_table_vram_unpin(adev);
534}
535
536static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
537{
538 amdgpu_gart_table_vram_free(adev);
539 amdgpu_gart_fini(adev);
540}
541
542static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
543{
544 /*
545 * number of VMs
546 * VMID 0 is reserved for System
547 * amdgpu graphics/compute will use VMIDs 1-7
548 * amdkfd will use VMIDs 8-15
549 */
550 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
551 amdgpu_vm_manager_init(adev);
552
553 /* base offset of vram pages */
554 if (adev->flags & AMD_IS_APU) {
72518269 555 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
df70502e
KW		 556 tmp <<= 22;
557 adev->vm_manager.vram_base_offset = tmp;
558 } else
559 adev->vm_manager.vram_base_offset = 0;
560
561 return 0;
562}
563
564static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
565{
566}
567
568static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
569 u32 status, u32 addr, u32 mc_client)
570{
571 u32 mc_id;
72518269
TSD		 572 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
573 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
574 PROTECTIONS);
df70502e
KW		 575 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
576 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
577
72518269
TSD		 578 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
579 MEMORY_CLIENT_ID);
df70502e 580
075719c3 581 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
df70502e 582 protections, vmid, addr,
72518269
TSD		 583 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
584 MEMORY_CLIENT_RW) ?
df70502e
KW		 585 "write" : "read", block, mc_client, mc_id);
586}
587
588/*
589static const u32 mc_cg_registers[] = {
590 MC_HUB_MISC_HUB_CG,
591 MC_HUB_MISC_SIP_CG,
592 MC_HUB_MISC_VM_CG,
593 MC_XPB_CLK_GAT,
594 ATC_MISC_CG,
595 MC_CITF_MISC_WR_CG,
596 MC_CITF_MISC_RD_CG,
597 MC_CITF_MISC_VM_CG,
598 VM_L2_CG,
599};
600
601static const u32 mc_cg_ls_en[] = {
602 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
603 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
604 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
605 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
606 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
607 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
608 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
609 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
610 VM_L2_CG__MEM_LS_ENABLE_MASK,
611};
612
613static const u32 mc_cg_en[] = {
614 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
615 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
616 MC_HUB_MISC_VM_CG__ENABLE_MASK,
617 MC_XPB_CLK_GAT__ENABLE_MASK,
618 ATC_MISC_CG__ENABLE_MASK,
619 MC_CITF_MISC_WR_CG__ENABLE_MASK,
620 MC_CITF_MISC_RD_CG__ENABLE_MASK,
621 MC_CITF_MISC_VM_CG__ENABLE_MASK,
622 VM_L2_CG__ENABLE_MASK,
623};
624
625static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
626 bool enable)
627{
628 int i;
629 u32 orig, data;
630
631 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
632 orig = data = RREG32(mc_cg_registers[i]);
633 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
634 data |= mc_cg_ls_en[i];
635 else
636 data &= ~mc_cg_ls_en[i];
637 if (data != orig)
638 WREG32(mc_cg_registers[i], data);
639 }
640}
641
642static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
643 bool enable)
644{
645 int i;
646 u32 orig, data;
647
648 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
649 orig = data = RREG32(mc_cg_registers[i]);
650 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
651 data |= mc_cg_en[i];
652 else
653 data &= ~mc_cg_en[i];
654 if (data != orig)
655 WREG32(mc_cg_registers[i], data);
656 }
657}
658
659static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
660 bool enable)
661{
662 u32 orig, data;
663
664 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
665
666 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
667 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
668 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
669 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
670 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
671 } else {
672 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
673 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
674 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
675 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
676 }
677
678 if (orig != data)
679 WREG32_PCIE(ixPCIE_CNTL2, data);
680}
681
682static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
683 bool enable)
684{
685 u32 orig, data;
686
72518269 687 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
df70502e
KW		 688
689 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
690 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
691 else
692 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
693
694 if (orig != data)
72518269 695 WREG32(mmHDP_HOST_PATH_CNTL, data);
df70502e
KW		 696}
697
698static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
699 bool enable)
700{
701 u32 orig, data;
702
72518269 703 orig = data = RREG32(mmHDP_MEM_POWER_LS);
df70502e
KW		 704
705 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
706 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
707 else
708 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
709
710 if (orig != data)
72518269 711 WREG32(mmHDP_MEM_POWER_LS, data);
df70502e
KW		 712}
713*/
714
715static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
716{
717 switch (mc_seq_vram_type) {
718 case MC_SEQ_MISC0__MT__GDDR1:
719 return AMDGPU_VRAM_TYPE_GDDR1;
720 case MC_SEQ_MISC0__MT__DDR2:
721 return AMDGPU_VRAM_TYPE_DDR2;
722 case MC_SEQ_MISC0__MT__GDDR3:
723 return AMDGPU_VRAM_TYPE_GDDR3;
724 case MC_SEQ_MISC0__MT__GDDR4:
725 return AMDGPU_VRAM_TYPE_GDDR4;
726 case MC_SEQ_MISC0__MT__GDDR5:
727 return AMDGPU_VRAM_TYPE_GDDR5;
728 case MC_SEQ_MISC0__MT__DDR3:
729 return AMDGPU_VRAM_TYPE_DDR3;
730 default:
731 return AMDGPU_VRAM_TYPE_UNKNOWN;
732 }
733}
734
735static int gmc_v6_0_early_init(void *handle)
736{
737 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
738
739 gmc_v6_0_set_gart_funcs(adev);
740 gmc_v6_0_set_irq_funcs(adev);
741
742 if (adev->flags & AMD_IS_APU) {
743 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
744 } else {
72518269 745 u32 tmp = RREG32(mmMC_SEQ_MISC0);
df70502e
KW		 746 tmp &= MC_SEQ_MISC0__MT__MASK;
747 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
748 }
749
750 return 0;
751}
752
753static int gmc_v6_0_late_init(void *handle)
754{
755 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
756
757 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
758}
759
760static int gmc_v6_0_sw_init(void *handle)
761{
762 int r;
763 int dma_bits;
764 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
765
766 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
767 if (r)
768 return r;
769
770 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
771 if (r)
772 return r;
773
774 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
775
776 adev->mc.mc_mask = 0xffffffffffULL;
777
778 adev->need_dma32 = false;
779 dma_bits = adev->need_dma32 ? 32 : 40;
780 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
781 if (r) {
782 adev->need_dma32 = true;
783 dma_bits = 32;
075719c3 784 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
df70502e
KW		 785 }
786 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
787 if (r) {
788 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
075719c3 789 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
df70502e
KW		 790 }
791
792 r = gmc_v6_0_init_microcode(adev);
793 if (r) {
075719c3 794 dev_err(adev->dev, "Failed to load mc firmware!\n");
df70502e
KW		 795 return r;
796 }
797
798 r = amdgpu_ttm_global_init(adev);
799 if (r) {
800 return r;
801 }
802
803 r = gmc_v6_0_mc_init(adev);
804 if (r)
805 return r;
806
807 r = amdgpu_bo_init(adev);
808 if (r)
809 return r;
810
811 r = gmc_v6_0_gart_init(adev);
812 if (r)
813 return r;
814
815 if (!adev->vm_manager.enabled) {
816 r = gmc_v6_0_vm_init(adev);
817 if (r) {
818 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
819 return r;
820 }
821 adev->vm_manager.enabled = true;
822 }
823
824 return r;
825}
826
827static int gmc_v6_0_sw_fini(void *handle)
828{
829 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
830
831 if (adev->vm_manager.enabled) {
832 gmc_v6_0_vm_fini(adev);
833 adev->vm_manager.enabled = false;
834 }
835 gmc_v6_0_gart_fini(adev);
836 amdgpu_gem_force_release(adev);
837 amdgpu_bo_fini(adev);
838
839 return 0;
840}
841
842static int gmc_v6_0_hw_init(void *handle)
843{
844 int r;
845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
846
847 gmc_v6_0_mc_program(adev);
848
849 if (!(adev->flags & AMD_IS_APU)) {
850 r = gmc_v6_0_mc_load_microcode(adev);
851 if (r) {
075719c3 852 dev_err(adev->dev, "Failed to load MC firmware!\n");
df70502e
KW		 853 return r;
854 }
855 }
856
857 r = gmc_v6_0_gart_enable(adev);
858 if (r)
859 return r;
860
861 return r;
862}
863
864static int gmc_v6_0_hw_fini(void *handle)
865{
866 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
867
868 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
869 gmc_v6_0_gart_disable(adev);
870
871 return 0;
872}
873
874static int gmc_v6_0_suspend(void *handle)
875{
876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
877
878 if (adev->vm_manager.enabled) {
879 gmc_v6_0_vm_fini(adev);
880 adev->vm_manager.enabled = false;
881 }
882 gmc_v6_0_hw_fini(adev);
883
884 return 0;
885}
886
887static int gmc_v6_0_resume(void *handle)
888{
889 int r;
890 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
891
892 r = gmc_v6_0_hw_init(adev);
893 if (r)
894 return r;
895
896 if (!adev->vm_manager.enabled) {
897 r = gmc_v6_0_vm_init(adev);
898 if (r) {
899 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
900 return r;
901 }
902 adev->vm_manager.enabled = true;
903 }
904
905 return r;
906}
907
908static bool gmc_v6_0_is_idle(void *handle)
909{
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
72518269 911 u32 tmp = RREG32(mmSRBM_STATUS);
df70502e
KW		 912
913 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
914 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
915 return false;
916
917 return true;
918}
919
920static int gmc_v6_0_wait_for_idle(void *handle)
921{
922 unsigned i;
923 u32 tmp;
924 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
925
926 for (i = 0; i < adev->usec_timeout; i++) {
72518269 927 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
df70502e
KW		 928 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
929 SRBM_STATUS__MCC_BUSY_MASK |
930 SRBM_STATUS__MCD_BUSY_MASK |
931 SRBM_STATUS__VMC_BUSY_MASK);
932 if (!tmp)
933 return 0;
934 udelay(1);
935 }
936 return -ETIMEDOUT;
937
938}
939
940static int gmc_v6_0_soft_reset(void *handle)
941{
942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
943 struct amdgpu_mode_mc_save save;
944 u32 srbm_soft_reset = 0;
72518269 945 u32 tmp = RREG32(mmSRBM_STATUS);
df70502e
KW		 946
947 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
948 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
72518269 949 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
df70502e
KW		 950
951 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
952 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
953 if (!(adev->flags & AMD_IS_APU))
954 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
72518269 955 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
df70502e
KW		 956 }
957
958 if (srbm_soft_reset) {
959 gmc_v6_0_mc_stop(adev, &save);
960 if (gmc_v6_0_wait_for_idle(adev)) {
961 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
962 }
963
964
72518269 965 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 966 tmp |= srbm_soft_reset;
967 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
72518269
TSD		 968 WREG32(mmSRBM_SOFT_RESET, tmp);
969 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 970
971 udelay(50);
972
973 tmp &= ~srbm_soft_reset;
72518269
TSD		 974 WREG32(mmSRBM_SOFT_RESET, tmp);
975 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 976
977 udelay(50);
978
979 gmc_v6_0_mc_resume(adev, &save);
980 udelay(50);
981 }
982
983 return 0;
984}
985
986static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
987 struct amdgpu_irq_src *src,
988 unsigned type,
989 enum amdgpu_interrupt_state state)
990{
991 u32 tmp;
992 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
993 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
994 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
995 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
996 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
997 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
998
999 switch (state) {
1000 case AMDGPU_IRQ_STATE_DISABLE:
72518269 1001 tmp = RREG32(mmVM_CONTEXT0_CNTL);
df70502e 1002 tmp &= ~bits;
72518269
TSD		 1003 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1004 tmp = RREG32(mmVM_CONTEXT1_CNTL);
df70502e 1005 tmp &= ~bits;
72518269 1006 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 1007 break;
1008 case AMDGPU_IRQ_STATE_ENABLE:
72518269 1009 tmp = RREG32(mmVM_CONTEXT0_CNTL);
df70502e 1010 tmp |= bits;
72518269
TSD		 1011 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1012 tmp = RREG32(mmVM_CONTEXT1_CNTL);
df70502e 1013 tmp |= bits;
72518269 1014 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 1015 break;
1016 default:
1017 break;
1018 }
1019
1020 return 0;
1021}
1022
1023static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1024 struct amdgpu_irq_src *source,
1025 struct amdgpu_iv_entry *entry)
1026{
1027 u32 addr, status;
1028
72518269
TSD		 1029 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1030 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1031 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
df70502e
KW		 1032
1033 if (!addr && !status)
1034 return 0;
1035
1036 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1037 gmc_v6_0_set_fault_enable_default(adev, false);
1038
1039 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1040 entry->src_id, entry->src_data);
1041 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1042 addr);
1043 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1044 status);
1045 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1046
1047 return 0;
1048}
1049
1050static int gmc_v6_0_set_clockgating_state(void *handle,
1051 enum amd_clockgating_state state)
1052{
1053 return 0;
1054}
1055
1056static int gmc_v6_0_set_powergating_state(void *handle,
1057 enum amd_powergating_state state)
1058{
1059 return 0;
1060}
1061
a1255107 1062static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
df70502e
KW		 1063 .name = "gmc_v6_0",
1064 .early_init = gmc_v6_0_early_init,
1065 .late_init = gmc_v6_0_late_init,
1066 .sw_init = gmc_v6_0_sw_init,
1067 .sw_fini = gmc_v6_0_sw_fini,
1068 .hw_init = gmc_v6_0_hw_init,
1069 .hw_fini = gmc_v6_0_hw_fini,
1070 .suspend = gmc_v6_0_suspend,
1071 .resume = gmc_v6_0_resume,
1072 .is_idle = gmc_v6_0_is_idle,
1073 .wait_for_idle = gmc_v6_0_wait_for_idle,
1074 .soft_reset = gmc_v6_0_soft_reset,
1075 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1076 .set_powergating_state = gmc_v6_0_set_powergating_state,
1077};
1078
1079static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1080 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1081 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1082};
1083
1084static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1085 .set = gmc_v6_0_vm_fault_interrupt_state,
1086 .process = gmc_v6_0_process_interrupt,
1087};
1088
1089static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1090{
1091 if (adev->gart.gart_funcs == NULL)
1092 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1093}
1094
1095static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1096{
1097 adev->mc.vm_fault.num_types = 1;
1098 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1099}
1100
a1255107
AD		 1101const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1102{
1103 .type = AMD_IP_BLOCK_TYPE_GMC,
1104 .major = 6,
1105 .minor = 0,
1106 .rev = 0,
1107 .funcs = &gmc_v6_0_ip_funcs,
1108};
Linux 6.x block layer and io_uring tree(s)