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drm/amdgpu: refine SR-IOV firmware VRAM reservation to protect data
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gmc_v6_0.c
CommitLineData
df70502e
KW		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
248a1d6f 24#include <drm/drmP.h>
df70502e
KW		 25#include "amdgpu.h"
26#include "gmc_v6_0.h"
27#include "amdgpu_ucode.h"
72518269
TSD		 28
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gmc/gmc_6_0_d.h"
34#include "gmc/gmc_6_0_sh_mask.h"
35#include "dce/dce_6_0_d.h"
36#include "dce/dce_6_0_sh_mask.h"
37#include "si_enums.h"
df70502e
KW		 38
39static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
40static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
41static int gmc_v6_0_wait_for_idle(void *handle);
42
43MODULE_FIRMWARE("radeon/tahiti_mc.bin");
44MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
45MODULE_FIRMWARE("radeon/verde_mc.bin");
46MODULE_FIRMWARE("radeon/oland_mc.bin");
f1d877be 47MODULE_FIRMWARE("radeon/si58_mc.bin");
df70502e 48
72518269
TSD		 49#define MC_SEQ_MISC0__MT__MASK 0xf0000000
50#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
51#define MC_SEQ_MISC0__MT__DDR2 0x20000000
52#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
53#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
54#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
55#define MC_SEQ_MISC0__MT__HBM 0x60000000
56#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
57
58
df70502e
KW		 59static const u32 crtc_offsets[6] =
60{
61 SI_CRTC0_REGISTER_OFFSET,
62 SI_CRTC1_REGISTER_OFFSET,
63 SI_CRTC2_REGISTER_OFFSET,
64 SI_CRTC3_REGISTER_OFFSET,
65 SI_CRTC4_REGISTER_OFFSET,
66 SI_CRTC5_REGISTER_OFFSET
67};
68
e4f6b39e 69static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
df70502e
KW		 70{
71 u32 blackout;
72
df70502e
KW		 73 gmc_v6_0_wait_for_idle((void *)adev);
74
72518269
TSD		 75 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
76 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
df70502e 77 /* Block CPU access */
72518269 78 WREG32(mmBIF_FB_EN, 0);
df70502e
KW		 79 /* blackout the MC */
80 blackout = REG_SET_FIELD(blackout,
72518269
TSD		 81 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
82 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
df70502e
KW		 83 }
84 /* wait for the MC to settle */
85 udelay(100);
86
87}
88
e4f6b39e 89static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
df70502e
KW		 90{
91 u32 tmp;
92
93 /* unblackout the MC */
72518269
TSD		 94 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
95 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
96 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
df70502e 97 /* allow CPU access */
72518269
TSD		 98 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
99 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
100 WREG32(mmBIF_FB_EN, tmp);
df70502e
KW		 101}
102
103static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
104{
105 const char *chip_name;
106 char fw_name[30];
107 int err;
f1d877be 108 bool is_58_fw = false;
df70502e
KW		 109
110 DRM_DEBUG("\n");
111
112 switch (adev->asic_type) {
113 case CHIP_TAHITI:
114 chip_name = "tahiti";
115 break;
116 case CHIP_PITCAIRN:
117 chip_name = "pitcairn";
118 break;
119 case CHIP_VERDE:
120 chip_name = "verde";
121 break;
122 case CHIP_OLAND:
123 chip_name = "oland";
124 break;
125 case CHIP_HAINAN:
126 chip_name = "hainan";
127 break;
128 default: BUG();
129 }
130
f1d877be
AD		 131 /* this memory configuration requires special firmware */
132 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
133 is_58_fw = true;
134
135 if (is_58_fw)
136 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
137 else
138 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
df70502e
KW		 139 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
140 if (err)
141 goto out;
142
143 err = amdgpu_ucode_validate(adev->mc.fw);
144
145out:
146 if (err) {
075719c3 147 dev_err(adev->dev,
df70502e
KW		 148 "si_mc: Failed to load firmware \"%s\"\n",
149 fw_name);
150 release_firmware(adev->mc.fw);
151 adev->mc.fw = NULL;
152 }
153 return err;
154}
155
156static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
157{
158 const __le32 *new_fw_data = NULL;
159 u32 running;
160 const __le32 *new_io_mc_regs = NULL;
161 int i, regs_size, ucode_size;
162 const struct mc_firmware_header_v1_0 *hdr;
163
164 if (!adev->mc.fw)
165 return -EINVAL;
166
167 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
168
169 amdgpu_ucode_print_mc_hdr(&hdr->header);
170
171 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
172 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
173 new_io_mc_regs = (const __le32 *)
174 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
175 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
176 new_fw_data = (const __le32 *)
177 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
178
72518269 179 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
df70502e
KW		 180
181 if (running == 0) {
182
183 /* reset the engine and set to writable */
72518269
TSD		 184 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
df70502e
KW		 186
187 /* load mc io regs */
188 for (i = 0; i < regs_size; i++) {
72518269
TSD		 189 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
190 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
df70502e
KW		 191 }
192 /* load the MC ucode */
193 for (i = 0; i < ucode_size; i++) {
72518269 194 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
df70502e
KW		 195 }
196
197 /* put the engine back into the active state */
72518269
TSD		 198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
df70502e
KW		 201
202 /* wait for training to complete */
203 for (i = 0; i < adev->usec_timeout; i++) {
72518269 204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
df70502e
KW		 205 break;
206 udelay(1);
207 }
208 for (i = 0; i < adev->usec_timeout; i++) {
72518269 209 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
df70502e
KW		 210 break;
211 udelay(1);
212 }
213
214 }
215
216 return 0;
217}
218
219static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
220 struct amdgpu_mc *mc)
221{
ba3a5b83
AD		 222 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
223 base <<= 24;
224
df70502e
KW		 225 if (mc->mc_vram_size > 0xFFC0000000ULL) {
226 dev_warn(adev->dev, "limiting VRAM\n");
227 mc->real_vram_size = 0xFFC0000000ULL;
228 mc->mc_vram_size = 0xFFC0000000ULL;
229 }
ba3a5b83 230 amdgpu_vram_location(adev, &adev->mc, base);
6f02a696 231 amdgpu_gart_location(adev, mc);
df70502e
KW		 232}
233
234static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
235{
df70502e
KW		 236 int i, j;
237
238 /* Initialize HDP */
239 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
240 WREG32((0xb05 + j), 0x00000000);
241 WREG32((0xb06 + j), 0x00000000);
242 WREG32((0xb07 + j), 0x00000000);
243 WREG32((0xb08 + j), 0x00000000);
244 WREG32((0xb09 + j), 0x00000000);
245 }
72518269 246 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
df70502e 247
df70502e
KW		 248 if (gmc_v6_0_wait_for_idle((void *)adev)) {
249 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
250 }
251
03ba88cf
AD		 252 if (adev->mode_info.num_crtc) {
253 u32 tmp;
254
255 /* Lockout access through VGA aperture*/
256 tmp = RREG32(mmVGA_HDP_CONTROL);
257 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
258 WREG32(mmVGA_HDP_CONTROL, tmp);
259
260 /* disable VGA render */
261 tmp = RREG32(mmVGA_RENDER_CONTROL);
262 tmp &= ~VGA_VSTATUS_CNTL;
263 WREG32(mmVGA_RENDER_CONTROL, tmp);
264 }
df70502e 265 /* Update configuration */
72518269 266 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
df70502e 267 adev->mc.vram_start >> 12);
72518269 268 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
df70502e 269 adev->mc.vram_end >> 12);
72518269 270 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
df70502e 271 adev->vram_scratch.gpu_addr >> 12);
72518269
TSD		 272 WREG32(mmMC_VM_AGP_BASE, 0);
273 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
274 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
df70502e
KW		 275
276 if (gmc_v6_0_wait_for_idle((void *)adev)) {
277 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
278 }
df70502e
KW		 279}
280
281static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
282{
283
284 u32 tmp;
285 int chansize, numchan;
286
72518269
TSD		 287 tmp = RREG32(mmMC_ARB_RAMCFG);
288 if (tmp & (1 << 11)) {
df70502e 289 chansize = 16;
72518269 290 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
df70502e
KW		 291 chansize = 64;
292 } else {
293 chansize = 32;
294 }
72518269
TSD		 295 tmp = RREG32(mmMC_SHARED_CHMAP);
296 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
df70502e
KW		 297 case 0:
298 default:
299 numchan = 1;
300 break;
301 case 1:
302 numchan = 2;
303 break;
304 case 2:
305 numchan = 4;
306 break;
307 case 3:
308 numchan = 8;
309 break;
310 case 4:
311 numchan = 3;
312 break;
313 case 5:
314 numchan = 6;
315 break;
316 case 6:
317 numchan = 10;
318 break;
319 case 7:
320 numchan = 12;
321 break;
322 case 8:
323 numchan = 16;
324 break;
325 }
326 adev->mc.vram_width = numchan * chansize;
327 /* Could aper size report 0 ? */
328 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
329 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
330 /* size in MB on si */
72518269
TSD		 331 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
332 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
df70502e
KW		 333 adev->mc.visible_vram_size = adev->mc.aper_size;
334
c3db7b5a
AD		 335 /* set the gart size */
336 if (amdgpu_gart_size == -1) {
337 switch (adev->asic_type) {
338 case CHIP_HAINAN: /* no MM engines */
339 default:
340 adev->mc.gart_size = 256ULL << 20;
341 break;
342 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
343 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
344 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
345 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
346 adev->mc.gart_size = 1024ULL << 20;
347 break;
348 }
349 } else {
350 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
351 }
352
df70502e
KW		 353 gmc_v6_0_vram_gtt_location(adev, &adev->mc);
354
355 return 0;
356}
357
358static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
359 uint32_t vmid)
360{
72518269 361 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
df70502e 362
72518269 363 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
df70502e
KW		 364}
365
366static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
367 void *cpu_pt_addr,
368 uint32_t gpu_page_idx,
369 uint64_t addr,
6b777607 370 uint64_t flags)
df70502e
KW		 371{
372 void __iomem *ptr = (void *)cpu_pt_addr;
373 uint64_t value;
374
375 value = addr & 0xFFFFFFFFFFFFF000ULL;
376 value |= flags;
377 writeq(value, ptr + (gpu_page_idx * 8));
378
379 return 0;
380}
381
5463545b
AX		 382static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
383 uint32_t flags)
384{
385 uint64_t pte_flag = 0;
386
387 if (flags & AMDGPU_VM_PAGE_READABLE)
388 pte_flag |= AMDGPU_PTE_READABLE;
389 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
390 pte_flag |= AMDGPU_PTE_WRITEABLE;
391 if (flags & AMDGPU_VM_PAGE_PRT)
392 pte_flag |= AMDGPU_PTE_PRT;
393
394 return pte_flag;
395}
396
b1166325
CK		 397static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
398{
399 BUG_ON(addr & 0xFFFFFF0000000FFFULL);
400 return addr;
401}
402
df70502e
KW		 403static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
404 bool value)
405{
406 u32 tmp;
407
72518269
TSD		 408 tmp = RREG32(mmVM_CONTEXT1_CNTL);
409 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
410 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
411 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
412 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
413 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
414 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
415 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
416 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
417 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
418 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
419 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
420 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
421 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 422}
423
f7c35abe
CK		 424 /**
425 + * gmc_v8_0_set_prt - set PRT VM fault
426 + *
427 + * @adev: amdgpu_device pointer
428 + * @enable: enable/disable VM fault handling for PRT
429 +*/
430static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
431{
432 u32 tmp;
433
434 if (enable && !adev->mc.prt_warning) {
435 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
436 adev->mc.prt_warning = true;
437 }
438
439 tmp = RREG32(mmVM_PRT_CNTL);
440 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
441 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
442 enable);
443 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
444 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
445 enable);
446 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
447 L2_CACHE_STORE_INVALID_ENTRIES,
448 enable);
449 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
450 L1_TLB_STORE_INVALID_ENTRIES,
451 enable);
452 WREG32(mmVM_PRT_CNTL, tmp);
453
454 if (enable) {
455 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
456 uint32_t high = adev->vm_manager.max_pfn;
457
458 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
459 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
460 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
461 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
462 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
463 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
464 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
465 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
466 } else {
467 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
468 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
469 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
470 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
471 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
472 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
473 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
474 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
475 }
476}
477
df70502e
KW		 478static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
479{
480 int r, i;
e618d306 481 u32 field;
df70502e
KW		 482
483 if (adev->gart.robj == NULL) {
484 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
485 return -EINVAL;
486 }
487 r = amdgpu_gart_table_vram_pin(adev);
488 if (r)
489 return r;
490 /* Setup TLB control */
72518269 491 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
df70502e 492 (0xA << 7) |
72518269
TSD		 493 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
494 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
495 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
496 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
497 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
df70502e 498 /* Setup L2 cache */
72518269
TSD		 499 WREG32(mmVM_L2_CNTL,
500 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
501 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
502 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
503 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
504 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
505 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
506 WREG32(mmVM_L2_CNTL2,
507 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
508 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
e618d306
RH		 509
510 field = adev->vm_manager.fragment_size;
72518269
TSD		 511 WREG32(mmVM_L2_CNTL3,
512 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
e618d306
RH		 513 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
514 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
df70502e 515 /* setup context0 */
6f02a696
CK		 516 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
517 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
72518269
TSD		 518 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
519 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
df70502e 520 (u32)(adev->dummy_page.addr >> 12));
72518269
TSD		 521 WREG32(mmVM_CONTEXT0_CNTL2, 0);
522 WREG32(mmVM_CONTEXT0_CNTL,
523 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
524 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
525 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
df70502e
KW		 526
527 WREG32(0x575, 0);
528 WREG32(0x576, 0);
529 WREG32(0x577, 0);
530
531 /* empty context1-15 */
532 /* set vm size, must be a multiple of 4 */
72518269
TSD		 533 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
534 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
df70502e
KW		 535 /* Assign the pt base to something valid for now; the pts used for
536 * the VMs are determined by the application and setup and assigned
537 * on the fly in the vm part of radeon_gart.c
538 */
539 for (i = 1; i < 16; i++) {
540 if (i < 8)
72518269 541 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
df70502e
KW		 542 adev->gart.table_addr >> 12);
543 else
72518269 544 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
df70502e
KW		 545 adev->gart.table_addr >> 12);
546 }
547
548 /* enable context1-15 */
72518269 549 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
df70502e 550 (u32)(adev->dummy_page.addr >> 12));
72518269
TSD		 551 WREG32(mmVM_CONTEXT1_CNTL2, 4);
552 WREG32(mmVM_CONTEXT1_CNTL,
553 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
554 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
36b32a68
ZJ		 555 ((adev->vm_manager.block_size - 9)
556 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
a8447647
FC		 557 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
558 gmc_v6_0_set_fault_enable_default(adev, false);
559 else
560 gmc_v6_0_set_fault_enable_default(adev, true);
df70502e
KW		 561
562 gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
075719c3 563 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
6f02a696 564 (unsigned)(adev->mc.gart_size >> 20),
df70502e
KW		 565 (unsigned long long)adev->gart.table_addr);
566 adev->gart.ready = true;
567 return 0;
568}
569
570static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
571{
572 int r;
573
574 if (adev->gart.robj) {
075719c3 575 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
df70502e
KW		 576 return 0;
577 }
578 r = amdgpu_gart_init(adev);
579 if (r)
580 return r;
581 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
4b98e0c4 582 adev->gart.gart_pte_flags = 0;
df70502e
KW		 583 return amdgpu_gart_table_vram_alloc(adev);
584}
585
586static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
587{
588 /*unsigned i;
589
590 for (i = 1; i < 16; ++i) {
591 uint32_t reg;
592 if (i < 8)
593 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
594 else
595 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
596 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
597 }*/
598
599 /* Disable all tables */
72518269
TSD		 600 WREG32(mmVM_CONTEXT0_CNTL, 0);
601 WREG32(mmVM_CONTEXT1_CNTL, 0);
df70502e 602 /* Setup TLB control */
72518269
TSD		 603 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
604 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
605 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
df70502e 606 /* Setup L2 cache */
72518269
TSD		 607 WREG32(mmVM_L2_CNTL,
608 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
609 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
610 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
611 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
612 WREG32(mmVM_L2_CNTL2, 0);
613 WREG32(mmVM_L2_CNTL3,
614 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
615 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
df70502e
KW		 616 amdgpu_gart_table_vram_unpin(adev);
617}
618
619static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
620{
621 amdgpu_gart_table_vram_free(adev);
622 amdgpu_gart_fini(adev);
623}
624
df70502e
KW		 625static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
626 u32 status, u32 addr, u32 mc_client)
627{
628 u32 mc_id;
72518269
TSD		 629 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
630 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
631 PROTECTIONS);
df70502e
KW		 632 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
633 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
634
72518269
TSD		 635 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
636 MEMORY_CLIENT_ID);
df70502e 637
075719c3 638 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
df70502e 639 protections, vmid, addr,
72518269
TSD		 640 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
641 MEMORY_CLIENT_RW) ?
df70502e
KW		 642 "write" : "read", block, mc_client, mc_id);
643}
644
645/*
646static const u32 mc_cg_registers[] = {
647 MC_HUB_MISC_HUB_CG,
648 MC_HUB_MISC_SIP_CG,
649 MC_HUB_MISC_VM_CG,
650 MC_XPB_CLK_GAT,
651 ATC_MISC_CG,
652 MC_CITF_MISC_WR_CG,
653 MC_CITF_MISC_RD_CG,
654 MC_CITF_MISC_VM_CG,
655 VM_L2_CG,
656};
657
658static const u32 mc_cg_ls_en[] = {
659 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
660 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
661 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
662 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
663 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
664 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
665 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
666 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
667 VM_L2_CG__MEM_LS_ENABLE_MASK,
668};
669
670static const u32 mc_cg_en[] = {
671 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
672 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
673 MC_HUB_MISC_VM_CG__ENABLE_MASK,
674 MC_XPB_CLK_GAT__ENABLE_MASK,
675 ATC_MISC_CG__ENABLE_MASK,
676 MC_CITF_MISC_WR_CG__ENABLE_MASK,
677 MC_CITF_MISC_RD_CG__ENABLE_MASK,
678 MC_CITF_MISC_VM_CG__ENABLE_MASK,
679 VM_L2_CG__ENABLE_MASK,
680};
681
682static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
683 bool enable)
684{
685 int i;
686 u32 orig, data;
687
688 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
689 orig = data = RREG32(mc_cg_registers[i]);
690 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
691 data |= mc_cg_ls_en[i];
692 else
693 data &= ~mc_cg_ls_en[i];
694 if (data != orig)
695 WREG32(mc_cg_registers[i], data);
696 }
697}
698
699static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
700 bool enable)
701{
702 int i;
703 u32 orig, data;
704
705 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
706 orig = data = RREG32(mc_cg_registers[i]);
707 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
708 data |= mc_cg_en[i];
709 else
710 data &= ~mc_cg_en[i];
711 if (data != orig)
712 WREG32(mc_cg_registers[i], data);
713 }
714}
715
716static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
717 bool enable)
718{
719 u32 orig, data;
720
721 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
722
723 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
724 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
725 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
726 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
727 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
728 } else {
729 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
730 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
731 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
732 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
733 }
734
735 if (orig != data)
736 WREG32_PCIE(ixPCIE_CNTL2, data);
737}
738
739static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
740 bool enable)
741{
742 u32 orig, data;
743
72518269 744 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
df70502e
KW		 745
746 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
747 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
748 else
749 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
750
751 if (orig != data)
72518269 752 WREG32(mmHDP_HOST_PATH_CNTL, data);
df70502e
KW		 753}
754
755static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
756 bool enable)
757{
758 u32 orig, data;
759
72518269 760 orig = data = RREG32(mmHDP_MEM_POWER_LS);
df70502e
KW		 761
762 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
763 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
764 else
765 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
766
767 if (orig != data)
72518269 768 WREG32(mmHDP_MEM_POWER_LS, data);
df70502e
KW		 769}
770*/
771
772static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
773{
774 switch (mc_seq_vram_type) {
775 case MC_SEQ_MISC0__MT__GDDR1:
776 return AMDGPU_VRAM_TYPE_GDDR1;
777 case MC_SEQ_MISC0__MT__DDR2:
778 return AMDGPU_VRAM_TYPE_DDR2;
779 case MC_SEQ_MISC0__MT__GDDR3:
780 return AMDGPU_VRAM_TYPE_GDDR3;
781 case MC_SEQ_MISC0__MT__GDDR4:
782 return AMDGPU_VRAM_TYPE_GDDR4;
783 case MC_SEQ_MISC0__MT__GDDR5:
784 return AMDGPU_VRAM_TYPE_GDDR5;
785 case MC_SEQ_MISC0__MT__DDR3:
786 return AMDGPU_VRAM_TYPE_DDR3;
787 default:
788 return AMDGPU_VRAM_TYPE_UNKNOWN;
789 }
790}
791
792static int gmc_v6_0_early_init(void *handle)
793{
794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
795
796 gmc_v6_0_set_gart_funcs(adev);
797 gmc_v6_0_set_irq_funcs(adev);
798
df70502e
KW		 799 return 0;
800}
801
802static int gmc_v6_0_late_init(void *handle)
803{
804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
805
a8447647
FC		 806 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
807 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
808 else
809 return 0;
df70502e
KW		 810}
811
812static int gmc_v6_0_sw_init(void *handle)
813{
814 int r;
815 int dma_bits;
816 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
817
b8691c76
JQ		 818 if (adev->flags & AMD_IS_APU) {
819 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
820 } else {
821 u32 tmp = RREG32(mmMC_SEQ_MISC0);
822 tmp &= MC_SEQ_MISC0__MT__MASK;
823 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
824 }
825
d766e6a3 826 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
df70502e
KW		 827 if (r)
828 return r;
829
d766e6a3 830 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
df70502e
KW		 831 if (r)
832 return r;
833
a8ffeac9 834 amdgpu_vm_adjust_size(adev, 64, 9);
36b32a68
ZJ		 835 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
836
df70502e
KW		 837 adev->mc.mc_mask = 0xffffffffffULL;
838
916910ad
HR		 839 adev->mc.stolen_size = 256 * 1024;
840
df70502e
KW		 841 adev->need_dma32 = false;
842 dma_bits = adev->need_dma32 ? 32 : 40;
843 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
844 if (r) {
845 adev->need_dma32 = true;
846 dma_bits = 32;
075719c3 847 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
df70502e
KW		 848 }
849 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
850 if (r) {
851 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
075719c3 852 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
df70502e
KW		 853 }
854
855 r = gmc_v6_0_init_microcode(adev);
856 if (r) {
075719c3 857 dev_err(adev->dev, "Failed to load mc firmware!\n");
df70502e
KW		 858 return r;
859 }
860
df70502e
KW		 861 r = gmc_v6_0_mc_init(adev);
862 if (r)
863 return r;
864
865 r = amdgpu_bo_init(adev);
866 if (r)
867 return r;
868
869 r = gmc_v6_0_gart_init(adev);
870 if (r)
871 return r;
872
05ec3eda
CK		 873 /*
874 * number of VMs
875 * VMID 0 is reserved for System
876 * amdgpu graphics/compute will use VMIDs 1-7
877 * amdkfd will use VMIDs 8-15
878 */
879 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
880 adev->vm_manager.num_level = 1;
881 amdgpu_vm_manager_init(adev);
882
883 /* base offset of vram pages */
884 if (adev->flags & AMD_IS_APU) {
885 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
886
887 tmp <<= 22;
888 adev->vm_manager.vram_base_offset = tmp;
889 } else {
890 adev->vm_manager.vram_base_offset = 0;
df70502e
KW		 891 }
892
05ec3eda 893 return 0;
df70502e
KW		 894}
895
896static int gmc_v6_0_sw_fini(void *handle)
897{
898 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
899
05ec3eda 900 amdgpu_vm_manager_fini(adev);
df70502e
KW		 901 gmc_v6_0_gart_fini(adev);
902 amdgpu_gem_force_release(adev);
903 amdgpu_bo_fini(adev);
c833d8aa
ML		 904 release_firmware(adev->mc.fw);
905 adev->mc.fw = NULL;
df70502e
KW		 906
907 return 0;
908}
909
910static int gmc_v6_0_hw_init(void *handle)
911{
912 int r;
913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914
915 gmc_v6_0_mc_program(adev);
916
917 if (!(adev->flags & AMD_IS_APU)) {
918 r = gmc_v6_0_mc_load_microcode(adev);
919 if (r) {
075719c3 920 dev_err(adev->dev, "Failed to load MC firmware!\n");
df70502e
KW		 921 return r;
922 }
923 }
924
925 r = gmc_v6_0_gart_enable(adev);
926 if (r)
927 return r;
928
929 return r;
930}
931
932static int gmc_v6_0_hw_fini(void *handle)
933{
934 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
935
936 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
937 gmc_v6_0_gart_disable(adev);
938
939 return 0;
940}
941
942static int gmc_v6_0_suspend(void *handle)
943{
944 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
945
df70502e
KW		 946 gmc_v6_0_hw_fini(adev);
947
948 return 0;
949}
950
951static int gmc_v6_0_resume(void *handle)
952{
953 int r;
954 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
955
956 r = gmc_v6_0_hw_init(adev);
957 if (r)
958 return r;
959
b3c85a0f 960 amdgpu_vm_reset_all_ids(adev);
df70502e 961
b3c85a0f 962 return 0;
df70502e
KW		 963}
964
965static bool gmc_v6_0_is_idle(void *handle)
966{
967 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
72518269 968 u32 tmp = RREG32(mmSRBM_STATUS);
df70502e
KW		 969
970 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
971 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
972 return false;
973
974 return true;
975}
976
977static int gmc_v6_0_wait_for_idle(void *handle)
978{
979 unsigned i;
df70502e
KW		 980 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
981
982 for (i = 0; i < adev->usec_timeout; i++) {
9c2e1ae3 983 if (gmc_v6_0_is_idle(handle))
df70502e
KW		 984 return 0;
985 udelay(1);
986 }
987 return -ETIMEDOUT;
988
989}
990
991static int gmc_v6_0_soft_reset(void *handle)
992{
993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
df70502e 994 u32 srbm_soft_reset = 0;
72518269 995 u32 tmp = RREG32(mmSRBM_STATUS);
df70502e
KW		 996
997 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
998 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
72518269 999 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
df70502e
KW		 1000
1001 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1002 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1003 if (!(adev->flags & AMD_IS_APU))
1004 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
72518269 1005 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
df70502e
KW		 1006 }
1007
1008 if (srbm_soft_reset) {
e4f6b39e 1009 gmc_v6_0_mc_stop(adev);
df70502e
KW		 1010 if (gmc_v6_0_wait_for_idle(adev)) {
1011 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1012 }
1013
1014
72518269 1015 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 1016 tmp |= srbm_soft_reset;
1017 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
72518269
TSD		 1018 WREG32(mmSRBM_SOFT_RESET, tmp);
1019 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 1020
1021 udelay(50);
1022
1023 tmp &= ~srbm_soft_reset;
72518269
TSD		 1024 WREG32(mmSRBM_SOFT_RESET, tmp);
1025 tmp = RREG32(mmSRBM_SOFT_RESET);
df70502e
KW		 1026
1027 udelay(50);
1028
e4f6b39e 1029 gmc_v6_0_mc_resume(adev);
df70502e
KW		 1030 udelay(50);
1031 }
1032
1033 return 0;
1034}
1035
1036static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1037 struct amdgpu_irq_src *src,
1038 unsigned type,
1039 enum amdgpu_interrupt_state state)
1040{
1041 u32 tmp;
1042 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1043 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1044 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1045 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1046 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1047 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1048
1049 switch (state) {
1050 case AMDGPU_IRQ_STATE_DISABLE:
72518269 1051 tmp = RREG32(mmVM_CONTEXT0_CNTL);
df70502e 1052 tmp &= ~bits;
72518269
TSD		 1053 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1054 tmp = RREG32(mmVM_CONTEXT1_CNTL);
df70502e 1055 tmp &= ~bits;
72518269 1056 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 1057 break;
1058 case AMDGPU_IRQ_STATE_ENABLE:
72518269 1059 tmp = RREG32(mmVM_CONTEXT0_CNTL);
df70502e 1060 tmp |= bits;
72518269
TSD		 1061 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1062 tmp = RREG32(mmVM_CONTEXT1_CNTL);
df70502e 1063 tmp |= bits;
72518269 1064 WREG32(mmVM_CONTEXT1_CNTL, tmp);
df70502e
KW		 1065 break;
1066 default:
1067 break;
1068 }
1069
1070 return 0;
1071}
1072
1073static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1074 struct amdgpu_irq_src *source,
1075 struct amdgpu_iv_entry *entry)
1076{
1077 u32 addr, status;
1078
72518269
TSD		 1079 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1080 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1081 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
df70502e
KW		 1082
1083 if (!addr && !status)
1084 return 0;
1085
1086 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1087 gmc_v6_0_set_fault_enable_default(adev, false);
1088
01615881
EC		 1089 if (printk_ratelimit()) {
1090 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
7ccf5aa8 1091 entry->src_id, entry->src_data[0]);
01615881
EC		 1092 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1093 addr);
1094 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1095 status);
1096 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1097 }
df70502e
KW		 1098
1099 return 0;
1100}
1101
1102static int gmc_v6_0_set_clockgating_state(void *handle,
1103 enum amd_clockgating_state state)
1104{
1105 return 0;
1106}
1107
1108static int gmc_v6_0_set_powergating_state(void *handle,
1109 enum amd_powergating_state state)
1110{
1111 return 0;
1112}
1113
a1255107 1114static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
df70502e
KW		 1115 .name = "gmc_v6_0",
1116 .early_init = gmc_v6_0_early_init,
1117 .late_init = gmc_v6_0_late_init,
1118 .sw_init = gmc_v6_0_sw_init,
1119 .sw_fini = gmc_v6_0_sw_fini,
1120 .hw_init = gmc_v6_0_hw_init,
1121 .hw_fini = gmc_v6_0_hw_fini,
1122 .suspend = gmc_v6_0_suspend,
1123 .resume = gmc_v6_0_resume,
1124 .is_idle = gmc_v6_0_is_idle,
1125 .wait_for_idle = gmc_v6_0_wait_for_idle,
1126 .soft_reset = gmc_v6_0_soft_reset,
1127 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1128 .set_powergating_state = gmc_v6_0_set_powergating_state,
1129};
1130
1131static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1132 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1133 .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
f7c35abe 1134 .set_prt = gmc_v6_0_set_prt,
b1166325 1135 .get_vm_pde = gmc_v6_0_get_vm_pde,
5463545b 1136 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
df70502e
KW		 1137};
1138
1139static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1140 .set = gmc_v6_0_vm_fault_interrupt_state,
1141 .process = gmc_v6_0_process_interrupt,
1142};
1143
1144static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1145{
1146 if (adev->gart.gart_funcs == NULL)
1147 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1148}
1149
1150static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1151{
1152 adev->mc.vm_fault.num_types = 1;
1153 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1154}
1155
a1255107
AD		 1156const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1157{
1158 .type = AMD_IP_BLOCK_TYPE_GMC,
1159 .major = 6,
1160 .minor = 0,
1161 .rev = 0,
1162 .funcs = &gmc_v6_0_ip_funcs,
1163};
Linux 6.x block layer and io_uring tree(s)