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df70502e KW |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
248a1d6f | 24 | #include <drm/drmP.h> |
fd5fd480 | 25 | #include <drm/drm_cache.h> |
df70502e KW |
26 | #include "amdgpu.h" |
27 | #include "gmc_v6_0.h" | |
28 | #include "amdgpu_ucode.h" | |
72518269 TSD |
29 | |
30 | #include "bif/bif_3_0_d.h" | |
31 | #include "bif/bif_3_0_sh_mask.h" | |
32 | #include "oss/oss_1_0_d.h" | |
33 | #include "oss/oss_1_0_sh_mask.h" | |
34 | #include "gmc/gmc_6_0_d.h" | |
35 | #include "gmc/gmc_6_0_sh_mask.h" | |
36 | #include "dce/dce_6_0_d.h" | |
37 | #include "dce/dce_6_0_sh_mask.h" | |
38 | #include "si_enums.h" | |
df70502e | 39 | |
132f34e4 | 40 | static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); |
df70502e KW |
41 | static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); |
42 | static int gmc_v6_0_wait_for_idle(void *handle); | |
43 | ||
44 | MODULE_FIRMWARE("radeon/tahiti_mc.bin"); | |
45 | MODULE_FIRMWARE("radeon/pitcairn_mc.bin"); | |
46 | MODULE_FIRMWARE("radeon/verde_mc.bin"); | |
47 | MODULE_FIRMWARE("radeon/oland_mc.bin"); | |
f1d877be | 48 | MODULE_FIRMWARE("radeon/si58_mc.bin"); |
df70502e | 49 | |
72518269 TSD |
50 | #define MC_SEQ_MISC0__MT__MASK 0xf0000000 |
51 | #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 | |
52 | #define MC_SEQ_MISC0__MT__DDR2 0x20000000 | |
53 | #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 | |
54 | #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 | |
55 | #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 | |
56 | #define MC_SEQ_MISC0__MT__HBM 0x60000000 | |
57 | #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 | |
58 | ||
59 | ||
df70502e KW |
60 | static const u32 crtc_offsets[6] = |
61 | { | |
62 | SI_CRTC0_REGISTER_OFFSET, | |
63 | SI_CRTC1_REGISTER_OFFSET, | |
64 | SI_CRTC2_REGISTER_OFFSET, | |
65 | SI_CRTC3_REGISTER_OFFSET, | |
66 | SI_CRTC4_REGISTER_OFFSET, | |
67 | SI_CRTC5_REGISTER_OFFSET | |
68 | }; | |
69 | ||
e4f6b39e | 70 | static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) |
df70502e KW |
71 | { |
72 | u32 blackout; | |
73 | ||
df70502e KW |
74 | gmc_v6_0_wait_for_idle((void *)adev); |
75 | ||
72518269 TSD |
76 | blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
77 | if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { | |
df70502e | 78 | /* Block CPU access */ |
72518269 | 79 | WREG32(mmBIF_FB_EN, 0); |
df70502e KW |
80 | /* blackout the MC */ |
81 | blackout = REG_SET_FIELD(blackout, | |
72518269 TSD |
82 | MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); |
83 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); | |
df70502e KW |
84 | } |
85 | /* wait for the MC to settle */ | |
86 | udelay(100); | |
87 | ||
88 | } | |
89 | ||
e4f6b39e | 90 | static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) |
df70502e KW |
91 | { |
92 | u32 tmp; | |
93 | ||
94 | /* unblackout the MC */ | |
72518269 TSD |
95 | tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
96 | tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); | |
97 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); | |
df70502e | 98 | /* allow CPU access */ |
72518269 TSD |
99 | tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); |
100 | tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); | |
101 | WREG32(mmBIF_FB_EN, tmp); | |
df70502e KW |
102 | } |
103 | ||
104 | static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) | |
105 | { | |
106 | const char *chip_name; | |
107 | char fw_name[30]; | |
108 | int err; | |
f1d877be | 109 | bool is_58_fw = false; |
df70502e KW |
110 | |
111 | DRM_DEBUG("\n"); | |
112 | ||
113 | switch (adev->asic_type) { | |
114 | case CHIP_TAHITI: | |
115 | chip_name = "tahiti"; | |
116 | break; | |
117 | case CHIP_PITCAIRN: | |
118 | chip_name = "pitcairn"; | |
119 | break; | |
120 | case CHIP_VERDE: | |
121 | chip_name = "verde"; | |
122 | break; | |
123 | case CHIP_OLAND: | |
124 | chip_name = "oland"; | |
125 | break; | |
126 | case CHIP_HAINAN: | |
127 | chip_name = "hainan"; | |
128 | break; | |
129 | default: BUG(); | |
130 | } | |
131 | ||
f1d877be AD |
132 | /* this memory configuration requires special firmware */ |
133 | if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) | |
134 | is_58_fw = true; | |
135 | ||
136 | if (is_58_fw) | |
137 | snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin"); | |
138 | else | |
139 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); | |
770d13b1 | 140 | err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); |
df70502e KW |
141 | if (err) |
142 | goto out; | |
143 | ||
770d13b1 | 144 | err = amdgpu_ucode_validate(adev->gmc.fw); |
df70502e KW |
145 | |
146 | out: | |
147 | if (err) { | |
075719c3 | 148 | dev_err(adev->dev, |
df70502e KW |
149 | "si_mc: Failed to load firmware \"%s\"\n", |
150 | fw_name); | |
770d13b1 CK |
151 | release_firmware(adev->gmc.fw); |
152 | adev->gmc.fw = NULL; | |
df70502e KW |
153 | } |
154 | return err; | |
155 | } | |
156 | ||
157 | static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) | |
158 | { | |
159 | const __le32 *new_fw_data = NULL; | |
160 | u32 running; | |
161 | const __le32 *new_io_mc_regs = NULL; | |
162 | int i, regs_size, ucode_size; | |
163 | const struct mc_firmware_header_v1_0 *hdr; | |
164 | ||
770d13b1 | 165 | if (!adev->gmc.fw) |
df70502e KW |
166 | return -EINVAL; |
167 | ||
770d13b1 | 168 | hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; |
df70502e KW |
169 | |
170 | amdgpu_ucode_print_mc_hdr(&hdr->header); | |
171 | ||
770d13b1 | 172 | adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); |
df70502e KW |
173 | regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); |
174 | new_io_mc_regs = (const __le32 *) | |
770d13b1 | 175 | (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); |
df70502e KW |
176 | ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
177 | new_fw_data = (const __le32 *) | |
770d13b1 | 178 | (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
df70502e | 179 | |
72518269 | 180 | running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; |
df70502e KW |
181 | |
182 | if (running == 0) { | |
183 | ||
184 | /* reset the engine and set to writable */ | |
72518269 TSD |
185 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); |
186 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); | |
df70502e KW |
187 | |
188 | /* load mc io regs */ | |
189 | for (i = 0; i < regs_size; i++) { | |
72518269 TSD |
190 | WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); |
191 | WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); | |
df70502e KW |
192 | } |
193 | /* load the MC ucode */ | |
194 | for (i = 0; i < ucode_size; i++) { | |
72518269 | 195 | WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); |
df70502e KW |
196 | } |
197 | ||
198 | /* put the engine back into the active state */ | |
72518269 TSD |
199 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); |
200 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); | |
201 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); | |
df70502e KW |
202 | |
203 | /* wait for training to complete */ | |
204 | for (i = 0; i < adev->usec_timeout; i++) { | |
72518269 | 205 | if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) |
df70502e KW |
206 | break; |
207 | udelay(1); | |
208 | } | |
209 | for (i = 0; i < adev->usec_timeout; i++) { | |
72518269 | 210 | if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) |
df70502e KW |
211 | break; |
212 | udelay(1); | |
213 | } | |
214 | ||
215 | } | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, | |
770d13b1 | 221 | struct amdgpu_gmc *mc) |
df70502e | 222 | { |
ba3a5b83 AD |
223 | u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; |
224 | base <<= 24; | |
225 | ||
770d13b1 | 226 | amdgpu_device_vram_location(adev, &adev->gmc, base); |
2543e28a | 227 | amdgpu_device_gart_location(adev, mc); |
df70502e KW |
228 | } |
229 | ||
230 | static void gmc_v6_0_mc_program(struct amdgpu_device *adev) | |
231 | { | |
df70502e KW |
232 | int i, j; |
233 | ||
234 | /* Initialize HDP */ | |
235 | for (i = 0, j = 0; i < 32; i++, j += 0x6) { | |
236 | WREG32((0xb05 + j), 0x00000000); | |
237 | WREG32((0xb06 + j), 0x00000000); | |
238 | WREG32((0xb07 + j), 0x00000000); | |
239 | WREG32((0xb08 + j), 0x00000000); | |
240 | WREG32((0xb09 + j), 0x00000000); | |
241 | } | |
72518269 | 242 | WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); |
df70502e | 243 | |
df70502e KW |
244 | if (gmc_v6_0_wait_for_idle((void *)adev)) { |
245 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); | |
246 | } | |
247 | ||
03ba88cf AD |
248 | if (adev->mode_info.num_crtc) { |
249 | u32 tmp; | |
250 | ||
251 | /* Lockout access through VGA aperture*/ | |
252 | tmp = RREG32(mmVGA_HDP_CONTROL); | |
253 | tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; | |
254 | WREG32(mmVGA_HDP_CONTROL, tmp); | |
255 | ||
256 | /* disable VGA render */ | |
257 | tmp = RREG32(mmVGA_RENDER_CONTROL); | |
258 | tmp &= ~VGA_VSTATUS_CNTL; | |
259 | WREG32(mmVGA_RENDER_CONTROL, tmp); | |
260 | } | |
df70502e | 261 | /* Update configuration */ |
72518269 | 262 | WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
770d13b1 | 263 | adev->gmc.vram_start >> 12); |
72518269 | 264 | WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
770d13b1 | 265 | adev->gmc.vram_end >> 12); |
72518269 | 266 | WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, |
df70502e | 267 | adev->vram_scratch.gpu_addr >> 12); |
72518269 TSD |
268 | WREG32(mmMC_VM_AGP_BASE, 0); |
269 | WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); | |
270 | WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); | |
df70502e KW |
271 | |
272 | if (gmc_v6_0_wait_for_idle((void *)adev)) { | |
273 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); | |
274 | } | |
df70502e KW |
275 | } |
276 | ||
277 | static int gmc_v6_0_mc_init(struct amdgpu_device *adev) | |
278 | { | |
279 | ||
280 | u32 tmp; | |
281 | int chansize, numchan; | |
d6895ad3 | 282 | int r; |
df70502e | 283 | |
72518269 TSD |
284 | tmp = RREG32(mmMC_ARB_RAMCFG); |
285 | if (tmp & (1 << 11)) { | |
df70502e | 286 | chansize = 16; |
72518269 | 287 | } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { |
df70502e KW |
288 | chansize = 64; |
289 | } else { | |
290 | chansize = 32; | |
291 | } | |
72518269 TSD |
292 | tmp = RREG32(mmMC_SHARED_CHMAP); |
293 | switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { | |
df70502e KW |
294 | case 0: |
295 | default: | |
296 | numchan = 1; | |
297 | break; | |
298 | case 1: | |
299 | numchan = 2; | |
300 | break; | |
301 | case 2: | |
302 | numchan = 4; | |
303 | break; | |
304 | case 3: | |
305 | numchan = 8; | |
306 | break; | |
307 | case 4: | |
308 | numchan = 3; | |
309 | break; | |
310 | case 5: | |
311 | numchan = 6; | |
312 | break; | |
313 | case 6: | |
314 | numchan = 10; | |
315 | break; | |
316 | case 7: | |
317 | numchan = 12; | |
318 | break; | |
319 | case 8: | |
320 | numchan = 16; | |
321 | break; | |
322 | } | |
770d13b1 | 323 | adev->gmc.vram_width = numchan * chansize; |
df70502e | 324 | /* size in MB on si */ |
770d13b1 CK |
325 | adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
326 | adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; | |
d6895ad3 CK |
327 | |
328 | if (!(adev->flags & AMD_IS_APU)) { | |
329 | r = amdgpu_device_resize_fb_bar(adev); | |
330 | if (r) | |
331 | return r; | |
332 | } | |
770d13b1 CK |
333 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); |
334 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); | |
335 | adev->gmc.visible_vram_size = adev->gmc.aper_size; | |
df70502e | 336 | |
c3db7b5a AD |
337 | /* set the gart size */ |
338 | if (amdgpu_gart_size == -1) { | |
339 | switch (adev->asic_type) { | |
340 | case CHIP_HAINAN: /* no MM engines */ | |
341 | default: | |
770d13b1 | 342 | adev->gmc.gart_size = 256ULL << 20; |
c3db7b5a AD |
343 | break; |
344 | case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ | |
345 | case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ | |
346 | case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ | |
347 | case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ | |
770d13b1 | 348 | adev->gmc.gart_size = 1024ULL << 20; |
c3db7b5a AD |
349 | break; |
350 | } | |
351 | } else { | |
770d13b1 | 352 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
c3db7b5a AD |
353 | } |
354 | ||
770d13b1 | 355 | gmc_v6_0_vram_gtt_location(adev, &adev->gmc); |
df70502e KW |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
132f34e4 | 360 | static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) |
df70502e | 361 | { |
72518269 | 362 | WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); |
df70502e KW |
363 | } |
364 | ||
4fef88bd | 365 | static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
c633c00b | 366 | unsigned vmid, uint64_t pd_addr) |
4fef88bd CK |
367 | { |
368 | uint32_t reg; | |
369 | ||
370 | /* write new base address */ | |
371 | if (vmid < 8) | |
372 | reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; | |
373 | else | |
374 | reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); | |
375 | amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); | |
376 | ||
377 | /* bits 0-15 are the VM contexts0-15 */ | |
378 | amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); | |
379 | ||
380 | return pd_addr; | |
381 | } | |
382 | ||
132f34e4 CK |
383 | static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, |
384 | uint32_t gpu_page_idx, uint64_t addr, | |
385 | uint64_t flags) | |
df70502e KW |
386 | { |
387 | void __iomem *ptr = (void *)cpu_pt_addr; | |
388 | uint64_t value; | |
389 | ||
390 | value = addr & 0xFFFFFFFFFFFFF000ULL; | |
391 | value |= flags; | |
392 | writeq(value, ptr + (gpu_page_idx * 8)); | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
5463545b AX |
397 | static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, |
398 | uint32_t flags) | |
399 | { | |
400 | uint64_t pte_flag = 0; | |
401 | ||
402 | if (flags & AMDGPU_VM_PAGE_READABLE) | |
403 | pte_flag |= AMDGPU_PTE_READABLE; | |
404 | if (flags & AMDGPU_VM_PAGE_WRITEABLE) | |
405 | pte_flag |= AMDGPU_PTE_WRITEABLE; | |
406 | if (flags & AMDGPU_VM_PAGE_PRT) | |
407 | pte_flag |= AMDGPU_PTE_PRT; | |
408 | ||
409 | return pte_flag; | |
410 | } | |
411 | ||
3de676d8 CK |
412 | static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, |
413 | uint64_t *addr, uint64_t *flags) | |
b1166325 | 414 | { |
3de676d8 | 415 | BUG_ON(*addr & 0xFFFFFF0000000FFFULL); |
b1166325 CK |
416 | } |
417 | ||
df70502e KW |
418 | static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, |
419 | bool value) | |
420 | { | |
421 | u32 tmp; | |
422 | ||
72518269 TSD |
423 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
424 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
425 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
426 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
427 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
428 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
429 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
430 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
431 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
432 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
433 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
434 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
435 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
436 | WREG32(mmVM_CONTEXT1_CNTL, tmp); | |
df70502e KW |
437 | } |
438 | ||
f7c35abe CK |
439 | /** |
440 | + * gmc_v8_0_set_prt - set PRT VM fault | |
441 | + * | |
442 | + * @adev: amdgpu_device pointer | |
443 | + * @enable: enable/disable VM fault handling for PRT | |
444 | +*/ | |
445 | static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) | |
446 | { | |
447 | u32 tmp; | |
448 | ||
770d13b1 | 449 | if (enable && !adev->gmc.prt_warning) { |
f7c35abe | 450 | dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); |
770d13b1 | 451 | adev->gmc.prt_warning = true; |
f7c35abe CK |
452 | } |
453 | ||
454 | tmp = RREG32(mmVM_PRT_CNTL); | |
455 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, | |
456 | CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, | |
457 | enable); | |
458 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, | |
459 | TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, | |
460 | enable); | |
461 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, | |
462 | L2_CACHE_STORE_INVALID_ENTRIES, | |
463 | enable); | |
464 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, | |
465 | L1_TLB_STORE_INVALID_ENTRIES, | |
466 | enable); | |
467 | WREG32(mmVM_PRT_CNTL, tmp); | |
468 | ||
469 | if (enable) { | |
470 | uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; | |
a3e9a15a CK |
471 | uint32_t high = adev->vm_manager.max_pfn - |
472 | (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); | |
f7c35abe CK |
473 | |
474 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); | |
475 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); | |
476 | WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); | |
477 | WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); | |
478 | WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); | |
479 | WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); | |
480 | WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); | |
481 | WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); | |
482 | } else { | |
483 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); | |
484 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); | |
485 | WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); | |
486 | WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); | |
487 | WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); | |
488 | WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); | |
489 | WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); | |
490 | WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); | |
491 | } | |
492 | } | |
493 | ||
df70502e KW |
494 | static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) |
495 | { | |
ce1b1b66 | 496 | int r, i; |
e618d306 | 497 | u32 field; |
df70502e KW |
498 | |
499 | if (adev->gart.robj == NULL) { | |
500 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); | |
501 | return -EINVAL; | |
502 | } | |
ce1b1b66 ML |
503 | r = amdgpu_gart_table_vram_pin(adev); |
504 | if (r) | |
505 | return r; | |
df70502e | 506 | /* Setup TLB control */ |
72518269 | 507 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, |
df70502e | 508 | (0xA << 7) | |
72518269 TSD |
509 | MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | |
510 | MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | | |
511 | MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | | |
512 | MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | | |
513 | (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); | |
df70502e | 514 | /* Setup L2 cache */ |
72518269 TSD |
515 | WREG32(mmVM_L2_CNTL, |
516 | VM_L2_CNTL__ENABLE_L2_CACHE_MASK | | |
517 | VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | | |
518 | VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | | |
519 | VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | | |
520 | (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | | |
521 | (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); | |
522 | WREG32(mmVM_L2_CNTL2, | |
523 | VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | | |
524 | VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); | |
e618d306 RH |
525 | |
526 | field = adev->vm_manager.fragment_size; | |
72518269 TSD |
527 | WREG32(mmVM_L2_CNTL3, |
528 | VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | | |
e618d306 RH |
529 | (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | |
530 | (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); | |
df70502e | 531 | /* setup context0 */ |
770d13b1 CK |
532 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); |
533 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); | |
72518269 TSD |
534 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); |
535 | WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
92e71b06 | 536 | (u32)(adev->dummy_page_addr >> 12)); |
72518269 TSD |
537 | WREG32(mmVM_CONTEXT0_CNTL2, 0); |
538 | WREG32(mmVM_CONTEXT0_CNTL, | |
539 | VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | | |
540 | (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | | |
541 | VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); | |
df70502e KW |
542 | |
543 | WREG32(0x575, 0); | |
544 | WREG32(0x576, 0); | |
545 | WREG32(0x577, 0); | |
546 | ||
547 | /* empty context1-15 */ | |
548 | /* set vm size, must be a multiple of 4 */ | |
72518269 TSD |
549 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
550 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); | |
df70502e KW |
551 | /* Assign the pt base to something valid for now; the pts used for |
552 | * the VMs are determined by the application and setup and assigned | |
553 | * on the fly in the vm part of radeon_gart.c | |
554 | */ | |
555 | for (i = 1; i < 16; i++) { | |
556 | if (i < 8) | |
72518269 | 557 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, |
df70502e KW |
558 | adev->gart.table_addr >> 12); |
559 | else | |
72518269 | 560 | WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, |
df70502e KW |
561 | adev->gart.table_addr >> 12); |
562 | } | |
563 | ||
564 | /* enable context1-15 */ | |
72518269 | 565 | WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
92e71b06 | 566 | (u32)(adev->dummy_page_addr >> 12)); |
72518269 TSD |
567 | WREG32(mmVM_CONTEXT1_CNTL2, 4); |
568 | WREG32(mmVM_CONTEXT1_CNTL, | |
569 | VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | | |
570 | (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | | |
36b32a68 ZJ |
571 | ((adev->vm_manager.block_size - 9) |
572 | << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); | |
a8447647 FC |
573 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
574 | gmc_v6_0_set_fault_enable_default(adev, false); | |
575 | else | |
576 | gmc_v6_0_set_fault_enable_default(adev, true); | |
df70502e | 577 | |
132f34e4 | 578 | gmc_v6_0_flush_gpu_tlb(adev, 0); |
075719c3 | 579 | dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", |
770d13b1 | 580 | (unsigned)(adev->gmc.gart_size >> 20), |
df70502e KW |
581 | (unsigned long long)adev->gart.table_addr); |
582 | adev->gart.ready = true; | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int gmc_v6_0_gart_init(struct amdgpu_device *adev) | |
587 | { | |
588 | int r; | |
589 | ||
590 | if (adev->gart.robj) { | |
075719c3 | 591 | dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); |
df70502e KW |
592 | return 0; |
593 | } | |
594 | r = amdgpu_gart_init(adev); | |
595 | if (r) | |
596 | return r; | |
597 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; | |
4b98e0c4 | 598 | adev->gart.gart_pte_flags = 0; |
df70502e KW |
599 | return amdgpu_gart_table_vram_alloc(adev); |
600 | } | |
601 | ||
602 | static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) | |
603 | { | |
604 | /*unsigned i; | |
605 | ||
606 | for (i = 1; i < 16; ++i) { | |
607 | uint32_t reg; | |
608 | if (i < 8) | |
609 | reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; | |
610 | else | |
611 | reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); | |
612 | adev->vm_manager.saved_table_addr[i] = RREG32(reg); | |
613 | }*/ | |
614 | ||
615 | /* Disable all tables */ | |
72518269 TSD |
616 | WREG32(mmVM_CONTEXT0_CNTL, 0); |
617 | WREG32(mmVM_CONTEXT1_CNTL, 0); | |
df70502e | 618 | /* Setup TLB control */ |
72518269 TSD |
619 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, |
620 | MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | | |
621 | (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); | |
df70502e | 622 | /* Setup L2 cache */ |
72518269 TSD |
623 | WREG32(mmVM_L2_CNTL, |
624 | VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | | |
625 | VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | | |
626 | (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | | |
627 | (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); | |
628 | WREG32(mmVM_L2_CNTL2, 0); | |
629 | WREG32(mmVM_L2_CNTL3, | |
630 | VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | | |
631 | (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); | |
ce1b1b66 | 632 | amdgpu_gart_table_vram_unpin(adev); |
df70502e KW |
633 | } |
634 | ||
635 | static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) | |
636 | { | |
637 | amdgpu_gart_table_vram_free(adev); | |
638 | amdgpu_gart_fini(adev); | |
639 | } | |
640 | ||
df70502e KW |
641 | static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, |
642 | u32 status, u32 addr, u32 mc_client) | |
643 | { | |
644 | u32 mc_id; | |
72518269 TSD |
645 | u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); |
646 | u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, | |
647 | PROTECTIONS); | |
df70502e KW |
648 | char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, |
649 | (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; | |
650 | ||
72518269 TSD |
651 | mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
652 | MEMORY_CLIENT_ID); | |
df70502e | 653 | |
075719c3 | 654 | dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", |
df70502e | 655 | protections, vmid, addr, |
72518269 TSD |
656 | REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
657 | MEMORY_CLIENT_RW) ? | |
df70502e KW |
658 | "write" : "read", block, mc_client, mc_id); |
659 | } | |
660 | ||
661 | /* | |
662 | static const u32 mc_cg_registers[] = { | |
663 | MC_HUB_MISC_HUB_CG, | |
664 | MC_HUB_MISC_SIP_CG, | |
665 | MC_HUB_MISC_VM_CG, | |
666 | MC_XPB_CLK_GAT, | |
667 | ATC_MISC_CG, | |
668 | MC_CITF_MISC_WR_CG, | |
669 | MC_CITF_MISC_RD_CG, | |
670 | MC_CITF_MISC_VM_CG, | |
671 | VM_L2_CG, | |
672 | }; | |
673 | ||
674 | static const u32 mc_cg_ls_en[] = { | |
675 | MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, | |
676 | MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, | |
677 | MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, | |
678 | MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, | |
679 | ATC_MISC_CG__MEM_LS_ENABLE_MASK, | |
680 | MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, | |
681 | MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, | |
682 | MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, | |
683 | VM_L2_CG__MEM_LS_ENABLE_MASK, | |
684 | }; | |
685 | ||
686 | static const u32 mc_cg_en[] = { | |
687 | MC_HUB_MISC_HUB_CG__ENABLE_MASK, | |
688 | MC_HUB_MISC_SIP_CG__ENABLE_MASK, | |
689 | MC_HUB_MISC_VM_CG__ENABLE_MASK, | |
690 | MC_XPB_CLK_GAT__ENABLE_MASK, | |
691 | ATC_MISC_CG__ENABLE_MASK, | |
692 | MC_CITF_MISC_WR_CG__ENABLE_MASK, | |
693 | MC_CITF_MISC_RD_CG__ENABLE_MASK, | |
694 | MC_CITF_MISC_VM_CG__ENABLE_MASK, | |
695 | VM_L2_CG__ENABLE_MASK, | |
696 | }; | |
697 | ||
698 | static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, | |
699 | bool enable) | |
700 | { | |
701 | int i; | |
702 | u32 orig, data; | |
703 | ||
704 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { | |
705 | orig = data = RREG32(mc_cg_registers[i]); | |
706 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) | |
707 | data |= mc_cg_ls_en[i]; | |
708 | else | |
709 | data &= ~mc_cg_ls_en[i]; | |
710 | if (data != orig) | |
711 | WREG32(mc_cg_registers[i], data); | |
712 | } | |
713 | } | |
714 | ||
715 | static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, | |
716 | bool enable) | |
717 | { | |
718 | int i; | |
719 | u32 orig, data; | |
720 | ||
721 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { | |
722 | orig = data = RREG32(mc_cg_registers[i]); | |
723 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) | |
724 | data |= mc_cg_en[i]; | |
725 | else | |
726 | data &= ~mc_cg_en[i]; | |
727 | if (data != orig) | |
728 | WREG32(mc_cg_registers[i], data); | |
729 | } | |
730 | } | |
731 | ||
732 | static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, | |
733 | bool enable) | |
734 | { | |
735 | u32 orig, data; | |
736 | ||
737 | orig = data = RREG32_PCIE(ixPCIE_CNTL2); | |
738 | ||
739 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { | |
740 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); | |
741 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); | |
742 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); | |
743 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); | |
744 | } else { | |
745 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); | |
746 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); | |
747 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); | |
748 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); | |
749 | } | |
750 | ||
751 | if (orig != data) | |
752 | WREG32_PCIE(ixPCIE_CNTL2, data); | |
753 | } | |
754 | ||
755 | static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, | |
756 | bool enable) | |
757 | { | |
758 | u32 orig, data; | |
759 | ||
72518269 | 760 | orig = data = RREG32(mmHDP_HOST_PATH_CNTL); |
df70502e KW |
761 | |
762 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) | |
763 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); | |
764 | else | |
765 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); | |
766 | ||
767 | if (orig != data) | |
72518269 | 768 | WREG32(mmHDP_HOST_PATH_CNTL, data); |
df70502e KW |
769 | } |
770 | ||
771 | static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, | |
772 | bool enable) | |
773 | { | |
774 | u32 orig, data; | |
775 | ||
72518269 | 776 | orig = data = RREG32(mmHDP_MEM_POWER_LS); |
df70502e KW |
777 | |
778 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) | |
779 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); | |
780 | else | |
781 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); | |
782 | ||
783 | if (orig != data) | |
72518269 | 784 | WREG32(mmHDP_MEM_POWER_LS, data); |
df70502e KW |
785 | } |
786 | */ | |
787 | ||
788 | static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) | |
789 | { | |
790 | switch (mc_seq_vram_type) { | |
791 | case MC_SEQ_MISC0__MT__GDDR1: | |
792 | return AMDGPU_VRAM_TYPE_GDDR1; | |
793 | case MC_SEQ_MISC0__MT__DDR2: | |
794 | return AMDGPU_VRAM_TYPE_DDR2; | |
795 | case MC_SEQ_MISC0__MT__GDDR3: | |
796 | return AMDGPU_VRAM_TYPE_GDDR3; | |
797 | case MC_SEQ_MISC0__MT__GDDR4: | |
798 | return AMDGPU_VRAM_TYPE_GDDR4; | |
799 | case MC_SEQ_MISC0__MT__GDDR5: | |
800 | return AMDGPU_VRAM_TYPE_GDDR5; | |
801 | case MC_SEQ_MISC0__MT__DDR3: | |
802 | return AMDGPU_VRAM_TYPE_DDR3; | |
803 | default: | |
804 | return AMDGPU_VRAM_TYPE_UNKNOWN; | |
805 | } | |
806 | } | |
807 | ||
808 | static int gmc_v6_0_early_init(void *handle) | |
809 | { | |
810 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
811 | ||
132f34e4 | 812 | gmc_v6_0_set_gmc_funcs(adev); |
df70502e KW |
813 | gmc_v6_0_set_irq_funcs(adev); |
814 | ||
df70502e KW |
815 | return 0; |
816 | } | |
817 | ||
818 | static int gmc_v6_0_late_init(void *handle) | |
819 | { | |
820 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
821 | ||
6f752ec2 AG |
822 | amdgpu_bo_late_init(adev); |
823 | ||
a8447647 | 824 | if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) |
770d13b1 | 825 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
a8447647 FC |
826 | else |
827 | return 0; | |
df70502e KW |
828 | } |
829 | ||
ebdef28e AD |
830 | static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) |
831 | { | |
832 | u32 d1vga_control = RREG32(mmD1VGA_CONTROL); | |
833 | unsigned size; | |
834 | ||
835 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { | |
836 | size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ | |
837 | } else { | |
838 | u32 viewport = RREG32(mmVIEWPORT_SIZE); | |
839 | size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * | |
840 | REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * | |
841 | 4); | |
842 | } | |
843 | /* return 0 if the pre-OS buffer uses up most of vram */ | |
844 | if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) | |
845 | return 0; | |
846 | return size; | |
847 | } | |
848 | ||
df70502e KW |
849 | static int gmc_v6_0_sw_init(void *handle) |
850 | { | |
851 | int r; | |
852 | int dma_bits; | |
853 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
854 | ||
b8691c76 | 855 | if (adev->flags & AMD_IS_APU) { |
770d13b1 | 856 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; |
b8691c76 JQ |
857 | } else { |
858 | u32 tmp = RREG32(mmMC_SEQ_MISC0); | |
859 | tmp &= MC_SEQ_MISC0__MT__MASK; | |
770d13b1 | 860 | adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); |
b8691c76 JQ |
861 | } |
862 | ||
770d13b1 | 863 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); |
df70502e KW |
864 | if (r) |
865 | return r; | |
866 | ||
770d13b1 | 867 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); |
df70502e KW |
868 | if (r) |
869 | return r; | |
870 | ||
f3368128 | 871 | amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); |
36b32a68 | 872 | |
770d13b1 | 873 | adev->gmc.mc_mask = 0xffffffffffULL; |
df70502e KW |
874 | |
875 | adev->need_dma32 = false; | |
876 | dma_bits = adev->need_dma32 ? 32 : 40; | |
877 | r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); | |
878 | if (r) { | |
879 | adev->need_dma32 = true; | |
880 | dma_bits = 32; | |
075719c3 | 881 | dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); |
df70502e KW |
882 | } |
883 | r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); | |
884 | if (r) { | |
885 | pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); | |
075719c3 | 886 | dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); |
df70502e | 887 | } |
fd5fd480 | 888 | adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); |
df70502e KW |
889 | |
890 | r = gmc_v6_0_init_microcode(adev); | |
891 | if (r) { | |
075719c3 | 892 | dev_err(adev->dev, "Failed to load mc firmware!\n"); |
df70502e KW |
893 | return r; |
894 | } | |
895 | ||
df70502e KW |
896 | r = gmc_v6_0_mc_init(adev); |
897 | if (r) | |
898 | return r; | |
899 | ||
ebdef28e AD |
900 | adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev); |
901 | ||
df70502e KW |
902 | r = amdgpu_bo_init(adev); |
903 | if (r) | |
904 | return r; | |
905 | ||
906 | r = gmc_v6_0_gart_init(adev); | |
907 | if (r) | |
908 | return r; | |
909 | ||
05ec3eda CK |
910 | /* |
911 | * number of VMs | |
912 | * VMID 0 is reserved for System | |
913 | * amdgpu graphics/compute will use VMIDs 1-7 | |
914 | * amdkfd will use VMIDs 8-15 | |
915 | */ | |
916 | adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; | |
05ec3eda CK |
917 | amdgpu_vm_manager_init(adev); |
918 | ||
919 | /* base offset of vram pages */ | |
920 | if (adev->flags & AMD_IS_APU) { | |
921 | u64 tmp = RREG32(mmMC_VM_FB_OFFSET); | |
922 | ||
923 | tmp <<= 22; | |
924 | adev->vm_manager.vram_base_offset = tmp; | |
925 | } else { | |
926 | adev->vm_manager.vram_base_offset = 0; | |
df70502e KW |
927 | } |
928 | ||
05ec3eda | 929 | return 0; |
df70502e KW |
930 | } |
931 | ||
932 | static int gmc_v6_0_sw_fini(void *handle) | |
933 | { | |
934 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
935 | ||
f59548c8 | 936 | amdgpu_gem_force_release(adev); |
05ec3eda | 937 | amdgpu_vm_manager_fini(adev); |
df70502e | 938 | gmc_v6_0_gart_fini(adev); |
df70502e | 939 | amdgpu_bo_fini(adev); |
770d13b1 CK |
940 | release_firmware(adev->gmc.fw); |
941 | adev->gmc.fw = NULL; | |
df70502e KW |
942 | |
943 | return 0; | |
944 | } | |
945 | ||
946 | static int gmc_v6_0_hw_init(void *handle) | |
947 | { | |
948 | int r; | |
949 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
950 | ||
951 | gmc_v6_0_mc_program(adev); | |
952 | ||
953 | if (!(adev->flags & AMD_IS_APU)) { | |
954 | r = gmc_v6_0_mc_load_microcode(adev); | |
955 | if (r) { | |
075719c3 | 956 | dev_err(adev->dev, "Failed to load MC firmware!\n"); |
df70502e KW |
957 | return r; |
958 | } | |
959 | } | |
960 | ||
961 | r = gmc_v6_0_gart_enable(adev); | |
962 | if (r) | |
963 | return r; | |
964 | ||
965 | return r; | |
966 | } | |
967 | ||
968 | static int gmc_v6_0_hw_fini(void *handle) | |
969 | { | |
970 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
971 | ||
770d13b1 | 972 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
df70502e KW |
973 | gmc_v6_0_gart_disable(adev); |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | static int gmc_v6_0_suspend(void *handle) | |
979 | { | |
980 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
981 | ||
df70502e KW |
982 | gmc_v6_0_hw_fini(adev); |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
987 | static int gmc_v6_0_resume(void *handle) | |
988 | { | |
989 | int r; | |
990 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
991 | ||
992 | r = gmc_v6_0_hw_init(adev); | |
993 | if (r) | |
994 | return r; | |
995 | ||
620f774f | 996 | amdgpu_vmid_reset_all(adev); |
df70502e | 997 | |
b3c85a0f | 998 | return 0; |
df70502e KW |
999 | } |
1000 | ||
1001 | static bool gmc_v6_0_is_idle(void *handle) | |
1002 | { | |
1003 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
72518269 | 1004 | u32 tmp = RREG32(mmSRBM_STATUS); |
df70502e KW |
1005 | |
1006 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | | |
1007 | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) | |
1008 | return false; | |
1009 | ||
1010 | return true; | |
1011 | } | |
1012 | ||
1013 | static int gmc_v6_0_wait_for_idle(void *handle) | |
1014 | { | |
1015 | unsigned i; | |
df70502e KW |
1016 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1017 | ||
1018 | for (i = 0; i < adev->usec_timeout; i++) { | |
9c2e1ae3 | 1019 | if (gmc_v6_0_is_idle(handle)) |
df70502e KW |
1020 | return 0; |
1021 | udelay(1); | |
1022 | } | |
1023 | return -ETIMEDOUT; | |
1024 | ||
1025 | } | |
1026 | ||
1027 | static int gmc_v6_0_soft_reset(void *handle) | |
1028 | { | |
1029 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
df70502e | 1030 | u32 srbm_soft_reset = 0; |
72518269 | 1031 | u32 tmp = RREG32(mmSRBM_STATUS); |
df70502e KW |
1032 | |
1033 | if (tmp & SRBM_STATUS__VMC_BUSY_MASK) | |
1034 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, | |
72518269 | 1035 | SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); |
df70502e KW |
1036 | |
1037 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | | |
1038 | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { | |
1039 | if (!(adev->flags & AMD_IS_APU)) | |
1040 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, | |
72518269 | 1041 | SRBM_SOFT_RESET, SOFT_RESET_MC, 1); |
df70502e KW |
1042 | } |
1043 | ||
1044 | if (srbm_soft_reset) { | |
e4f6b39e | 1045 | gmc_v6_0_mc_stop(adev); |
df70502e KW |
1046 | if (gmc_v6_0_wait_for_idle(adev)) { |
1047 | dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); | |
1048 | } | |
1049 | ||
1050 | ||
72518269 | 1051 | tmp = RREG32(mmSRBM_SOFT_RESET); |
df70502e KW |
1052 | tmp |= srbm_soft_reset; |
1053 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
72518269 TSD |
1054 | WREG32(mmSRBM_SOFT_RESET, tmp); |
1055 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
df70502e KW |
1056 | |
1057 | udelay(50); | |
1058 | ||
1059 | tmp &= ~srbm_soft_reset; | |
72518269 TSD |
1060 | WREG32(mmSRBM_SOFT_RESET, tmp); |
1061 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
df70502e KW |
1062 | |
1063 | udelay(50); | |
1064 | ||
e4f6b39e | 1065 | gmc_v6_0_mc_resume(adev); |
df70502e KW |
1066 | udelay(50); |
1067 | } | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, | |
1073 | struct amdgpu_irq_src *src, | |
1074 | unsigned type, | |
1075 | enum amdgpu_interrupt_state state) | |
1076 | { | |
1077 | u32 tmp; | |
1078 | u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
1079 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
1080 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
1081 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
1082 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | |
1083 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); | |
1084 | ||
1085 | switch (state) { | |
1086 | case AMDGPU_IRQ_STATE_DISABLE: | |
72518269 | 1087 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
df70502e | 1088 | tmp &= ~bits; |
72518269 TSD |
1089 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
1090 | tmp = RREG32(mmVM_CONTEXT1_CNTL); | |
df70502e | 1091 | tmp &= ~bits; |
72518269 | 1092 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
df70502e KW |
1093 | break; |
1094 | case AMDGPU_IRQ_STATE_ENABLE: | |
72518269 | 1095 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
df70502e | 1096 | tmp |= bits; |
72518269 TSD |
1097 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
1098 | tmp = RREG32(mmVM_CONTEXT1_CNTL); | |
df70502e | 1099 | tmp |= bits; |
72518269 | 1100 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
df70502e KW |
1101 | break; |
1102 | default: | |
1103 | break; | |
1104 | } | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, | |
1110 | struct amdgpu_irq_src *source, | |
1111 | struct amdgpu_iv_entry *entry) | |
1112 | { | |
1113 | u32 addr, status; | |
1114 | ||
72518269 TSD |
1115 | addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); |
1116 | status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); | |
1117 | WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); | |
df70502e KW |
1118 | |
1119 | if (!addr && !status) | |
1120 | return 0; | |
1121 | ||
1122 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) | |
1123 | gmc_v6_0_set_fault_enable_default(adev, false); | |
1124 | ||
01615881 EC |
1125 | if (printk_ratelimit()) { |
1126 | dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", | |
7ccf5aa8 | 1127 | entry->src_id, entry->src_data[0]); |
01615881 EC |
1128 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
1129 | addr); | |
1130 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", | |
1131 | status); | |
1132 | gmc_v6_0_vm_decode_fault(adev, status, addr, 0); | |
1133 | } | |
df70502e KW |
1134 | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static int gmc_v6_0_set_clockgating_state(void *handle, | |
1139 | enum amd_clockgating_state state) | |
1140 | { | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static int gmc_v6_0_set_powergating_state(void *handle, | |
1145 | enum amd_powergating_state state) | |
1146 | { | |
1147 | return 0; | |
1148 | } | |
1149 | ||
a1255107 | 1150 | static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { |
df70502e KW |
1151 | .name = "gmc_v6_0", |
1152 | .early_init = gmc_v6_0_early_init, | |
1153 | .late_init = gmc_v6_0_late_init, | |
1154 | .sw_init = gmc_v6_0_sw_init, | |
1155 | .sw_fini = gmc_v6_0_sw_fini, | |
1156 | .hw_init = gmc_v6_0_hw_init, | |
1157 | .hw_fini = gmc_v6_0_hw_fini, | |
1158 | .suspend = gmc_v6_0_suspend, | |
1159 | .resume = gmc_v6_0_resume, | |
1160 | .is_idle = gmc_v6_0_is_idle, | |
1161 | .wait_for_idle = gmc_v6_0_wait_for_idle, | |
1162 | .soft_reset = gmc_v6_0_soft_reset, | |
1163 | .set_clockgating_state = gmc_v6_0_set_clockgating_state, | |
1164 | .set_powergating_state = gmc_v6_0_set_powergating_state, | |
1165 | }; | |
1166 | ||
132f34e4 CK |
1167 | static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { |
1168 | .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, | |
4fef88bd | 1169 | .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, |
132f34e4 | 1170 | .set_pte_pde = gmc_v6_0_set_pte_pde, |
f7c35abe | 1171 | .set_prt = gmc_v6_0_set_prt, |
b1166325 | 1172 | .get_vm_pde = gmc_v6_0_get_vm_pde, |
5463545b | 1173 | .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags |
df70502e KW |
1174 | }; |
1175 | ||
1176 | static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { | |
1177 | .set = gmc_v6_0_vm_fault_interrupt_state, | |
1178 | .process = gmc_v6_0_process_interrupt, | |
1179 | }; | |
1180 | ||
132f34e4 | 1181 | static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) |
df70502e | 1182 | { |
132f34e4 CK |
1183 | if (adev->gmc.gmc_funcs == NULL) |
1184 | adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; | |
df70502e KW |
1185 | } |
1186 | ||
1187 | static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) | |
1188 | { | |
770d13b1 CK |
1189 | adev->gmc.vm_fault.num_types = 1; |
1190 | adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; | |
df70502e KW |
1191 | } |
1192 | ||
a1255107 AD |
1193 | const struct amdgpu_ip_block_version gmc_v6_0_ip_block = |
1194 | { | |
1195 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1196 | .major = 6, | |
1197 | .minor = 0, | |
1198 | .rev = 0, | |
1199 | .funcs = &gmc_v6_0_ip_funcs, | |
1200 | }; |