projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: Fix register accesses in GFX v9.4.3
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_4_3.c
CommitLineData
7c0f7ee0
HZ		 1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24
25#include "amdgpu.h"
73c84f7c 26#include "amdgpu_xcp.h"
7c0f7ee0
HZ		 27#include "amdgpu_gfx.h"
28#include "soc15.h"
86301129 29#include "soc15d.h"
7c0f7ee0 30#include "soc15_common.h"
de7511ae 31#include "vega10_enum.h"
7c0f7ee0 32
86301129
LM		 33#include "clearstate_gfx9.h"
34#include "v9_structs.h"
35
36#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
37
7c0f7ee0
HZ		 38#include "gc/gc_9_4_3_offset.h"
39#include "gc/gc_9_4_3_sh_mask.h"
40
41#include "gfx_v9_4_3.h"
8e7fd193 42#include "amdgpu_xcp.h"
7c0f7ee0 43
86301129
LM		 44MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
45MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
46
47#define GFX9_MEC_HPD_SIZE 4096
7c0f7ee0
HZ		 48#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
49
86301129
LM		 50static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
51static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
52static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
53static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
54static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
55 struct amdgpu_cu_info *cu_info);
56
57static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
58 uint64_t queue_mask)
59{
60 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
61 amdgpu_ring_write(kiq_ring,
62 PACKET3_SET_RESOURCES_VMID_MASK(0) |
63 /* vmid_mask:0* queue_type:0 (KIQ) */
64 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
65 amdgpu_ring_write(kiq_ring,
66 lower_32_bits(queue_mask)); /* queue mask lo */
67 amdgpu_ring_write(kiq_ring,
68 upper_32_bits(queue_mask)); /* queue mask hi */
69 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
70 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
71 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
72 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
73}
74
75static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
76 struct amdgpu_ring *ring)
77{
78 struct amdgpu_device *adev = kiq_ring->adev;
79 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
80 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
81 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
82
83 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
84 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
85 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
86 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
87 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
88 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
89 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
90 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
91 /*queue_type: normal compute queue */
92 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
93 /* alloc format: all_on_one_pipe */
94 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
95 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
96 /* num_queues: must be 1 */
97 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
98 amdgpu_ring_write(kiq_ring,
99 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
100 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
101 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
102 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
103 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
104}
105
106static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
107 struct amdgpu_ring *ring,
108 enum amdgpu_unmap_queues_action action,
109 u64 gpu_addr, u64 seq)
110{
111 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
112
113 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
114 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
115 PACKET3_UNMAP_QUEUES_ACTION(action) |
116 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
117 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
118 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
119 amdgpu_ring_write(kiq_ring,
120 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
121
122 if (action == PREEMPT_QUEUES_NO_UNMAP) {
123 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
124 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
125 amdgpu_ring_write(kiq_ring, seq);
126 } else {
127 amdgpu_ring_write(kiq_ring, 0);
128 amdgpu_ring_write(kiq_ring, 0);
129 amdgpu_ring_write(kiq_ring, 0);
130 }
131}
132
133static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
134 struct amdgpu_ring *ring,
135 u64 addr,
136 u64 seq)
137{
138 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
139
140 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
141 amdgpu_ring_write(kiq_ring,
142 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
143 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
144 PACKET3_QUERY_STATUS_COMMAND(2));
145 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
146 amdgpu_ring_write(kiq_ring,
147 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
148 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
149 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
150 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
151 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
152 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
153}
154
155static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
156 uint16_t pasid, uint32_t flush_type,
157 bool all_hub)
158{
159 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
160 amdgpu_ring_write(kiq_ring,
161 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
162 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
163 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
164 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
165}
166
167static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
168 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
169 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
170 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
171 .kiq_query_status = gfx_v9_4_3_kiq_query_status,
172 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
173 .set_resources_size = 8,
174 .map_queues_size = 7,
175 .unmap_queues_size = 6,
176 .query_status_size = 7,
177 .invalidate_tlbs_size = 2,
178};
179
180static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
181{
8078f1c6
LL		 182 int i, num_xcc;
183
184 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
185 for (i = 0; i < num_xcc; i++)
6f917fdc 186 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
86301129
LM		 187}
188
189static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
190{
7aa8a266 191 int i, num_xcc, dev_inst;
86301129 192
8078f1c6 193 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
7aa8a266
LL		 194 for (i = 0; i < num_xcc; i++) {
195 dev_inst = GET_INST(GC, i);
196 if (dev_inst >= 2)
197 WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4);
198 }
86301129
LM		 199}
200
201static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
202 bool wc, uint32_t reg, uint32_t val)
203{
204 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
205 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
206 WRITE_DATA_DST_SEL(0) |
207 (wc ? WR_CONFIRM : 0));
208 amdgpu_ring_write(ring, reg);
209 amdgpu_ring_write(ring, 0);
210 amdgpu_ring_write(ring, val);
211}
212
213static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
214 int mem_space, int opt, uint32_t addr0,
215 uint32_t addr1, uint32_t ref, uint32_t mask,
216 uint32_t inv)
217{
218 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
219 amdgpu_ring_write(ring,
220 /* memory (1) or register (0) */
221 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
222 WAIT_REG_MEM_OPERATION(opt) | /* wait */
223 WAIT_REG_MEM_FUNCTION(3) | /* equal */
224 WAIT_REG_MEM_ENGINE(eng_sel)));
225
226 if (mem_space)
227 BUG_ON(addr0 & 0x3); /* Dword align */
228 amdgpu_ring_write(ring, addr0);
229 amdgpu_ring_write(ring, addr1);
230 amdgpu_ring_write(ring, ref);
231 amdgpu_ring_write(ring, mask);
232 amdgpu_ring_write(ring, inv); /* poll interval */
233}
234
235static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
236{
0b02364e 237 uint32_t scratch_reg0_offset, xcc_offset;
86301129
LM		 238 struct amdgpu_device *adev = ring->adev;
239 uint32_t tmp = 0;
240 unsigned i;
241 int r;
89cf4549 242
0b02364e
LL		 243 /* Use register offset which is local to XCC in the packet */
244 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
659a4ab8 245 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
89cf4549 246 WREG32(scratch_reg0_offset, 0xCAFEDEAD);
86301129 247
86301129
LM		 248 r = amdgpu_ring_alloc(ring, 3);
249 if (r)
250 return r;
251
252 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
0b02364e 253 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
86301129
LM		 254 amdgpu_ring_write(ring, 0xDEADBEEF);
255 amdgpu_ring_commit(ring);
256
257 for (i = 0; i < adev->usec_timeout; i++) {
89cf4549 258 tmp = RREG32(scratch_reg0_offset);
86301129
LM		 259 if (tmp == 0xDEADBEEF)
260 break;
261 udelay(1);
262 }
263
264 if (i >= adev->usec_timeout)
265 r = -ETIMEDOUT;
266 return r;
267}
268
269static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
270{
271 struct amdgpu_device *adev = ring->adev;
272 struct amdgpu_ib ib;
273 struct dma_fence *f = NULL;
274
275 unsigned index;
276 uint64_t gpu_addr;
277 uint32_t tmp;
278 long r;
279
280 r = amdgpu_device_wb_get(adev, &index);
281 if (r)
282 return r;
283
284 gpu_addr = adev->wb.gpu_addr + (index * 4);
285 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
286 memset(&ib, 0, sizeof(ib));
287 r = amdgpu_ib_get(adev, NULL, 16,
288 AMDGPU_IB_POOL_DIRECT, &ib);
289 if (r)
290 goto err1;
291
292 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
293 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
294 ib.ptr[2] = lower_32_bits(gpu_addr);
295 ib.ptr[3] = upper_32_bits(gpu_addr);
296 ib.ptr[4] = 0xDEADBEEF;
297 ib.length_dw = 5;
298
299 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
300 if (r)
301 goto err2;
302
303 r = dma_fence_wait_timeout(f, false, timeout);
304 if (r == 0) {
305 r = -ETIMEDOUT;
306 goto err2;
307 } else if (r < 0) {
308 goto err2;
309 }
310
311 tmp = adev->wb.wb[index];
312 if (tmp == 0xDEADBEEF)
313 r = 0;
314 else
315 r = -EINVAL;
316
317err2:
318 amdgpu_ib_free(adev, &ib, NULL);
319 dma_fence_put(f);
320err1:
321 amdgpu_device_wb_free(adev, index);
322 return r;
323}
324
325
326/* This value might differs per partition */
de7511ae
HZ		 327static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
328{
329 uint64_t clock;
330
331 amdgpu_gfx_off_ctrl(adev, false);
332 mutex_lock(&adev->gfx.gpu_clock_mutex);
659a4ab8
LL		 333 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
334 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |
335 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
de7511ae
HZ		 336 mutex_unlock(&adev->gfx.gpu_clock_mutex);
337 amdgpu_gfx_off_ctrl(adev, true);
338
339 return clock;
340}
341
86301129
LM		 342static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
343{
344 amdgpu_ucode_release(&adev->gfx.pfp_fw);
345 amdgpu_ucode_release(&adev->gfx.me_fw);
346 amdgpu_ucode_release(&adev->gfx.ce_fw);
347 amdgpu_ucode_release(&adev->gfx.rlc_fw);
348 amdgpu_ucode_release(&adev->gfx.mec_fw);
349 amdgpu_ucode_release(&adev->gfx.mec2_fw);
350
351 kfree(adev->gfx.rlc.register_list_format);
352}
353
354static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
355 const char *chip_name)
356{
357 char fw_name[30];
358 int err;
359 const struct rlc_firmware_header_v2_0 *rlc_hdr;
360 uint16_t version_major;
361 uint16_t version_minor;
362
363 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
364
365 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
366 if (err)
367 goto out;
368 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
369
370 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
371 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
372 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
373out:
374 if (err)
375 amdgpu_ucode_release(&adev->gfx.rlc_fw);
376
377 return err;
378}
379
380static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
381{
382 return true;
383}
384
385static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
386{
387 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
388 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
389}
390
391static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
392 const char *chip_name)
393{
394 char fw_name[30];
395 int err;
396
397 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
398
399 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
400 if (err)
401 goto out;
402 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
403 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
404
405 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
406 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
407
408 gfx_v9_4_3_check_if_need_gfxoff(adev);
409
410out:
411 if (err)
412 amdgpu_ucode_release(&adev->gfx.mec_fw);
413 return err;
414}
415
416static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
417{
418 const char *chip_name;
419 int r;
420
421 chip_name = "gc_9_4_3";
422
423 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);
424 if (r)
425 return r;
426
427 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);
428 if (r)
429 return r;
430
431 return r;
432}
433
86301129
LM		 434static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
435{
436 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
437 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
438}
439
440static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
441{
8078f1c6 442 int r, i, num_xcc;
86301129
LM		 443 u32 *hpd;
444 const __le32 *fw_data;
445 unsigned fw_size;
446 u32 *fw;
447 size_t mec_hpd_size;
448
449 const struct gfx_firmware_header_v1_0 *mec_hdr;
450
8078f1c6
LL		 451 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
452 for (i = 0; i < num_xcc; i++)
6f917fdc
LM		 453 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
454 AMDGPU_MAX_COMPUTE_QUEUES);
86301129
LM		 455
456 /* take ownership of the relevant compute queues */
457 amdgpu_gfx_compute_queue_acquire(adev);
d524180b
LL		 458 mec_hpd_size =
459 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
86301129
LM		 460 if (mec_hpd_size) {
461 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
228ce176
RB		 462 AMDGPU_GEM_DOMAIN_VRAM |
463 AMDGPU_GEM_DOMAIN_GTT,
86301129
LM		 464 &adev->gfx.mec.hpd_eop_obj,
465 &adev->gfx.mec.hpd_eop_gpu_addr,
466 (void **)&hpd);
467 if (r) {
468 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
469 gfx_v9_4_3_mec_fini(adev);
470 return r;
471 }
472
473 if (amdgpu_emu_mode == 1) {
474 for (i = 0; i < mec_hpd_size / 4; i++) {
475 memset((void *)(hpd + i), 0, 4);
476 if (i % 50 == 0)
477 msleep(1);
478 }
479 } else {
480 memset(hpd, 0, mec_hpd_size);
481 }
482
483 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
484 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
485 }
486
487 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
488
489 fw_data = (const __le32 *)
490 (adev->gfx.mec_fw->data +
491 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
492 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
493
494 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
496 &adev->gfx.mec.mec_fw_obj,
497 &adev->gfx.mec.mec_fw_gpu_addr,
498 (void **)&fw);
499 if (r) {
500 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
501 gfx_v9_4_3_mec_fini(adev);
502 return r;
503 }
504
505 memcpy(fw, fw_data, fw_size);
506
507 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
508 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
509
510 return 0;
511}
512
880f8b3f
LL		 513static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
514 u32 sh_num, u32 instance, int xcc_id)
de7511ae
HZ		 515{
516 u32 data;
517
518 if (instance == 0xffffffff)
519 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
520 INSTANCE_BROADCAST_WRITES, 1);
521 else
522 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
523 INSTANCE_INDEX, instance);
524
525 if (se_num == 0xffffffff)
526 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
527 SE_BROADCAST_WRITES, 1);
528 else
529 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
530
531 if (sh_num == 0xffffffff)
532 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
533 SH_BROADCAST_WRITES, 1);
534 else
535 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
536
659a4ab8 537 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
de7511ae
HZ		 538}
539
553f973a 540static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)
de7511ae 541{
553f973a 542 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
de7511ae
HZ		 543 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
544 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
545 (address << SQ_IND_INDEX__INDEX__SHIFT) |
546 (SQ_IND_INDEX__FORCE_READ_MASK));
553f973a 547 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
de7511ae
HZ		 548}
549
553f973a 550static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
de7511ae
HZ		 551 uint32_t wave, uint32_t thread,
552 uint32_t regno, uint32_t num, uint32_t *out)
553{
553f973a 554 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
de7511ae
HZ		 555 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
556 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
557 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
558 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
559 (SQ_IND_INDEX__FORCE_READ_MASK) |
560 (SQ_IND_INDEX__AUTO_INCR_MASK));
561 while (num--)
553f973a 562 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
de7511ae
HZ		 563}
564
565static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
553f973a 566 uint32_t xcc_id, uint32_t simd, uint32_t wave,
de7511ae
HZ		 567 uint32_t *dst, int *no_fields)
568{
569 /* type 1 wave data */
570 dst[(*no_fields)++] = 1;
553f973a
TSD		 571 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
572 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
573 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
574 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
575 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
576 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID);
577 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
578 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
579 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC);
580 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC);
581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS);
582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0);
584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0);
585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE);
de7511ae
HZ		 586}
587
553f973a 588static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
de7511ae
HZ		 589 uint32_t wave, uint32_t start,
590 uint32_t size, uint32_t *dst)
591{
553f973a 592 wave_read_regs(adev, xcc_id, simd, wave, 0,
de7511ae
HZ		 593 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
594}
595
553f973a 596static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
de7511ae
HZ		 597 uint32_t wave, uint32_t thread,
598 uint32_t start, uint32_t size,
599 uint32_t *dst)
600{
553f973a 601 wave_read_regs(adev, xcc_id, simd, wave, thread,
de7511ae
HZ		 602 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
603}
604
605static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
553f973a 606 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
de7511ae 607{
553f973a 608 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
de7511ae 609}
ea2d2f8e 610
de7511ae 611
98a54e88 612static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
8e7fd193 613 int num_xccs_per_xcp)
98a54e88 614{
8e7fd193 615 int i, num_xcc;
98a54e88 616 u32 tmp = 0;
98a54e88 617
8078f1c6 618 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
98a54e88 619
8078f1c6 620 for (i = 0; i < num_xcc; i++) {
98a54e88 621 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
8e7fd193 622 num_xccs_per_xcp);
98a54e88 623 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
8e7fd193 624 i % num_xccs_per_xcp);
659a4ab8 625 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp);
98a54e88
LM		 626 }
627
8e7fd193 628 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
98a54e88
LM		 629
630 return 0;
631}
632
98b2e9ca
LM		 633static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
634{
635 int xcc;
636
637 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
638 if (!xcc) {
639 dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
640 return -EINVAL;
641 }
642
643 return xcc - 1;
644}
645
86301129
LM		 646static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
647 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
880f8b3f 648 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
86301129
LM		 649 .read_wave_data = &gfx_v9_4_3_read_wave_data,
650 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
651 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
652 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
98a54e88 653 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
98b2e9ca 654 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
86301129
LM		 655};
656
657static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
658{
659 u32 gb_addr_config;
660
661 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
662
663 switch (adev->ip_versions[GC_HWIP][0]) {
664 case IP_VERSION(9, 4, 3):
665 adev->gfx.config.max_hw_contexts = 8;
666 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
667 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
668 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
669 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
659a4ab8 670 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
86301129
LM		 671 break;
672 default:
673 BUG();
674 break;
675 }
676
677 adev->gfx.config.gb_addr_config = gb_addr_config;
678
679 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
680 REG_GET_FIELD(
681 adev->gfx.config.gb_addr_config,
682 GB_ADDR_CONFIG,
683 NUM_PIPES);
684
685 adev->gfx.config.max_tile_pipes =
686 adev->gfx.config.gb_addr_config_fields.num_pipes;
687
688 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
689 REG_GET_FIELD(
690 adev->gfx.config.gb_addr_config,
691 GB_ADDR_CONFIG,
692 NUM_BANKS);
693 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
694 REG_GET_FIELD(
695 adev->gfx.config.gb_addr_config,
696 GB_ADDR_CONFIG,
697 MAX_COMPRESSED_FRAGS);
698 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
699 REG_GET_FIELD(
700 adev->gfx.config.gb_addr_config,
701 GB_ADDR_CONFIG,
702 NUM_RB_PER_SE);
703 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
704 REG_GET_FIELD(
705 adev->gfx.config.gb_addr_config,
706 GB_ADDR_CONFIG,
707 NUM_SHADER_ENGINES);
708 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
709 REG_GET_FIELD(
710 adev->gfx.config.gb_addr_config,
711 GB_ADDR_CONFIG,
712 PIPE_INTERLEAVE_SIZE));
713
714 return 0;
715}
716
717static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
6f917fdc 718 int xcc_id, int mec, int pipe, int queue)
86301129
LM		 719{
720 unsigned irq_type;
721 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
722 unsigned int hw_prio;
233bb373 723 uint32_t xcc_doorbell_start;
86301129 724
233bb373
LL		 725 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
726 ring_id];
86301129
LM		 727
728 /* mec0 is me1 */
6f917fdc 729 ring->xcc_id = xcc_id;
86301129
LM		 730 ring->me = mec + 1;
731 ring->pipe = pipe;
732 ring->queue = queue;
733
734 ring->ring_obj = NULL;
735 ring->use_doorbell = true;
233bb373
LL		 736 xcc_doorbell_start = adev->doorbell_index.mec_ring0 +
737 xcc_id * adev->doorbell_index.xcc_doorbell_range;
738 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1;
739 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
740 (ring_id + xcc_id * adev->gfx.num_compute_rings) *
741 GFX9_MEC_HPD_SIZE;
3566938b 742 ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
6f917fdc
LM		 743 sprintf(ring->name, "comp_%d.%d.%d.%d",
744 ring->xcc_id, ring->me, ring->pipe, ring->queue);
86301129
LM		 745
746 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
747 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
748 + ring->pipe;
749 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
750 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
751 /* type-2 packets are deprecated on MEC, use type-3 instead */
752 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
753 hw_prio, NULL);
754}
755
756static int gfx_v9_4_3_sw_init(void *handle)
757{
8078f1c6 758 int i, j, k, r, ring_id, xcc_id, num_xcc;
86301129
LM		 759 struct amdgpu_kiq *kiq;
760 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
761
762 adev->gfx.mec.num_mec = 2;
763 adev->gfx.mec.num_pipe_per_mec = 4;
764 adev->gfx.mec.num_queue_per_pipe = 8;
765
8078f1c6
LL		 766 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
767
86301129
LM		 768 /* EOP Event */
769 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
770 if (r)
771 return r;
772
773 /* Privileged reg */
774 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
775 &adev->gfx.priv_reg_irq);
776 if (r)
777 return r;
778
779 /* Privileged inst */
780 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
781 &adev->gfx.priv_inst_irq);
782 if (r)
783 return r;
784
785 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
786
787 r = adev->gfx.rlc.funcs->init(adev);
788 if (r) {
789 DRM_ERROR("Failed to init rlc BOs!\n");
790 return r;
791 }
792
793 r = gfx_v9_4_3_mec_init(adev);
794 if (r) {
795 DRM_ERROR("Failed to init MEC BOs!\n");
796 return r;
797 }
798
799 /* set up the compute queues - allocate horizontally across pipes */
8078f1c6 800 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
233bb373 801 ring_id = 0;
6f917fdc
LM		 802 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
803 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
804 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
805 k++) {
806 if (!amdgpu_gfx_is_mec_queue_enabled(
807 adev, xcc_id, i, k, j))
808 continue;
809
810 r = gfx_v9_4_3_compute_ring_init(adev,
811 ring_id,
812 xcc_id,
813 i, k, j);
814 if (r)
815 return r;
816
817 ring_id++;
818 }
86301129
LM		 819 }
820 }
86301129 821
6f917fdc
LM		 822 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id);
823 if (r) {
824 DRM_ERROR("Failed to init KIQ BOs!\n");
825 return r;
826 }
86301129 827
6f917fdc
LM		 828 kiq = &adev->gfx.kiq[xcc_id];
829 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id);
830 if (r)
831 return r;
86301129 832
6f917fdc
LM		 833 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
834 r = amdgpu_gfx_mqd_sw_init(adev,
835 sizeof(struct v9_mqd_allocation), xcc_id);
836 if (r)
837 return r;
838 }
86301129
LM		 839
840 r = gfx_v9_4_3_gpu_early_init(adev);
841 if (r)
842 return r;
843
98a54e88
LM		 844 r = amdgpu_gfx_sysfs_init(adev);
845 if (r)
846 return r;
847
86301129
LM		 848 return 0;
849}
850
851static int gfx_v9_4_3_sw_fini(void *handle)
852{
8078f1c6 853 int i, num_xcc;
86301129
LM		 854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
855
8078f1c6
LL		 856 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
857 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
86301129
LM		 858 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
859
8078f1c6 860 for (i = 0; i < num_xcc; i++) {
6f917fdc
LM		 861 amdgpu_gfx_mqd_sw_fini(adev, i);
862 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
863 amdgpu_gfx_kiq_fini(adev, i);
864 }
86301129
LM		 865
866 gfx_v9_4_3_mec_fini(adev);
867 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
868 gfx_v9_4_3_free_microcode(adev);
993d218f 869 amdgpu_gfx_sysfs_fini(adev);
86301129
LM		 870
871 return 0;
872}
873
86301129 874#define DEFAULT_SH_MEM_BASES (0x6000)
880f8b3f
LL		 875static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
876 int xcc_id)
86301129
LM		 877{
878 int i;
879 uint32_t sh_mem_config;
880 uint32_t sh_mem_bases;
881
882 /*
883 * Configure apertures:
884 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
885 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
886 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
887 */
888 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
889
890 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
891 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
892 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
893
894 mutex_lock(&adev->srbm_mutex);
895 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
659a4ab8 896 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
86301129 897 /* CP and shaders */
659a4ab8
LL		 898 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);
899 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);
86301129 900 }
659a4ab8 901 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
86301129
LM		 902 mutex_unlock(&adev->srbm_mutex);
903
904 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
905 acccess. These should be enabled by FW for target VMIDs. */
906 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
659a4ab8
LL		 907 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
908 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
909 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);
910 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);
86301129
LM		 911 }
912}
913
880f8b3f 914static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)
86301129
LM		 915{
916 int vmid;
917
918 /*
919 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
920 * access. Compute VMIDs should be enabled by FW for target VMIDs,
921 * the driver can enable them for graphics. VMID0 should maintain
922 * access so that HWS firmware can save/restore entries.
923 */
924 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
659a4ab8
LL		 925 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
926 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
927 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
928 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
86301129
LM		 929 }
930}
931
44b5cf2e
LL		 932static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
933 int xcc_id)
86301129
LM		 934{
935 u32 tmp;
44b5cf2e 936 int i;
86301129
LM		 937
938 /* XXX SH_MEM regs */
939 /* where to put LDS, scratch, GPUVM in FSA64 space */
940 mutex_lock(&adev->srbm_mutex);
f4caf584 941 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
44b5cf2e
LL		 942 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
943 /* CP and shaders */
944 if (i == 0) {
945 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
946 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
947 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
948 !!adev->gmc.noretry);
949 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
950 regSH_MEM_CONFIG, tmp);
951 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
952 regSH_MEM_BASES, 0);
953 } else {
954 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
955 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
956 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
957 !!adev->gmc.noretry);
958 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
959 regSH_MEM_CONFIG, tmp);
960 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
961 (adev->gmc.private_aperture_start >>
962 48));
963 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
964 (adev->gmc.shared_aperture_start >>
965 48));
966 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
967 regSH_MEM_BASES, tmp);
86301129
LM		 968 }
969 }
659a4ab8 970 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
86301129
LM		 971
972 mutex_unlock(&adev->srbm_mutex);
973
44b5cf2e
LL		 974 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
975 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
976}
977
978static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
979{
980 int i, num_xcc;
981
982 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
983
984 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
985 adev->gfx.config.db_debug2 =
986 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
987
988 for (i = 0; i < num_xcc; i++)
989 gfx_v9_4_3_xcc_constants_init(adev, i);
86301129
LM		 990}
991
880f8b3f
LL		 992static void
993gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev,
994 int xcc_id)
86301129 995{
659a4ab8 996 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);
86301129
LM		 997}
998
880f8b3f 999static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)
86301129 1000{
86301129
LM		 1001 /*
1002 * Rlc save restore list is workable since v2_1.
1003 * And it's needed by gfxoff feature.
1004 */
1005 if (adev->gfx.rlc.is_rlc_v2_1)
880f8b3f 1006 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);
86301129
LM		 1007}
1008
880f8b3f 1009static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
86301129
LM		 1010{
1011 uint32_t data;
1012
659a4ab8 1013 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);
86301129 1014 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
659a4ab8 1015 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);
86301129
LM		 1016}
1017
880f8b3f
LL		 1018static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev,
1019 int xcc_id)
e6a02e2c
LL		 1020{
1021 uint32_t tmp = 0;
8078f1c6 1022 int num_xcc;
e6a02e2c 1023
8078f1c6
LL		 1024 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1025 switch (num_xcc) {
e6a02e2c
LL		 1026 /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */
1027 case 1:
659a4ab8 1028 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, 0x8);
e6a02e2c
LL		 1029 break;
1030 case 2:
1031 tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID);
a8027fcd 1032 tmp = tmp | (adev->gfx.num_xcc_per_xcp << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP));
659a4ab8 1033 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, tmp);
e6a02e2c 1034
e6a02e2c
LL		 1035 break;
1036 default:
1037 break;
1038 }
1039}
1040
7c0f7ee0
HZ		 1041static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
1042{
1043 uint32_t rlc_setting;
1044
1045 /* if RLC is not enabled, do nothing */
659a4ab8 1046 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);
7c0f7ee0
HZ		 1047 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
1048 return false;
1049
1050 return true;
1051}
1052
880f8b3f 1053static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7c0f7ee0
HZ		 1054{
1055 uint32_t data;
1056 unsigned i;
1057
1058 data = RLC_SAFE_MODE__CMD_MASK;
1059 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
659a4ab8 1060 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
7c0f7ee0
HZ		 1061
1062 /* wait for RLC_SAFE_MODE */
1063 for (i = 0; i < adev->usec_timeout; i++) {
1e91a5f7 1064 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
7c0f7ee0
HZ		 1065 break;
1066 udelay(1);
1067 }
1068}
1069
880f8b3f
LL		 1070static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev,
1071 int xcc_id)
7c0f7ee0
HZ		 1072{
1073 uint32_t data;
1074
1075 data = RLC_SAFE_MODE__CMD_MASK;
659a4ab8 1076 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
7c0f7ee0
HZ		 1077}
1078
1079static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1080{
1081 /* init spm vmid with 0xf */
1082 if (adev->gfx.rlc.funcs->update_spm_vmid)
1083 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1084
1085 return 0;
1086}
1087
880f8b3f
LL		 1088static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev,
1089 int xcc_id)
7c0f7ee0
HZ		 1090{
1091 u32 i, j, k;
1092 u32 mask;
1093
1094 mutex_lock(&adev->grbm_idx_mutex);
1095 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1096 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
880f8b3f
LL		 1097 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1098 xcc_id);
7c0f7ee0 1099 for (k = 0; k < adev->usec_timeout; k++) {
1e91a5f7 1100 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)
7c0f7ee0
HZ		 1101 break;
1102 udelay(1);
1103 }
1104 if (k == adev->usec_timeout) {
880f8b3f
LL		 1105 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1106 0xffffffff,
1107 0xffffffff, xcc_id);
7c0f7ee0
HZ		 1108 mutex_unlock(&adev->grbm_idx_mutex);
1109 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1110 i, j);
1111 return;
1112 }
1113 }
1114 }
880f8b3f
LL		 1115 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
1116 xcc_id);
7c0f7ee0
HZ		 1117 mutex_unlock(&adev->grbm_idx_mutex);
1118
1119 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1120 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1121 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1122 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1123 for (k = 0; k < adev->usec_timeout; k++) {
1e91a5f7 1124 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
7c0f7ee0
HZ		 1125 break;
1126 udelay(1);
1127 }
1128}
1129
880f8b3f
LL		 1130static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1131 bool enable, int xcc_id)
7c0f7ee0
HZ		 1132{
1133 u32 tmp;
1134
1135 /* These interrupts should be enabled to drive DS clock */
1136
659a4ab8 1137 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
7c0f7ee0
HZ		 1138
1139 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1140 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1141 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
7c0f7ee0 1142
659a4ab8 1143 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
7c0f7ee0
HZ		 1144}
1145
44b5cf2e
LL		 1146static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1147{
1148 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1149 RLC_ENABLE_F32, 0);
1150 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1151 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1152}
1153
7c0f7ee0
HZ		 1154static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1155{
8078f1c6 1156 int i, num_xcc;
6f917fdc 1157
8078f1c6 1158 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
44b5cf2e
LL		 1159 for (i = 0; i < num_xcc; i++)
1160 gfx_v9_4_3_xcc_rlc_stop(adev, i);
1161}
1162
1163static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1164{
1165 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1166 SOFT_RESET_RLC, 1);
1167 udelay(50);
1168 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1169 SOFT_RESET_RLC, 0);
1170 udelay(50);
7c0f7ee0
HZ		 1171}
1172
1173static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
1174{
8078f1c6 1175 int i, num_xcc;
6f917fdc 1176
8078f1c6 1177 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
44b5cf2e
LL		 1178 for (i = 0; i < num_xcc; i++)
1179 gfx_v9_4_3_xcc_rlc_reset(adev, i);
1180}
1181
1182static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1183{
1184 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1185 RLC_ENABLE_F32, 1);
1186 udelay(50);
1187
1188 /* carrizo do enable cp interrupt after cp inited */
1189 if (!(adev->flags & AMD_IS_APU)) {
1190 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
6f917fdc
LM		 1191 udelay(50);
1192 }
7c0f7ee0
HZ		 1193}
1194
1195static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev)
1196{
1197#ifdef AMDGPU_RLC_DEBUG_RETRY
1198 u32 rlc_ucode_ver;
1199#endif
8078f1c6 1200 int i, num_xcc;
7c0f7ee0 1201
8078f1c6
LL		 1202 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1203 for (i = 0; i < num_xcc; i++) {
44b5cf2e 1204 gfx_v9_4_3_xcc_rlc_start(adev, i);
7c0f7ee0 1205#ifdef AMDGPU_RLC_DEBUG_RETRY
6f917fdc 1206 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
659a4ab8 1207 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
6f917fdc
LM		 1208 if (rlc_ucode_ver == 0x108) {
1209 dev_info(adev->dev,
1210 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1211 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1212 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1213 * default is 0x9C4 to create a 100us interval */
659a4ab8 1214 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);
6f917fdc
LM		 1215 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1216 * to disable the page fault retry interrupts, default is
1217 * 0x100 (256) */
659a4ab8 1218 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);
6f917fdc 1219 }
7c0f7ee0 1220#endif
6f917fdc 1221 }
7c0f7ee0
HZ		 1222}
1223
880f8b3f
LL		 1224static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev,
1225 int xcc_id)
7c0f7ee0
HZ		 1226{
1227 const struct rlc_firmware_header_v2_0 *hdr;
1228 const __le32 *fw_data;
1229 unsigned i, fw_size;
1230
1231 if (!adev->gfx.rlc_fw)
1232 return -EINVAL;
1233
1234 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1235 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1236
1237 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1238 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1239 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1240
659a4ab8 1241 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,
7c0f7ee0
HZ		 1242 RLCG_UCODE_LOADING_START_ADDRESS);
1243 for (i = 0; i < fw_size; i++) {
1244 if (amdgpu_emu_mode == 1 && i % 100 == 0) {
1245 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i);
1246 msleep(1);
1247 }
659a4ab8 1248 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
7c0f7ee0 1249 }
659a4ab8 1250 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
7c0f7ee0
HZ		 1251
1252 return 0;
1253}
1254
44b5cf2e 1255static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
7c0f7ee0 1256{
44b5cf2e 1257 int r;
7c0f7ee0 1258
44b5cf2e 1259 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
7c0f7ee0 1260
44b5cf2e
LL		 1261 /* disable CG */
1262 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
7c0f7ee0 1263
44b5cf2e 1264 gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
7c0f7ee0 1265
44b5cf2e
LL		 1266 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1267 /* legacy rlc firmware loading */
1268 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1269 if (r)
1270 return r;
7c0f7ee0
HZ		 1271 }
1272
44b5cf2e
LL		 1273 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1274
1275 return 0;
1276}
1277
1278static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1279{
1280 int r, i, num_xcc;
1281
1282 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1283 for (i = 0; i < num_xcc; i++) {
1284 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1285 if (r)
1286 return r;
1287 }
7c0f7ee0
HZ		 1288
1289 return 0;
1290}
1291
6f917fdc
LM		 1292static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
1293 unsigned vmid)
7c0f7ee0
HZ		 1294{
1295 u32 reg, data;
1296
659a4ab8 1297 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
7c0f7ee0
HZ		 1298 if (amdgpu_sriov_is_pp_one_vf(adev))
1299 data = RREG32_NO_KIQ(reg);
1300 else
1301 data = RREG32(reg);
1302
1303 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
1304 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1305
1306 if (amdgpu_sriov_is_pp_one_vf(adev))
659a4ab8 1307 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
7c0f7ee0 1308 else
659a4ab8 1309 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
7c0f7ee0
HZ		 1310}
1311
1312static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {
1313 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1314 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1315};
1316
1317static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
1318 uint32_t offset,
1319 struct soc15_reg_rlcg *entries, int arr_size)
1320{
659a4ab8 1321 int i, inst;
7c0f7ee0
HZ		 1322 uint32_t reg;
1323
1324 if (!entries)
1325 return false;
1326
1327 for (i = 0; i < arr_size; i++) {
1328 const struct soc15_reg_rlcg *entry;
1329
1330 entry = &entries[i];
659a4ab8
LL		 1331 inst = adev->ip_map.logical_to_dev_inst ?
1332 adev->ip_map.logical_to_dev_inst(
1333 adev, entry->hwip, entry->instance) :
1334 entry->instance;
1335 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
1336 entry->reg;
7c0f7ee0
HZ		 1337 if (offset == reg)
1338 return true;
1339 }
1340
1341 return false;
1342}
1343
1344static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
1345{
1346 return gfx_v9_4_3_check_rlcg_range(adev, offset,
1347 (void *)rlcg_access_gc_9_4_3,
1348 ARRAY_SIZE(rlcg_access_gc_9_4_3));
1349}
1350
880f8b3f
LL		 1351static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
1352 bool enable, int xcc_id)
86301129
LM		 1353{
1354 if (enable) {
659a4ab8 1355 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
86301129 1356 } else {
659a4ab8 1357 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
86301129 1358 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6f917fdc 1359 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
86301129
LM		 1360 }
1361 udelay(50);
1362}
de7511ae 1363
880f8b3f
LL		 1364static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev,
1365 int xcc_id)
86301129
LM		 1366{
1367 const struct gfx_firmware_header_v1_0 *mec_hdr;
1368 const __le32 *fw_data;
1369 unsigned i;
1370 u32 tmp;
1371 u32 mec_ucode_addr_offset;
1372 u32 mec_ucode_data_offset;
1373
1374 if (!adev->gfx.mec_fw)
1375 return -EINVAL;
1376
880f8b3f 1377 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
86301129
LM		 1378
1379 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1380 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1381
1382 fw_data = (const __le32 *)
1383 (adev->gfx.mec_fw->data +
1384 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1385 tmp = 0;
1386 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1387 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
659a4ab8 1388 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
86301129 1389
659a4ab8 1390 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,
86301129 1391 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
659a4ab8 1392 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,
86301129
LM		 1393 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1394
1395 mec_ucode_addr_offset =
659a4ab8 1396 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
86301129 1397 mec_ucode_data_offset =
659a4ab8 1398 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
86301129
LM		 1399
1400 /* MEC1 */
1401 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
1402 for (i = 0; i < mec_hdr->jt_size; i++)
1403 WREG32(mec_ucode_data_offset,
1404 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1405
1406 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1407 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1408
1409 return 0;
1410}
1411
1412/* KIQ functions */
880f8b3f 1413static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
86301129
LM		 1414{
1415 uint32_t tmp;
1416 struct amdgpu_device *adev = ring->adev;
1417
1418 /* tell RLC which is KIQ queue */
659a4ab8 1419 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
86301129
LM		 1420 tmp &= 0xffffff00;
1421 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
659a4ab8 1422 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
86301129 1423 tmp |= 0x80;
659a4ab8 1424 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
86301129
LM		 1425}
1426
1427static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
1428{
1429 struct amdgpu_device *adev = ring->adev;
1430
1431 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1432 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
1433 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
1434 mqd->cp_hqd_queue_priority =
1435 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
1436 }
1437 }
1438}
1439
c1d3f627 1440static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
86301129
LM		 1441{
1442 struct amdgpu_device *adev = ring->adev;
1443 struct v9_mqd *mqd = ring->mqd_ptr;
1444 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1445 uint32_t tmp;
1446
1447 mqd->header = 0xC0310800;
1448 mqd->compute_pipelinestat_enable = 0x00000001;
1449 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1450 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1451 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1452 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1453 mqd->compute_misc_reserved = 0x00000003;
1454
1455 mqd->dynamic_cu_mask_addr_lo =
1456 lower_32_bits(ring->mqd_gpu_addr
1457 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1458 mqd->dynamic_cu_mask_addr_hi =
1459 upper_32_bits(ring->mqd_gpu_addr
1460 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1461
1462 eop_base_addr = ring->eop_gpu_addr >> 8;
1463 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1464 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1465
1466 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
c1d3f627 1467 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
86301129
LM		 1468 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1469 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
1470
1471 mqd->cp_hqd_eop_control = tmp;
1472
1473 /* enable doorbell? */
c1d3f627 1474 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
86301129
LM		 1475
1476 if (ring->use_doorbell) {
1477 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1478 DOORBELL_OFFSET, ring->doorbell_index);
1479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1480 DOORBELL_EN, 1);
1481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1482 DOORBELL_SOURCE, 0);
1483 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1484 DOORBELL_HIT, 0);
1485 } else {
1486 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1487 DOORBELL_EN, 0);
1488 }
1489
1490 mqd->cp_hqd_pq_doorbell_control = tmp;
1491
1492 /* disable the queue if it's active */
1493 ring->wptr = 0;
1494 mqd->cp_hqd_dequeue_request = 0;
1495 mqd->cp_hqd_pq_rptr = 0;
1496 mqd->cp_hqd_pq_wptr_lo = 0;
1497 mqd->cp_hqd_pq_wptr_hi = 0;
1498
1499 /* set the pointer to the MQD */
1500 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1501 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1502
1503 /* set MQD vmid to 0 */
c1d3f627 1504 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
86301129
LM		 1505 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1506 mqd->cp_mqd_control = tmp;
1507
1508 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1509 hqd_gpu_addr = ring->gpu_addr >> 8;
1510 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1511 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1512
1513 /* set up the HQD, this is similar to CP_RB0_CNTL */
c1d3f627 1514 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
86301129
LM		 1515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1516 (order_base_2(ring->ring_size / 4) - 1));
1517 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1518 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1519#ifdef __BIG_ENDIAN
1520 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1521#endif
1522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1523 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1524 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1525 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1526 mqd->cp_hqd_pq_control = tmp;
1527
1528 /* set the wb address whether it's enabled or not */
1529 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1530 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1531 mqd->cp_hqd_pq_rptr_report_addr_hi =
1532 upper_32_bits(wb_gpu_addr) & 0xffff;
1533
1534 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1535 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1536 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1537 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1538
1539 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1540 ring->wptr = 0;
c1d3f627 1541 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);
86301129
LM		 1542
1543 /* set the vmid for the queue */
1544 mqd->cp_hqd_vmid = 0;
1545
c1d3f627 1546 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
86301129
LM		 1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1548 mqd->cp_hqd_persistent_state = tmp;
1549
1550 /* set MIN_IB_AVAIL_SIZE */
c1d3f627 1551 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
86301129
LM		 1552 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1553 mqd->cp_hqd_ib_control = tmp;
1554
1555 /* set static priority for a queue/ring */
1556 gfx_v9_4_3_mqd_set_priority(ring, mqd);
c1d3f627 1557 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
86301129
LM		 1558
1559 /* map_queues packet doesn't need activate the queue,
1560 * so only kiq need set this field.
1561 */
1562 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
1563 mqd->cp_hqd_active = 1;
1564
1565 return 0;
1566}
1567
880f8b3f
LL		 1568static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring,
1569 int xcc_id)
86301129
LM		 1570{
1571 struct amdgpu_device *adev = ring->adev;
1572 struct v9_mqd *mqd = ring->mqd_ptr;
1573 int j;
1574
1575 /* disable wptr polling */
5a8b26a8 1576 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
86301129 1577
659a4ab8 1578 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,
86301129 1579 mqd->cp_hqd_eop_base_addr_lo);
659a4ab8 1580 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,
86301129
LM		 1581 mqd->cp_hqd_eop_base_addr_hi);
1582
1583 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
659a4ab8 1584 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,
86301129
LM		 1585 mqd->cp_hqd_eop_control);
1586
1587 /* enable doorbell? */
659a4ab8 1588 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
86301129
LM		 1589 mqd->cp_hqd_pq_doorbell_control);
1590
1591 /* disable the queue if it's active */
659a4ab8
LL		 1592 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1593 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
86301129 1594 for (j = 0; j < adev->usec_timeout; j++) {
659a4ab8 1595 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
86301129
LM		 1596 break;
1597 udelay(1);
1598 }
659a4ab8 1599 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
86301129 1600 mqd->cp_hqd_dequeue_request);
659a4ab8 1601 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,
86301129 1602 mqd->cp_hqd_pq_rptr);
659a4ab8 1603 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
86301129 1604 mqd->cp_hqd_pq_wptr_lo);
659a4ab8 1605 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
86301129
LM		 1606 mqd->cp_hqd_pq_wptr_hi);
1607 }
1608
1609 /* set the pointer to the MQD */
659a4ab8 1610 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,
86301129 1611 mqd->cp_mqd_base_addr_lo);
659a4ab8 1612 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,
86301129
LM		 1613 mqd->cp_mqd_base_addr_hi);
1614
1615 /* set MQD vmid to 0 */
659a4ab8 1616 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,
86301129
LM		 1617 mqd->cp_mqd_control);
1618
1619 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
659a4ab8 1620 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,
86301129 1621 mqd->cp_hqd_pq_base_lo);
659a4ab8 1622 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,
86301129
LM		 1623 mqd->cp_hqd_pq_base_hi);
1624
1625 /* set up the HQD, this is similar to CP_RB0_CNTL */
659a4ab8 1626 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,
86301129
LM		 1627 mqd->cp_hqd_pq_control);
1628
1629 /* set the wb address whether it's enabled or not */
659a4ab8 1630 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
86301129 1631 mqd->cp_hqd_pq_rptr_report_addr_lo);
659a4ab8 1632 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
86301129
LM		 1633 mqd->cp_hqd_pq_rptr_report_addr_hi);
1634
1635 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
659a4ab8 1636 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
86301129 1637 mqd->cp_hqd_pq_wptr_poll_addr_lo);
659a4ab8 1638 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
86301129
LM		 1639 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1640
1641 /* enable the doorbell if requested */
1642 if (ring->use_doorbell) {
233bb373
LL		 1643 WREG32_SOC15(
1644 GC, GET_INST(GC, xcc_id),
1645 regCP_MEC_DOORBELL_RANGE_LOWER,
1646 ((adev->doorbell_index.kiq +
1647 xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1648 2) << 2);
1649 WREG32_SOC15(
1650 GC, GET_INST(GC, xcc_id),
1651 regCP_MEC_DOORBELL_RANGE_UPPER,
1652 ((adev->doorbell_index.userqueue_end +
1653 xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1654 2) << 2);
86301129
LM		 1655 }
1656
659a4ab8 1657 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
86301129
LM		 1658 mqd->cp_hqd_pq_doorbell_control);
1659
1660 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
659a4ab8 1661 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
86301129 1662 mqd->cp_hqd_pq_wptr_lo);
659a4ab8 1663 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
86301129
LM		 1664 mqd->cp_hqd_pq_wptr_hi);
1665
1666 /* set the vmid for the queue */
659a4ab8 1667 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);
86301129 1668
659a4ab8 1669 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
86301129
LM		 1670 mqd->cp_hqd_persistent_state);
1671
1672 /* activate the queue */
659a4ab8 1673 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,
86301129
LM		 1674 mqd->cp_hqd_active);
1675
1676 if (ring->use_doorbell)
5a8b26a8 1677 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);
86301129
LM		 1678
1679 return 0;
1680}
1681
fee500fa 1682static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring,
880f8b3f 1683 int xcc_id)
86301129
LM		 1684{
1685 struct amdgpu_device *adev = ring->adev;
1686 int j;
1687
1688 /* disable the queue if it's active */
659a4ab8 1689 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
86301129 1690
659a4ab8 1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
86301129
LM		 1692
1693 for (j = 0; j < adev->usec_timeout; j++) {
659a4ab8 1694 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
86301129
LM		 1695 break;
1696 udelay(1);
1697 }
1698
1699 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
fee500fa 1700 DRM_DEBUG("%s dequeue request failed.\n", ring->name);
86301129
LM		 1701
1702 /* Manual disable if dequeue request times out */
659a4ab8 1703 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);
86301129
LM		 1704 }
1705
659a4ab8 1706 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
86301129
LM		 1707 0);
1708 }
1709
659a4ab8
LL		 1710 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
1711 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
1712 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0);
1713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
1714 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1715 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1716 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1717 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
86301129
LM		 1718
1719 return 0;
1720}
1721
880f8b3f 1722static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
86301129
LM		 1723{
1724 struct amdgpu_device *adev = ring->adev;
1725 struct v9_mqd *mqd = ring->mqd_ptr;
1726 struct v9_mqd *tmp_mqd;
1727
880f8b3f 1728 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id);
86301129
LM		 1729
1730 /* GPU could be in bad state during probe, driver trigger the reset
1731 * after load the SMU, in this case , the mqd is not be initialized.
1732 * driver need to re-init the mqd.
1733 * check mqd->cp_hqd_pq_control since this value should not be 0
1734 */
6f917fdc 1735 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
86301129
LM		 1736 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
1737 /* for GPU_RESET case , reset MQD to a clean status */
6f917fdc
LM		 1738 if (adev->gfx.kiq[xcc_id].mqd_backup)
1739 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
86301129
LM		 1740
1741 /* reset ring buffer */
1742 ring->wptr = 0;
1743 amdgpu_ring_clear_ring(ring);
86301129 1744 mutex_lock(&adev->srbm_mutex);
659a4ab8 1745 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
880f8b3f 1746 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
659a4ab8 1747 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
86301129
LM		 1748 mutex_unlock(&adev->srbm_mutex);
1749 } else {
1750 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1751 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1752 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1753 mutex_lock(&adev->srbm_mutex);
659a4ab8 1754 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
c1d3f627 1755 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
880f8b3f 1756 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
659a4ab8 1757 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
86301129
LM		 1758 mutex_unlock(&adev->srbm_mutex);
1759
6f917fdc
LM		 1760 if (adev->gfx.kiq[xcc_id].mqd_backup)
1761 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
86301129
LM		 1762 }
1763
1764 return 0;
1765}
1766
880f8b3f 1767static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)
86301129
LM		 1768{
1769 struct amdgpu_device *adev = ring->adev;
1770 struct v9_mqd *mqd = ring->mqd_ptr;
1771 int mqd_idx = ring - &adev->gfx.compute_ring[0];
1772 struct v9_mqd *tmp_mqd;
1773
1774 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
1775 * is not be initialized before
1776 */
1777 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1778
1779 if (!tmp_mqd->cp_hqd_pq_control ||
1780 (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
1781 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1782 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1783 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1784 mutex_lock(&adev->srbm_mutex);
659a4ab8 1785 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
c1d3f627 1786 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
659a4ab8 1787 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
86301129
LM		 1788 mutex_unlock(&adev->srbm_mutex);
1789
1790 if (adev->gfx.mec.mqd_backup[mqd_idx])
1791 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
45b54a7d
AD		 1792 } else {
1793 /* restore MQD to a clean status */
86301129
LM		 1794 if (adev->gfx.mec.mqd_backup[mqd_idx])
1795 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
86301129
LM		 1796 /* reset ring buffer */
1797 ring->wptr = 0;
1798 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
1799 amdgpu_ring_clear_ring(ring);
86301129
LM		 1800 }
1801
1802 return 0;
1803}
1804
fee500fa
SZ		 1805static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)
1806{
1807 struct amdgpu_ring *ring;
1808 int j;
1809
1810 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1811 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings];
1812 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1813 mutex_lock(&adev->srbm_mutex);
1814 soc15_grbm_select(adev, ring->me,
1815 ring->pipe,
1816 ring->queue, 0, GET_INST(GC, xcc_id));
1817 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id);
1818 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1819 mutex_unlock(&adev->srbm_mutex);
1820 }
1821 }
1822
1823 return 0;
1824}
1825
880f8b3f 1826static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
86301129
LM		 1827{
1828 struct amdgpu_ring *ring;
1829 int r;
1830
6f917fdc 1831 ring = &adev->gfx.kiq[xcc_id].ring;
86301129
LM		 1832
1833 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1834 if (unlikely(r != 0))
1835 return r;
1836
1837 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
f4409a23
DC		 1838 if (unlikely(r != 0)) {
1839 amdgpu_bo_unreserve(ring->mqd_obj);
86301129 1840 return r;
f4409a23 1841 }
86301129 1842
880f8b3f 1843 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
86301129
LM		 1844 amdgpu_bo_kunmap(ring->mqd_obj);
1845 ring->mqd_ptr = NULL;
1846 amdgpu_bo_unreserve(ring->mqd_obj);
1847 ring->sched.ready = true;
1848 return 0;
1849}
1850
880f8b3f 1851static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
86301129
LM		 1852{
1853 struct amdgpu_ring *ring = NULL;
1854 int r = 0, i;
1855
880f8b3f 1856 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
86301129
LM		 1857
1858 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6f917fdc 1859 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
86301129
LM		 1860
1861 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1862 if (unlikely(r != 0))
1863 goto done;
1864 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1865 if (!r) {
880f8b3f 1866 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);
86301129
LM		 1867 amdgpu_bo_kunmap(ring->mqd_obj);
1868 ring->mqd_ptr = NULL;
1869 }
1870 amdgpu_bo_unreserve(ring->mqd_obj);
1871 if (r)
1872 goto done;
1873 }
1874
6f917fdc 1875 r = amdgpu_gfx_enable_kcq(adev, xcc_id);
86301129
LM		 1876done:
1877 return r;
1878}
1879
44b5cf2e 1880static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
86301129 1881{
86301129 1882 struct amdgpu_ring *ring;
44b5cf2e 1883 int r, j;
86301129 1884
44b5cf2e 1885 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
6f917fdc 1886
44b5cf2e
LL		 1887 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1888 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
86301129 1889
44b5cf2e
LL		 1890 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1891 if (r)
1892 return r;
1893 }
86301129 1894
44b5cf2e
LL		 1895 /* set the virtual and physical id based on partition_mode */
1896 gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id);
e6a02e2c 1897
44b5cf2e
LL		 1898 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
1899 if (r)
1900 return r;
1901
1902 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
1903 if (r)
1904 return r;
86301129 1905
44b5cf2e
LL		 1906 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1907 ring = &adev->gfx.compute_ring
1908 [j + xcc_id * adev->gfx.num_compute_rings];
1909 r = amdgpu_ring_test_helper(ring);
6f917fdc
LM		 1910 if (r)
1911 return r;
44b5cf2e 1912 }
86301129 1913
44b5cf2e 1914 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
86301129 1915
44b5cf2e
LL		 1916 return 0;
1917}
1918
1919static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
1920{
1921 int r, i, num_xcc;
1922
ded7d99e
LL		 1923 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1924 AMDGPU_XCP_FL_NONE) ==
1925 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
b6b85c8b
LL		 1926 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr,
1927 amdgpu_user_partt_mode);
1928
1929 if (r)
1930 return r;
8e7fd193 1931
44b5cf2e
LL		 1932 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1933 for (i = 0; i < num_xcc; i++) {
1934 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
1935 if (r)
1936 return r;
86301129
LM		 1937 }
1938
86301129
LM		 1939 return 0;
1940}
1941
880f8b3f
LL		 1942static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,
1943 int xcc_id)
86301129 1944{
880f8b3f 1945 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
86301129
LM		 1946}
1947
44b5cf2e
LL		 1948static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
1949{
1950 if (amdgpu_gfx_disable_kcq(adev, xcc_id))
1951 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
1952
1953 /* Use deinitialize sequence from CAIL when unbinding device
1954 * from driver, otherwise KIQ is hanging when binding back
1955 */
1956 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1957 mutex_lock(&adev->srbm_mutex);
1958 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
1959 adev->gfx.kiq[xcc_id].ring.pipe,
1960 adev->gfx.kiq[xcc_id].ring.queue, 0,
1961 GET_INST(GC, xcc_id));
fee500fa 1962 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
44b5cf2e
LL		 1963 xcc_id);
1964 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1965 mutex_unlock(&adev->srbm_mutex);
1966 }
1967
fee500fa 1968 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
44b5cf2e
LL		 1969 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
1970
1971 /* Skip suspend with A+A reset */
1972 if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) {
1973 dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n");
1974 return;
1975 }
1976
1977 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1978}
1979
86301129
LM		 1980static int gfx_v9_4_3_hw_init(void *handle)
1981{
1982 int r;
1983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1984
1985 gfx_v9_4_3_init_golden_registers(adev);
1986
1987 gfx_v9_4_3_constants_init(adev);
1988
1989 r = adev->gfx.rlc.funcs->resume(adev);
1990 if (r)
1991 return r;
1992
1993 r = gfx_v9_4_3_cp_resume(adev);
1994 if (r)
1995 return r;
1996
1997 return r;
1998}
1999
2000static int gfx_v9_4_3_hw_fini(void *handle)
2001{
2002 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8078f1c6 2003 int i, num_xcc;
86301129
LM		 2004
2005 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2006 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2007
8078f1c6
LL		 2008 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2009 for (i = 0; i < num_xcc; i++) {
44b5cf2e 2010 gfx_v9_4_3_xcc_fini(adev, i);
86301129
LM		 2011 }
2012
86301129
LM		 2013 return 0;
2014}
2015
2016static int gfx_v9_4_3_suspend(void *handle)
2017{
2018 return gfx_v9_4_3_hw_fini(handle);
2019}
2020
2021static int gfx_v9_4_3_resume(void *handle)
2022{
2023 return gfx_v9_4_3_hw_init(handle);
2024}
2025
2026static bool gfx_v9_4_3_is_idle(void *handle)
2027{
2028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8078f1c6 2029 int i, num_xcc;
86301129 2030
8078f1c6
LL		 2031 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2032 for (i = 0; i < num_xcc; i++) {
659a4ab8 2033 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
6f917fdc
LM		 2034 GRBM_STATUS, GUI_ACTIVE))
2035 return false;
2036 }
2037 return true;
86301129
LM		 2038}
2039
2040static int gfx_v9_4_3_wait_for_idle(void *handle)
2041{
2042 unsigned i;
2043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2044
2045 for (i = 0; i < adev->usec_timeout; i++) {
2046 if (gfx_v9_4_3_is_idle(handle))
2047 return 0;
2048 udelay(1);
2049 }
2050 return -ETIMEDOUT;
2051}
2052
2053static int gfx_v9_4_3_soft_reset(void *handle)
2054{
2055 u32 grbm_soft_reset = 0;
2056 u32 tmp;
2057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2058
2059 /* GRBM_STATUS */
659a4ab8 2060 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
86301129
LM		 2061 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2062 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2063 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2064 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2065 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2066 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2067 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2068 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2069 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2070 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2071 }
2072
2073 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2074 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2075 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2076 }
2077
2078 /* GRBM_STATUS2 */
659a4ab8 2079 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
86301129
LM		 2080 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2081 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2082 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2083
2084
2085 if (grbm_soft_reset) {
2086 /* stop the rlc */
2087 adev->gfx.rlc.funcs->stop(adev);
2088
2089 /* Disable MEC parsing/prefetching */
880f8b3f 2090 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
86301129
LM		 2091
2092 if (grbm_soft_reset) {
659a4ab8 2093 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
86301129
LM		 2094 tmp |= grbm_soft_reset;
2095 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
659a4ab8
LL		 2096 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2097 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
86301129
LM		 2098
2099 udelay(50);
2100
2101 tmp &= ~grbm_soft_reset;
659a4ab8
LL		 2102 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2103 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
86301129
LM		 2104 }
2105
2106 /* Wait a little for things to settle down */
2107 udelay(50);
2108 }
2109 return 0;
2110}
2111
2112static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
2113 uint32_t vmid,
2114 uint32_t gds_base, uint32_t gds_size,
2115 uint32_t gws_base, uint32_t gws_size,
2116 uint32_t oa_base, uint32_t oa_size)
2117{
2118 struct amdgpu_device *adev = ring->adev;
2119
2120 /* GDS Base */
2121 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
659a4ab8 2122 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
86301129
LM		 2123 gds_base);
2124
2125 /* GDS Size */
2126 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
659a4ab8 2127 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
86301129
LM		 2128 gds_size);
2129
2130 /* GWS */
2131 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
659a4ab8 2132 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
86301129
LM		 2133 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2134
2135 /* OA */
2136 gfx_v9_4_3_write_data_to_reg(ring, 0, false,
659a4ab8 2137 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
86301129
LM		 2138 (1 << (oa_size + oa_base)) - (1 << oa_base));
2139}
2140
2141static int gfx_v9_4_3_early_init(void *handle)
2142{
2143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8078f1c6 2144 int num_xcc;
86301129 2145
8078f1c6 2146 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
0fa49d10 2147
86301129
LM		 2148 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2149 AMDGPU_MAX_COMPUTE_RINGS);
2150 gfx_v9_4_3_set_kiq_pm4_funcs(adev);
2151 gfx_v9_4_3_set_ring_funcs(adev);
2152 gfx_v9_4_3_set_irq_funcs(adev);
2153 gfx_v9_4_3_set_gds_init(adev);
2154 gfx_v9_4_3_set_rlc_funcs(adev);
2155
2156 return gfx_v9_4_3_init_microcode(adev);
2157}
2158
2159static int gfx_v9_4_3_late_init(void *handle)
2160{
2161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2162 int r;
2163
2164 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2165 if (r)
2166 return r;
2167
2168 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2169 if (r)
2170 return r;
2171
2172 return 0;
2173}
2174
34fd9d68
LL		 2175static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev,
2176 bool enable, int xcc_id)
2177{
2178 uint32_t def, data;
2179
2180 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
2181 return;
2182
2183 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2184 regRLC_CGTT_MGCG_OVERRIDE);
2185
2186 if (enable)
2187 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2188 else
2189 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2190
2191 if (def != data)
2192 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2193 regRLC_CGTT_MGCG_OVERRIDE, data);
2194
2195 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL);
2196
2197 if (enable)
2198 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
2199 else
2200 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
2201
2202 if (def != data)
2203 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data);
2204}
2205
2206static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev,
2207 bool enable, int xcc_id)
2208{
2209 uint32_t def, data;
2210
2211 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
2212 return;
2213
2214 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2215 regRLC_CGTT_MGCG_OVERRIDE);
2216
2217 if (enable)
2218 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2219 else
2220 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2221
2222 if (def != data)
2223 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2224 regRLC_CGTT_MGCG_OVERRIDE, data);
2225}
2226
880f8b3f
LL		 2227static void
2228gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2229 bool enable, int xcc_id)
86301129
LM		 2230{
2231 uint32_t data, def;
2232
86301129
LM		 2233 /* It is disabled by HW by default */
2234 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2235 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
659a4ab8 2236 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
86301129
LM		 2237
2238 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2239 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
b7c7011e 2240 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
86301129
LM		 2241 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2242
86301129 2243 if (def != data)
659a4ab8 2244 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
86301129
LM		 2245
2246 /* MGLS is a global flag to control all MGLS in GFX */
2247 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2248 /* 2 - RLC memory Light sleep */
2249 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
659a4ab8 2250 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
86301129
LM		 2251 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2252 if (def != data)
659a4ab8 2253 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
86301129
LM		 2254 }
2255 /* 3 - CP memory Light sleep */
2256 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
659a4ab8 2257 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
86301129
LM		 2258 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2259 if (def != data)
659a4ab8 2260 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
86301129
LM		 2261 }
2262 }
2263 } else {
2264 /* 1 - MGCG_OVERRIDE */
659a4ab8 2265 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
86301129
LM		 2266
2267 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2268 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2269 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2270 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2271
2272 if (def != data)
659a4ab8 2273 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
86301129
LM		 2274
2275 /* 2 - disable MGLS in RLC */
659a4ab8 2276 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
86301129
LM		 2277 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2278 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
659a4ab8 2279 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
86301129
LM		 2280 }
2281
2282 /* 3 - disable MGLS in CP */
659a4ab8 2283 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
86301129
LM		 2284 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2285 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
659a4ab8 2286 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
86301129
LM		 2287 }
2288 }
2289
86301129
LM		 2290}
2291
880f8b3f
LL		 2292static void
2293gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2294 bool enable, int xcc_id)
86301129
LM		 2295{
2296 uint32_t def, data;
2297
86301129 2298 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
b7c7011e 2299
659a4ab8 2300 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
86301129
LM		 2301 /* unset CGCG override */
2302 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2303 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2304 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2305 else
2306 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2307 /* update CGCG and CGLS override bits */
2308 if (def != data)
659a4ab8 2309 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
86301129
LM		 2310
2311 /* enable cgcg FSM(0x0000363F) */
659a4ab8 2312 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
86301129 2313
b7c7011e
LL		 2314 data = (0x36
2315 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2316 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
86301129
LM		 2317 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2318 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2319 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2320 if (def != data)
659a4ab8 2321 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
86301129
LM		 2322
2323 /* set IDLE_POLL_COUNT(0x00900100) */
659a4ab8 2324 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);
86301129
LM		 2325 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2326 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2327 if (def != data)
659a4ab8 2328 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);
86301129 2329 } else {
659a4ab8 2330 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
86301129
LM		 2331 /* reset CGCG/CGLS bits */
2332 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2333 /* disable cgcg and cgls in FSM */
2334 if (def != data)
659a4ab8 2335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
86301129
LM		 2336 }
2337
86301129
LM		 2338}
2339
880f8b3f
LL		 2340static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev,
2341 bool enable, int xcc_id)
86301129 2342{
34fd9d68
LL		 2343 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
2344
86301129 2345 if (enable) {
34fd9d68
LL		 2346 /* FGCG */
2347 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2348 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2349
86301129
LM		 2350 /* CGCG/CGLS should be enabled after MGCG/MGLS
2351 * === MGCG + MGLS ===
2352 */
880f8b3f
LL		 2353 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2354 xcc_id);
86301129 2355 /* === CGCG + CGLS === */
880f8b3f
LL		 2356 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2357 xcc_id);
86301129
LM		 2358 } else {
2359 /* CGCG/CGLS should be disabled before MGCG/MGLS
2360 * === CGCG + CGLS ===
2361 */
880f8b3f
LL		 2362 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2363 xcc_id);
86301129 2364 /* === MGCG + MGLS === */
880f8b3f
LL		 2365 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2366 xcc_id);
34fd9d68
LL		 2367
2368 /* FGCG */
2369 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2370 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
86301129 2371 }
34fd9d68
LL		 2372
2373 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
2374
86301129
LM		 2375 return 0;
2376}
2377
2378static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
2379 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
880f8b3f
LL		 2380 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode,
2381 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode,
86301129 2382 .init = gfx_v9_4_3_rlc_init,
86301129
LM		 2383 .resume = gfx_v9_4_3_rlc_resume,
2384 .stop = gfx_v9_4_3_rlc_stop,
2385 .reset = gfx_v9_4_3_rlc_reset,
2386 .start = gfx_v9_4_3_rlc_start,
2387 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
2388 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
2389};
2390
2391static int gfx_v9_4_3_set_powergating_state(void *handle,
2392 enum amd_powergating_state state)
2393{
2394 return 0;
2395}
2396
2397static int gfx_v9_4_3_set_clockgating_state(void *handle,
2398 enum amd_clockgating_state state)
2399{
2400 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8078f1c6 2401 int i, num_xcc;
86301129
LM		 2402
2403 if (amdgpu_sriov_vf(adev))
2404 return 0;
2405
8078f1c6 2406 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
86301129
LM		 2407 switch (adev->ip_versions[GC_HWIP][0]) {
2408 case IP_VERSION(9, 4, 3):
8078f1c6 2409 for (i = 0; i < num_xcc; i++)
880f8b3f
LL		 2410 gfx_v9_4_3_xcc_update_gfx_clock_gating(
2411 adev, state == AMD_CG_STATE_GATE, i);
86301129
LM		 2412 break;
2413 default:
2414 break;
2415 }
2416 return 0;
2417}
2418
2419static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
2420{
2421 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2422 int data;
2423
2424 if (amdgpu_sriov_vf(adev))
2425 *flags = 0;
2426
2427 /* AMD_CG_SUPPORT_GFX_MGCG */
659a4ab8 2428 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
86301129
LM		 2429 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2430 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2431
2432 /* AMD_CG_SUPPORT_GFX_CGCG */
659a4ab8 2433 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
86301129
LM		 2434 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2435 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2436
2437 /* AMD_CG_SUPPORT_GFX_CGLS */
2438 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2439 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2440
2441 /* AMD_CG_SUPPORT_GFX_RLC_LS */
659a4ab8 2442 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
86301129
LM		 2443 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2444 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2445
2446 /* AMD_CG_SUPPORT_GFX_CP_LS */
659a4ab8 2447 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
86301129
LM		 2448 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2449 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2450}
2451
2452static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2453{
2454 struct amdgpu_device *adev = ring->adev;
2455 u32 ref_and_mask, reg_mem_engine;
2456 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
2457
2458 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2459 switch (ring->me) {
2460 case 1:
2461 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2462 break;
2463 case 2:
2464 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2465 break;
2466 default:
2467 return;
2468 }
2469 reg_mem_engine = 0;
2470 } else {
2471 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2472 reg_mem_engine = 1; /* pfp */
2473 }
2474
2475 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2476 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
2477 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
2478 ref_and_mask, ref_and_mask, 0x20);
2479}
2480
2481static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
2482 struct amdgpu_job *job,
2483 struct amdgpu_ib *ib,
2484 uint32_t flags)
2485{
2486 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2487 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2488
2489 /* Currently, there is a high possibility to get wave ID mismatch
2490 * between ME and GDS, leading to a hw deadlock, because ME generates
2491 * different wave IDs than the GDS expects. This situation happens
2492 * randomly when at least 5 compute pipes use GDS ordered append.
2493 * The wave IDs generated by ME are also wrong after suspend/resume.
2494 * Those are probably bugs somewhere else in the kernel driver.
2495 *
2496 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2497 * GDS to 0 for this ring (me/pipe).
2498 */
2499 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2500 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2501 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
2502 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2503 }
2504
2505 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2506 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2507 amdgpu_ring_write(ring,
2508#ifdef __BIG_ENDIAN
2509 (2 << 0) |
2510#endif
2511 lower_32_bits(ib->gpu_addr));
2512 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2513 amdgpu_ring_write(ring, control);
2514}
2515
2516static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2517 u64 seq, unsigned flags)
2518{
2519 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2520 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2521 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
2522
2523 /* RELEASE_MEM - flush caches, send int */
2524 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2525 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
2526 EOP_TC_NC_ACTION_EN) :
2527 (EOP_TCL1_ACTION_EN |
2528 EOP_TC_ACTION_EN |
2529 EOP_TC_WB_ACTION_EN |
2530 EOP_TC_MD_ACTION_EN)) |
2531 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2532 EVENT_INDEX(5)));
2533 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2534
2535 /*
2536 * the address should be Qword aligned if 64bit write, Dword
2537 * aligned if only send 32bit data low (discard data high)
2538 */
2539 if (write64bit)
2540 BUG_ON(addr & 0x7);
2541 else
2542 BUG_ON(addr & 0x3);
2543 amdgpu_ring_write(ring, lower_32_bits(addr));
2544 amdgpu_ring_write(ring, upper_32_bits(addr));
2545 amdgpu_ring_write(ring, lower_32_bits(seq));
2546 amdgpu_ring_write(ring, upper_32_bits(seq));
2547 amdgpu_ring_write(ring, 0);
2548}
2549
2550static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2551{
2552 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2553 uint32_t seq = ring->fence_drv.sync_seq;
2554 uint64_t addr = ring->fence_drv.gpu_addr;
2555
2556 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
2557 lower_32_bits(addr), upper_32_bits(addr),
2558 seq, 0xffffffff, 4);
2559}
2560
2561static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
2562 unsigned vmid, uint64_t pd_addr)
2563{
2564 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2565}
2566
2567static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
2568{
2569 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2570}
2571
2572static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
2573{
2574 u64 wptr;
2575
2576 /* XXX check if swapping is necessary on BE */
2577 if (ring->use_doorbell)
2578 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2579 else
2580 BUG();
2581 return wptr;
2582}
2583
2584static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
2585{
2586 struct amdgpu_device *adev = ring->adev;
2587
2588 /* XXX check if swapping is necessary on BE */
2589 if (ring->use_doorbell) {
2590 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2591 WDOORBELL64(ring->doorbell_index, ring->wptr);
2592 } else {
2593 BUG(); /* only DOORBELL method supported on gfx9 now */
2594 }
2595}
2596
2597static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2598 u64 seq, unsigned int flags)
2599{
2600 struct amdgpu_device *adev = ring->adev;
2601
2602 /* we only allocate 32bit for each seq wb address */
2603 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2604
2605 /* write fence seq to the "addr" */
2606 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2607 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2608 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2609 amdgpu_ring_write(ring, lower_32_bits(addr));
2610 amdgpu_ring_write(ring, upper_32_bits(addr));
2611 amdgpu_ring_write(ring, lower_32_bits(seq));
2612
2613 if (flags & AMDGPU_FENCE_FLAG_INT) {
2614 /* set register to trigger INT */
2615 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2616 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2617 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
659a4ab8 2618 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
86301129
LM		 2619 amdgpu_ring_write(ring, 0);
2620 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2621 }
2622}
2623
2624static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
2625 uint32_t reg_val_offs)
2626{
2627 struct amdgpu_device *adev = ring->adev;
2628
2629 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2630 amdgpu_ring_write(ring, 0 | /* src: register*/
2631 (5 << 8) | /* dst: memory */
2632 (1 << 20)); /* write confirm */
2633 amdgpu_ring_write(ring, reg);
2634 amdgpu_ring_write(ring, 0);
2635 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2636 reg_val_offs * 4));
2637 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2638 reg_val_offs * 4));
2639}
2640
2641static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2642 uint32_t val)
2643{
2644 uint32_t cmd = 0;
2645
2646 switch (ring->funcs->type) {
2647 case AMDGPU_RING_TYPE_GFX:
2648 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
2649 break;
2650 case AMDGPU_RING_TYPE_KIQ:
2651 cmd = (1 << 16); /* no inc addr */
2652 break;
2653 default:
2654 cmd = WR_CONFIRM;
2655 break;
2656 }
2657 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2658 amdgpu_ring_write(ring, cmd);
2659 amdgpu_ring_write(ring, reg);
2660 amdgpu_ring_write(ring, 0);
2661 amdgpu_ring_write(ring, val);
2662}
2663
2664static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
2665 uint32_t val, uint32_t mask)
2666{
2667 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
2668}
2669
2670static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
2671 uint32_t reg0, uint32_t reg1,
2672 uint32_t ref, uint32_t mask)
2673{
2674 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2675 ref, mask);
2676}
2677
880f8b3f
LL		 2678static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2679 struct amdgpu_device *adev, int me, int pipe,
2680 enum amdgpu_interrupt_state state, int xcc_id)
86301129
LM		 2681{
2682 u32 mec_int_cntl, mec_int_cntl_reg;
2683
2684 /*
2685 * amdgpu controls only the first MEC. That's why this function only
2686 * handles the setting of interrupts for this specific MEC. All other
2687 * pipes' interrupts are set by amdkfd.
2688 */
2689
2690 if (me == 1) {
2691 switch (pipe) {
2692 case 0:
659a4ab8 2693 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
86301129
LM		 2694 break;
2695 case 1:
659a4ab8 2696 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
86301129
LM		 2697 break;
2698 case 2:
659a4ab8 2699 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
86301129
LM		 2700 break;
2701 case 3:
659a4ab8 2702 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
86301129
LM		 2703 break;
2704 default:
2705 DRM_DEBUG("invalid pipe %d\n", pipe);
2706 return;
2707 }
2708 } else {
2709 DRM_DEBUG("invalid me %d\n", me);
2710 return;
2711 }
2712
2713 switch (state) {
2714 case AMDGPU_IRQ_STATE_DISABLE:
2715 mec_int_cntl = RREG32(mec_int_cntl_reg);
2716 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2717 TIME_STAMP_INT_ENABLE, 0);
2718 WREG32(mec_int_cntl_reg, mec_int_cntl);
2719 break;
2720 case AMDGPU_IRQ_STATE_ENABLE:
2721 mec_int_cntl = RREG32(mec_int_cntl_reg);
2722 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2723 TIME_STAMP_INT_ENABLE, 1);
2724 WREG32(mec_int_cntl_reg, mec_int_cntl);
2725 break;
2726 default:
2727 break;
2728 }
2729}
2730
2731static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
2732 struct amdgpu_irq_src *source,
2733 unsigned type,
2734 enum amdgpu_interrupt_state state)
2735{
8078f1c6 2736 int i, num_xcc;
6f917fdc 2737
8078f1c6 2738 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
86301129
LM		 2739 switch (state) {
2740 case AMDGPU_IRQ_STATE_DISABLE:
2741 case AMDGPU_IRQ_STATE_ENABLE:
8078f1c6 2742 for (i = 0; i < num_xcc; i++)
659a4ab8 2743 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
6f917fdc
LM		 2744 PRIV_REG_INT_ENABLE,
2745 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
86301129
LM		 2746 break;
2747 default:
2748 break;
2749 }
2750
2751 return 0;
2752}
2753
2754static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
2755 struct amdgpu_irq_src *source,
2756 unsigned type,
2757 enum amdgpu_interrupt_state state)
2758{
8078f1c6 2759 int i, num_xcc;
6f917fdc 2760
8078f1c6 2761 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
86301129
LM		 2762 switch (state) {
2763 case AMDGPU_IRQ_STATE_DISABLE:
2764 case AMDGPU_IRQ_STATE_ENABLE:
8078f1c6 2765 for (i = 0; i < num_xcc; i++)
659a4ab8 2766 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
6f917fdc
LM		 2767 PRIV_INSTR_INT_ENABLE,
2768 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
86301129
LM		 2769 break;
2770 default:
2771 break;
2772 }
2773
2774 return 0;
2775}
2776
2777static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
2778 struct amdgpu_irq_src *src,
2779 unsigned type,
2780 enum amdgpu_interrupt_state state)
2781{
8078f1c6
LL		 2782 int i, num_xcc;
2783
2784 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2785 for (i = 0; i < num_xcc; i++) {
6f917fdc
LM		 2786 switch (type) {
2787 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
880f8b3f
LL		 2788 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2789 adev, 1, 0, state, i);
6f917fdc
LM		 2790 break;
2791 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
880f8b3f
LL		 2792 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2793 adev, 1, 1, state, i);
6f917fdc
LM		 2794 break;
2795 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
880f8b3f
LL		 2796 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2797 adev, 1, 2, state, i);
6f917fdc
LM		 2798 break;
2799 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
880f8b3f
LL		 2800 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2801 adev, 1, 3, state, i);
6f917fdc
LM		 2802 break;
2803 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
880f8b3f
LL		 2804 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2805 adev, 2, 0, state, i);
6f917fdc
LM		 2806 break;
2807 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
880f8b3f
LL		 2808 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2809 adev, 2, 1, state, i);
6f917fdc
LM		 2810 break;
2811 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
880f8b3f
LL		 2812 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2813 adev, 2, 2, state, i);
6f917fdc
LM		 2814 break;
2815 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
880f8b3f
LL		 2816 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2817 adev, 2, 3, state, i);
6f917fdc
LM		 2818 break;
2819 default:
2820 break;
2821 }
86301129 2822 }
6f917fdc 2823
86301129
LM		 2824 return 0;
2825}
2826
2827static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
2828 struct amdgpu_irq_src *source,
2829 struct amdgpu_iv_entry *entry)
2830{
870d1e5a 2831 int i, xcc_id;
86301129
LM		 2832 u8 me_id, pipe_id, queue_id;
2833 struct amdgpu_ring *ring;
2834
2835 DRM_DEBUG("IH: CP EOP\n");
2836 me_id = (entry->ring_id & 0x0c) >> 2;
2837 pipe_id = (entry->ring_id & 0x03) >> 0;
2838 queue_id = (entry->ring_id & 0x70) >> 4;
2839
870d1e5a
LL		 2840 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2841
2842 if (xcc_id == -EINVAL)
2843 return -EINVAL;
15091a6f 2844
86301129
LM		 2845 switch (me_id) {
2846 case 0:
2847 case 1:
2848 case 2:
2849 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
870d1e5a
LL		 2850 ring = &adev->gfx.compute_ring
2851 [i +
2852 xcc_id * adev->gfx.num_compute_rings];
86301129
LM		 2853 /* Per-queue interrupt is supported for MEC starting from VI.
2854 * The interrupt can only be enabled/disabled per pipe instead of per queue.
2855 */
8078f1c6 2856
86301129
LM		 2857 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2858 amdgpu_fence_process(ring);
2859 }
2860 break;
2861 }
2862 return 0;
2863}
2864
2865static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
2866 struct amdgpu_iv_entry *entry)
2867{
2868 u8 me_id, pipe_id, queue_id;
2869 struct amdgpu_ring *ring;
870d1e5a 2870 int i, xcc_id;
86301129
LM		 2871
2872 me_id = (entry->ring_id & 0x0c) >> 2;
2873 pipe_id = (entry->ring_id & 0x03) >> 0;
2874 queue_id = (entry->ring_id & 0x70) >> 4;
2875
870d1e5a
LL		 2876 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2877
2878 if (xcc_id == -EINVAL)
2879 return;
2880
86301129
LM		 2881 switch (me_id) {
2882 case 0:
2883 case 1:
2884 case 2:
2885 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
870d1e5a
LL		 2886 ring = &adev->gfx.compute_ring
2887 [i +
2888 xcc_id * adev->gfx.num_compute_rings];
86301129
LM		 2889 if (ring->me == me_id && ring->pipe == pipe_id &&
2890 ring->queue == queue_id)
2891 drm_sched_fault(&ring->sched);
2892 }
2893 break;
2894 }
2895}
2896
2897static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
2898 struct amdgpu_irq_src *source,
2899 struct amdgpu_iv_entry *entry)
2900{
2901 DRM_ERROR("Illegal register access in command stream\n");
2902 gfx_v9_4_3_fault(adev, entry);
2903 return 0;
2904}
2905
2906static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
2907 struct amdgpu_irq_src *source,
2908 struct amdgpu_iv_entry *entry)
2909{
2910 DRM_ERROR("Illegal instruction in command stream\n");
2911 gfx_v9_4_3_fault(adev, entry);
2912 return 0;
2913}
2914
2915static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
2916{
2917 const unsigned int cp_coher_cntl =
2918 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
2919 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
2920 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
2921 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
2922 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
2923
2924 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
2925 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
2926 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
2927 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
2928 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
2929 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
2930 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
2931 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
2932}
2933
2934static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
2935 uint32_t pipe, bool enable)
2936{
2937 struct amdgpu_device *adev = ring->adev;
2938 uint32_t val;
2939 uint32_t wcl_cs_reg;
2940
2941 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
2942 val = enable ? 0x1 : 0x7f;
2943
2944 switch (pipe) {
2945 case 0:
659a4ab8 2946 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
86301129
LM		 2947 break;
2948 case 1:
659a4ab8 2949 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
86301129
LM		 2950 break;
2951 case 2:
659a4ab8 2952 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
86301129
LM		 2953 break;
2954 case 3:
659a4ab8 2955 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
86301129
LM		 2956 break;
2957 default:
2958 DRM_DEBUG("invalid pipe %d\n", pipe);
2959 return;
2960 }
2961
2962 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
2963
2964}
2965static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
2966{
2967 struct amdgpu_device *adev = ring->adev;
2968 uint32_t val;
2969 int i;
2970
2971 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
2972 * number of gfx waves. Setting 5 bit will make sure gfx only gets
2973 * around 25% of gpu resources.
2974 */
2975 val = enable ? 0x1f : 0x07ffffff;
2976 amdgpu_ring_emit_wreg(ring,
659a4ab8 2977 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
86301129
LM		 2978 val);
2979
2980 /* Restrict waves for normal/low priority compute queues as well
2981 * to get best QoS for high priority compute jobs.
2982 *
2983 * amdgpu controls only 1st ME(0-3 CS pipes).
2984 */
2985 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2986 if (i != ring->pipe)
2987 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
2988
2989 }
2990}
2991
2992static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
2993 .name = "gfx_v9_4_3",
2994 .early_init = gfx_v9_4_3_early_init,
2995 .late_init = gfx_v9_4_3_late_init,
2996 .sw_init = gfx_v9_4_3_sw_init,
2997 .sw_fini = gfx_v9_4_3_sw_fini,
2998 .hw_init = gfx_v9_4_3_hw_init,
2999 .hw_fini = gfx_v9_4_3_hw_fini,
3000 .suspend = gfx_v9_4_3_suspend,
3001 .resume = gfx_v9_4_3_resume,
3002 .is_idle = gfx_v9_4_3_is_idle,
3003 .wait_for_idle = gfx_v9_4_3_wait_for_idle,
3004 .soft_reset = gfx_v9_4_3_soft_reset,
3005 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
3006 .set_powergating_state = gfx_v9_4_3_set_powergating_state,
3007 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
3008};
3009
3010static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
3011 .type = AMDGPU_RING_TYPE_COMPUTE,
3012 .align_mask = 0xff,
3013 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3014 .support_64bit_ptrs = true,
3015 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
3016 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
3017 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
3018 .emit_frame_size =
3019 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
3020 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
3021 5 + /* hdp invalidate */
3022 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
3023 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
3024 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
3025 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
3026 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
3027 7 + /* gfx_v9_4_3_emit_mem_sync */
3028 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
3029 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
3030 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
3031 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
3032 .emit_fence = gfx_v9_4_3_ring_emit_fence,
3033 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
3034 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
3035 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
3036 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
3037 .test_ring = gfx_v9_4_3_ring_test_ring,
3038 .test_ib = gfx_v9_4_3_ring_test_ib,
3039 .insert_nop = amdgpu_ring_insert_nop,
3040 .pad_ib = amdgpu_ring_generic_pad_ib,
3041 .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
3042 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
3043 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
3044 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
3045 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
3046};
3047
3048static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
3049 .type = AMDGPU_RING_TYPE_KIQ,
3050 .align_mask = 0xff,
3051 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3052 .support_64bit_ptrs = true,
3053 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
3054 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
3055 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
3056 .emit_frame_size =
3057 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
3058 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
3059 5 + /* hdp invalidate */
3060 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
3061 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
3062 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
3063 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
3064 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
3065 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
3066 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
3067 .test_ring = gfx_v9_4_3_ring_test_ring,
3068 .insert_nop = amdgpu_ring_insert_nop,
3069 .pad_ib = amdgpu_ring_generic_pad_ib,
3070 .emit_rreg = gfx_v9_4_3_ring_emit_rreg,
3071 .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
3072 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
3073 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
3074};
3075
3076static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
3077{
8078f1c6 3078 int i, j, num_xcc;
86301129 3079
8078f1c6
LL		 3080 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
3081 for (i = 0; i < num_xcc; i++) {
6f917fdc 3082 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
86301129 3083
6f917fdc
LM		 3084 for (j = 0; j < adev->gfx.num_compute_rings; j++)
3085 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
3086 = &gfx_v9_4_3_ring_funcs_compute;
3087 }
86301129
LM		 3088}
3089
3090static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
3091 .set = gfx_v9_4_3_set_eop_interrupt_state,
3092 .process = gfx_v9_4_3_eop_irq,
3093};
3094
3095static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
3096 .set = gfx_v9_4_3_set_priv_reg_fault_state,
3097 .process = gfx_v9_4_3_priv_reg_irq,
3098};
3099
3100static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
3101 .set = gfx_v9_4_3_set_priv_inst_fault_state,
3102 .process = gfx_v9_4_3_priv_inst_irq,
3103};
3104
3105static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
3106{
3107 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3108 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
3109
3110 adev->gfx.priv_reg_irq.num_types = 1;
3111 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
3112
3113 adev->gfx.priv_inst_irq.num_types = 1;
3114 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
3115}
3116
3117static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
3118{
3119 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
3120}
3121
3122
3123static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
3124{
3125 /* init asci gds info */
3126 switch (adev->ip_versions[GC_HWIP][0]) {
3127 case IP_VERSION(9, 4, 3):
3128 /* 9.4.3 removed all the GDS internal memory,
3129 * only support GWS opcode in kernel, like barrier
3130 * semaphore.etc */
3131 adev->gds.gds_size = 0;
3132 break;
3133 default:
3134 adev->gds.gds_size = 0x10000;
3135 break;
3136 }
3137
3138 switch (adev->ip_versions[GC_HWIP][0]) {
3139 case IP_VERSION(9, 4, 3):
3140 /* deprecated for 9.4.3, no usage at all */
3141 adev->gds.gds_compute_max_wave_id = 0;
3142 break;
3143 default:
3144 /* this really depends on the chip */
3145 adev->gds.gds_compute_max_wave_id = 0x7ff;
3146 break;
3147 }
3148
3149 adev->gds.gws_size = 64;
3150 adev->gds.oa_size = 16;
3151}
3152
3153static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3154 u32 bitmap)
3155{
3156 u32 data;
3157
3158 if (!bitmap)
3159 return;
3160
3161 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3162 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3163
659a4ab8 3164 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data);
86301129
LM		 3165}
3166
3167static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev)
3168{
3169 u32 data, mask;
3170
659a4ab8
LL		 3171 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG);
3172 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG);
86301129
LM		 3173
3174 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3175 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3176
3177 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3178
3179 return (~data) & mask;
3180}
3181
3182static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
3183 struct amdgpu_cu_info *cu_info)
3184{
3185 int i, j, k, counter, active_cu_number = 0;
3186 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3187 unsigned disable_masks[4 * 4];
3188
3189 if (!adev || !cu_info)
3190 return -EINVAL;
3191
3192 /*
3193 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
3194 */
3195 if (adev->gfx.config.max_shader_engines *
3196 adev->gfx.config.max_sh_per_se > 16)
3197 return -EINVAL;
3198
3199 amdgpu_gfx_parse_disable_cu(disable_masks,
3200 adev->gfx.config.max_shader_engines,
3201 adev->gfx.config.max_sh_per_se);
3202
3203 mutex_lock(&adev->grbm_idx_mutex);
3204 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3205 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3206 mask = 1;
3207 ao_bitmap = 0;
3208 counter = 0;
880f8b3f 3209 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0);
86301129
LM		 3210 gfx_v9_4_3_set_user_cu_inactive_bitmap(
3211 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
3212 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev);
3213
3214 /*
3215 * The bitmap(and ao_cu_bitmap) in cu_info structure is
3216 * 4x4 size array, and it's usually suitable for Vega
3217 * ASICs which has 4*2 SE/SH layout.
3218 * But for Arcturus, SE/SH layout is changed to 8*1.
3219 * To mostly reduce the impact, we make it compatible
3220 * with current bitmap array as below:
3221 * SE4,SH0 --> bitmap[0][1]
3222 * SE5,SH0 --> bitmap[1][1]
3223 * SE6,SH0 --> bitmap[2][1]
3224 * SE7,SH0 --> bitmap[3][1]
3225 */
3226 cu_info->bitmap[i % 4][j + i / 4] = bitmap;
3227
3228 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3229 if (bitmap & mask) {
3230 if (counter < adev->gfx.config.max_cu_per_sh)
3231 ao_bitmap |= mask;
3232 counter++;
3233 }
3234 mask <<= 1;
3235 }
3236 active_cu_number += counter;
3237 if (i < 2 && j < 2)
3238 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3239 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
3240 }
3241 }
880f8b3f
LL		 3242 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3243 0);
86301129
LM		 3244 mutex_unlock(&adev->grbm_idx_mutex);
3245
3246 cu_info->number = active_cu_number;
3247 cu_info->ao_cu_mask = ao_cu_mask;
3248 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
3249
3250 return 0;
3251}
3252
3253const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
3254 .type = AMD_IP_BLOCK_TYPE_GFX,
3255 .major = 9,
3256 .minor = 4,
3257 .rev = 0,
3258 .funcs = &gfx_v9_4_3_ip_funcs,
7c0f7ee0 3259};
73c84f7c
LL		 3260
3261static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)
3262{
3263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3264 uint32_t tmp_mask;
3265 int i, r;
3266
3267 /* TODO : Initialize golden regs */
3268 /* gfx_v9_4_3_init_golden_registers(adev); */
3269
3270 tmp_mask = inst_mask;
3271 for_each_inst(i, tmp_mask)
3272 gfx_v9_4_3_xcc_constants_init(adev, i);
3273
3274 tmp_mask = inst_mask;
3275 for_each_inst(i, tmp_mask) {
3276 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
3277 if (r)
3278 return r;
3279 }
3280
3281 tmp_mask = inst_mask;
3282 for_each_inst(i, tmp_mask) {
3283 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
3284 if (r)
3285 return r;
3286 }
3287
3288 return 0;
3289}
3290
3291static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)
3292{
3293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3294 int i;
3295
3296 for_each_inst(i, inst_mask)
3297 gfx_v9_4_3_xcc_fini(adev, i);
3298
3299 return 0;
3300}
3301
3302struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
3303 .suspend = &gfx_v9_4_3_xcp_suspend,
3304 .resume = &gfx_v9_4_3_xcp_resume
3305};
Linux 6.x block layer and io_uring tree(s)