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drm/amdgpu/sdma4: Update vega12 sdma golden setting.
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
c1b24a14 23#include <linux/kernel.h>
b1023571 24#include <linux/firmware.h>
248a1d6f 25#include <drm/drmP.h>
b1023571
KW		 26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "soc15.h"
29#include "soc15d.h"
30
cde5c34f
FX		 31#include "gc/gc_9_0_offset.h"
32#include "gc/gc_9_0_sh_mask.h"
fb960bd2 33#include "vega10_enum.h"
75199b8c 34#include "hdp/hdp_4_0_offset.h"
b1023571
KW		 35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
268cb4c7 41#define GFX9_MEC_HPD_SIZE 2048
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
b1023571
KW		 52
53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
946a4d5b
SL		 67static const struct soc15_reg_golden golden_settings_gc_9_0[] =
68{
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
b1023571
KW		 92};
93
946a4d5b 94static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
b1023571 95{
946a4d5b
SL		 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
b1023571
KW		 103};
104
946a4d5b
SL		 105static const struct soc15_reg_golden golden_settings_gc_9_1[] =
106{
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
a5fdb336
CZ		 128};
129
946a4d5b 130static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
a5fdb336 131{
946a4d5b
SL		 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
b1023571
KW		 139};
140
946a4d5b 141static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
f5eaffcc 142{
946a4d5b
SL		 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
f5eaffcc
KW		 145};
146
b1023571 147#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
7b6ba9ea 148#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
b1023571
KW		 149
150static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
151static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
152static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
153static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
154static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
155 struct amdgpu_cu_info *cu_info);
156static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
157static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 158static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 159
160static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
161{
162 switch (adev->asic_type) {
163 case CHIP_VEGA10:
946a4d5b 164 soc15_program_register_sequence(adev,
b1023571 165 golden_settings_gc_9_0,
c47b41a7 166 ARRAY_SIZE(golden_settings_gc_9_0));
946a4d5b 167 soc15_program_register_sequence(adev,
b1023571 168 golden_settings_gc_9_0_vg10,
c47b41a7 169 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
b1023571 170 break;
a5fdb336 171 case CHIP_RAVEN:
946a4d5b 172 soc15_program_register_sequence(adev,
a5fdb336 173 golden_settings_gc_9_1,
c47b41a7 174 ARRAY_SIZE(golden_settings_gc_9_1));
946a4d5b 175 soc15_program_register_sequence(adev,
a5fdb336 176 golden_settings_gc_9_1_rv1,
c47b41a7 177 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
a5fdb336 178 break;
b1023571
KW		 179 default:
180 break;
181 }
f5eaffcc 182
946a4d5b 183 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
f5eaffcc 184 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
b1023571
KW		 185}
186
187static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
188{
6a05148f 189 adev->gfx.scratch.num_reg = 8;
b1023571
KW		 190 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
191 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
192}
193
194static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
195 bool wc, uint32_t reg, uint32_t val)
196{
197 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
198 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
199 WRITE_DATA_DST_SEL(0) |
200 (wc ? WR_CONFIRM : 0));
201 amdgpu_ring_write(ring, reg);
202 amdgpu_ring_write(ring, 0);
203 amdgpu_ring_write(ring, val);
204}
205
206static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
207 int mem_space, int opt, uint32_t addr0,
208 uint32_t addr1, uint32_t ref, uint32_t mask,
209 uint32_t inv)
210{
211 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
212 amdgpu_ring_write(ring,
213 /* memory (1) or register (0) */
214 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
215 WAIT_REG_MEM_OPERATION(opt) | /* wait */
216 WAIT_REG_MEM_FUNCTION(3) | /* equal */
217 WAIT_REG_MEM_ENGINE(eng_sel)));
218
219 if (mem_space)
220 BUG_ON(addr0 & 0x3); /* Dword align */
221 amdgpu_ring_write(ring, addr0);
222 amdgpu_ring_write(ring, addr1);
223 amdgpu_ring_write(ring, ref);
224 amdgpu_ring_write(ring, mask);
225 amdgpu_ring_write(ring, inv); /* poll interval */
226}
227
228static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
229{
230 struct amdgpu_device *adev = ring->adev;
231 uint32_t scratch;
232 uint32_t tmp = 0;
233 unsigned i;
234 int r;
235
236 r = amdgpu_gfx_scratch_get(adev, &scratch);
237 if (r) {
238 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
239 return r;
240 }
241 WREG32(scratch, 0xCAFEDEAD);
242 r = amdgpu_ring_alloc(ring, 3);
243 if (r) {
244 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
245 ring->idx, r);
246 amdgpu_gfx_scratch_free(adev, scratch);
247 return r;
248 }
249 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
250 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
251 amdgpu_ring_write(ring, 0xDEADBEEF);
252 amdgpu_ring_commit(ring);
253
254 for (i = 0; i < adev->usec_timeout; i++) {
255 tmp = RREG32(scratch);
256 if (tmp == 0xDEADBEEF)
257 break;
258 DRM_UDELAY(1);
259 }
260 if (i < adev->usec_timeout) {
9953b72f 261 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
b1023571
KW		 262 ring->idx, i);
263 } else {
264 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
265 ring->idx, scratch, tmp);
266 r = -EINVAL;
267 }
268 amdgpu_gfx_scratch_free(adev, scratch);
269 return r;
270}
271
272static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
273{
ed9324af
ML		 274 struct amdgpu_device *adev = ring->adev;
275 struct amdgpu_ib ib;
276 struct dma_fence *f = NULL;
277
278 unsigned index;
279 uint64_t gpu_addr;
280 uint32_t tmp;
281 long r;
282
283 r = amdgpu_device_wb_get(adev, &index);
284 if (r) {
285 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
286 return r;
287 }
288
289 gpu_addr = adev->wb.gpu_addr + (index * 4);
290 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
291 memset(&ib, 0, sizeof(ib));
292 r = amdgpu_ib_get(adev, NULL, 16, &ib);
293 if (r) {
294 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
295 goto err1;
296 }
297 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
298 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
299 ib.ptr[2] = lower_32_bits(gpu_addr);
300 ib.ptr[3] = upper_32_bits(gpu_addr);
301 ib.ptr[4] = 0xDEADBEEF;
302 ib.length_dw = 5;
b1023571 303
ed9324af
ML		 304 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
305 if (r)
306 goto err2;
b1023571 307
ed9324af
ML		 308 r = dma_fence_wait_timeout(f, false, timeout);
309 if (r == 0) {
310 DRM_ERROR("amdgpu: IB test timed out.\n");
311 r = -ETIMEDOUT;
312 goto err2;
313 } else if (r < 0) {
314 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
315 goto err2;
316 }
317
318 tmp = adev->wb.wb[index];
319 if (tmp == 0xDEADBEEF) {
320 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
321 r = 0;
322 } else {
323 DRM_ERROR("ib test on ring %d failed\n", ring->idx);
324 r = -EINVAL;
325 }
b1023571 326
b1023571 327err2:
ed9324af
ML		 328 amdgpu_ib_free(adev, &ib, NULL);
329 dma_fence_put(f);
b1023571 330err1:
ed9324af
ML		 331 amdgpu_device_wb_free(adev, index);
332 return r;
b1023571
KW		 333}
334
c833d8aa
ML		 335
336static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
337{
338 release_firmware(adev->gfx.pfp_fw);
339 adev->gfx.pfp_fw = NULL;
340 release_firmware(adev->gfx.me_fw);
341 adev->gfx.me_fw = NULL;
342 release_firmware(adev->gfx.ce_fw);
343 adev->gfx.ce_fw = NULL;
344 release_firmware(adev->gfx.rlc_fw);
345 adev->gfx.rlc_fw = NULL;
346 release_firmware(adev->gfx.mec_fw);
347 adev->gfx.mec_fw = NULL;
348 release_firmware(adev->gfx.mec2_fw);
349 adev->gfx.mec2_fw = NULL;
350
351 kfree(adev->gfx.rlc.register_list_format);
352}
353
b1023571
KW		 354static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
355{
356 const char *chip_name;
357 char fw_name[30];
358 int err;
359 struct amdgpu_firmware_info *info = NULL;
360 const struct common_firmware_header *header = NULL;
361 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 362 const struct rlc_firmware_header_v2_0 *rlc_hdr;
363 unsigned int *tmp = NULL;
364 unsigned int i = 0;
b1023571
KW		 365
366 DRM_DEBUG("\n");
367
368 switch (adev->asic_type) {
369 case CHIP_VEGA10:
370 chip_name = "vega10";
371 break;
eaa85724
CZ		 372 case CHIP_RAVEN:
373 chip_name = "raven";
374 break;
b1023571
KW		 375 default:
376 BUG();
377 }
378
379 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
380 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
381 if (err)
382 goto out;
383 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
384 if (err)
385 goto out;
386 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
387 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
388 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
389
390 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
391 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
392 if (err)
393 goto out;
394 err = amdgpu_ucode_validate(adev->gfx.me_fw);
395 if (err)
396 goto out;
397 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
398 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
399 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
400
401 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
402 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
403 if (err)
404 goto out;
405 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
406 if (err)
407 goto out;
408 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
409 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
410 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
411
412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
413 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
414 if (err)
415 goto out;
416 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 417 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
418 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
419 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
420 adev->gfx.rlc.save_and_restore_offset =
421 le32_to_cpu(rlc_hdr->save_and_restore_offset);
422 adev->gfx.rlc.clear_state_descriptor_offset =
423 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
424 adev->gfx.rlc.avail_scratch_ram_locations =
425 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
426 adev->gfx.rlc.reg_restore_list_size =
427 le32_to_cpu(rlc_hdr->reg_restore_list_size);
428 adev->gfx.rlc.reg_list_format_start =
429 le32_to_cpu(rlc_hdr->reg_list_format_start);
430 adev->gfx.rlc.reg_list_format_separate_start =
431 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
432 adev->gfx.rlc.starting_offsets_start =
433 le32_to_cpu(rlc_hdr->starting_offsets_start);
434 adev->gfx.rlc.reg_list_format_size_bytes =
435 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
436 adev->gfx.rlc.reg_list_size_bytes =
437 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
438 adev->gfx.rlc.register_list_format =
439 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
440 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
441 if (!adev->gfx.rlc.register_list_format) {
442 err = -ENOMEM;
443 goto out;
444 }
445
446 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
447 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
448 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
449 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
450
451 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
452
453 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
454 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
455 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
456 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 457
458 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
459 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
460 if (err)
461 goto out;
462 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
463 if (err)
464 goto out;
465 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
466 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
467 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
468
469
470 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
471 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
472 if (!err) {
473 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
474 if (err)
475 goto out;
476 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
477 adev->gfx.mec2_fw->data;
478 adev->gfx.mec2_fw_version =
479 le32_to_cpu(cp_hdr->header.ucode_version);
480 adev->gfx.mec2_feature_version =
481 le32_to_cpu(cp_hdr->ucode_feature_version);
482 } else {
483 err = 0;
484 adev->gfx.mec2_fw = NULL;
485 }
486
487 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
488 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
489 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
490 info->fw = adev->gfx.pfp_fw;
491 header = (const struct common_firmware_header *)info->fw->data;
492 adev->firmware.fw_size +=
493 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
494
495 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
496 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
497 info->fw = adev->gfx.me_fw;
498 header = (const struct common_firmware_header *)info->fw->data;
499 adev->firmware.fw_size +=
500 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
501
502 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
503 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
504 info->fw = adev->gfx.ce_fw;
505 header = (const struct common_firmware_header *)info->fw->data;
506 adev->firmware.fw_size +=
507 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
508
509 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
510 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
511 info->fw = adev->gfx.rlc_fw;
512 header = (const struct common_firmware_header *)info->fw->data;
513 adev->firmware.fw_size +=
514 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
515
516 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
517 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
518 info->fw = adev->gfx.mec_fw;
519 header = (const struct common_firmware_header *)info->fw->data;
520 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
521 adev->firmware.fw_size +=
522 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
523
524 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
525 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
526 info->fw = adev->gfx.mec_fw;
527 adev->firmware.fw_size +=
528 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
529
530 if (adev->gfx.mec2_fw) {
531 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
532 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
533 info->fw = adev->gfx.mec2_fw;
534 header = (const struct common_firmware_header *)info->fw->data;
535 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
536 adev->firmware.fw_size +=
537 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
538 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
539 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
540 info->fw = adev->gfx.mec2_fw;
541 adev->firmware.fw_size +=
542 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
543 }
544
545 }
546
547out:
548 if (err) {
549 dev_err(adev->dev,
550 "gfx9: Failed to load firmware \"%s\"\n",
551 fw_name);
552 release_firmware(adev->gfx.pfp_fw);
553 adev->gfx.pfp_fw = NULL;
554 release_firmware(adev->gfx.me_fw);
555 adev->gfx.me_fw = NULL;
556 release_firmware(adev->gfx.ce_fw);
557 adev->gfx.ce_fw = NULL;
558 release_firmware(adev->gfx.rlc_fw);
559 adev->gfx.rlc_fw = NULL;
560 release_firmware(adev->gfx.mec_fw);
561 adev->gfx.mec_fw = NULL;
562 release_firmware(adev->gfx.mec2_fw);
563 adev->gfx.mec2_fw = NULL;
564 }
565 return err;
566}
567
c9719c69
HZ		 568static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
569{
570 u32 count = 0;
571 const struct cs_section_def *sect = NULL;
572 const struct cs_extent_def *ext = NULL;
573
574 /* begin clear state */
575 count += 2;
576 /* context control state */
577 count += 3;
578
579 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
580 for (ext = sect->section; ext->extent != NULL; ++ext) {
581 if (sect->id == SECT_CONTEXT)
582 count += 2 + ext->reg_count;
583 else
584 return 0;
585 }
586 }
587
588 /* end clear state */
589 count += 2;
590 /* clear state */
591 count += 2;
592
593 return count;
594}
595
596static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
597 volatile u32 *buffer)
598{
599 u32 count = 0, i;
600 const struct cs_section_def *sect = NULL;
601 const struct cs_extent_def *ext = NULL;
602
603 if (adev->gfx.rlc.cs_data == NULL)
604 return;
605 if (buffer == NULL)
606 return;
607
608 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
609 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
610
611 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
612 buffer[count++] = cpu_to_le32(0x80000000);
613 buffer[count++] = cpu_to_le32(0x80000000);
614
615 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
616 for (ext = sect->section; ext->extent != NULL; ++ext) {
617 if (sect->id == SECT_CONTEXT) {
618 buffer[count++] =
619 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
620 buffer[count++] = cpu_to_le32(ext->reg_index -
621 PACKET3_SET_CONTEXT_REG_START);
622 for (i = 0; i < ext->reg_count; i++)
623 buffer[count++] = cpu_to_le32(ext->extent[i]);
624 } else {
625 return;
626 }
627 }
628 }
629
630 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
631 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
632
633 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
634 buffer[count++] = cpu_to_le32(0);
635}
636
ba7bb665
HZ		 637static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
638{
e5475e16 639 uint32_t data;
ba7bb665
HZ		 640
641 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
642 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
643 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
644 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
645 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
646
647 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
648 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
649
650 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
651 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
652
653 mutex_lock(&adev->grbm_idx_mutex);
654 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
655 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
656 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
657
658 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
e5475e16
TSD		 659 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
660 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
661 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
ba7bb665
HZ		 662 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
663
664 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
665 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
666 data &= 0x0000FFFF;
667 data |= 0x00C00000;
668 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
669
670 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
671 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
672
673 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
674 * but used for RLC_LB_CNTL configuration */
675 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
e5475e16
TSD		 676 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
677 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
ba7bb665
HZ		 678 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
679 mutex_unlock(&adev->grbm_idx_mutex);
680}
681
e8835e0e
HZ		 682static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
683{
e5475e16 684 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
e8835e0e
HZ		 685}
686
c9719c69
HZ		 687static void rv_init_cp_jump_table(struct amdgpu_device *adev)
688{
689 const __le32 *fw_data;
690 volatile u32 *dst_ptr;
691 int me, i, max_me = 5;
692 u32 bo_offset = 0;
693 u32 table_offset, table_size;
694
695 /* write the cp table buffer */
696 dst_ptr = adev->gfx.rlc.cp_table_ptr;
697 for (me = 0; me < max_me; me++) {
698 if (me == 0) {
699 const struct gfx_firmware_header_v1_0 *hdr =
700 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
701 fw_data = (const __le32 *)
702 (adev->gfx.ce_fw->data +
703 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
704 table_offset = le32_to_cpu(hdr->jt_offset);
705 table_size = le32_to_cpu(hdr->jt_size);
706 } else if (me == 1) {
707 const struct gfx_firmware_header_v1_0 *hdr =
708 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
709 fw_data = (const __le32 *)
710 (adev->gfx.pfp_fw->data +
711 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
712 table_offset = le32_to_cpu(hdr->jt_offset);
713 table_size = le32_to_cpu(hdr->jt_size);
714 } else if (me == 2) {
715 const struct gfx_firmware_header_v1_0 *hdr =
716 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
717 fw_data = (const __le32 *)
718 (adev->gfx.me_fw->data +
719 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
720 table_offset = le32_to_cpu(hdr->jt_offset);
721 table_size = le32_to_cpu(hdr->jt_size);
722 } else if (me == 3) {
723 const struct gfx_firmware_header_v1_0 *hdr =
724 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
725 fw_data = (const __le32 *)
726 (adev->gfx.mec_fw->data +
727 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
728 table_offset = le32_to_cpu(hdr->jt_offset);
729 table_size = le32_to_cpu(hdr->jt_size);
730 } else if (me == 4) {
731 const struct gfx_firmware_header_v1_0 *hdr =
732 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
733 fw_data = (const __le32 *)
734 (adev->gfx.mec2_fw->data +
735 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
736 table_offset = le32_to_cpu(hdr->jt_offset);
737 table_size = le32_to_cpu(hdr->jt_size);
738 }
739
740 for (i = 0; i < table_size; i ++) {
741 dst_ptr[bo_offset + i] =
742 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
743 }
744
745 bo_offset += table_size;
746 }
747}
748
749static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
750{
751 /* clear state block */
752 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
753 &adev->gfx.rlc.clear_state_gpu_addr,
754 (void **)&adev->gfx.rlc.cs_ptr);
755
756 /* jump table block */
757 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
758 &adev->gfx.rlc.cp_table_gpu_addr,
759 (void **)&adev->gfx.rlc.cp_table_ptr);
760}
761
762static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
763{
764 volatile u32 *dst_ptr;
765 u32 dws;
766 const struct cs_section_def *cs_data;
767 int r;
768
769 adev->gfx.rlc.cs_data = gfx9_cs_data;
770
771 cs_data = adev->gfx.rlc.cs_data;
772
773 if (cs_data) {
774 /* clear state block */
775 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
a4a02777
CK		 776 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
777 AMDGPU_GEM_DOMAIN_VRAM,
778 &adev->gfx.rlc.clear_state_obj,
779 &adev->gfx.rlc.clear_state_gpu_addr,
780 (void **)&adev->gfx.rlc.cs_ptr);
781 if (r) {
782 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
783 r);
784 gfx_v9_0_rlc_fini(adev);
785 return r;
c9719c69
HZ		 786 }
787 /* set up the cs buffer */
788 dst_ptr = adev->gfx.rlc.cs_ptr;
789 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
790 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
791 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
792 }
793
794 if (adev->asic_type == CHIP_RAVEN) {
795 /* TODO: double check the cp_table_size for RV */
796 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
a4a02777
CK		 797 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
798 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
799 &adev->gfx.rlc.cp_table_obj,
800 &adev->gfx.rlc.cp_table_gpu_addr,
801 (void **)&adev->gfx.rlc.cp_table_ptr);
802 if (r) {
803 dev_err(adev->dev,
804 "(%d) failed to create cp table bo\n", r);
805 gfx_v9_0_rlc_fini(adev);
806 return r;
c9719c69
HZ		 807 }
808
809 rv_init_cp_jump_table(adev);
810 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
811 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
ba7bb665
HZ		 812
813 gfx_v9_0_init_lbpw(adev);
c9719c69
HZ		 814 }
815
816 return 0;
817}
818
b1023571
KW		 819static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
820{
078af1a3
CK		 821 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
822 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
b1023571
KW		 823}
824
b1023571
KW		 825static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
826{
827 int r;
828 u32 *hpd;
829 const __le32 *fw_data;
830 unsigned fw_size;
831 u32 *fw;
42794b27 832 size_t mec_hpd_size;
b1023571
KW		 833
834 const struct gfx_firmware_header_v1_0 *mec_hdr;
835
78c16834
AR		 836 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
837
78c16834 838 /* take ownership of the relevant compute queues */
41f6a99a 839 amdgpu_gfx_compute_queue_acquire(adev);
78c16834 840 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
b1023571 841
a4a02777
CK		 842 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
843 AMDGPU_GEM_DOMAIN_GTT,
844 &adev->gfx.mec.hpd_eop_obj,
845 &adev->gfx.mec.hpd_eop_gpu_addr,
846 (void **)&hpd);
b1023571 847 if (r) {
a4a02777 848 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
b1023571
KW		 849 gfx_v9_0_mec_fini(adev);
850 return r;
851 }
852
853 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
854
855 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
856 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
857
858 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
859
860 fw_data = (const __le32 *)
861 (adev->gfx.mec_fw->data +
862 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
863 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
864
a4a02777
CK		 865 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
866 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
867 &adev->gfx.mec.mec_fw_obj,
868 &adev->gfx.mec.mec_fw_gpu_addr,
869 (void **)&fw);
b1023571 870 if (r) {
a4a02777 871 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
b1023571
KW		 872 gfx_v9_0_mec_fini(adev);
873 return r;
874 }
a4a02777 875
b1023571
KW		 876 memcpy(fw, fw_data, fw_size);
877
878 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
879 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
880
b1023571
KW		 881 return 0;
882}
883
884static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
885{
5e78835a 886 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 887 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
888 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
889 (address << SQ_IND_INDEX__INDEX__SHIFT) |
890 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 891 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 892}
893
894static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
895 uint32_t wave, uint32_t thread,
896 uint32_t regno, uint32_t num, uint32_t *out)
897{
5e78835a 898 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 899 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
900 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
901 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
902 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
903 (SQ_IND_INDEX__FORCE_READ_MASK) |
904 (SQ_IND_INDEX__AUTO_INCR_MASK));
905 while (num--)
5e78835a 906 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 907}
908
909static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
910{
911 /* type 1 wave data */
912 dst[(*no_fields)++] = 1;
913 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
914 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
915 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
916 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
917 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
918 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
919 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
920 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
921 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
922 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
923 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
924 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
925 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
926 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
927}
928
929static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
930 uint32_t wave, uint32_t start,
931 uint32_t size, uint32_t *dst)
932{
933 wave_read_regs(
934 adev, simd, wave, 0,
935 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
936}
937
822770ad
NH		 938static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
939 uint32_t wave, uint32_t thread,
940 uint32_t start, uint32_t size,
941 uint32_t *dst)
942{
943 wave_read_regs(
944 adev, simd, wave, thread,
945 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
946}
b1023571
KW		 947
948static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
949 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
950 .select_se_sh = &gfx_v9_0_select_se_sh,
951 .read_wave_data = &gfx_v9_0_read_wave_data,
952 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
822770ad 953 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
b1023571
KW		 954};
955
956static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
957{
958 u32 gb_addr_config;
959
960 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
961
962 switch (adev->asic_type) {
963 case CHIP_VEGA10:
b1023571 964 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 965 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
966 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
967 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
968 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
969 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
970 break;
5cf7433d
CZ		 971 case CHIP_RAVEN:
972 adev->gfx.config.max_hw_contexts = 8;
973 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
974 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
975 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
976 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
977 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
978 break;
b1023571
KW		 979 default:
980 BUG();
981 break;
982 }
983
984 adev->gfx.config.gb_addr_config = gb_addr_config;
985
986 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
987 REG_GET_FIELD(
988 adev->gfx.config.gb_addr_config,
989 GB_ADDR_CONFIG,
990 NUM_PIPES);
ad7d0ff3
AD		 991
992 adev->gfx.config.max_tile_pipes =
993 adev->gfx.config.gb_addr_config_fields.num_pipes;
994
b1023571
KW		 995 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
996 REG_GET_FIELD(
997 adev->gfx.config.gb_addr_config,
998 GB_ADDR_CONFIG,
999 NUM_BANKS);
1000 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1001 REG_GET_FIELD(
1002 adev->gfx.config.gb_addr_config,
1003 GB_ADDR_CONFIG,
1004 MAX_COMPRESSED_FRAGS);
1005 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1006 REG_GET_FIELD(
1007 adev->gfx.config.gb_addr_config,
1008 GB_ADDR_CONFIG,
1009 NUM_RB_PER_SE);
1010 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1011 REG_GET_FIELD(
1012 adev->gfx.config.gb_addr_config,
1013 GB_ADDR_CONFIG,
1014 NUM_SHADER_ENGINES);
1015 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1016 REG_GET_FIELD(
1017 adev->gfx.config.gb_addr_config,
1018 GB_ADDR_CONFIG,
1019 PIPE_INTERLEAVE_SIZE));
1020}
1021
1022static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1023 struct amdgpu_ngg_buf *ngg_buf,
1024 int size_se,
1025 int default_size_se)
1026{
1027 int r;
1028
1029 if (size_se < 0) {
1030 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1031 return -EINVAL;
1032 }
1033 size_se = size_se ? size_se : default_size_se;
1034
42ce2243 1035 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1036 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1037 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1038 &ngg_buf->bo,
1039 &ngg_buf->gpu_addr,
1040 NULL);
1041 if (r) {
1042 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1043 return r;
1044 }
1045 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1046
1047 return r;
1048}
1049
1050static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1051{
1052 int i;
1053
1054 for (i = 0; i < NGG_BUF_MAX; i++)
1055 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1056 &adev->gfx.ngg.buf[i].gpu_addr,
1057 NULL);
1058
1059 memset(&adev->gfx.ngg.buf[0], 0,
1060 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1061
1062 adev->gfx.ngg.init = false;
1063
1064 return 0;
1065}
1066
1067static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1068{
1069 int r;
1070
1071 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1072 return 0;
1073
1074 /* GDS reserve memory: 64 bytes alignment */
1075 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1076 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1077 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
d33bba4d
JZ		 1078 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1079 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 1080
1081 /* Primitive Buffer */
af8baf15 1082 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1083 amdgpu_prim_buf_per_se,
1084 64 * 1024);
1085 if (r) {
1086 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1087 goto err;
1088 }
1089
1090 /* Position Buffer */
af8baf15 1091 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1092 amdgpu_pos_buf_per_se,
1093 256 * 1024);
1094 if (r) {
1095 dev_err(adev->dev, "Failed to create Position Buffer\n");
1096 goto err;
1097 }
1098
1099 /* Control Sideband */
af8baf15 1100 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1101 amdgpu_cntl_sb_buf_per_se,
1102 256);
1103 if (r) {
1104 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1105 goto err;
1106 }
1107
1108 /* Parameter Cache, not created by default */
1109 if (amdgpu_param_buf_per_se <= 0)
1110 goto out;
1111
af8baf15 1112 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1113 amdgpu_param_buf_per_se,
1114 512 * 1024);
1115 if (r) {
1116 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1117 goto err;
1118 }
1119
1120out:
1121 adev->gfx.ngg.init = true;
1122 return 0;
1123err:
1124 gfx_v9_0_ngg_fini(adev);
1125 return r;
1126}
1127
1128static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1129{
1130 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1131 int r;
91629eff 1132 u32 data, base;
b1023571
KW		 1133
1134 if (!amdgpu_ngg)
1135 return 0;
1136
1137 /* Program buffer size */
91629eff
TSD		 1138 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1139 adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1140 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1141 adev->gfx.ngg.buf[NGG_POS].size >> 8);
5e78835a 1142 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571 1143
91629eff
TSD		 1144 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1145 adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1146 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1147 adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
5e78835a 1148 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1149
1150 /* Program buffer base address */
af8baf15 1151 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1152 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1153 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1154
af8baf15 1155 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1156 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1157 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1158
af8baf15 1159 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1160 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1161 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1162
af8baf15 1163 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1164 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1165 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1166
af8baf15 1167 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1168 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1169 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1170
af8baf15 1171 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1172 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1173 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1174
1175 /* Clear GDS reserved memory */
1176 r = amdgpu_ring_alloc(ring, 17);
1177 if (r) {
1178 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1179 ring->idx, r);
1180 return r;
1181 }
1182
1183 gfx_v9_0_write_data_to_reg(ring, 0, false,
946a4d5b 1184 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
b1023571
KW		 1185 (adev->gds.mem.total_size +
1186 adev->gfx.ngg.gds_reserve_size) >>
1187 AMDGPU_GDS_SHIFT);
1188
1189 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1190 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
d33bba4d 1191 PACKET3_DMA_DATA_DST_SEL(1) |
b1023571
KW		 1192 PACKET3_DMA_DATA_SRC_SEL(2)));
1193 amdgpu_ring_write(ring, 0);
1194 amdgpu_ring_write(ring, 0);
1195 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1196 amdgpu_ring_write(ring, 0);
d33bba4d
JZ		 1197 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1198 adev->gfx.ngg.gds_reserve_size);
b1023571
KW		 1199
1200 gfx_v9_0_write_data_to_reg(ring, 0, false,
946a4d5b 1201 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
b1023571
KW		 1202
1203 amdgpu_ring_commit(ring);
1204
1205 return 0;
1206}
1207
1361f455
AD		 1208static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1209 int mec, int pipe, int queue)
1210{
1211 int r;
1212 unsigned irq_type;
1213 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1214
1215 ring = &adev->gfx.compute_ring[ring_id];
1216
1217 /* mec0 is me1 */
1218 ring->me = mec + 1;
1219 ring->pipe = pipe;
1220 ring->queue = queue;
1221
1222 ring->ring_obj = NULL;
1223 ring->use_doorbell = true;
7366af81 1224 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1361f455
AD		 1225 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1226 + (ring_id * GFX9_MEC_HPD_SIZE);
1227 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1228
1229 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1230 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1231 + ring->pipe;
1232
1233 /* type-2 packets are deprecated on MEC, use type-3 instead */
1234 r = amdgpu_ring_init(adev, ring, 1024,
1235 &adev->gfx.eop_irq, irq_type);
1236 if (r)
1237 return r;
1238
1239
1240 return 0;
1241}
1242
b1023571
KW		 1243static int gfx_v9_0_sw_init(void *handle)
1244{
1361f455 1245 int i, j, k, r, ring_id;
b1023571 1246 struct amdgpu_ring *ring;
ac104e99 1247 struct amdgpu_kiq *kiq;
b1023571
KW		 1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249
4853bbb6
AD		 1250 switch (adev->asic_type) {
1251 case CHIP_VEGA10:
1252 case CHIP_RAVEN:
1253 adev->gfx.mec.num_mec = 2;
1254 break;
1255 default:
1256 adev->gfx.mec.num_mec = 1;
1257 break;
1258 }
1259
1260 adev->gfx.mec.num_pipe_per_mec = 4;
1261 adev->gfx.mec.num_queue_per_pipe = 8;
1262
97031e25 1263 /* KIQ event */
3760f76c 1264 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
97031e25
XY		 1265 if (r)
1266 return r;
1267
b1023571 1268 /* EOP Event */
3760f76c 1269 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
b1023571
KW		 1270 if (r)
1271 return r;
1272
1273 /* Privileged reg */
3760f76c 1274 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
b1023571
KW		 1275 &adev->gfx.priv_reg_irq);
1276 if (r)
1277 return r;
1278
1279 /* Privileged inst */
3760f76c 1280 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
b1023571
KW		 1281 &adev->gfx.priv_inst_irq);
1282 if (r)
1283 return r;
1284
1285 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1286
1287 gfx_v9_0_scratch_init(adev);
1288
1289 r = gfx_v9_0_init_microcode(adev);
1290 if (r) {
1291 DRM_ERROR("Failed to load gfx firmware!\n");
1292 return r;
1293 }
1294
c9719c69
HZ		 1295 r = gfx_v9_0_rlc_init(adev);
1296 if (r) {
1297 DRM_ERROR("Failed to init rlc BOs!\n");
1298 return r;
1299 }
1300
b1023571
KW		 1301 r = gfx_v9_0_mec_init(adev);
1302 if (r) {
1303 DRM_ERROR("Failed to init MEC BOs!\n");
1304 return r;
1305 }
1306
1307 /* set up the gfx ring */
1308 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1309 ring = &adev->gfx.gfx_ring[i];
1310 ring->ring_obj = NULL;
f6886c47
TSD		 1311 if (!i)
1312 sprintf(ring->name, "gfx");
1313 else
1314 sprintf(ring->name, "gfx_%d", i);
b1023571
KW		 1315 ring->use_doorbell = true;
1316 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1317 r = amdgpu_ring_init(adev, ring, 1024,
1318 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1319 if (r)
1320 return r;
1321 }
1322
1361f455
AD		 1323 /* set up the compute queues - allocate horizontally across pipes */
1324 ring_id = 0;
1325 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1326 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1327 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 1328 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1361f455
AD		 1329 continue;
1330
1331 r = gfx_v9_0_compute_ring_init(adev,
1332 ring_id,
1333 i, k, j);
1334 if (r)
1335 return r;
1336
1337 ring_id++;
1338 }
b1023571 1339 }
b1023571
KW		 1340 }
1341
71c37505 1342 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
e30a5223
AD		 1343 if (r) {
1344 DRM_ERROR("Failed to init KIQ BOs!\n");
1345 return r;
1346 }
ac104e99 1347
e30a5223 1348 kiq = &adev->gfx.kiq;
71c37505 1349 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
e30a5223
AD		 1350 if (r)
1351 return r;
464826d6 1352
e30a5223 1353 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
ffe6d881 1354 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
e30a5223
AD		 1355 if (r)
1356 return r;
ac104e99 1357
b1023571
KW		 1358 /* reserve GDS, GWS and OA resource for gfx */
1359 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1360 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1361 &adev->gds.gds_gfx_bo, NULL, NULL);
1362 if (r)
1363 return r;
1364
1365 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1366 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1367 &adev->gds.gws_gfx_bo, NULL, NULL);
1368 if (r)
1369 return r;
1370
1371 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1372 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1373 &adev->gds.oa_gfx_bo, NULL, NULL);
1374 if (r)
1375 return r;
1376
1377 adev->gfx.ce_ram_size = 0x8000;
1378
1379 gfx_v9_0_gpu_early_init(adev);
1380
1381 r = gfx_v9_0_ngg_init(adev);
1382 if (r)
1383 return r;
1384
1385 return 0;
1386}
1387
1388
1389static int gfx_v9_0_sw_fini(void *handle)
1390{
1391 int i;
1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1393
1394 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1395 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1396 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1397
1398 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1399 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1400 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1401 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1402
b9683c21 1403 amdgpu_gfx_compute_mqd_sw_fini(adev);
71c37505
AD		 1404 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1405 amdgpu_gfx_kiq_fini(adev);
ac104e99 1406
b1023571
KW		 1407 gfx_v9_0_mec_fini(adev);
1408 gfx_v9_0_ngg_fini(adev);
9862def9
ML		 1409 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1410 &adev->gfx.rlc.clear_state_gpu_addr,
1411 (void **)&adev->gfx.rlc.cs_ptr);
1412 if (adev->asic_type == CHIP_RAVEN) {
1413 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1414 &adev->gfx.rlc.cp_table_gpu_addr,
1415 (void **)&adev->gfx.rlc.cp_table_ptr);
1416 }
c833d8aa 1417 gfx_v9_0_free_microcode(adev);
b1023571
KW		 1418
1419 return 0;
1420}
1421
1422
1423static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1424{
1425 /* TODO */
1426}
1427
1428static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1429{
be448a4d 1430 u32 data;
b1023571 1431
be448a4d
NH		 1432 if (instance == 0xffffffff)
1433 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1434 else
1435 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1436
1437 if (se_num == 0xffffffff)
b1023571 1438 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
be448a4d 1439 else
b1023571 1440 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
be448a4d
NH		 1441
1442 if (sh_num == 0xffffffff)
1443 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1444 else
b1023571 1445 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
be448a4d 1446
5e78835a 1447 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1448}
1449
b1023571
KW		 1450static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1451{
1452 u32 data, mask;
1453
5e78835a
TSD		 1454 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1455 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1456
1457 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1458 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1459
378506a7
AD		 1460 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1461 adev->gfx.config.max_sh_per_se);
b1023571
KW		 1462
1463 return (~data) & mask;
1464}
1465
1466static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1467{
1468 int i, j;
2572c24c 1469 u32 data;
b1023571
KW		 1470 u32 active_rbs = 0;
1471 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1472 adev->gfx.config.max_sh_per_se;
1473
1474 mutex_lock(&adev->grbm_idx_mutex);
1475 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1476 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1477 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1478 data = gfx_v9_0_get_rb_active_bitmap(adev);
1479 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1480 rb_bitmap_width_per_sh);
1481 }
1482 }
1483 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1484 mutex_unlock(&adev->grbm_idx_mutex);
1485
1486 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1487 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1488}
1489
1490#define DEFAULT_SH_MEM_BASES (0x6000)
1491#define FIRST_COMPUTE_VMID (8)
1492#define LAST_COMPUTE_VMID (16)
1493static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1494{
1495 int i;
1496 uint32_t sh_mem_config;
1497 uint32_t sh_mem_bases;
1498
1499 /*
1500 * Configure apertures:
1501 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1502 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1503 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1504 */
1505 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1506
1507 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1508 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1509 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1510
1511 mutex_lock(&adev->srbm_mutex);
1512 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1513 soc15_grbm_select(adev, 0, 0, 0, i);
1514 /* CP and shaders */
5e78835a
TSD		 1515 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1516 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1517 }
1518 soc15_grbm_select(adev, 0, 0, 0, 0);
1519 mutex_unlock(&adev->srbm_mutex);
1520}
1521
1522static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1523{
1524 u32 tmp;
1525 int i;
1526
40f06773 1527 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1528
1529 gfx_v9_0_tiling_mode_table_init(adev);
1530
1531 gfx_v9_0_setup_rb(adev);
1532 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1533
1534 /* XXX SH_MEM regs */
1535 /* where to put LDS, scratch, GPUVM in FSA64 space */
1536 mutex_lock(&adev->srbm_mutex);
32b646b2 1537 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
b1023571
KW		 1538 soc15_grbm_select(adev, 0, 0, 0, i);
1539 /* CP and shaders */
a7ea6548
AD		 1540 if (i == 0) {
1541 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1542 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1543 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1544 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1545 } else {
1546 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1547 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1548 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
770d13b1 1549 tmp = adev->gmc.shared_aperture_start >> 48;
a7ea6548
AD		 1550 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1551 }
b1023571
KW		 1552 }
1553 soc15_grbm_select(adev, 0, 0, 0, 0);
1554
1555 mutex_unlock(&adev->srbm_mutex);
1556
1557 gfx_v9_0_init_compute_vmid(adev);
1558
1559 mutex_lock(&adev->grbm_idx_mutex);
1560 /*
1561 * making sure that the following register writes will be broadcasted
1562 * to all the shaders
1563 */
1564 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1565
5e78835a 1566 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1567 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1568 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1569 (adev->gfx.config.sc_prim_fifo_size_backend <<
1570 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1571 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1572 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1573 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1574 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1575 mutex_unlock(&adev->grbm_idx_mutex);
1576
1577}
1578
1579static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1580{
1581 u32 i, j, k;
1582 u32 mask;
1583
1584 mutex_lock(&adev->grbm_idx_mutex);
1585 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1586 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1587 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1588 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1589 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1590 break;
1591 udelay(1);
1592 }
1366b2d0 1593 if (k == adev->usec_timeout) {
1594 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1595 0xffffffff, 0xffffffff);
1596 mutex_unlock(&adev->grbm_idx_mutex);
1597 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1598 i, j);
1599 return;
1600 }
b1023571
KW		 1601 }
1602 }
1603 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1604 mutex_unlock(&adev->grbm_idx_mutex);
1605
1606 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1607 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1608 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1609 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1610 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1611 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1612 break;
1613 udelay(1);
1614 }
1615}
1616
1617static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1618 bool enable)
1619{
5e78835a 1620 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1621
b1023571
KW		 1622 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1623 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1624 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1625 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1626
5e78835a 1627 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1628}
1629
6bce4667
HZ		 1630static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1631{
1632 /* csib */
1633 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1634 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1635 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1636 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1637 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1638 adev->gfx.rlc.clear_state_size);
1639}
1640
1641static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1642 int indirect_offset,
1643 int list_size,
1644 int *unique_indirect_regs,
1645 int *unique_indirect_reg_count,
1646 int max_indirect_reg_count,
1647 int *indirect_start_offsets,
1648 int *indirect_start_offsets_count,
1649 int max_indirect_start_offsets_count)
1650{
1651 int idx;
1652 bool new_entry = true;
1653
1654 for (; indirect_offset < list_size; indirect_offset++) {
1655
1656 if (new_entry) {
1657 new_entry = false;
1658 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1659 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1660 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1661 }
1662
1663 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1664 new_entry = true;
1665 continue;
1666 }
1667
1668 indirect_offset += 2;
1669
1670 /* look for the matching indice */
1671 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1672 if (unique_indirect_regs[idx] ==
1673 register_list_format[indirect_offset])
1674 break;
1675 }
1676
1677 if (idx >= *unique_indirect_reg_count) {
1678 unique_indirect_regs[*unique_indirect_reg_count] =
1679 register_list_format[indirect_offset];
1680 idx = *unique_indirect_reg_count;
1681 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1682 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1683 }
1684
1685 register_list_format[indirect_offset] = idx;
1686 }
1687}
1688
1689static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1690{
1691 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1692 int unique_indirect_reg_count = 0;
1693
1694 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1695 int indirect_start_offsets_count = 0;
1696
1697 int list_size = 0;
1698 int i = 0;
1699 u32 tmp = 0;
1700
1701 u32 *register_list_format =
1702 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1703 if (!register_list_format)
1704 return -ENOMEM;
1705 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1706 adev->gfx.rlc.reg_list_format_size_bytes);
1707
1708 /* setup unique_indirect_regs array and indirect_start_offsets array */
1709 gfx_v9_0_parse_ind_reg_list(register_list_format,
1710 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1711 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1712 unique_indirect_regs,
1713 &unique_indirect_reg_count,
c1b24a14 1714 ARRAY_SIZE(unique_indirect_regs),
6bce4667
HZ		 1715 indirect_start_offsets,
1716 &indirect_start_offsets_count,
c1b24a14 1717 ARRAY_SIZE(indirect_start_offsets));
6bce4667
HZ		 1718
1719 /* enable auto inc in case it is disabled */
1720 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1721 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1722 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1723
1724 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1725 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1726 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1727 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1728 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1729 adev->gfx.rlc.register_restore[i]);
1730
1731 /* load direct register */
1732 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1733 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1734 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1735 adev->gfx.rlc.register_restore[i]);
1736
1737 /* load indirect register */
1738 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1739 adev->gfx.rlc.reg_list_format_start);
1740 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1741 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1742 register_list_format[i]);
1743
1744 /* set save/restore list size */
1745 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1746 list_size = list_size >> 1;
1747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1748 adev->gfx.rlc.reg_restore_list_size);
1749 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1750
1751 /* write the starting offsets to RLC scratch ram */
1752 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1753 adev->gfx.rlc.starting_offsets_start);
c1b24a14 1754 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
6bce4667
HZ		 1755 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1756 indirect_start_offsets[i]);
1757
1758 /* load unique indirect regs*/
c1b24a14 1759 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
6bce4667
HZ		 1760 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1761 unique_indirect_regs[i] & 0x3FFFF);
1762 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1763 unique_indirect_regs[i] >> 20);
1764 }
1765
1766 kfree(register_list_format);
1767 return 0;
1768}
1769
1770static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1771{
0e5293d0 1772 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
6bce4667
HZ		 1773}
1774
91d3130a
HZ		 1775static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1776 bool enable)
1777{
1778 uint32_t data = 0;
1779 uint32_t default_data = 0;
1780
1781 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1782 if (enable == true) {
1783 /* enable GFXIP control over CGPG */
1784 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1785 if(default_data != data)
1786 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1787
1788 /* update status */
1789 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1790 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1791 if(default_data != data)
1792 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1793 } else {
1794 /* restore GFXIP control over GCPG */
1795 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1796 if(default_data != data)
1797 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1798 }
1799}
1800
1801static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1802{
1803 uint32_t data = 0;
1804
1805 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1806 AMD_PG_SUPPORT_GFX_SMG |
1807 AMD_PG_SUPPORT_GFX_DMG)) {
1808 /* init IDLE_POLL_COUNT = 60 */
1809 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1810 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1811 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1812 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1813
1814 /* init RLC PG Delay */
1815 data = 0;
1816 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1817 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1818 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1819 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1820 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1821
1822 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1823 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1824 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1825 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1826
1827 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1828 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1829 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1830 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1831
1832 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1833 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1834
1835 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1836 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1837 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1838
1839 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1840 }
1841}
1842
ed5ad1e4
HZ		 1843static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1844 bool enable)
1845{
1846 uint32_t data = 0;
1847 uint32_t default_data = 0;
1848
1849 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e24c7f06
TSD		 1850 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1851 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
1852 enable ? 1 : 0);
1853 if (default_data != data)
1854 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1855}
1856
1857static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1858 bool enable)
1859{
1860 uint32_t data = 0;
1861 uint32_t default_data = 0;
1862
1863 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
b926fe8e
TSD		 1864 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1865 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
1866 enable ? 1 : 0);
1867 if(default_data != data)
1868 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
ed5ad1e4
HZ		 1869}
1870
3a6cc477
HZ		 1871static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
1872 bool enable)
1873{
1874 uint32_t data = 0;
1875 uint32_t default_data = 0;
1876
1877 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
54cfe0fc
TSD		 1878 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1879 CP_PG_DISABLE,
1880 enable ? 0 : 1);
1881 if(default_data != data)
1882 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
3a6cc477
HZ		 1883}
1884
197f95c8
HZ		 1885static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
1886 bool enable)
1887{
1888 uint32_t data, default_data;
1889
1890 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
f55ee212
TSD		 1891 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1892 GFX_POWER_GATING_ENABLE,
1893 enable ? 1 : 0);
197f95c8
HZ		 1894 if(default_data != data)
1895 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1896}
1897
1898static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
1899 bool enable)
1900{
1901 uint32_t data, default_data;
1902
1903 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
513f8133
TSD		 1904 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1905 GFX_PIPELINE_PG_ENABLE,
1906 enable ? 1 : 0);
197f95c8
HZ		 1907 if(default_data != data)
1908 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1909
1910 if (!enable)
1911 /* read any GFX register to wake up GFX */
1912 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
1913}
1914
552c8f76 1915static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
1916 bool enable)
18924c71
HZ		 1917{
1918 uint32_t data, default_data;
1919
1920 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
7915c8fd
TSD		 1921 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1922 STATIC_PER_CU_PG_ENABLE,
1923 enable ? 1 : 0);
18924c71
HZ		 1924 if(default_data != data)
1925 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1926}
1927
552c8f76 1928static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
18924c71
HZ		 1929 bool enable)
1930{
1931 uint32_t data, default_data;
1932
1933 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
e567fa69
TSD		 1934 data = REG_SET_FIELD(data, RLC_PG_CNTL,
1935 DYN_PER_CU_PG_ENABLE,
1936 enable ? 1 : 0);
18924c71
HZ		 1937 if(default_data != data)
1938 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1939}
1940
6bce4667
HZ		 1941static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1942{
1943 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1944 AMD_PG_SUPPORT_GFX_SMG |
1945 AMD_PG_SUPPORT_GFX_DMG |
1946 AMD_PG_SUPPORT_CP |
1947 AMD_PG_SUPPORT_GDS |
1948 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1949 gfx_v9_0_init_csb(adev);
1950 gfx_v9_0_init_rlc_save_restore_list(adev);
1951 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1952
1953 if (adev->asic_type == CHIP_RAVEN) {
1954 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1955 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1956 gfx_v9_0_init_gfx_power_gating(adev);
3a6cc477 1957
ed5ad1e4
HZ		 1958 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1959 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1960 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1961 } else {
1962 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1963 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1964 }
3a6cc477
HZ		 1965
1966 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
1967 gfx_v9_0_enable_cp_power_gating(adev, true);
1968 else
1969 gfx_v9_0_enable_cp_power_gating(adev, false);
91d3130a 1970 }
6bce4667
HZ		 1971 }
1972}
1973
b1023571
KW		 1974void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1975{
b08796ce 1976 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
b1023571 1977 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
b1023571
KW		 1978 gfx_v9_0_wait_for_rlc_serdes(adev);
1979}
1980
1981static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1982{
596c8e8b 1983 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 1984 udelay(50);
596c8e8b 1985 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 1986 udelay(50);
1987}
1988
1989static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1990{
1991#ifdef AMDGPU_RLC_DEBUG_RETRY
1992 u32 rlc_ucode_ver;
1993#endif
b1023571 1994
342cda25 1995 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1996
1997 /* carrizo do enable cp interrupt after cp inited */
1998 if (!(adev->flags & AMD_IS_APU))
1999 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2000
2001 udelay(50);
2002
2003#ifdef AMDGPU_RLC_DEBUG_RETRY
2004 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2005 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2006 if(rlc_ucode_ver == 0x108) {
2007 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2008 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2009 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2010 * default is 0x9C4 to create a 100us interval */
5e78835a 2011 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2012 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2013 * to disable the page fault retry interrupts, default is
b1023571 2014 * 0x100 (256) */
5e78835a 2015 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2016 }
2017#endif
2018}
2019
2020static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2021{
2022 const struct rlc_firmware_header_v2_0 *hdr;
2023 const __le32 *fw_data;
2024 unsigned i, fw_size;
2025
2026 if (!adev->gfx.rlc_fw)
2027 return -EINVAL;
2028
2029 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2030 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2031
2032 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2033 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2034 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2035
5e78835a 2036 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2037 RLCG_UCODE_LOADING_START_ADDRESS);
2038 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2039 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2040 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2041
2042 return 0;
2043}
2044
2045static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2046{
2047 int r;
2048
f840cc5f
ML		 2049 if (amdgpu_sriov_vf(adev)) {
2050 gfx_v9_0_init_csb(adev);
cfee05bc 2051 return 0;
f840cc5f 2052 }
cfee05bc 2053
b1023571
KW		 2054 gfx_v9_0_rlc_stop(adev);
2055
2056 /* disable CG */
5e78835a 2057 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2058
2059 /* disable PG */
5e78835a 2060 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2061
2062 gfx_v9_0_rlc_reset(adev);
2063
6bce4667
HZ		 2064 gfx_v9_0_init_pg(adev);
2065
b1023571
KW		 2066 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2067 /* legacy rlc firmware loading */
2068 r = gfx_v9_0_rlc_load_microcode(adev);
2069 if (r)
2070 return r;
2071 }
2072
e8835e0e
HZ		 2073 if (adev->asic_type == CHIP_RAVEN) {
2074 if (amdgpu_lbpw != 0)
2075 gfx_v9_0_enable_lbpw(adev, true);
2076 else
2077 gfx_v9_0_enable_lbpw(adev, false);
2078 }
2079
b1023571
KW		 2080 gfx_v9_0_rlc_start(adev);
2081
2082 return 0;
2083}
2084
2085static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2086{
2087 int i;
5e78835a 2088 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2089
ea64468e
TSD		 2090 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2091 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2092 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2093 if (!enable) {
b1023571
KW		 2094 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2095 adev->gfx.gfx_ring[i].ready = false;
2096 }
5e78835a 2097 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2098 udelay(50);
2099}
2100
2101static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2102{
2103 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2104 const struct gfx_firmware_header_v1_0 *ce_hdr;
2105 const struct gfx_firmware_header_v1_0 *me_hdr;
2106 const __le32 *fw_data;
2107 unsigned i, fw_size;
2108
2109 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2110 return -EINVAL;
2111
2112 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2113 adev->gfx.pfp_fw->data;
2114 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2115 adev->gfx.ce_fw->data;
2116 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2117 adev->gfx.me_fw->data;
2118
2119 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2120 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2121 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2122
2123 gfx_v9_0_cp_gfx_enable(adev, false);
2124
2125 /* PFP */
2126 fw_data = (const __le32 *)
2127 (adev->gfx.pfp_fw->data +
2128 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2129 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2130 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2131 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2132 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2133 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2134
2135 /* CE */
2136 fw_data = (const __le32 *)
2137 (adev->gfx.ce_fw->data +
2138 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2139 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2140 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2141 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2142 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2143 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2144
2145 /* ME */
2146 fw_data = (const __le32 *)
2147 (adev->gfx.me_fw->data +
2148 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2149 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2150 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2151 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2152 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2153 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2154
2155 return 0;
2156}
2157
b1023571
KW		 2158static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2159{
2160 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2161 const struct cs_section_def *sect = NULL;
2162 const struct cs_extent_def *ext = NULL;
d5de797f 2163 int r, i, tmp;
b1023571
KW		 2164
2165 /* init the CP */
5e78835a
TSD		 2166 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2167 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2168
2169 gfx_v9_0_cp_gfx_enable(adev, true);
2170
d5de797f 2171 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
b1023571
KW		 2172 if (r) {
2173 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2174 return r;
2175 }
2176
2177 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2178 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2179
2180 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2181 amdgpu_ring_write(ring, 0x80000000);
2182 amdgpu_ring_write(ring, 0x80000000);
2183
2184 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2185 for (ext = sect->section; ext->extent != NULL; ++ext) {
2186 if (sect->id == SECT_CONTEXT) {
2187 amdgpu_ring_write(ring,
2188 PACKET3(PACKET3_SET_CONTEXT_REG,
2189 ext->reg_count));
2190 amdgpu_ring_write(ring,
2191 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2192 for (i = 0; i < ext->reg_count; i++)
2193 amdgpu_ring_write(ring, ext->extent[i]);
2194 }
2195 }
2196 }
2197
2198 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2199 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2200
2201 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2202 amdgpu_ring_write(ring, 0);
2203
2204 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2205 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2206 amdgpu_ring_write(ring, 0x8000);
2207 amdgpu_ring_write(ring, 0x8000);
2208
d5de797f
KW		 2209 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2210 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2211 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2212 amdgpu_ring_write(ring, tmp);
2213 amdgpu_ring_write(ring, 0);
2214
b1023571
KW		 2215 amdgpu_ring_commit(ring);
2216
2217 return 0;
2218}
2219
2220static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2221{
2222 struct amdgpu_ring *ring;
2223 u32 tmp;
2224 u32 rb_bufsz;
3fc08b61 2225 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2226
2227 /* Set the write pointer delay */
5e78835a 2228 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2229
2230 /* set the RB to use vmid 0 */
5e78835a 2231 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2232
2233 /* Set ring buffer size */
2234 ring = &adev->gfx.gfx_ring[0];
2235 rb_bufsz = order_base_2(ring->ring_size / 8);
2236 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2237 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2238#ifdef __BIG_ENDIAN
2239 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2240#endif
5e78835a 2241 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2242
2243 /* Initialize the ring buffer's write pointers */
2244 ring->wptr = 0;
5e78835a
TSD		 2245 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2246 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2247
2248 /* set the wb address wether it's enabled or not */
2249 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2250 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2251 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2252
3fc08b61 2253 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2254 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2255 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2256
b1023571 2257 mdelay(1);
5e78835a 2258 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2259
2260 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2261 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2262 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2263
5e78835a 2264 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2265 if (ring->use_doorbell) {
2266 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2267 DOORBELL_OFFSET, ring->doorbell_index);
2268 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2269 DOORBELL_EN, 1);
2270 } else {
2271 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2272 }
5e78835a 2273 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2274
2275 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2276 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2277 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2278
5e78835a 2279 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2280 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2281
2282
2283 /* start the ring */
2284 gfx_v9_0_cp_gfx_start(adev);
2285 ring->ready = true;
2286
2287 return 0;
2288}
2289
2290static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2291{
2292 int i;
2293
2294 if (enable) {
5e78835a 2295 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2296 } else {
5e78835a 2297 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2298 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2299 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2300 adev->gfx.compute_ring[i].ready = false;
ac104e99 2301 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2302 }
2303 udelay(50);
2304}
2305
b1023571
KW		 2306static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2307{
2308 const struct gfx_firmware_header_v1_0 *mec_hdr;
2309 const __le32 *fw_data;
2310 unsigned i;
2311 u32 tmp;
2312
2313 if (!adev->gfx.mec_fw)
2314 return -EINVAL;
2315
2316 gfx_v9_0_cp_compute_enable(adev, false);
2317
2318 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2319 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2320
2321 fw_data = (const __le32 *)
2322 (adev->gfx.mec_fw->data +
2323 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2324 tmp = 0;
2325 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2326 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2327 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2328
5e78835a 2329 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2330 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2331 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2332 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2333
b1023571 2334 /* MEC1 */
5e78835a 2335 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2336 mec_hdr->jt_offset);
2337 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2338 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2339 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2340
5e78835a 2341 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2342 adev->gfx.mec_fw_version);
2343 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2344
2345 return 0;
2346}
2347
464826d6
XY		 2348/* KIQ functions */
2349static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
b1023571 2350{
464826d6
XY		 2351 uint32_t tmp;
2352 struct amdgpu_device *adev = ring->adev;
b1023571 2353
464826d6 2354 /* tell RLC which is KIQ queue */
5e78835a 2355 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2356 tmp &= 0xffffff00;
2357 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2358 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2359 tmp |= 0x80;
5e78835a 2360 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2361}
b1023571 2362
0f1dfd52 2363static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
464826d6 2364{
bd3402ea 2365 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2fdde9fa 2366 uint32_t scratch, tmp = 0;
de65513a 2367 uint64_t queue_mask = 0;
2fdde9fa 2368 int r, i;
b1023571 2369
de65513a
AR		 2370 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2371 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2372 continue;
b1023571 2373
de65513a
AR		 2374 /* This situation may be hit in the future if a new HW
2375 * generation exposes more than 64 queues. If so, the
2376 * definition of queue_mask needs updating */
1d11ee89 2377 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
de65513a
AR		 2378 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2379 break;
b1023571 2380 }
b1023571 2381
de65513a
AR		 2382 queue_mask |= (1ull << i);
2383 }
b1023571 2384
2fdde9fa
AD		 2385 r = amdgpu_gfx_scratch_get(adev, &scratch);
2386 if (r) {
2387 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2388 return r;
b1023571 2389 }
2fdde9fa 2390 WREG32(scratch, 0xCAFEDEAD);
b1023571 2391
0f1dfd52 2392 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2fdde9fa
AD		 2393 if (r) {
2394 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2395 amdgpu_gfx_scratch_free(adev, scratch);
b1023571 2396 return r;
2fdde9fa 2397 }
b1023571 2398
0f1dfd52
AD		 2399 /* set resources */
2400 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2401 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2402 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
de65513a
AR		 2403 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2404 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
0f1dfd52
AD		 2405 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2406 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2407 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2408 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
bd3402ea
AD		 2409 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2410 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2411 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2412 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2413
2414 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2415 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2416 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2417 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2418 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2419 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2420 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2421 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2422 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
f4534f06 2423 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
bd3402ea
AD		 2424 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2425 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2426 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2427 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2428 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2429 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2430 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2431 }
2fdde9fa
AD		 2432 /* write to scratch for completion */
2433 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2434 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2435 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2436 amdgpu_ring_commit(kiq_ring);
b1023571 2437
2fdde9fa
AD		 2438 for (i = 0; i < adev->usec_timeout; i++) {
2439 tmp = RREG32(scratch);
2440 if (tmp == 0xDEADBEEF)
2441 break;
2442 DRM_UDELAY(1);
2443 }
2444 if (i >= adev->usec_timeout) {
2445 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2446 scratch, tmp);
2447 r = -EINVAL;
2448 }
2449 amdgpu_gfx_scratch_free(adev, scratch);
464826d6 2450
2fdde9fa 2451 return r;
464826d6
XY		 2452}
2453
e322edc3 2454static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2455{
33fb8698 2456 struct amdgpu_device *adev = ring->adev;
e322edc3 2457 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2458 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2459 uint32_t tmp;
2460
2461 mqd->header = 0xC0310800;
2462 mqd->compute_pipelinestat_enable = 0x00000001;
2463 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2464 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2465 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2466 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2467 mqd->compute_misc_reserved = 0x00000003;
2468
ffe6d881
AD		 2469 mqd->dynamic_cu_mask_addr_lo =
2470 lower_32_bits(ring->mqd_gpu_addr
2471 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2472 mqd->dynamic_cu_mask_addr_hi =
2473 upper_32_bits(ring->mqd_gpu_addr
2474 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2475
d72f2f46 2476 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2477 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2478 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2479
2480 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2481 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6 2482 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
268cb4c7 2483 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
464826d6
XY		 2484
2485 mqd->cp_hqd_eop_control = tmp;
2486
2487 /* enable doorbell? */
5e78835a 2488 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2489
2490 if (ring->use_doorbell) {
2491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2492 DOORBELL_OFFSET, ring->doorbell_index);
2493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2494 DOORBELL_EN, 1);
2495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2496 DOORBELL_SOURCE, 0);
2497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2498 DOORBELL_HIT, 0);
78888cff 2499 } else {
464826d6
XY		 2500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2501 DOORBELL_EN, 0);
78888cff 2502 }
464826d6
XY		 2503
2504 mqd->cp_hqd_pq_doorbell_control = tmp;
2505
2506 /* disable the queue if it's active */
2507 ring->wptr = 0;
2508 mqd->cp_hqd_dequeue_request = 0;
2509 mqd->cp_hqd_pq_rptr = 0;
2510 mqd->cp_hqd_pq_wptr_lo = 0;
2511 mqd->cp_hqd_pq_wptr_hi = 0;
2512
2513 /* set the pointer to the MQD */
33fb8698
AD		 2514 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2515 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2516
2517 /* set MQD vmid to 0 */
5e78835a 2518 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2519 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2520 mqd->cp_mqd_control = tmp;
2521
2522 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2523 hqd_gpu_addr = ring->gpu_addr >> 8;
2524 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2525 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2526
2527 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2528 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2530 (order_base_2(ring->ring_size / 4) - 1));
2531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2532 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2533#ifdef __BIG_ENDIAN
2534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2535#endif
2536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2540 mqd->cp_hqd_pq_control = tmp;
2541
2542 /* set the wb address whether it's enabled or not */
2543 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2544 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2545 mqd->cp_hqd_pq_rptr_report_addr_hi =
2546 upper_32_bits(wb_gpu_addr) & 0xffff;
2547
2548 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2549 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2550 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2551 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2552
2553 tmp = 0;
2554 /* enable the doorbell if requested */
2555 if (ring->use_doorbell) {
5e78835a 2556 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2557 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2558 DOORBELL_OFFSET, ring->doorbell_index);
2559
2560 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2561 DOORBELL_EN, 1);
2562 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2563 DOORBELL_SOURCE, 0);
2564 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2565 DOORBELL_HIT, 0);
2566 }
2567
2568 mqd->cp_hqd_pq_doorbell_control = tmp;
2569
2570 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2571 ring->wptr = 0;
0274a9c5 2572 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2573
2574 /* set the vmid for the queue */
2575 mqd->cp_hqd_vmid = 0;
2576
0274a9c5 2577 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2578 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2579 mqd->cp_hqd_persistent_state = tmp;
2580
fca4ce69
AD		 2581 /* set MIN_IB_AVAIL_SIZE */
2582 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2583 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2584 mqd->cp_hqd_ib_control = tmp;
2585
464826d6
XY		 2586 /* activate the queue */
2587 mqd->cp_hqd_active = 1;
2588
2589 return 0;
2590}
2591
e322edc3 2592static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2593{
33fb8698 2594 struct amdgpu_device *adev = ring->adev;
e322edc3 2595 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2596 int j;
2597
2598 /* disable wptr polling */
72edadd5 2599 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2600
5e78835a 2601 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2602 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2603 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2604 mqd->cp_hqd_eop_base_addr_hi);
2605
2606 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2607 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2608 mqd->cp_hqd_eop_control);
2609
2610 /* enable doorbell? */
5e78835a 2611 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2612 mqd->cp_hqd_pq_doorbell_control);
2613
2614 /* disable the queue if it's active */
5e78835a
TSD		 2615 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2616 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2617 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2618 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2619 break;
2620 udelay(1);
2621 }
5e78835a 2622 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2623 mqd->cp_hqd_dequeue_request);
5e78835a 2624 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2625 mqd->cp_hqd_pq_rptr);
5e78835a 2626 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2627 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2628 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2629 mqd->cp_hqd_pq_wptr_hi);
2630 }
2631
2632 /* set the pointer to the MQD */
5e78835a 2633 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2634 mqd->cp_mqd_base_addr_lo);
5e78835a 2635 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2636 mqd->cp_mqd_base_addr_hi);
2637
2638 /* set MQD vmid to 0 */
5e78835a 2639 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2640 mqd->cp_mqd_control);
2641
2642 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2643 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2644 mqd->cp_hqd_pq_base_lo);
5e78835a 2645 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2646 mqd->cp_hqd_pq_base_hi);
2647
2648 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2649 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2650 mqd->cp_hqd_pq_control);
2651
2652 /* set the wb address whether it's enabled or not */
5e78835a 2653 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2654 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2655 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2656 mqd->cp_hqd_pq_rptr_report_addr_hi);
2657
2658 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2659 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2660 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2661 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2662 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2663
2664 /* enable the doorbell if requested */
2665 if (ring->use_doorbell) {
5e78835a 2666 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2667 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2668 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2669 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2670 }
2671
5e78835a 2672 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2673 mqd->cp_hqd_pq_doorbell_control);
2674
2675 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2676 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2677 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2678 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2679 mqd->cp_hqd_pq_wptr_hi);
2680
2681 /* set the vmid for the queue */
5e78835a 2682 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2683
5e78835a 2684 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2685 mqd->cp_hqd_persistent_state);
2686
2687 /* activate the queue */
5e78835a 2688 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2689 mqd->cp_hqd_active);
2690
72edadd5
TSD		 2691 if (ring->use_doorbell)
2692 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2693
2694 return 0;
2695}
2696
e322edc3 2697static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2698{
2699 struct amdgpu_device *adev = ring->adev;
e322edc3 2700 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2701 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2702
898b7893 2703 gfx_v9_0_kiq_setting(ring);
464826d6 2704
13a752e3 2705 if (adev->in_gpu_reset) { /* for GPU_RESET case */
464826d6 2706 /* reset MQD to a clean status */
0ef376ca 2707 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2708 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2709
2710 /* reset ring buffer */
2711 ring->wptr = 0;
b98724db 2712 amdgpu_ring_clear_ring(ring);
464826d6 2713
898b7893
AD		 2714 mutex_lock(&adev->srbm_mutex);
2715 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2716 gfx_v9_0_kiq_init_register(ring);
2717 soc15_grbm_select(adev, 0, 0, 0, 0);
2718 mutex_unlock(&adev->srbm_mutex);
464826d6 2719 } else {
ffe6d881
AD		 2720 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2721 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2722 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
ba0c19f5
AD		 2723 mutex_lock(&adev->srbm_mutex);
2724 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2725 gfx_v9_0_mqd_init(ring);
2726 gfx_v9_0_kiq_init_register(ring);
2727 soc15_grbm_select(adev, 0, 0, 0, 0);
2728 mutex_unlock(&adev->srbm_mutex);
2729
2730 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2731 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
464826d6
XY		 2732 }
2733
0f1dfd52 2734 return 0;
898b7893
AD		 2735}
2736
2737static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2738{
2739 struct amdgpu_device *adev = ring->adev;
898b7893
AD		 2740 struct v9_mqd *mqd = ring->mqd_ptr;
2741 int mqd_idx = ring - &adev->gfx.compute_ring[0];
898b7893 2742
13a752e3 2743 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
ffe6d881
AD		 2744 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2745 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2746 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
464826d6
XY		 2747 mutex_lock(&adev->srbm_mutex);
2748 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2749 gfx_v9_0_mqd_init(ring);
464826d6
XY		 2750 soc15_grbm_select(adev, 0, 0, 0, 0);
2751 mutex_unlock(&adev->srbm_mutex);
2752
898b7893 2753 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2754 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
13a752e3 2755 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
464826d6 2756 /* reset MQD to a clean status */
898b7893 2757 if (adev->gfx.mec.mqd_backup[mqd_idx])
ffe6d881 2758 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
464826d6
XY		 2759
2760 /* reset ring buffer */
2761 ring->wptr = 0;
898b7893 2762 amdgpu_ring_clear_ring(ring);
ba0c19f5
AD		 2763 } else {
2764 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2765 }
2766
464826d6
XY		 2767 return 0;
2768}
2769
2770static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2771{
2772 struct amdgpu_ring *ring = NULL;
2773 int r = 0, i;
2774
2775 gfx_v9_0_cp_compute_enable(adev, true);
2776
2777 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2778
2779 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2780 if (unlikely(r != 0))
2781 goto done;
2782
2783 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2784 if (!r) {
e322edc3 2785 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2786 amdgpu_bo_kunmap(ring->mqd_obj);
2787 ring->mqd_ptr = NULL;
464826d6 2788 }
e1d53aa8
AD		 2789 amdgpu_bo_unreserve(ring->mqd_obj);
2790 if (r)
2791 goto done;
464826d6
XY		 2792
2793 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2794 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2795
2796 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2797 if (unlikely(r != 0))
2798 goto done;
2799 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2800 if (!r) {
898b7893 2801 r = gfx_v9_0_kcq_init_queue(ring);
464826d6
XY		 2802 amdgpu_bo_kunmap(ring->mqd_obj);
2803 ring->mqd_ptr = NULL;
464826d6 2804 }
e1d53aa8
AD		 2805 amdgpu_bo_unreserve(ring->mqd_obj);
2806 if (r)
2807 goto done;
464826d6
XY		 2808 }
2809
0f1dfd52 2810 r = gfx_v9_0_kiq_kcq_enable(adev);
e1d53aa8
AD		 2811done:
2812 return r;
464826d6
XY		 2813}
2814
b1023571
KW		 2815static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2816{
bd3402ea 2817 int r, i;
b1023571
KW		 2818 struct amdgpu_ring *ring;
2819
2820 if (!(adev->flags & AMD_IS_APU))
2821 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2822
2823 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2824 /* legacy firmware loading */
2825 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2826 if (r)
2827 return r;
2828
2829 r = gfx_v9_0_cp_compute_load_microcode(adev);
2830 if (r)
2831 return r;
2832 }
2833
2834 r = gfx_v9_0_cp_gfx_resume(adev);
2835 if (r)
2836 return r;
2837
e30a5223 2838 r = gfx_v9_0_kiq_resume(adev);
b1023571
KW		 2839 if (r)
2840 return r;
2841
2842 ring = &adev->gfx.gfx_ring[0];
2843 r = amdgpu_ring_test_ring(ring);
2844 if (r) {
2845 ring->ready = false;
2846 return r;
2847 }
e30a5223
AD		 2848
2849 ring = &adev->gfx.kiq.ring;
2850 ring->ready = true;
2851 r = amdgpu_ring_test_ring(ring);
2852 if (r)
2853 ring->ready = false;
2854
b1023571
KW		 2855 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2856 ring = &adev->gfx.compute_ring[i];
2857
2858 ring->ready = true;
2859 r = amdgpu_ring_test_ring(ring);
2860 if (r)
2861 ring->ready = false;
2862 }
2863
2864 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2865
2866 return 0;
2867}
2868
2869static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2870{
2871 gfx_v9_0_cp_gfx_enable(adev, enable);
2872 gfx_v9_0_cp_compute_enable(adev, enable);
2873}
2874
2875static int gfx_v9_0_hw_init(void *handle)
2876{
2877 int r;
2878 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2879
2880 gfx_v9_0_init_golden_registers(adev);
2881
2882 gfx_v9_0_gpu_init(adev);
2883
2884 r = gfx_v9_0_rlc_resume(adev);
2885 if (r)
2886 return r;
2887
2888 r = gfx_v9_0_cp_resume(adev);
2889 if (r)
2890 return r;
2891
2892 r = gfx_v9_0_ngg_en(adev);
2893 if (r)
2894 return r;
2895
2896 return r;
2897}
2898
85f95ad6
ML		 2899static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
2900{
2901 struct amdgpu_device *adev = kiq_ring->adev;
2902 uint32_t scratch, tmp = 0;
2903 int r, i;
2904
2905 r = amdgpu_gfx_scratch_get(adev, &scratch);
2906 if (r) {
2907 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2908 return r;
2909 }
2910 WREG32(scratch, 0xCAFEDEAD);
2911
2912 r = amdgpu_ring_alloc(kiq_ring, 10);
2913 if (r) {
2914 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2915 amdgpu_gfx_scratch_free(adev, scratch);
2916 return r;
2917 }
2918
2919 /* unmap queues */
2920 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2921 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2922 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
2923 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
2924 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
2925 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
2926 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
2927 amdgpu_ring_write(kiq_ring, 0);
2928 amdgpu_ring_write(kiq_ring, 0);
2929 amdgpu_ring_write(kiq_ring, 0);
2930 /* write to scratch for completion */
2931 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2932 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2933 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2934 amdgpu_ring_commit(kiq_ring);
2935
2936 for (i = 0; i < adev->usec_timeout; i++) {
2937 tmp = RREG32(scratch);
2938 if (tmp == 0xDEADBEEF)
2939 break;
2940 DRM_UDELAY(1);
2941 }
2942 if (i >= adev->usec_timeout) {
2943 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
2944 r = -EINVAL;
2945 }
2946 amdgpu_gfx_scratch_free(adev, scratch);
2947 return r;
2948}
2949
2950
b1023571
KW		 2951static int gfx_v9_0_hw_fini(void *handle)
2952{
2953 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
85f95ad6 2954 int i;
b1023571
KW		 2955
2956 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2957 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
85f95ad6
ML		 2958
2959 /* disable KCQ to avoid CPC touch memory not valid anymore */
2960 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2961 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
2962
464826d6 2963 if (amdgpu_sriov_vf(adev)) {
9f0178fb
ML		 2964 gfx_v9_0_cp_gfx_enable(adev, false);
2965 /* must disable polling for SRIOV when hw finished, otherwise
2966 * CPC engine may still keep fetching WB address which is already
2967 * invalid after sw finished and trigger DMAR reading error in
2968 * hypervisor side.
2969 */
2970 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6
XY		 2971 return 0;
2972 }
b1023571
KW		 2973 gfx_v9_0_cp_enable(adev, false);
2974 gfx_v9_0_rlc_stop(adev);
b1023571
KW		 2975
2976 return 0;
2977}
2978
2979static int gfx_v9_0_suspend(void *handle)
2980{
2981 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2982
e30a5223 2983 adev->gfx.in_suspend = true;
b1023571
KW		 2984 return gfx_v9_0_hw_fini(adev);
2985}
2986
2987static int gfx_v9_0_resume(void *handle)
2988{
2989 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e30a5223 2990 int r;
b1023571 2991
e30a5223
AD		 2992 r = gfx_v9_0_hw_init(adev);
2993 adev->gfx.in_suspend = false;
2994 return r;
b1023571
KW		 2995}
2996
2997static bool gfx_v9_0_is_idle(void *handle)
2998{
2999 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3000
5e78835a 3001 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 3002 GRBM_STATUS, GUI_ACTIVE))
3003 return false;
3004 else
3005 return true;
3006}
3007
3008static int gfx_v9_0_wait_for_idle(void *handle)
3009{
3010 unsigned i;
b1023571
KW		 3011 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3012
3013 for (i = 0; i < adev->usec_timeout; i++) {
2b9bdfa7 3014 if (gfx_v9_0_is_idle(handle))
b1023571
KW		 3015 return 0;
3016 udelay(1);
3017 }
3018 return -ETIMEDOUT;
3019}
3020
b1023571
KW		 3021static int gfx_v9_0_soft_reset(void *handle)
3022{
3023 u32 grbm_soft_reset = 0;
3024 u32 tmp;
3025 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3026
3027 /* GRBM_STATUS */
5e78835a 3028 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3029 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3030 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3031 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3032 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3033 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3034 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3035 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3036 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3037 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3038 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3039 }
3040
3041 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3042 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3043 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3044 }
3045
3046 /* GRBM_STATUS2 */
5e78835a 3047 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3048 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3049 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3050 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3051
3052
75bac5c6 3053 if (grbm_soft_reset) {
b1023571
KW		 3054 /* stop the rlc */
3055 gfx_v9_0_rlc_stop(adev);
3056
3057 /* Disable GFX parsing/prefetching */
3058 gfx_v9_0_cp_gfx_enable(adev, false);
3059
3060 /* Disable MEC parsing/prefetching */
3061 gfx_v9_0_cp_compute_enable(adev, false);
3062
3063 if (grbm_soft_reset) {
5e78835a 3064 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3065 tmp |= grbm_soft_reset;
3066 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3067 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3068 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3069
3070 udelay(50);
3071
3072 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3073 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3074 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3075 }
3076
3077 /* Wait a little for things to settle down */
3078 udelay(50);
b1023571
KW		 3079 }
3080 return 0;
3081}
3082
3083static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3084{
3085 uint64_t clock;
3086
3087 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3088 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3089 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3090 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3091 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3092 return clock;
3093}
3094
3095static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3096 uint32_t vmid,
3097 uint32_t gds_base, uint32_t gds_size,
3098 uint32_t gws_base, uint32_t gws_size,
3099 uint32_t oa_base, uint32_t oa_size)
3100{
946a4d5b
SL		 3101 struct amdgpu_device *adev = ring->adev;
3102
b1023571
KW		 3103 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3104 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3105
3106 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3107 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3108
3109 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3110 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3111
3112 /* GDS Base */
3113 gfx_v9_0_write_data_to_reg(ring, 0, false,
946a4d5b 3114 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
b1023571
KW		 3115 gds_base);
3116
3117 /* GDS Size */
3118 gfx_v9_0_write_data_to_reg(ring, 0, false,
946a4d5b 3119 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
b1023571
KW		 3120 gds_size);
3121
3122 /* GWS */
3123 gfx_v9_0_write_data_to_reg(ring, 0, false,
946a4d5b 3124 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
b1023571
KW		 3125 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3126
3127 /* OA */
3128 gfx_v9_0_write_data_to_reg(ring, 0, false,
946a4d5b 3129 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
b1023571
KW		 3130 (1 << (oa_size + oa_base)) - (1 << oa_base));
3131}
3132
3133static int gfx_v9_0_early_init(void *handle)
3134{
3135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3136
3137 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
78c16834 3138 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b1023571
KW		 3139 gfx_v9_0_set_ring_funcs(adev);
3140 gfx_v9_0_set_irq_funcs(adev);
3141 gfx_v9_0_set_gds_init(adev);
3142 gfx_v9_0_set_rlc_funcs(adev);
3143
3144 return 0;
3145}
3146
3147static int gfx_v9_0_late_init(void *handle)
3148{
3149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3150 int r;
3151
3152 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3153 if (r)
3154 return r;
3155
3156 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3157 if (r)
3158 return r;
3159
3160 return 0;
3161}
3162
3163static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3164{
3165 uint32_t rlc_setting, data;
3166 unsigned i;
3167
3168 if (adev->gfx.rlc.in_safe_mode)
3169 return;
3170
3171 /* if RLC is not enabled, do nothing */
5e78835a 3172 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3173 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3174 return;
3175
3176 if (adev->cg_flags &
3177 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3178 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3179 data = RLC_SAFE_MODE__CMD_MASK;
3180 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3181 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3182
3183 /* wait for RLC_SAFE_MODE */
3184 for (i = 0; i < adev->usec_timeout; i++) {
3185 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3186 break;
3187 udelay(1);
3188 }
3189 adev->gfx.rlc.in_safe_mode = true;
3190 }
3191}
3192
3193static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3194{
3195 uint32_t rlc_setting, data;
3196
3197 if (!adev->gfx.rlc.in_safe_mode)
3198 return;
3199
3200 /* if RLC is not enabled, do nothing */
5e78835a 3201 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3202 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3203 return;
3204
3205 if (adev->cg_flags &
3206 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3207 /*
3208 * Try to exit safe mode only if it is already in safe
3209 * mode.
3210 */
3211 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3212 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3213 adev->gfx.rlc.in_safe_mode = false;
3214 }
3215}
3216
197f95c8
HZ		 3217static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3218 bool enable)
3219{
3220 /* TODO: double check if we need to perform under safe mdoe */
3221 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3222
3223 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3224 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3225 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3226 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3227 } else {
3228 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3229 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3230 }
3231
3232 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3233}
3234
18924c71
HZ		 3235static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3236 bool enable)
3237{
3238 /* TODO: double check if we need to perform under safe mode */
3239 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3240
3241 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3242 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3243 else
3244 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3245
3246 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3247 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3248 else
3249 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3250
3251 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3252}
3253
b1023571
KW		 3254static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3255 bool enable)
3256{
3257 uint32_t data, def;
3258
3259 /* It is disabled by HW by default */
3260 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3261 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3262 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3263 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3264 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3265 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3266 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3267
3268 /* only for Vega10 & Raven1 */
3269 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3270
3271 if (def != data)
5e78835a 3272 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3273
3274 /* MGLS is a global flag to control all MGLS in GFX */
3275 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3276 /* 2 - RLC memory Light sleep */
3277 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3278 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3279 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3280 if (def != data)
5e78835a 3281 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3282 }
3283 /* 3 - CP memory Light sleep */
3284 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3285 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3286 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3287 if (def != data)
5e78835a 3288 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3289 }
3290 }
3291 } else {
3292 /* 1 - MGCG_OVERRIDE */
5e78835a 3293 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3294 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3295 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3296 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3297 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3298 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3299 if (def != data)
5e78835a 3300 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3301
3302 /* 2 - disable MGLS in RLC */
5e78835a 3303 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3304 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3305 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3306 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3307 }
3308
3309 /* 3 - disable MGLS in CP */
5e78835a 3310 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3311 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3312 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3313 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3314 }
3315 }
3316}
3317
3318static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3319 bool enable)
3320{
3321 uint32_t data, def;
3322
3323 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3324
3325 /* Enable 3D CGCG/CGLS */
3326 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3327 /* write cmd to clear cgcg/cgls ov */
5e78835a 3328 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3329 /* unset CGCG override */
3330 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3331 /* update CGCG and CGLS override bits */
3332 if (def != data)
5e78835a 3333 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3334 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3335 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3336 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3337 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3338 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3339 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3340 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3341 if (def != data)
5e78835a 3342 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3343
3344 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3345 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3346 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3347 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3348 if (def != data)
5e78835a 3349 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3350 } else {
3351 /* Disable CGCG/CGLS */
5e78835a 3352 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3353 /* disable cgcg, cgls should be disabled */
3354 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3355 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3356 /* disable cgcg and cgls in FSM */
3357 if (def != data)
5e78835a 3358 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3359 }
3360
3361 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3362}
3363
3364static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3365 bool enable)
3366{
3367 uint32_t def, data;
3368
3369 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3370
3371 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3372 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3373 /* unset CGCG override */
3374 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3375 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3376 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3377 else
3378 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3379 /* update CGCG and CGLS override bits */
3380 if (def != data)
5e78835a 3381 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3382
3383 /* enable cgcg FSM(0x0020003F) */
5e78835a 3384 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3385 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3386 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3387 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3388 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3389 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3390 if (def != data)
5e78835a 3391 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3392
3393 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3394 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3395 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3396 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3397 if (def != data)
5e78835a 3398 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3399 } else {
5e78835a 3400 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3401 /* reset CGCG/CGLS bits */
3402 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3403 /* disable cgcg and cgls in FSM */
3404 if (def != data)
5e78835a 3405 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3406 }
3407
3408 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3409}
3410
3411static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3412 bool enable)
3413{
3414 if (enable) {
3415 /* CGCG/CGLS should be enabled after MGCG/MGLS
3416 * === MGCG + MGLS ===
3417 */
3418 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3419 /* === CGCG /CGLS for GFX 3D Only === */
3420 gfx_v9_0_update_3d_clock_gating(adev, enable);
3421 /* === CGCG + CGLS === */
3422 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3423 } else {
3424 /* CGCG/CGLS should be disabled before MGCG/MGLS
3425 * === CGCG + CGLS ===
3426 */
3427 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3428 /* === CGCG /CGLS for GFX 3D Only === */
3429 gfx_v9_0_update_3d_clock_gating(adev, enable);
3430 /* === MGCG + MGLS === */
3431 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3432 }
3433 return 0;
3434}
3435
3436static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3437 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3438 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3439};
3440
3441static int gfx_v9_0_set_powergating_state(void *handle,
3442 enum amd_powergating_state state)
3443{
5897c99e 3444 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197f95c8 3445 bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
5897c99e
HZ		 3446
3447 switch (adev->asic_type) {
3448 case CHIP_RAVEN:
3449 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3450 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3451 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3452 } else {
3453 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3454 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3455 }
3456
3457 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3458 gfx_v9_0_enable_cp_power_gating(adev, true);
3459 else
3460 gfx_v9_0_enable_cp_power_gating(adev, false);
197f95c8
HZ		 3461
3462 /* update gfx cgpg state */
3463 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
18924c71
HZ		 3464
3465 /* update mgcg state */
3466 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5897c99e
HZ		 3467 break;
3468 default:
3469 break;
3470 }
3471
b1023571
KW		 3472 return 0;
3473}
3474
3475static int gfx_v9_0_set_clockgating_state(void *handle,
3476 enum amd_clockgating_state state)
3477{
3478 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3479
fb82afab
XY		 3480 if (amdgpu_sriov_vf(adev))
3481 return 0;
3482
b1023571
KW		 3483 switch (adev->asic_type) {
3484 case CHIP_VEGA10:
a4dc61f5 3485 case CHIP_RAVEN:
b1023571
KW		 3486 gfx_v9_0_update_gfx_clock_gating(adev,
3487 state == AMD_CG_STATE_GATE ? true : false);
3488 break;
3489 default:
3490 break;
3491 }
3492 return 0;
3493}
3494
12ad27fa
HR		 3495static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3496{
3497 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3498 int data;
3499
3500 if (amdgpu_sriov_vf(adev))
3501 *flags = 0;
3502
3503 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3504 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3505 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3506 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3507
3508 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3509 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3510 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3511 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3512
3513 /* AMD_CG_SUPPORT_GFX_CGLS */
3514 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3515 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3516
3517 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3518 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3519 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3520 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3521
3522 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3523 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3524 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3525 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3526
3527 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3528 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3529 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3530 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3531
3532 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3533 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3534 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3535}
3536
b1023571
KW		 3537static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3538{
3539 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3540}
3541
3542static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3543{
3544 struct amdgpu_device *adev = ring->adev;
3545 u64 wptr;
3546
3547 /* XXX check if swapping is necessary on BE */
3548 if (ring->use_doorbell) {
3549 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3550 } else {
5e78835a
TSD		 3551 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3552 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3553 }
3554
3555 return wptr;
3556}
3557
3558static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3559{
3560 struct amdgpu_device *adev = ring->adev;
3561
3562 if (ring->use_doorbell) {
3563 /* XXX check if swapping is necessary on BE */
3564 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3565 WDOORBELL64(ring->doorbell_index, ring->wptr);
3566 } else {
5e78835a
TSD		 3567 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3568 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3569 }
3570}
3571
3572static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3573{
946a4d5b 3574 struct amdgpu_device *adev = ring->adev;
b1023571 3575 u32 ref_and_mask, reg_mem_engine;
bf383fb6 3576 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
b1023571
KW		 3577
3578 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3579 switch (ring->me) {
3580 case 1:
3581 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3582 break;
3583 case 2:
3584 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3585 break;
3586 default:
3587 return;
3588 }
3589 reg_mem_engine = 0;
3590 } else {
3591 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3592 reg_mem_engine = 1; /* pfp */
3593 }
3594
3595 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
946a4d5b
SL		 3596 adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3597 adev->nbio_funcs->get_hdp_flush_done_offset(adev),
b1023571
KW		 3598 ref_and_mask, ref_and_mask, 0x20);
3599}
3600
b1023571
KW		 3601static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3602 struct amdgpu_ib *ib,
c4f46f22 3603 unsigned vmid, bool ctx_switch)
b1023571 3604{
eaa05d52 3605 u32 header, control = 0;
b1023571 3606
eaa05d52
ML		 3607 if (ib->flags & AMDGPU_IB_FLAG_CE)
3608 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3609 else
3610 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3611
c4f46f22 3612 control |= ib->length_dw | (vmid << 24);
b1023571 3613
635e7132 3614 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3615 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3616
635e7132
ML		 3617 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3618 gfx_v9_0_ring_emit_de_meta(ring);
3619 }
3620
eaa05d52
ML		 3621 amdgpu_ring_write(ring, header);
3622BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3623 amdgpu_ring_write(ring,
b1023571 3624#ifdef __BIG_ENDIAN
eaa05d52 3625 (2 << 0) |
b1023571 3626#endif
eaa05d52
ML		 3627 lower_32_bits(ib->gpu_addr));
3628 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3629 amdgpu_ring_write(ring, control);
b1023571
KW		 3630}
3631
b1023571
KW		 3632static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3633 struct amdgpu_ib *ib,
c4f46f22 3634 unsigned vmid, bool ctx_switch)
b1023571 3635{
c4f46f22 3636 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
b1023571
KW		 3637
3638 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3639 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3640 amdgpu_ring_write(ring,
3641#ifdef __BIG_ENDIAN
3642 (2 << 0) |
3643#endif
3644 lower_32_bits(ib->gpu_addr));
3645 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3646 amdgpu_ring_write(ring, control);
3647}
3648
3649static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3650 u64 seq, unsigned flags)
3651{
3652 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3653 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3654
3655 /* RELEASE_MEM - flush caches, send int */
3656 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3657 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3658 EOP_TC_ACTION_EN |
3659 EOP_TC_WB_ACTION_EN |
3660 EOP_TC_MD_ACTION_EN |
3661 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3662 EVENT_INDEX(5)));
3663 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3664
3665 /*
3666 * the address should be Qword aligned if 64bit write, Dword
3667 * aligned if only send 32bit data low (discard data high)
3668 */
3669 if (write64bit)
3670 BUG_ON(addr & 0x7);
3671 else
3672 BUG_ON(addr & 0x3);
3673 amdgpu_ring_write(ring, lower_32_bits(addr));
3674 amdgpu_ring_write(ring, upper_32_bits(addr));
3675 amdgpu_ring_write(ring, lower_32_bits(seq));
3676 amdgpu_ring_write(ring, upper_32_bits(seq));
3677 amdgpu_ring_write(ring, 0);
3678}
3679
3680static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3681{
3682 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3683 uint32_t seq = ring->fence_drv.sync_seq;
3684 uint64_t addr = ring->fence_drv.gpu_addr;
3685
3686 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3687 lower_32_bits(addr), upper_32_bits(addr),
3688 seq, 0xffffffff, 4);
3689}
3690
3691static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
c633c00b 3692 unsigned vmid, uint64_t pd_addr)
b1023571 3693{
c633c00b 3694 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
b1023571 3695
b1023571 3696 /* compute doesn't have PFP */
9096d6e5 3697 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
b1023571
KW		 3698 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3699 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3700 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3701 }
3702}
3703
3704static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3705{
3706 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3707}
3708
3709static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3710{
3711 u64 wptr;
3712
3713 /* XXX check if swapping is necessary on BE */
3714 if (ring->use_doorbell)
3715 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3716 else
3717 BUG();
3718 return wptr;
3719}
3720
761c77c1
AR		 3721static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
3722 bool acquire)
3723{
3724 struct amdgpu_device *adev = ring->adev;
3725 int pipe_num, tmp, reg;
3726 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
3727
3728 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
3729
3730 /* first me only has 2 entries, GFX and HP3D */
3731 if (ring->me > 0)
3732 pipe_num -= 2;
3733
3734 reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
3735 tmp = RREG32(reg);
3736 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
3737 WREG32(reg, tmp);
3738}
3739
3740static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
3741 struct amdgpu_ring *ring,
3742 bool acquire)
3743{
3744 int i, pipe;
3745 bool reserve;
3746 struct amdgpu_ring *iring;
3747
3748 mutex_lock(&adev->gfx.pipe_reserve_mutex);
3749 pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
3750 if (acquire)
3751 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
3752 else
3753 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
3754
3755 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
3756 /* Clear all reservations - everyone reacquires all resources */
3757 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
3758 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
3759 true);
3760
3761 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
3762 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
3763 true);
3764 } else {
3765 /* Lower all pipes without a current reservation */
3766 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
3767 iring = &adev->gfx.gfx_ring[i];
3768 pipe = amdgpu_gfx_queue_to_bit(adev,
3769 iring->me,
3770 iring->pipe,
3771 0);
3772 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
3773 gfx_v9_0_ring_set_pipe_percent(iring, reserve);
3774 }
3775
3776 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
3777 iring = &adev->gfx.compute_ring[i];
3778 pipe = amdgpu_gfx_queue_to_bit(adev,
3779 iring->me,
3780 iring->pipe,
3781 0);
3782 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
3783 gfx_v9_0_ring_set_pipe_percent(iring, reserve);
3784 }
3785 }
3786
3787 mutex_unlock(&adev->gfx.pipe_reserve_mutex);
3788}
3789
3790static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
3791 struct amdgpu_ring *ring,
3792 bool acquire)
3793{
3794 uint32_t pipe_priority = acquire ? 0x2 : 0x0;
3795 uint32_t queue_priority = acquire ? 0xf : 0x0;
3796
3797 mutex_lock(&adev->srbm_mutex);
3798 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3799
3800 WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
3801 WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
3802
3803 soc15_grbm_select(adev, 0, 0, 0, 0);
3804 mutex_unlock(&adev->srbm_mutex);
3805}
3806
3807static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
3808 enum drm_sched_priority priority)
3809{
3810 struct amdgpu_device *adev = ring->adev;
3811 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
3812
3813 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
3814 return;
3815
3816 gfx_v9_0_hqd_set_priority(adev, ring, acquire);
3817 gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
3818}
3819
b1023571
KW		 3820static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3821{
3822 struct amdgpu_device *adev = ring->adev;
3823
3824 /* XXX check if swapping is necessary on BE */
3825 if (ring->use_doorbell) {
3826 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3827 WDOORBELL64(ring->doorbell_index, ring->wptr);
3828 } else{
3829 BUG(); /* only DOORBELL method supported on gfx9 now */
3830 }
3831}
3832
aa6faa44
XY		 3833static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3834 u64 seq, unsigned int flags)
3835{
cd29253f
SL		 3836 struct amdgpu_device *adev = ring->adev;
3837
aa6faa44
XY		 3838 /* we only allocate 32bit for each seq wb address */
3839 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3840
3841 /* write fence seq to the "addr" */
3842 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3843 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3844 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3845 amdgpu_ring_write(ring, lower_32_bits(addr));
3846 amdgpu_ring_write(ring, upper_32_bits(addr));
3847 amdgpu_ring_write(ring, lower_32_bits(seq));
3848
3849 if (flags & AMDGPU_FENCE_FLAG_INT) {
3850 /* set register to trigger INT */
3851 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3852 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3853 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3854 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3855 amdgpu_ring_write(ring, 0);
3856 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3857 }
3858}
3859
b1023571
KW		 3860static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3861{
3862 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3863 amdgpu_ring_write(ring, 0);
3864}
3865
cca02cd3
XY		 3866static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3867{
d81a2209 3868 struct v9_ce_ib_state ce_payload = {0};
cca02cd3
XY		 3869 uint64_t csa_addr;
3870 int cnt;
3871
3872 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
6f05c4e9 3873 csa_addr = amdgpu_csa_vaddr(ring->adev);
cca02cd3
XY		 3874
3875 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3876 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3877 WRITE_DATA_DST_SEL(8) |
3878 WR_CONFIRM) |
3879 WRITE_DATA_CACHE_POLICY(0));
3880 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3881 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3882 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3883}
3884
3885static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3886{
d81a2209 3887 struct v9_de_ib_state de_payload = {0};
cca02cd3
XY		 3888 uint64_t csa_addr, gds_addr;
3889 int cnt;
3890
6f05c4e9 3891 csa_addr = amdgpu_csa_vaddr(ring->adev);
cca02cd3
XY		 3892 gds_addr = csa_addr + 4096;
3893 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3894 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3895
3896 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3897 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3898 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3899 WRITE_DATA_DST_SEL(8) |
3900 WR_CONFIRM) |
3901 WRITE_DATA_CACHE_POLICY(0));
3902 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3903 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3904 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3905}
3906
2ea6ab27
ML		 3907static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3908{
3909 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3910 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3911}
3912
b1023571
KW		 3913static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3914{
3915 uint32_t dw2 = 0;
3916
cca02cd3
XY		 3917 if (amdgpu_sriov_vf(ring->adev))
3918 gfx_v9_0_ring_emit_ce_meta(ring);
3919
2ea6ab27
ML		 3920 gfx_v9_0_ring_emit_tmz(ring, true);
3921
b1023571
KW		 3922 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3923 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3924 /* set load_global_config & load_global_uconfig */
3925 dw2 |= 0x8001;
3926 /* set load_cs_sh_regs */
3927 dw2 |= 0x01000000;
3928 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3929 dw2 |= 0x10002;
3930
3931 /* set load_ce_ram if preamble presented */
3932 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3933 dw2 |= 0x10000000;
3934 } else {
3935 /* still load_ce_ram if this is the first time preamble presented
3936 * although there is no context switch happens.
3937 */
3938 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3939 dw2 |= 0x10000000;
3940 }
3941
3942 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3943 amdgpu_ring_write(ring, dw2);
3944 amdgpu_ring_write(ring, 0);
3945}
3946
9a5e02b5
ML		 3947static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3948{
3949 unsigned ret;
3950 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3951 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3952 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3953 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3954 ret = ring->wptr & ring->buf_mask;
3955 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3956 return ret;
3957}
3958
3959static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3960{
3961 unsigned cur;
3962 BUG_ON(offset > ring->buf_mask);
3963 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3964
3965 cur = (ring->wptr & ring->buf_mask) - 1;
3966 if (likely(cur > offset))
3967 ring->ring[offset] = cur - offset;
3968 else
3969 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3970}
3971
aa6faa44
XY		 3972static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3973{
3974 struct amdgpu_device *adev = ring->adev;
3975
3976 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3977 amdgpu_ring_write(ring, 0 | /* src: register*/
3978 (5 << 8) | /* dst: memory */
3979 (1 << 20)); /* write confirm */
3980 amdgpu_ring_write(ring, reg);
3981 amdgpu_ring_write(ring, 0);
3982 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3983 adev->virt.reg_val_offs * 4));
3984 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3985 adev->virt.reg_val_offs * 4));
3986}
3987
3988static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
254e825b 3989 uint32_t val)
aa6faa44 3990{
254e825b
CK		 3991 uint32_t cmd = 0;
3992
3993 switch (ring->funcs->type) {
3994 case AMDGPU_RING_TYPE_GFX:
3995 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
3996 break;
3997 case AMDGPU_RING_TYPE_KIQ:
3998 cmd = (1 << 16); /* no inc addr */
3999 break;
4000 default:
4001 cmd = WR_CONFIRM;
4002 break;
4003 }
aa6faa44 4004 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
254e825b 4005 amdgpu_ring_write(ring, cmd);
aa6faa44
XY		 4006 amdgpu_ring_write(ring, reg);
4007 amdgpu_ring_write(ring, 0);
4008 amdgpu_ring_write(ring, val);
4009}
4010
230fcc34
CK		 4011static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4012 uint32_t val, uint32_t mask)
4013{
4014 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4015}
4016
b1023571
KW		 4017static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4018 enum amdgpu_interrupt_state state)
4019{
b1023571
KW		 4020 switch (state) {
4021 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4022 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 4023 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4024 TIME_STAMP_INT_ENABLE,
4025 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4026 break;
4027 default:
4028 break;
4029 }
4030}
4031
4032static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4033 int me, int pipe,
4034 enum amdgpu_interrupt_state state)
4035{
4036 u32 mec_int_cntl, mec_int_cntl_reg;
4037
4038 /*
d0c55cdf
AD		 4039 * amdgpu controls only the first MEC. That's why this function only
4040 * handles the setting of interrupts for this specific MEC. All other
b1023571
KW		 4041 * pipes' interrupts are set by amdkfd.
4042 */
4043
4044 if (me == 1) {
4045 switch (pipe) {
4046 case 0:
4047 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4048 break;
d0c55cdf
AD		 4049 case 1:
4050 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4051 break;
4052 case 2:
4053 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4054 break;
4055 case 3:
4056 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4057 break;
b1023571
KW		 4058 default:
4059 DRM_DEBUG("invalid pipe %d\n", pipe);
4060 return;
4061 }
4062 } else {
4063 DRM_DEBUG("invalid me %d\n", me);
4064 return;
4065 }
4066
4067 switch (state) {
4068 case AMDGPU_IRQ_STATE_DISABLE:
4069 mec_int_cntl = RREG32(mec_int_cntl_reg);
4070 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4071 TIME_STAMP_INT_ENABLE, 0);
4072 WREG32(mec_int_cntl_reg, mec_int_cntl);
4073 break;
4074 case AMDGPU_IRQ_STATE_ENABLE:
4075 mec_int_cntl = RREG32(mec_int_cntl_reg);
4076 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4077 TIME_STAMP_INT_ENABLE, 1);
4078 WREG32(mec_int_cntl_reg, mec_int_cntl);
4079 break;
4080 default:
4081 break;
4082 }
4083}
4084
4085static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4086 struct amdgpu_irq_src *source,
4087 unsigned type,
4088 enum amdgpu_interrupt_state state)
4089{
b1023571
KW		 4090 switch (state) {
4091 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4092 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 4093 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4094 PRIV_REG_INT_ENABLE,
4095 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4096 break;
4097 default:
4098 break;
4099 }
4100
4101 return 0;
4102}
4103
4104static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4105 struct amdgpu_irq_src *source,
4106 unsigned type,
4107 enum amdgpu_interrupt_state state)
4108{
b1023571
KW		 4109 switch (state) {
4110 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 4111 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 4112 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4113 PRIV_INSTR_INT_ENABLE,
4114 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 4115 default:
4116 break;
4117 }
4118
4119 return 0;
4120}
4121
4122static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4123 struct amdgpu_irq_src *src,
4124 unsigned type,
4125 enum amdgpu_interrupt_state state)
4126{
4127 switch (type) {
4128 case AMDGPU_CP_IRQ_GFX_EOP:
4129 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4130 break;
4131 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4132 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4133 break;
4134 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4135 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4136 break;
4137 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4138 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4139 break;
4140 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4141 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4142 break;
4143 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4144 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4145 break;
4146 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4147 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4148 break;
4149 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4150 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4151 break;
4152 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4153 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4154 break;
4155 default:
4156 break;
4157 }
4158 return 0;
4159}
4160
4161static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4162 struct amdgpu_irq_src *source,
4163 struct amdgpu_iv_entry *entry)
4164{
4165 int i;
4166 u8 me_id, pipe_id, queue_id;
4167 struct amdgpu_ring *ring;
4168
4169 DRM_DEBUG("IH: CP EOP\n");
4170 me_id = (entry->ring_id & 0x0c) >> 2;
4171 pipe_id = (entry->ring_id & 0x03) >> 0;
4172 queue_id = (entry->ring_id & 0x70) >> 4;
4173
4174 switch (me_id) {
4175 case 0:
4176 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4177 break;
4178 case 1:
4179 case 2:
4180 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4181 ring = &adev->gfx.compute_ring[i];
4182 /* Per-queue interrupt is supported for MEC starting from VI.
4183 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4184 */
4185 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4186 amdgpu_fence_process(ring);
4187 }
4188 break;
4189 }
4190 return 0;
4191}
4192
4193static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4194 struct amdgpu_irq_src *source,
4195 struct amdgpu_iv_entry *entry)
4196{
4197 DRM_ERROR("Illegal register access in command stream\n");
4198 schedule_work(&adev->reset_work);
4199 return 0;
4200}
4201
4202static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4203 struct amdgpu_irq_src *source,
4204 struct amdgpu_iv_entry *entry)
4205{
4206 DRM_ERROR("Illegal instruction in command stream\n");
4207 schedule_work(&adev->reset_work);
4208 return 0;
4209}
4210
97031e25
XY		 4211static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4212 struct amdgpu_irq_src *src,
4213 unsigned int type,
4214 enum amdgpu_interrupt_state state)
4215{
4216 uint32_t tmp, target;
1c4ecf48 4217 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4218
4219 if (ring->me == 1)
4220 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4221 else
4222 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4223 target += ring->pipe;
4224
4225 switch (type) {
4226 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4227 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4228 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4229 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4230 GENERIC2_INT_ENABLE, 0);
5e78835a 4231 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4232
4233 tmp = RREG32(target);
4234 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4235 GENERIC2_INT_ENABLE, 0);
4236 WREG32(target, tmp);
4237 } else {
5e78835a 4238 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4239 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4240 GENERIC2_INT_ENABLE, 1);
5e78835a 4241 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4242
4243 tmp = RREG32(target);
4244 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4245 GENERIC2_INT_ENABLE, 1);
4246 WREG32(target, tmp);
4247 }
4248 break;
4249 default:
4250 BUG(); /* kiq only support GENERIC2_INT now */
4251 break;
4252 }
4253 return 0;
4254}
4255
4256static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4257 struct amdgpu_irq_src *source,
4258 struct amdgpu_iv_entry *entry)
4259{
4260 u8 me_id, pipe_id, queue_id;
1c4ecf48 4261 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4262
4263 me_id = (entry->ring_id & 0x0c) >> 2;
4264 pipe_id = (entry->ring_id & 0x03) >> 0;
4265 queue_id = (entry->ring_id & 0x70) >> 4;
4266 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4267 me_id, pipe_id, queue_id);
4268
4269 amdgpu_fence_process(ring);
4270 return 0;
4271}
4272
fa04b6ba 4273static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
b1023571
KW		 4274 .name = "gfx_v9_0",
4275 .early_init = gfx_v9_0_early_init,
4276 .late_init = gfx_v9_0_late_init,
4277 .sw_init = gfx_v9_0_sw_init,
4278 .sw_fini = gfx_v9_0_sw_fini,
4279 .hw_init = gfx_v9_0_hw_init,
4280 .hw_fini = gfx_v9_0_hw_fini,
4281 .suspend = gfx_v9_0_suspend,
4282 .resume = gfx_v9_0_resume,
4283 .is_idle = gfx_v9_0_is_idle,
4284 .wait_for_idle = gfx_v9_0_wait_for_idle,
4285 .soft_reset = gfx_v9_0_soft_reset,
4286 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4287 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4288 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4289};
4290
4291static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4292 .type = AMDGPU_RING_TYPE_GFX,
4293 .align_mask = 0xff,
4294 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4295 .support_64bit_ptrs = true,
0eeb68b3 4296 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4297 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4298 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4299 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4300 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4301 5 + /* COND_EXEC */
4302 7 + /* PIPELINE_SYNC */
f732b6b3
CK		 4303 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4304 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4305 2 + /* VM_FLUSH */
e9d672b2
ML		 4306 8 + /* FENCE for VM_FLUSH */
4307 20 + /* GDS switch */
4308 4 + /* double SWITCH_BUFFER,
4309 the first COND_EXEC jump to the place just
4310 prior to this double SWITCH_BUFFER */
4311 5 + /* COND_EXEC */
4312 7 + /* HDP_flush */
4313 4 + /* VGT_flush */
4314 14 + /* CE_META */
4315 31 + /* DE_META */
4316 3 + /* CNTX_CTRL */
4317 5 + /* HDP_INVL */
4318 8 + 8 + /* FENCE x2 */
4319 2, /* SWITCH_BUFFER */
b1023571
KW		 4320 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4321 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4322 .emit_fence = gfx_v9_0_ring_emit_fence,
4323 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4324 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4325 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4326 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
b1023571
KW		 4327 .test_ring = gfx_v9_0_ring_test_ring,
4328 .test_ib = gfx_v9_0_ring_test_ib,
4329 .insert_nop = amdgpu_ring_insert_nop,
4330 .pad_ib = amdgpu_ring_generic_pad_ib,
4331 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4332 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4333 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4334 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4335 .emit_tmz = gfx_v9_0_ring_emit_tmz,
254e825b 4336 .emit_wreg = gfx_v9_0_ring_emit_wreg,
230fcc34 4337 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
b1023571
KW		 4338};
4339
4340static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4341 .type = AMDGPU_RING_TYPE_COMPUTE,
4342 .align_mask = 0xff,
4343 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4344 .support_64bit_ptrs = true,
0eeb68b3 4345 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4346 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4347 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4348 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4349 .emit_frame_size =
4350 20 + /* gfx_v9_0_ring_emit_gds_switch */
4351 7 + /* gfx_v9_0_ring_emit_hdp_flush */
2ee150cd 4352 5 + /* hdp invalidate */
b1023571 4353 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
f732b6b3
CK		 4354 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4355 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4356 2 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4357 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4358 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4359 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4360 .emit_fence = gfx_v9_0_ring_emit_fence,
4361 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4362 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4363 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4364 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
b1023571
KW		 4365 .test_ring = gfx_v9_0_ring_test_ring,
4366 .test_ib = gfx_v9_0_ring_test_ib,
4367 .insert_nop = amdgpu_ring_insert_nop,
4368 .pad_ib = amdgpu_ring_generic_pad_ib,
761c77c1 4369 .set_priority = gfx_v9_0_ring_set_priority_compute,
254e825b 4370 .emit_wreg = gfx_v9_0_ring_emit_wreg,
230fcc34 4371 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
b1023571
KW		 4372};
4373
aa6faa44
XY		 4374static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4375 .type = AMDGPU_RING_TYPE_KIQ,
4376 .align_mask = 0xff,
4377 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4378 .support_64bit_ptrs = true,
0eeb68b3 4379 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4380 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4381 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4382 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4383 .emit_frame_size =
4384 20 + /* gfx_v9_0_ring_emit_gds_switch */
4385 7 + /* gfx_v9_0_ring_emit_hdp_flush */
2ee150cd 4386 5 + /* hdp invalidate */
aa6faa44 4387 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
f732b6b3
CK		 4388 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4389 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4390 2 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4391 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4392 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4393 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4394 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4395 .test_ring = gfx_v9_0_ring_test_ring,
4396 .test_ib = gfx_v9_0_ring_test_ib,
4397 .insert_nop = amdgpu_ring_insert_nop,
4398 .pad_ib = amdgpu_ring_generic_pad_ib,
4399 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4400 .emit_wreg = gfx_v9_0_ring_emit_wreg,
230fcc34 4401 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
aa6faa44 4402};
b1023571
KW		 4403
4404static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4405{
4406 int i;
4407
aa6faa44
XY		 4408 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4409
b1023571
KW		 4410 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4411 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4412
4413 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4414 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4415}
4416
97031e25
XY		 4417static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4418 .set = gfx_v9_0_kiq_set_interrupt_state,
4419 .process = gfx_v9_0_kiq_irq,
4420};
4421
b1023571
KW		 4422static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4423 .set = gfx_v9_0_set_eop_interrupt_state,
4424 .process = gfx_v9_0_eop_irq,
4425};
4426
4427static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4428 .set = gfx_v9_0_set_priv_reg_fault_state,
4429 .process = gfx_v9_0_priv_reg_irq,
4430};
4431
4432static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4433 .set = gfx_v9_0_set_priv_inst_fault_state,
4434 .process = gfx_v9_0_priv_inst_irq,
4435};
4436
4437static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4438{
4439 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4440 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4441
4442 adev->gfx.priv_reg_irq.num_types = 1;
4443 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4444
4445 adev->gfx.priv_inst_irq.num_types = 1;
4446 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4447
4448 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4449 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4450}
4451
4452static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4453{
4454 switch (adev->asic_type) {
4455 case CHIP_VEGA10:
a4dc61f5 4456 case CHIP_RAVEN:
b1023571
KW		 4457 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4458 break;
4459 default:
4460 break;
4461 }
4462}
4463
4464static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4465{
4466 /* init asci gds info */
5e78835a 4467 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4468 adev->gds.gws.total_size = 64;
4469 adev->gds.oa.total_size = 16;
4470
4471 if (adev->gds.mem.total_size == 64 * 1024) {
4472 adev->gds.mem.gfx_partition_size = 4096;
4473 adev->gds.mem.cs_partition_size = 4096;
4474
4475 adev->gds.gws.gfx_partition_size = 4;
4476 adev->gds.gws.cs_partition_size = 4;
4477
4478 adev->gds.oa.gfx_partition_size = 4;
4479 adev->gds.oa.cs_partition_size = 1;
4480 } else {
4481 adev->gds.mem.gfx_partition_size = 1024;
4482 adev->gds.mem.cs_partition_size = 1024;
4483
4484 adev->gds.gws.gfx_partition_size = 16;
4485 adev->gds.gws.cs_partition_size = 16;
4486
4487 adev->gds.oa.gfx_partition_size = 4;
4488 adev->gds.oa.cs_partition_size = 4;
4489 }
4490}
4491
c94d38f0
NH		 4492static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4493 u32 bitmap)
4494{
4495 u32 data;
4496
4497 if (!bitmap)
4498 return;
4499
4500 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4501 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4502
4503 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4504}
4505
b1023571
KW		 4506static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4507{
4508 u32 data, mask;
4509
5e78835a
TSD		 4510 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4511 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4512
4513 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4514 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4515
378506a7 4516 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
b1023571
KW		 4517
4518 return (~data) & mask;
4519}
4520
4521static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4522 struct amdgpu_cu_info *cu_info)
4523{
4524 int i, j, k, counter, active_cu_number = 0;
4525 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
c94d38f0 4526 unsigned disable_masks[4 * 2];
b1023571
KW		 4527
4528 if (!adev || !cu_info)
4529 return -EINVAL;
4530
c94d38f0
NH		 4531 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4532
b1023571
KW		 4533 mutex_lock(&adev->grbm_idx_mutex);
4534 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4535 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4536 mask = 1;
4537 ao_bitmap = 0;
4538 counter = 0;
4539 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
c94d38f0
NH		 4540 if (i < 4 && j < 2)
4541 gfx_v9_0_set_user_cu_inactive_bitmap(
4542 adev, disable_masks[i * 2 + j]);
b1023571
KW		 4543 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4544 cu_info->bitmap[i][j] = bitmap;
4545
fe723cd3 4546 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4547 if (bitmap & mask) {
fe723cd3 4548 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4549 ao_bitmap |= mask;
4550 counter ++;
4551 }
4552 mask <<= 1;
4553 }
4554 active_cu_number += counter;
dbfe85ea
FC		 4555 if (i < 2 && j < 2)
4556 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4557 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
b1023571
KW		 4558 }
4559 }
4560 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4561 mutex_unlock(&adev->grbm_idx_mutex);
4562
4563 cu_info->number = active_cu_number;
4564 cu_info->ao_cu_mask = ao_cu_mask;
4565
4566 return 0;
4567}
4568
b1023571
KW		 4569const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4570{
4571 .type = AMD_IP_BLOCK_TYPE_GFX,
4572 .major = 9,
4573 .minor = 0,
4574 .rev = 0,
4575 .funcs = &gfx_v9_0_ip_funcs,
4576};
Linux 6.x block layer and io_uring tree(s)