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drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
6bce4667
HZ		 42#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
43#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
44#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
b1023571 45
91d3130a
HZ		 46#define mmPWR_MISC_CNTL_STATUS 0x0183
47#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
48#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
49#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
50#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
51#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
52
b1023571
KW		 53MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
54MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
55MODULE_FIRMWARE("amdgpu/vega10_me.bin");
56MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
57MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
58MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
59
060d124b
CZ		 60MODULE_FIRMWARE("amdgpu/raven_ce.bin");
61MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
62MODULE_FIRMWARE("amdgpu/raven_me.bin");
63MODULE_FIRMWARE("amdgpu/raven_mec.bin");
64MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
65MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
66
b1023571
KW		 67static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
68{
69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
85 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
86 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
87 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
89 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
90 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
91 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
93 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
94 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
95 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
97 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
98 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
99 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
101};
102
103static const u32 golden_settings_gc_9_0[] =
104{
105 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
b1023571
KW		 106 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
108 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
109 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
110 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
111 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
112 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
113};
114
115static const u32 golden_settings_gc_9_0_vg10[] =
116{
117 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
118 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
119 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
120 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
121 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
122 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
123 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
124 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
125};
126
a5fdb336
CZ		 127static const u32 golden_settings_gc_9_1[] =
128{
129 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
130 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
131 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
132 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
133 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
134 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
135 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
136 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
137 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
138 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
139};
140
141static const u32 golden_settings_gc_9_1_rv1[] =
142{
143 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x26013042,
144 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x26013042,
145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x00048000,
146 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
147};
b1023571 148
5cf7433d
CZ		 149#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
150#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x26013042
151
b1023571
KW		 152static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
153static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
154static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
155static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
156static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
157 struct amdgpu_cu_info *cu_info);
158static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
159static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
635e7132 160static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
b1023571
KW		 161
162static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
163{
164 switch (adev->asic_type) {
165 case CHIP_VEGA10:
166 amdgpu_program_register_sequence(adev,
167 golden_settings_gc_9_0,
168 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
169 amdgpu_program_register_sequence(adev,
170 golden_settings_gc_9_0_vg10,
171 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
172 break;
a5fdb336
CZ		 173 case CHIP_RAVEN:
174 amdgpu_program_register_sequence(adev,
175 golden_settings_gc_9_1,
176 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
177 amdgpu_program_register_sequence(adev,
178 golden_settings_gc_9_1_rv1,
179 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
180 break;
b1023571
KW		 181 default:
182 break;
183 }
184}
185
186static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
187{
188 adev->gfx.scratch.num_reg = 7;
189 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
190 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
191}
192
193static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
194 bool wc, uint32_t reg, uint32_t val)
195{
196 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
197 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
198 WRITE_DATA_DST_SEL(0) |
199 (wc ? WR_CONFIRM : 0));
200 amdgpu_ring_write(ring, reg);
201 amdgpu_ring_write(ring, 0);
202 amdgpu_ring_write(ring, val);
203}
204
205static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
206 int mem_space, int opt, uint32_t addr0,
207 uint32_t addr1, uint32_t ref, uint32_t mask,
208 uint32_t inv)
209{
210 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
211 amdgpu_ring_write(ring,
212 /* memory (1) or register (0) */
213 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
214 WAIT_REG_MEM_OPERATION(opt) | /* wait */
215 WAIT_REG_MEM_FUNCTION(3) | /* equal */
216 WAIT_REG_MEM_ENGINE(eng_sel)));
217
218 if (mem_space)
219 BUG_ON(addr0 & 0x3); /* Dword align */
220 amdgpu_ring_write(ring, addr0);
221 amdgpu_ring_write(ring, addr1);
222 amdgpu_ring_write(ring, ref);
223 amdgpu_ring_write(ring, mask);
224 amdgpu_ring_write(ring, inv); /* poll interval */
225}
226
227static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
228{
229 struct amdgpu_device *adev = ring->adev;
230 uint32_t scratch;
231 uint32_t tmp = 0;
232 unsigned i;
233 int r;
234
235 r = amdgpu_gfx_scratch_get(adev, &scratch);
236 if (r) {
237 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
238 return r;
239 }
240 WREG32(scratch, 0xCAFEDEAD);
241 r = amdgpu_ring_alloc(ring, 3);
242 if (r) {
243 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
244 ring->idx, r);
245 amdgpu_gfx_scratch_free(adev, scratch);
246 return r;
247 }
248 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
249 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
250 amdgpu_ring_write(ring, 0xDEADBEEF);
251 amdgpu_ring_commit(ring);
252
253 for (i = 0; i < adev->usec_timeout; i++) {
254 tmp = RREG32(scratch);
255 if (tmp == 0xDEADBEEF)
256 break;
257 DRM_UDELAY(1);
258 }
259 if (i < adev->usec_timeout) {
260 DRM_INFO("ring test on %d succeeded in %d usecs\n",
261 ring->idx, i);
262 } else {
263 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
264 ring->idx, scratch, tmp);
265 r = -EINVAL;
266 }
267 amdgpu_gfx_scratch_free(adev, scratch);
268 return r;
269}
270
271static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
272{
273 struct amdgpu_device *adev = ring->adev;
274 struct amdgpu_ib ib;
275 struct dma_fence *f = NULL;
276 uint32_t scratch;
277 uint32_t tmp = 0;
278 long r;
279
280 r = amdgpu_gfx_scratch_get(adev, &scratch);
281 if (r) {
282 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
283 return r;
284 }
285 WREG32(scratch, 0xCAFEDEAD);
286 memset(&ib, 0, sizeof(ib));
287 r = amdgpu_ib_get(adev, NULL, 256, &ib);
288 if (r) {
289 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
290 goto err1;
291 }
292 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
293 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
294 ib.ptr[2] = 0xDEADBEEF;
295 ib.length_dw = 3;
296
297 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
298 if (r)
299 goto err2;
300
301 r = dma_fence_wait_timeout(f, false, timeout);
302 if (r == 0) {
303 DRM_ERROR("amdgpu: IB test timed out.\n");
304 r = -ETIMEDOUT;
305 goto err2;
306 } else if (r < 0) {
307 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
308 goto err2;
309 }
310 tmp = RREG32(scratch);
311 if (tmp == 0xDEADBEEF) {
312 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
313 r = 0;
314 } else {
315 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
316 scratch, tmp);
317 r = -EINVAL;
318 }
319err2:
320 amdgpu_ib_free(adev, &ib, NULL);
321 dma_fence_put(f);
322err1:
323 amdgpu_gfx_scratch_free(adev, scratch);
324 return r;
325}
326
327static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
328{
329 const char *chip_name;
330 char fw_name[30];
331 int err;
332 struct amdgpu_firmware_info *info = NULL;
333 const struct common_firmware_header *header = NULL;
334 const struct gfx_firmware_header_v1_0 *cp_hdr;
a4d41ad0
HZ		 335 const struct rlc_firmware_header_v2_0 *rlc_hdr;
336 unsigned int *tmp = NULL;
337 unsigned int i = 0;
b1023571
KW		 338
339 DRM_DEBUG("\n");
340
341 switch (adev->asic_type) {
342 case CHIP_VEGA10:
343 chip_name = "vega10";
344 break;
eaa85724
CZ		 345 case CHIP_RAVEN:
346 chip_name = "raven";
347 break;
b1023571
KW		 348 default:
349 BUG();
350 }
351
352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
353 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
354 if (err)
355 goto out;
356 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
357 if (err)
358 goto out;
359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
360 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
361 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
362
363 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
364 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
365 if (err)
366 goto out;
367 err = amdgpu_ucode_validate(adev->gfx.me_fw);
368 if (err)
369 goto out;
370 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
371 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
372 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
373
374 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
375 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
376 if (err)
377 goto out;
378 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
379 if (err)
380 goto out;
381 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
382 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
383 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
384
385 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
386 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
387 if (err)
388 goto out;
389 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
a4d41ad0
HZ		 390 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
391 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
392 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
393 adev->gfx.rlc.save_and_restore_offset =
394 le32_to_cpu(rlc_hdr->save_and_restore_offset);
395 adev->gfx.rlc.clear_state_descriptor_offset =
396 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
397 adev->gfx.rlc.avail_scratch_ram_locations =
398 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
399 adev->gfx.rlc.reg_restore_list_size =
400 le32_to_cpu(rlc_hdr->reg_restore_list_size);
401 adev->gfx.rlc.reg_list_format_start =
402 le32_to_cpu(rlc_hdr->reg_list_format_start);
403 adev->gfx.rlc.reg_list_format_separate_start =
404 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
405 adev->gfx.rlc.starting_offsets_start =
406 le32_to_cpu(rlc_hdr->starting_offsets_start);
407 adev->gfx.rlc.reg_list_format_size_bytes =
408 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
409 adev->gfx.rlc.reg_list_size_bytes =
410 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
411 adev->gfx.rlc.register_list_format =
412 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
413 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
414 if (!adev->gfx.rlc.register_list_format) {
415 err = -ENOMEM;
416 goto out;
417 }
418
419 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
420 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
421 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
422 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
423
424 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
425
426 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
427 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
428 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
429 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
b1023571
KW		 430
431 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
432 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
433 if (err)
434 goto out;
435 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
436 if (err)
437 goto out;
438 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
439 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
440 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
441
442
443 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
444 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
445 if (!err) {
446 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
447 if (err)
448 goto out;
449 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
450 adev->gfx.mec2_fw->data;
451 adev->gfx.mec2_fw_version =
452 le32_to_cpu(cp_hdr->header.ucode_version);
453 adev->gfx.mec2_feature_version =
454 le32_to_cpu(cp_hdr->ucode_feature_version);
455 } else {
456 err = 0;
457 adev->gfx.mec2_fw = NULL;
458 }
459
460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
461 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
462 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
463 info->fw = adev->gfx.pfp_fw;
464 header = (const struct common_firmware_header *)info->fw->data;
465 adev->firmware.fw_size +=
466 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
467
468 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
469 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
470 info->fw = adev->gfx.me_fw;
471 header = (const struct common_firmware_header *)info->fw->data;
472 adev->firmware.fw_size +=
473 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
474
475 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
476 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
477 info->fw = adev->gfx.ce_fw;
478 header = (const struct common_firmware_header *)info->fw->data;
479 adev->firmware.fw_size +=
480 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
481
482 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
483 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
484 info->fw = adev->gfx.rlc_fw;
485 header = (const struct common_firmware_header *)info->fw->data;
486 adev->firmware.fw_size +=
487 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
488
489 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
490 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
491 info->fw = adev->gfx.mec_fw;
492 header = (const struct common_firmware_header *)info->fw->data;
493 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
494 adev->firmware.fw_size +=
495 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
496
497 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
498 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
499 info->fw = adev->gfx.mec_fw;
500 adev->firmware.fw_size +=
501 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
502
503 if (adev->gfx.mec2_fw) {
504 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
505 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
506 info->fw = adev->gfx.mec2_fw;
507 header = (const struct common_firmware_header *)info->fw->data;
508 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
509 adev->firmware.fw_size +=
510 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
511 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
512 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
513 info->fw = adev->gfx.mec2_fw;
514 adev->firmware.fw_size +=
515 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
516 }
517
518 }
519
520out:
521 if (err) {
522 dev_err(adev->dev,
523 "gfx9: Failed to load firmware \"%s\"\n",
524 fw_name);
525 release_firmware(adev->gfx.pfp_fw);
526 adev->gfx.pfp_fw = NULL;
527 release_firmware(adev->gfx.me_fw);
528 adev->gfx.me_fw = NULL;
529 release_firmware(adev->gfx.ce_fw);
530 adev->gfx.ce_fw = NULL;
531 release_firmware(adev->gfx.rlc_fw);
532 adev->gfx.rlc_fw = NULL;
533 release_firmware(adev->gfx.mec_fw);
534 adev->gfx.mec_fw = NULL;
535 release_firmware(adev->gfx.mec2_fw);
536 adev->gfx.mec2_fw = NULL;
537 }
538 return err;
539}
540
c9719c69
HZ		 541static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
542{
543 u32 count = 0;
544 const struct cs_section_def *sect = NULL;
545 const struct cs_extent_def *ext = NULL;
546
547 /* begin clear state */
548 count += 2;
549 /* context control state */
550 count += 3;
551
552 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
553 for (ext = sect->section; ext->extent != NULL; ++ext) {
554 if (sect->id == SECT_CONTEXT)
555 count += 2 + ext->reg_count;
556 else
557 return 0;
558 }
559 }
560
561 /* end clear state */
562 count += 2;
563 /* clear state */
564 count += 2;
565
566 return count;
567}
568
569static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
570 volatile u32 *buffer)
571{
572 u32 count = 0, i;
573 const struct cs_section_def *sect = NULL;
574 const struct cs_extent_def *ext = NULL;
575
576 if (adev->gfx.rlc.cs_data == NULL)
577 return;
578 if (buffer == NULL)
579 return;
580
581 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
582 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
583
584 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
585 buffer[count++] = cpu_to_le32(0x80000000);
586 buffer[count++] = cpu_to_le32(0x80000000);
587
588 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
589 for (ext = sect->section; ext->extent != NULL; ++ext) {
590 if (sect->id == SECT_CONTEXT) {
591 buffer[count++] =
592 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
593 buffer[count++] = cpu_to_le32(ext->reg_index -
594 PACKET3_SET_CONTEXT_REG_START);
595 for (i = 0; i < ext->reg_count; i++)
596 buffer[count++] = cpu_to_le32(ext->extent[i]);
597 } else {
598 return;
599 }
600 }
601 }
602
603 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
604 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
605
606 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
607 buffer[count++] = cpu_to_le32(0);
608}
609
610static void rv_init_cp_jump_table(struct amdgpu_device *adev)
611{
612 const __le32 *fw_data;
613 volatile u32 *dst_ptr;
614 int me, i, max_me = 5;
615 u32 bo_offset = 0;
616 u32 table_offset, table_size;
617
618 /* write the cp table buffer */
619 dst_ptr = adev->gfx.rlc.cp_table_ptr;
620 for (me = 0; me < max_me; me++) {
621 if (me == 0) {
622 const struct gfx_firmware_header_v1_0 *hdr =
623 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
624 fw_data = (const __le32 *)
625 (adev->gfx.ce_fw->data +
626 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
627 table_offset = le32_to_cpu(hdr->jt_offset);
628 table_size = le32_to_cpu(hdr->jt_size);
629 } else if (me == 1) {
630 const struct gfx_firmware_header_v1_0 *hdr =
631 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
632 fw_data = (const __le32 *)
633 (adev->gfx.pfp_fw->data +
634 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
635 table_offset = le32_to_cpu(hdr->jt_offset);
636 table_size = le32_to_cpu(hdr->jt_size);
637 } else if (me == 2) {
638 const struct gfx_firmware_header_v1_0 *hdr =
639 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
640 fw_data = (const __le32 *)
641 (adev->gfx.me_fw->data +
642 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
643 table_offset = le32_to_cpu(hdr->jt_offset);
644 table_size = le32_to_cpu(hdr->jt_size);
645 } else if (me == 3) {
646 const struct gfx_firmware_header_v1_0 *hdr =
647 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
648 fw_data = (const __le32 *)
649 (adev->gfx.mec_fw->data +
650 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
651 table_offset = le32_to_cpu(hdr->jt_offset);
652 table_size = le32_to_cpu(hdr->jt_size);
653 } else if (me == 4) {
654 const struct gfx_firmware_header_v1_0 *hdr =
655 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
656 fw_data = (const __le32 *)
657 (adev->gfx.mec2_fw->data +
658 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
659 table_offset = le32_to_cpu(hdr->jt_offset);
660 table_size = le32_to_cpu(hdr->jt_size);
661 }
662
663 for (i = 0; i < table_size; i ++) {
664 dst_ptr[bo_offset + i] =
665 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
666 }
667
668 bo_offset += table_size;
669 }
670}
671
672static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
673{
674 /* clear state block */
675 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
676 &adev->gfx.rlc.clear_state_gpu_addr,
677 (void **)&adev->gfx.rlc.cs_ptr);
678
679 /* jump table block */
680 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
681 &adev->gfx.rlc.cp_table_gpu_addr,
682 (void **)&adev->gfx.rlc.cp_table_ptr);
683}
684
685static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
686{
687 volatile u32 *dst_ptr;
688 u32 dws;
689 const struct cs_section_def *cs_data;
690 int r;
691
692 adev->gfx.rlc.cs_data = gfx9_cs_data;
693
694 cs_data = adev->gfx.rlc.cs_data;
695
696 if (cs_data) {
697 /* clear state block */
698 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
699 if (adev->gfx.rlc.clear_state_obj == NULL) {
700 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
701 AMDGPU_GEM_DOMAIN_VRAM,
702 &adev->gfx.rlc.clear_state_obj,
703 &adev->gfx.rlc.clear_state_gpu_addr,
704 (void **)&adev->gfx.rlc.cs_ptr);
705 if (r) {
706 dev_err(adev->dev,
707 "(%d) failed to create rlc csb bo\n", r);
708 gfx_v9_0_rlc_fini(adev);
709 return r;
710 }
711 }
712 /* set up the cs buffer */
713 dst_ptr = adev->gfx.rlc.cs_ptr;
714 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
715 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
716 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
717 }
718
719 if (adev->asic_type == CHIP_RAVEN) {
720 /* TODO: double check the cp_table_size for RV */
721 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
722 if (adev->gfx.rlc.cp_table_obj == NULL) {
723 r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
724 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
725 &adev->gfx.rlc.cp_table_obj,
726 &adev->gfx.rlc.cp_table_gpu_addr,
727 (void **)&adev->gfx.rlc.cp_table_ptr);
728 if (r) {
729 dev_err(adev->dev,
730 "(%d) failed to create cp table bo\n", r);
731 gfx_v9_0_rlc_fini(adev);
732 return r;
733 }
734 }
735
736 rv_init_cp_jump_table(adev);
737 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
738 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
739 }
740
741 return 0;
742}
743
b1023571
KW		 744static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
745{
746 int r;
747
748 if (adev->gfx.mec.hpd_eop_obj) {
c81a1a74 749 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
b1023571
KW		 750 if (unlikely(r != 0))
751 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
752 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
753 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
754
755 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
756 adev->gfx.mec.hpd_eop_obj = NULL;
757 }
758 if (adev->gfx.mec.mec_fw_obj) {
c81a1a74 759 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
b1023571
KW		 760 if (unlikely(r != 0))
761 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
762 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
763 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
764
765 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
766 adev->gfx.mec.mec_fw_obj = NULL;
767 }
768}
769
770#define MEC_HPD_SIZE 2048
771
772static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
773{
774 int r;
775 u32 *hpd;
776 const __le32 *fw_data;
777 unsigned fw_size;
778 u32 *fw;
779
780 const struct gfx_firmware_header_v1_0 *mec_hdr;
781
782 /*
783 * we assign only 1 pipe because all other pipes will
784 * be handled by KFD
785 */
786 adev->gfx.mec.num_mec = 1;
787 adev->gfx.mec.num_pipe = 1;
788 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
789
790 if (adev->gfx.mec.hpd_eop_obj == NULL) {
791 r = amdgpu_bo_create(adev,
792 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
793 PAGE_SIZE, true,
794 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
795 &adev->gfx.mec.hpd_eop_obj);
796 if (r) {
797 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
798 return r;
799 }
800 }
801
802 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
803 if (unlikely(r != 0)) {
804 gfx_v9_0_mec_fini(adev);
805 return r;
806 }
807 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
808 &adev->gfx.mec.hpd_eop_gpu_addr);
809 if (r) {
810 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
811 gfx_v9_0_mec_fini(adev);
812 return r;
813 }
814 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
815 if (r) {
816 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
817 gfx_v9_0_mec_fini(adev);
818 return r;
819 }
820
821 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
822
823 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
824 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
825
826 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
827
828 fw_data = (const __le32 *)
829 (adev->gfx.mec_fw->data +
830 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
831 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
832
833 if (adev->gfx.mec.mec_fw_obj == NULL) {
834 r = amdgpu_bo_create(adev,
835 mec_hdr->header.ucode_size_bytes,
836 PAGE_SIZE, true,
837 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
838 &adev->gfx.mec.mec_fw_obj);
839 if (r) {
840 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
841 return r;
842 }
843 }
844
845 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
846 if (unlikely(r != 0)) {
847 gfx_v9_0_mec_fini(adev);
848 return r;
849 }
850 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
851 &adev->gfx.mec.mec_fw_gpu_addr);
852 if (r) {
853 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
854 gfx_v9_0_mec_fini(adev);
855 return r;
856 }
857 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
858 if (r) {
859 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
860 gfx_v9_0_mec_fini(adev);
861 return r;
862 }
863 memcpy(fw, fw_data, fw_size);
864
865 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
866 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
867
868
869 return 0;
870}
871
ac104e99
XY		 872static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
873{
874 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
875
876 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
877}
878
879static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
880{
881 int r;
882 u32 *hpd;
883 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
884
885 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
886 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
887 &kiq->eop_gpu_addr, (void **)&hpd);
888 if (r) {
889 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
890 return r;
891 }
892
893 memset(hpd, 0, MEC_HPD_SIZE);
894
c81a1a74 895 r = amdgpu_bo_reserve(kiq->eop_obj, true);
f7618a63
AD		 896 if (unlikely(r != 0))
897 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
ac104e99 898 amdgpu_bo_kunmap(kiq->eop_obj);
f7618a63 899 amdgpu_bo_unreserve(kiq->eop_obj);
ac104e99
XY		 900
901 return 0;
902}
903
904static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
905 struct amdgpu_ring *ring,
906 struct amdgpu_irq_src *irq)
907{
d72f2f46 908 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
ac104e99
XY		 909 int r = 0;
910
cdf6adb2
SL		 911 mutex_init(&kiq->ring_mutex);
912
ac104e99
XY		 913 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
914 if (r)
915 return r;
916
917 ring->adev = NULL;
918 ring->ring_obj = NULL;
919 ring->use_doorbell = true;
920 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
921 if (adev->gfx.mec2_fw) {
922 ring->me = 2;
923 ring->pipe = 0;
924 } else {
925 ring->me = 1;
926 ring->pipe = 1;
927 }
928
ac104e99 929 ring->queue = 0;
d72f2f46 930 ring->eop_gpu_addr = kiq->eop_gpu_addr;
ac104e99
XY		 931 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
932 r = amdgpu_ring_init(adev, ring, 1024,
933 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
934 if (r)
935 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
936
937 return r;
938}
939static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
940 struct amdgpu_irq_src *irq)
941{
942 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
943 amdgpu_ring_fini(ring);
ac104e99
XY		 944}
945
464826d6 946/* create MQD for each compute queue */
e935c211 947static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
464826d6
XY		 948{
949 struct amdgpu_ring *ring = NULL;
950 int r, i;
951
952 /* create MQD for KIQ */
953 ring = &adev->gfx.kiq.ring;
954 if (!ring->mqd_obj) {
955 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 956 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
957 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 958 if (r) {
959 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
960 return r;
961 }
962
0ef376ca
AD		 963 /* prepare MQD backup */
964 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
965 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
966 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
464826d6
XY		 967 }
968
969 /* create MQD for each KCQ */
b4fcf7f0 970 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
464826d6
XY		 971 ring = &adev->gfx.compute_ring[i];
972 if (!ring->mqd_obj) {
973 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 974 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
975 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 976 if (r) {
977 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
978 return r;
979 }
980
0ef376ca
AD		 981 /* prepare MQD backup */
982 adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
983 if (!adev->gfx.mec.mqd_backup[i])
984 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
464826d6
XY		 985 }
986 }
987
988 return 0;
989}
990
e935c211 991static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
464826d6
XY		 992{
993 struct amdgpu_ring *ring = NULL;
994 int i;
995
996 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
997 ring = &adev->gfx.compute_ring[i];
0ef376ca 998 kfree(adev->gfx.mec.mqd_backup[i]);
464826d6
XY		 999 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1000 }
1001
1002 ring = &adev->gfx.kiq.ring;
0ef376ca 1003 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
464826d6
XY		 1004 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1005}
1006
b1023571
KW		 1007static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1008{
5e78835a 1009 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 1010 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1011 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1012 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1013 (SQ_IND_INDEX__FORCE_READ_MASK));
5e78835a 1014 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 1015}
1016
1017static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1018 uint32_t wave, uint32_t thread,
1019 uint32_t regno, uint32_t num, uint32_t *out)
1020{
5e78835a 1021 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
b1023571
KW		 1022 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1023 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1024 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1025 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1026 (SQ_IND_INDEX__FORCE_READ_MASK) |
1027 (SQ_IND_INDEX__AUTO_INCR_MASK));
1028 while (num--)
5e78835a 1029 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
b1023571
KW		 1030}
1031
1032static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1033{
1034 /* type 1 wave data */
1035 dst[(*no_fields)++] = 1;
1036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1050}
1051
1052static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1053 uint32_t wave, uint32_t start,
1054 uint32_t size, uint32_t *dst)
1055{
1056 wave_read_regs(
1057 adev, simd, wave, 0,
1058 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1059}
1060
1061
1062static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1063 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1064 .select_se_sh = &gfx_v9_0_select_se_sh,
1065 .read_wave_data = &gfx_v9_0_read_wave_data,
1066 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1067};
1068
1069static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1070{
1071 u32 gb_addr_config;
1072
1073 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1074
1075 switch (adev->asic_type) {
1076 case CHIP_VEGA10:
b1023571 1077 adev->gfx.config.max_hw_contexts = 8;
b1023571
KW		 1078 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1079 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1080 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1081 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1082 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1083 break;
5cf7433d
CZ		 1084 case CHIP_RAVEN:
1085 adev->gfx.config.max_hw_contexts = 8;
1086 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1087 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1088 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1089 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1090 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1091 break;
b1023571
KW		 1092 default:
1093 BUG();
1094 break;
1095 }
1096
1097 adev->gfx.config.gb_addr_config = gb_addr_config;
1098
1099 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1100 REG_GET_FIELD(
1101 adev->gfx.config.gb_addr_config,
1102 GB_ADDR_CONFIG,
1103 NUM_PIPES);
ad7d0ff3
AD		 1104
1105 adev->gfx.config.max_tile_pipes =
1106 adev->gfx.config.gb_addr_config_fields.num_pipes;
1107
b1023571
KW		 1108 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1109 REG_GET_FIELD(
1110 adev->gfx.config.gb_addr_config,
1111 GB_ADDR_CONFIG,
1112 NUM_BANKS);
1113 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1114 REG_GET_FIELD(
1115 adev->gfx.config.gb_addr_config,
1116 GB_ADDR_CONFIG,
1117 MAX_COMPRESSED_FRAGS);
1118 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1119 REG_GET_FIELD(
1120 adev->gfx.config.gb_addr_config,
1121 GB_ADDR_CONFIG,
1122 NUM_RB_PER_SE);
1123 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1124 REG_GET_FIELD(
1125 adev->gfx.config.gb_addr_config,
1126 GB_ADDR_CONFIG,
1127 NUM_SHADER_ENGINES);
1128 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1129 REG_GET_FIELD(
1130 adev->gfx.config.gb_addr_config,
1131 GB_ADDR_CONFIG,
1132 PIPE_INTERLEAVE_SIZE));
1133}
1134
1135static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1136 struct amdgpu_ngg_buf *ngg_buf,
1137 int size_se,
1138 int default_size_se)
1139{
1140 int r;
1141
1142 if (size_se < 0) {
1143 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1144 return -EINVAL;
1145 }
1146 size_se = size_se ? size_se : default_size_se;
1147
42ce2243 1148 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
b1023571
KW		 1149 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1150 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1151 &ngg_buf->bo,
1152 &ngg_buf->gpu_addr,
1153 NULL);
1154 if (r) {
1155 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1156 return r;
1157 }
1158 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1159
1160 return r;
1161}
1162
1163static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1164{
1165 int i;
1166
1167 for (i = 0; i < NGG_BUF_MAX; i++)
1168 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1169 &adev->gfx.ngg.buf[i].gpu_addr,
1170 NULL);
1171
1172 memset(&adev->gfx.ngg.buf[0], 0,
1173 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1174
1175 adev->gfx.ngg.init = false;
1176
1177 return 0;
1178}
1179
1180static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1181{
1182 int r;
1183
1184 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1185 return 0;
1186
1187 /* GDS reserve memory: 64 bytes alignment */
1188 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1189 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1190 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1191 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1192 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1193
1194 /* Primitive Buffer */
af8baf15 1195 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
b1023571
KW		 1196 amdgpu_prim_buf_per_se,
1197 64 * 1024);
1198 if (r) {
1199 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1200 goto err;
1201 }
1202
1203 /* Position Buffer */
af8baf15 1204 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
b1023571
KW		 1205 amdgpu_pos_buf_per_se,
1206 256 * 1024);
1207 if (r) {
1208 dev_err(adev->dev, "Failed to create Position Buffer\n");
1209 goto err;
1210 }
1211
1212 /* Control Sideband */
af8baf15 1213 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
b1023571
KW		 1214 amdgpu_cntl_sb_buf_per_se,
1215 256);
1216 if (r) {
1217 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1218 goto err;
1219 }
1220
1221 /* Parameter Cache, not created by default */
1222 if (amdgpu_param_buf_per_se <= 0)
1223 goto out;
1224
af8baf15 1225 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
b1023571
KW		 1226 amdgpu_param_buf_per_se,
1227 512 * 1024);
1228 if (r) {
1229 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1230 goto err;
1231 }
1232
1233out:
1234 adev->gfx.ngg.init = true;
1235 return 0;
1236err:
1237 gfx_v9_0_ngg_fini(adev);
1238 return r;
1239}
1240
1241static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1242{
1243 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1244 int r;
1245 u32 data;
1246 u32 size;
1247 u32 base;
1248
1249 if (!amdgpu_ngg)
1250 return 0;
1251
1252 /* Program buffer size */
1253 data = 0;
af8baf15 1254 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
b1023571
KW		 1255 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1256
af8baf15 1257 size = adev->gfx.ngg.buf[NGG_POS].size / 256;
b1023571
KW		 1258 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1259
5e78835a 1260 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
b1023571
KW		 1261
1262 data = 0;
af8baf15 1263 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
b1023571
KW		 1264 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1265
af8baf15 1266 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
b1023571
KW		 1267 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1268
5e78835a 1269 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
b1023571
KW		 1270
1271 /* Program buffer base address */
af8baf15 1272 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1273 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
5e78835a 1274 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
b1023571 1275
af8baf15 1276 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
b1023571 1277 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
5e78835a 1278 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
b1023571 1279
af8baf15 1280 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1281 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
5e78835a 1282 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
b1023571 1283
af8baf15 1284 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
b1023571 1285 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
5e78835a 1286 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
b1023571 1287
af8baf15 1288 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1289 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
5e78835a 1290 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
b1023571 1291
af8baf15 1292 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
b1023571 1293 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
5e78835a 1294 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
b1023571
KW		 1295
1296 /* Clear GDS reserved memory */
1297 r = amdgpu_ring_alloc(ring, 17);
1298 if (r) {
1299 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1300 ring->idx, r);
1301 return r;
1302 }
1303
1304 gfx_v9_0_write_data_to_reg(ring, 0, false,
1305 amdgpu_gds_reg_offset[0].mem_size,
1306 (adev->gds.mem.total_size +
1307 adev->gfx.ngg.gds_reserve_size) >>
1308 AMDGPU_GDS_SHIFT);
1309
1310 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1311 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1312 PACKET3_DMA_DATA_SRC_SEL(2)));
1313 amdgpu_ring_write(ring, 0);
1314 amdgpu_ring_write(ring, 0);
1315 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1316 amdgpu_ring_write(ring, 0);
1317 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1318
1319
1320 gfx_v9_0_write_data_to_reg(ring, 0, false,
1321 amdgpu_gds_reg_offset[0].mem_size, 0);
1322
1323 amdgpu_ring_commit(ring);
1324
1325 return 0;
1326}
1327
1328static int gfx_v9_0_sw_init(void *handle)
1329{
1330 int i, r;
1331 struct amdgpu_ring *ring;
ac104e99 1332 struct amdgpu_kiq *kiq;
b1023571
KW		 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334
97031e25
XY		 1335 /* KIQ event */
1336 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1337 if (r)
1338 return r;
1339
b1023571
KW		 1340 /* EOP Event */
1341 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1342 if (r)
1343 return r;
1344
1345 /* Privileged reg */
1346 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1347 &adev->gfx.priv_reg_irq);
1348 if (r)
1349 return r;
1350
1351 /* Privileged inst */
1352 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1353 &adev->gfx.priv_inst_irq);
1354 if (r)
1355 return r;
1356
1357 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1358
1359 gfx_v9_0_scratch_init(adev);
1360
1361 r = gfx_v9_0_init_microcode(adev);
1362 if (r) {
1363 DRM_ERROR("Failed to load gfx firmware!\n");
1364 return r;
1365 }
1366
c9719c69
HZ		 1367 r = gfx_v9_0_rlc_init(adev);
1368 if (r) {
1369 DRM_ERROR("Failed to init rlc BOs!\n");
1370 return r;
1371 }
1372
b1023571
KW		 1373 r = gfx_v9_0_mec_init(adev);
1374 if (r) {
1375 DRM_ERROR("Failed to init MEC BOs!\n");
1376 return r;
1377 }
1378
1379 /* set up the gfx ring */
1380 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1381 ring = &adev->gfx.gfx_ring[i];
1382 ring->ring_obj = NULL;
1383 sprintf(ring->name, "gfx");
1384 ring->use_doorbell = true;
1385 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1386 r = amdgpu_ring_init(adev, ring, 1024,
1387 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1388 if (r)
1389 return r;
1390 }
1391
1392 /* set up the compute queues */
1393 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1394 unsigned irq_type;
1395
1396 /* max 32 queues per MEC */
1397 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1398 DRM_ERROR("Too many (%d) compute rings!\n", i);
1399 break;
1400 }
1401 ring = &adev->gfx.compute_ring[i];
1402 ring->ring_obj = NULL;
1403 ring->use_doorbell = true;
1404 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1405 ring->me = 1; /* first MEC */
1406 ring->pipe = i / 8;
1407 ring->queue = i % 8;
d72f2f46 1408 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
e182e234 1409 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
b1023571
KW		 1410 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1411 /* type-2 packets are deprecated on MEC, use type-3 instead */
1412 r = amdgpu_ring_init(adev, ring, 1024,
1413 &adev->gfx.eop_irq, irq_type);
1414 if (r)
1415 return r;
1416 }
1417
ac104e99
XY		 1418 if (amdgpu_sriov_vf(adev)) {
1419 r = gfx_v9_0_kiq_init(adev);
1420 if (r) {
1421 DRM_ERROR("Failed to init KIQ BOs!\n");
1422 return r;
1423 }
1424
1425 kiq = &adev->gfx.kiq;
1426 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1427 if (r)
1428 return r;
464826d6
XY		 1429
1430 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
e935c211 1431 r = gfx_v9_0_compute_mqd_sw_init(adev);
464826d6
XY		 1432 if (r)
1433 return r;
ac104e99
XY		 1434 }
1435
b1023571
KW		 1436 /* reserve GDS, GWS and OA resource for gfx */
1437 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1439 &adev->gds.gds_gfx_bo, NULL, NULL);
1440 if (r)
1441 return r;
1442
1443 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1444 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1445 &adev->gds.gws_gfx_bo, NULL, NULL);
1446 if (r)
1447 return r;
1448
1449 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1450 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1451 &adev->gds.oa_gfx_bo, NULL, NULL);
1452 if (r)
1453 return r;
1454
1455 adev->gfx.ce_ram_size = 0x8000;
1456
1457 gfx_v9_0_gpu_early_init(adev);
1458
1459 r = gfx_v9_0_ngg_init(adev);
1460 if (r)
1461 return r;
1462
1463 return 0;
1464}
1465
1466
1467static int gfx_v9_0_sw_fini(void *handle)
1468{
1469 int i;
1470 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471
1472 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1473 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1474 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1475
1476 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1477 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1478 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1479 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1480
ac104e99 1481 if (amdgpu_sriov_vf(adev)) {
e935c211 1482 gfx_v9_0_compute_mqd_sw_fini(adev);
ac104e99
XY		 1483 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1484 gfx_v9_0_kiq_fini(adev);
1485 }
1486
b1023571
KW		 1487 gfx_v9_0_mec_fini(adev);
1488 gfx_v9_0_ngg_fini(adev);
1489
1490 return 0;
1491}
1492
1493
1494static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1495{
1496 /* TODO */
1497}
1498
1499static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1500{
1501 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1502
1503 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1504 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1505 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1506 } else if (se_num == 0xffffffff) {
1507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1508 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1509 } else if (sh_num == 0xffffffff) {
1510 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1512 } else {
1513 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1514 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1515 }
5e78835a 1516 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
b1023571
KW		 1517}
1518
1519static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1520{
1521 return (u32)((1ULL << bit_width) - 1);
1522}
1523
1524static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1525{
1526 u32 data, mask;
1527
5e78835a
TSD		 1528 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1529 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
b1023571
KW		 1530
1531 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1532 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1533
1534 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1535 adev->gfx.config.max_sh_per_se);
1536
1537 return (~data) & mask;
1538}
1539
1540static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1541{
1542 int i, j;
2572c24c 1543 u32 data;
b1023571
KW		 1544 u32 active_rbs = 0;
1545 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1546 adev->gfx.config.max_sh_per_se;
1547
1548 mutex_lock(&adev->grbm_idx_mutex);
1549 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1550 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1551 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1552 data = gfx_v9_0_get_rb_active_bitmap(adev);
1553 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1554 rb_bitmap_width_per_sh);
1555 }
1556 }
1557 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1558 mutex_unlock(&adev->grbm_idx_mutex);
1559
1560 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1561 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1562}
1563
1564#define DEFAULT_SH_MEM_BASES (0x6000)
1565#define FIRST_COMPUTE_VMID (8)
1566#define LAST_COMPUTE_VMID (16)
1567static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1568{
1569 int i;
1570 uint32_t sh_mem_config;
1571 uint32_t sh_mem_bases;
1572
1573 /*
1574 * Configure apertures:
1575 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1576 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1577 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1578 */
1579 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1580
1581 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1582 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
eaa05d52 1583 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
b1023571
KW		 1584
1585 mutex_lock(&adev->srbm_mutex);
1586 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1587 soc15_grbm_select(adev, 0, 0, 0, i);
1588 /* CP and shaders */
5e78835a
TSD		 1589 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1590 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
b1023571
KW		 1591 }
1592 soc15_grbm_select(adev, 0, 0, 0, 0);
1593 mutex_unlock(&adev->srbm_mutex);
1594}
1595
1596static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1597{
1598 u32 tmp;
1599 int i;
1600
40f06773 1601 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
b1023571
KW		 1602
1603 gfx_v9_0_tiling_mode_table_init(adev);
1604
1605 gfx_v9_0_setup_rb(adev);
1606 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1607
1608 /* XXX SH_MEM regs */
1609 /* where to put LDS, scratch, GPUVM in FSA64 space */
1610 mutex_lock(&adev->srbm_mutex);
1611 for (i = 0; i < 16; i++) {
1612 soc15_grbm_select(adev, 0, 0, 0, i);
1613 /* CP and shaders */
1614 tmp = 0;
1615 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1616 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5e78835a
TSD		 1617 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1618 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
b1023571
KW		 1619 }
1620 soc15_grbm_select(adev, 0, 0, 0, 0);
1621
1622 mutex_unlock(&adev->srbm_mutex);
1623
1624 gfx_v9_0_init_compute_vmid(adev);
1625
1626 mutex_lock(&adev->grbm_idx_mutex);
1627 /*
1628 * making sure that the following register writes will be broadcasted
1629 * to all the shaders
1630 */
1631 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1632
5e78835a 1633 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
b1023571
KW		 1634 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1635 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1636 (adev->gfx.config.sc_prim_fifo_size_backend <<
1637 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1638 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1639 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1640 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1641 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1642 mutex_unlock(&adev->grbm_idx_mutex);
1643
1644}
1645
1646static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1647{
1648 u32 i, j, k;
1649 u32 mask;
1650
1651 mutex_lock(&adev->grbm_idx_mutex);
1652 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1653 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1654 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1655 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1656 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
b1023571
KW		 1657 break;
1658 udelay(1);
1659 }
1660 }
1661 }
1662 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1663 mutex_unlock(&adev->grbm_idx_mutex);
1664
1665 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1666 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1667 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1668 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1669 for (k = 0; k < adev->usec_timeout; k++) {
5e78835a 1670 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
b1023571
KW		 1671 break;
1672 udelay(1);
1673 }
1674}
1675
1676static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1677 bool enable)
1678{
5e78835a 1679 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
b1023571 1680
b1023571
KW		 1681 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1682 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1683 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1684 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1685
5e78835a 1686 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
b1023571
KW		 1687}
1688
6bce4667
HZ		 1689static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1690{
1691 /* csib */
1692 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1693 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1694 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1695 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1696 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1697 adev->gfx.rlc.clear_state_size);
1698}
1699
1700static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1701 int indirect_offset,
1702 int list_size,
1703 int *unique_indirect_regs,
1704 int *unique_indirect_reg_count,
1705 int max_indirect_reg_count,
1706 int *indirect_start_offsets,
1707 int *indirect_start_offsets_count,
1708 int max_indirect_start_offsets_count)
1709{
1710 int idx;
1711 bool new_entry = true;
1712
1713 for (; indirect_offset < list_size; indirect_offset++) {
1714
1715 if (new_entry) {
1716 new_entry = false;
1717 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1718 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1719 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1720 }
1721
1722 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1723 new_entry = true;
1724 continue;
1725 }
1726
1727 indirect_offset += 2;
1728
1729 /* look for the matching indice */
1730 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1731 if (unique_indirect_regs[idx] ==
1732 register_list_format[indirect_offset])
1733 break;
1734 }
1735
1736 if (idx >= *unique_indirect_reg_count) {
1737 unique_indirect_regs[*unique_indirect_reg_count] =
1738 register_list_format[indirect_offset];
1739 idx = *unique_indirect_reg_count;
1740 *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1741 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1742 }
1743
1744 register_list_format[indirect_offset] = idx;
1745 }
1746}
1747
1748static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1749{
1750 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1751 int unique_indirect_reg_count = 0;
1752
1753 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1754 int indirect_start_offsets_count = 0;
1755
1756 int list_size = 0;
1757 int i = 0;
1758 u32 tmp = 0;
1759
1760 u32 *register_list_format =
1761 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1762 if (!register_list_format)
1763 return -ENOMEM;
1764 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1765 adev->gfx.rlc.reg_list_format_size_bytes);
1766
1767 /* setup unique_indirect_regs array and indirect_start_offsets array */
1768 gfx_v9_0_parse_ind_reg_list(register_list_format,
1769 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1770 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1771 unique_indirect_regs,
1772 &unique_indirect_reg_count,
1773 sizeof(unique_indirect_regs)/sizeof(int),
1774 indirect_start_offsets,
1775 &indirect_start_offsets_count,
1776 sizeof(indirect_start_offsets)/sizeof(int));
1777
1778 /* enable auto inc in case it is disabled */
1779 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1780 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1781 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1782
1783 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1784 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1785 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1786 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1787 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1788 adev->gfx.rlc.register_restore[i]);
1789
1790 /* load direct register */
1791 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1792 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1794 adev->gfx.rlc.register_restore[i]);
1795
1796 /* load indirect register */
1797 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1798 adev->gfx.rlc.reg_list_format_start);
1799 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1800 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1801 register_list_format[i]);
1802
1803 /* set save/restore list size */
1804 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1805 list_size = list_size >> 1;
1806 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1807 adev->gfx.rlc.reg_restore_list_size);
1808 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1809
1810 /* write the starting offsets to RLC scratch ram */
1811 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1812 adev->gfx.rlc.starting_offsets_start);
1813 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1814 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1815 indirect_start_offsets[i]);
1816
1817 /* load unique indirect regs*/
1818 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1819 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1820 unique_indirect_regs[i] & 0x3FFFF);
1821 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1822 unique_indirect_regs[i] >> 20);
1823 }
1824
1825 kfree(register_list_format);
1826 return 0;
1827}
1828
1829static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1830{
1831 u32 tmp = 0;
1832
1833 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1834 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1835 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1836}
1837
91d3130a
HZ		 1838static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1839 bool enable)
1840{
1841 uint32_t data = 0;
1842 uint32_t default_data = 0;
1843
1844 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1845 if (enable == true) {
1846 /* enable GFXIP control over CGPG */
1847 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1848 if(default_data != data)
1849 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1850
1851 /* update status */
1852 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1853 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1854 if(default_data != data)
1855 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1856 } else {
1857 /* restore GFXIP control over GCPG */
1858 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1859 if(default_data != data)
1860 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1861 }
1862}
1863
1864static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
1865{
1866 uint32_t data = 0;
1867
1868 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1869 AMD_PG_SUPPORT_GFX_SMG |
1870 AMD_PG_SUPPORT_GFX_DMG)) {
1871 /* init IDLE_POLL_COUNT = 60 */
1872 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
1873 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
1874 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
1875 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
1876
1877 /* init RLC PG Delay */
1878 data = 0;
1879 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
1880 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
1881 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
1882 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
1883 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
1884
1885 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
1886 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
1887 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
1888 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
1889
1890 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
1891 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
1892 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
1893 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
1894
1895 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
1896 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
1897
1898 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
1899 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
1900 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
1901
1902 pwr_10_0_gfxip_control_over_cgpg(adev, true);
1903 }
1904}
1905
ed5ad1e4
HZ		 1906static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
1907 bool enable)
1908{
1909 uint32_t data = 0;
1910 uint32_t default_data = 0;
1911
1912 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1913
1914 if (enable == true) {
1915 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1916 if (default_data != data)
1917 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1918 } else {
1919 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
1920 if(default_data != data)
1921 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1922 }
1923}
1924
1925static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
1926 bool enable)
1927{
1928 uint32_t data = 0;
1929 uint32_t default_data = 0;
1930
1931 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
1932
1933 if (enable == true) {
1934 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1935 if(default_data != data)
1936 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1937 } else {
1938 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
1939 if(default_data != data)
1940 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
1941 }
1942}
1943
6bce4667
HZ		 1944static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
1945{
1946 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
1947 AMD_PG_SUPPORT_GFX_SMG |
1948 AMD_PG_SUPPORT_GFX_DMG |
1949 AMD_PG_SUPPORT_CP |
1950 AMD_PG_SUPPORT_GDS |
1951 AMD_PG_SUPPORT_RLC_SMU_HS)) {
1952 gfx_v9_0_init_csb(adev);
1953 gfx_v9_0_init_rlc_save_restore_list(adev);
1954 gfx_v9_0_enable_save_restore_machine(adev);
91d3130a
HZ		 1955
1956 if (adev->asic_type == CHIP_RAVEN) {
1957 WREG32(mmRLC_JUMP_TABLE_RESTORE,
1958 adev->gfx.rlc.cp_table_gpu_addr >> 8);
1959 gfx_v9_0_init_gfx_power_gating(adev);
ed5ad1e4
HZ		 1960 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
1961 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
1962 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
1963 } else {
1964 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
1965 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
1966 }
91d3130a 1967 }
6bce4667
HZ		 1968 }
1969}
1970
b1023571
KW		 1971void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1972{
5e78835a 1973 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 1974
1975 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5e78835a 1976 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
b1023571
KW		 1977
1978 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1979
1980 gfx_v9_0_wait_for_rlc_serdes(adev);
1981}
1982
1983static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1984{
596c8e8b 1985 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
b1023571 1986 udelay(50);
596c8e8b 1987 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
b1023571
KW		 1988 udelay(50);
1989}
1990
1991static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1992{
1993#ifdef AMDGPU_RLC_DEBUG_RETRY
1994 u32 rlc_ucode_ver;
1995#endif
b1023571 1996
342cda25 1997 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1998
1999 /* carrizo do enable cp interrupt after cp inited */
2000 if (!(adev->flags & AMD_IS_APU))
2001 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2002
2003 udelay(50);
2004
2005#ifdef AMDGPU_RLC_DEBUG_RETRY
2006 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
5e78835a 2007 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
b1023571
KW		 2008 if(rlc_ucode_ver == 0x108) {
2009 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2010 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2011 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2012 * default is 0x9C4 to create a 100us interval */
5e78835a 2013 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
b1023571 2014 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
eaa05d52 2015 * to disable the page fault retry interrupts, default is
b1023571 2016 * 0x100 (256) */
5e78835a 2017 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
b1023571
KW		 2018 }
2019#endif
2020}
2021
2022static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2023{
2024 const struct rlc_firmware_header_v2_0 *hdr;
2025 const __le32 *fw_data;
2026 unsigned i, fw_size;
2027
2028 if (!adev->gfx.rlc_fw)
2029 return -EINVAL;
2030
2031 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2032 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2033
2034 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2035 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2036 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2037
5e78835a 2038 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
b1023571
KW		 2039 RLCG_UCODE_LOADING_START_ADDRESS);
2040 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2041 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2042 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
b1023571
KW		 2043
2044 return 0;
2045}
2046
2047static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2048{
2049 int r;
2050
cfee05bc
ML		 2051 if (amdgpu_sriov_vf(adev))
2052 return 0;
2053
b1023571
KW		 2054 gfx_v9_0_rlc_stop(adev);
2055
2056 /* disable CG */
5e78835a 2057 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
b1023571
KW		 2058
2059 /* disable PG */
5e78835a 2060 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
b1023571
KW		 2061
2062 gfx_v9_0_rlc_reset(adev);
2063
6bce4667
HZ		 2064 gfx_v9_0_init_pg(adev);
2065
b1023571
KW		 2066 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2067 /* legacy rlc firmware loading */
2068 r = gfx_v9_0_rlc_load_microcode(adev);
2069 if (r)
2070 return r;
2071 }
2072
2073 gfx_v9_0_rlc_start(adev);
2074
2075 return 0;
2076}
2077
2078static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2079{
2080 int i;
5e78835a 2081 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
b1023571 2082
ea64468e
TSD		 2083 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2084 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2085 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2086 if (!enable) {
b1023571
KW		 2087 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2088 adev->gfx.gfx_ring[i].ready = false;
2089 }
5e78835a 2090 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
b1023571
KW		 2091 udelay(50);
2092}
2093
2094static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2095{
2096 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2097 const struct gfx_firmware_header_v1_0 *ce_hdr;
2098 const struct gfx_firmware_header_v1_0 *me_hdr;
2099 const __le32 *fw_data;
2100 unsigned i, fw_size;
2101
2102 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2103 return -EINVAL;
2104
2105 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2106 adev->gfx.pfp_fw->data;
2107 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2108 adev->gfx.ce_fw->data;
2109 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2110 adev->gfx.me_fw->data;
2111
2112 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2113 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2114 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2115
2116 gfx_v9_0_cp_gfx_enable(adev, false);
2117
2118 /* PFP */
2119 fw_data = (const __le32 *)
2120 (adev->gfx.pfp_fw->data +
2121 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2122 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
5e78835a 2123 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
b1023571 2124 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2125 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2126 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
b1023571
KW		 2127
2128 /* CE */
2129 fw_data = (const __le32 *)
2130 (adev->gfx.ce_fw->data +
2131 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2132 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
5e78835a 2133 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
b1023571 2134 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2135 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2136 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
b1023571
KW		 2137
2138 /* ME */
2139 fw_data = (const __le32 *)
2140 (adev->gfx.me_fw->data +
2141 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2142 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
5e78835a 2143 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
b1023571 2144 for (i = 0; i < fw_size; i++)
5e78835a
TSD		 2145 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2146 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
b1023571
KW		 2147
2148 return 0;
2149}
2150
b1023571
KW		 2151static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2152{
2153 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2154 const struct cs_section_def *sect = NULL;
2155 const struct cs_extent_def *ext = NULL;
2156 int r, i;
2157
2158 /* init the CP */
5e78835a
TSD		 2159 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2160 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
b1023571
KW		 2161
2162 gfx_v9_0_cp_gfx_enable(adev, true);
2163
2164 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
2165 if (r) {
2166 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2167 return r;
2168 }
2169
2170 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2171 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2172
2173 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2174 amdgpu_ring_write(ring, 0x80000000);
2175 amdgpu_ring_write(ring, 0x80000000);
2176
2177 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2178 for (ext = sect->section; ext->extent != NULL; ++ext) {
2179 if (sect->id == SECT_CONTEXT) {
2180 amdgpu_ring_write(ring,
2181 PACKET3(PACKET3_SET_CONTEXT_REG,
2182 ext->reg_count));
2183 amdgpu_ring_write(ring,
2184 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2185 for (i = 0; i < ext->reg_count; i++)
2186 amdgpu_ring_write(ring, ext->extent[i]);
2187 }
2188 }
2189 }
2190
2191 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2192 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2193
2194 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2195 amdgpu_ring_write(ring, 0);
2196
2197 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2198 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2199 amdgpu_ring_write(ring, 0x8000);
2200 amdgpu_ring_write(ring, 0x8000);
2201
2202 amdgpu_ring_commit(ring);
2203
2204 return 0;
2205}
2206
2207static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2208{
2209 struct amdgpu_ring *ring;
2210 u32 tmp;
2211 u32 rb_bufsz;
3fc08b61 2212 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 2213
2214 /* Set the write pointer delay */
5e78835a 2215 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
b1023571
KW		 2216
2217 /* set the RB to use vmid 0 */
5e78835a 2218 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
b1023571
KW		 2219
2220 /* Set ring buffer size */
2221 ring = &adev->gfx.gfx_ring[0];
2222 rb_bufsz = order_base_2(ring->ring_size / 8);
2223 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2224 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2225#ifdef __BIG_ENDIAN
2226 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2227#endif
5e78835a 2228 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2229
2230 /* Initialize the ring buffer's write pointers */
2231 ring->wptr = 0;
5e78835a
TSD		 2232 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2233 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 2234
2235 /* set the wb address wether it's enabled or not */
2236 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5e78835a
TSD		 2237 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2238 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
b1023571 2239
3fc08b61 2240 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5e78835a
TSD		 2241 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2242 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3fc08b61 2243
b1023571 2244 mdelay(1);
5e78835a 2245 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
b1023571
KW		 2246
2247 rb_addr = ring->gpu_addr >> 8;
5e78835a
TSD		 2248 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2249 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
b1023571 2250
5e78835a 2251 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
b1023571
KW		 2252 if (ring->use_doorbell) {
2253 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2254 DOORBELL_OFFSET, ring->doorbell_index);
2255 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2256 DOORBELL_EN, 1);
2257 } else {
2258 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2259 }
5e78835a 2260 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
b1023571
KW		 2261
2262 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2263 DOORBELL_RANGE_LOWER, ring->doorbell_index);
5e78835a 2264 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
b1023571 2265
5e78835a 2266 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
b1023571
KW		 2267 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2268
2269
2270 /* start the ring */
2271 gfx_v9_0_cp_gfx_start(adev);
2272 ring->ready = true;
2273
2274 return 0;
2275}
2276
2277static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2278{
2279 int i;
2280
2281 if (enable) {
5e78835a 2282 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
b1023571 2283 } else {
5e78835a 2284 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
b1023571
KW		 2285 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2286 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2287 adev->gfx.compute_ring[i].ready = false;
ac104e99 2288 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 2289 }
2290 udelay(50);
2291}
2292
2293static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
2294{
2295 gfx_v9_0_cp_compute_enable(adev, true);
2296
2297 return 0;
2298}
2299
2300static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2301{
2302 const struct gfx_firmware_header_v1_0 *mec_hdr;
2303 const __le32 *fw_data;
2304 unsigned i;
2305 u32 tmp;
2306
2307 if (!adev->gfx.mec_fw)
2308 return -EINVAL;
2309
2310 gfx_v9_0_cp_compute_enable(adev, false);
2311
2312 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2313 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2314
2315 fw_data = (const __le32 *)
2316 (adev->gfx.mec_fw->data +
2317 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2318 tmp = 0;
2319 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2320 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5e78835a 2321 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
b1023571 2322
5e78835a 2323 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
b1023571 2324 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
5e78835a 2325 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
b1023571 2326 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
eaa05d52 2327
b1023571 2328 /* MEC1 */
5e78835a 2329 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2330 mec_hdr->jt_offset);
2331 for (i = 0; i < mec_hdr->jt_size; i++)
5e78835a 2332 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
b1023571
KW		 2333 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2334
5e78835a 2335 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
b1023571
KW		 2336 adev->gfx.mec_fw_version);
2337 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2338
2339 return 0;
2340}
2341
2342static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
2343{
2344 int i, r;
2345
2346 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2347 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2348
2349 if (ring->mqd_obj) {
c81a1a74 2350 r = amdgpu_bo_reserve(ring->mqd_obj, true);
b1023571
KW		 2351 if (unlikely(r != 0))
2352 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2353
2354 amdgpu_bo_unpin(ring->mqd_obj);
2355 amdgpu_bo_unreserve(ring->mqd_obj);
2356
2357 amdgpu_bo_unref(&ring->mqd_obj);
2358 ring->mqd_obj = NULL;
2359 }
2360 }
2361}
2362
2363static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
2364
2365static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
2366{
2367 int i, r;
2368 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2369 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2370 if (gfx_v9_0_init_queue(ring))
2371 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
2372 }
2373
2374 r = gfx_v9_0_cp_compute_start(adev);
2375 if (r)
2376 return r;
2377
2378 return 0;
2379}
2380
464826d6
XY		 2381/* KIQ functions */
2382static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2383{
2384 uint32_t tmp;
2385 struct amdgpu_device *adev = ring->adev;
2386
2387 /* tell RLC which is KIQ queue */
5e78835a 2388 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
464826d6
XY		 2389 tmp &= 0xffffff00;
2390 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5e78835a 2391 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6 2392 tmp |= 0x80;
5e78835a 2393 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
464826d6
XY		 2394}
2395
2fdde9fa 2396static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
464826d6 2397{
2fdde9fa
AD		 2398 struct amdgpu_device *adev = ring->adev;
2399 uint32_t scratch, tmp = 0;
2400 int r, i;
2401
2402 r = amdgpu_gfx_scratch_get(adev, &scratch);
2403 if (r) {
2404 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2405 return r;
2406 }
2407 WREG32(scratch, 0xCAFEDEAD);
2408
2409 r = amdgpu_ring_alloc(ring, 8);
2410 if (r) {
2411 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2412 amdgpu_gfx_scratch_free(adev, scratch);
2413 return r;
2414 }
2415 amdgpu_ring_alloc(ring, 11);
464826d6
XY		 2416 /* set resources */
2417 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
f1f7b443
AD		 2418 amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2419 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
464826d6
XY		 2420 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */
2421 amdgpu_ring_write(ring, 0); /* queue mask hi */
2422 amdgpu_ring_write(ring, 0); /* gws mask lo */
2423 amdgpu_ring_write(ring, 0); /* gws mask hi */
2424 amdgpu_ring_write(ring, 0); /* oac mask */
2425 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
2fdde9fa
AD		 2426 /* write to scratch for completion */
2427 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2428 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2429 amdgpu_ring_write(ring, 0xDEADBEEF);
464826d6 2430 amdgpu_ring_commit(ring);
2fdde9fa
AD		 2431
2432 for (i = 0; i < adev->usec_timeout; i++) {
2433 tmp = RREG32(scratch);
2434 if (tmp == 0xDEADBEEF)
2435 break;
2436 DRM_UDELAY(1);
2437 }
2438 if (i >= adev->usec_timeout) {
2439 DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n",
2440 scratch, tmp);
2441 r = -EINVAL;
2442 }
2443 amdgpu_gfx_scratch_free(adev, scratch);
2444
2445 return r;
464826d6
XY		 2446}
2447
2fdde9fa
AD		 2448static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
2449 struct amdgpu_ring *ring)
464826d6
XY		 2450{
2451 struct amdgpu_device *adev = kiq_ring->adev;
2452 uint64_t mqd_addr, wptr_addr;
2fdde9fa
AD		 2453 uint32_t scratch, tmp = 0;
2454 int r, i;
2455
2456 r = amdgpu_gfx_scratch_get(adev, &scratch);
2457 if (r) {
2458 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2459 return r;
2460 }
2461 WREG32(scratch, 0xCAFEDEAD);
2462
2463 r = amdgpu_ring_alloc(kiq_ring, 10);
2464 if (r) {
2465 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2466 amdgpu_gfx_scratch_free(adev, scratch);
2467 return r;
2468 }
464826d6
XY		 2469
2470 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2471 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
464826d6
XY		 2472
2473 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2474 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2475 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
f1f7b443
AD		 2476 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2477 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2478 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2479 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2480 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2481 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2482 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2483 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2484 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2485 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
464826d6
XY		 2486 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2487 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2488 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2489 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2fdde9fa
AD		 2490 /* write to scratch for completion */
2491 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2492 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2493 amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
464826d6 2494 amdgpu_ring_commit(kiq_ring);
2fdde9fa
AD		 2495
2496 for (i = 0; i < adev->usec_timeout; i++) {
2497 tmp = RREG32(scratch);
2498 if (tmp == 0xDEADBEEF)
2499 break;
2500 DRM_UDELAY(1);
2501 }
2502 if (i >= adev->usec_timeout) {
2503 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2504 scratch, tmp);
2505 r = -EINVAL;
2506 }
2507 amdgpu_gfx_scratch_free(adev, scratch);
2508
2509 return r;
464826d6
XY		 2510}
2511
e322edc3 2512static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 2513{
33fb8698 2514 struct amdgpu_device *adev = ring->adev;
e322edc3 2515 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2516 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2517 uint32_t tmp;
2518
2519 mqd->header = 0xC0310800;
2520 mqd->compute_pipelinestat_enable = 0x00000001;
2521 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2522 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2523 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2524 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2525 mqd->compute_misc_reserved = 0x00000003;
2526
d72f2f46 2527 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 2528 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2529 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2530
2531 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2532 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
464826d6
XY		 2533 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2534 (order_base_2(MEC_HPD_SIZE / 4) - 1));
2535
2536 mqd->cp_hqd_eop_control = tmp;
2537
2538 /* enable doorbell? */
5e78835a 2539 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2540
2541 if (ring->use_doorbell) {
2542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2543 DOORBELL_OFFSET, ring->doorbell_index);
2544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2545 DOORBELL_EN, 1);
2546 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2547 DOORBELL_SOURCE, 0);
2548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2549 DOORBELL_HIT, 0);
2550 }
2551 else
2552 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2553 DOORBELL_EN, 0);
2554
2555 mqd->cp_hqd_pq_doorbell_control = tmp;
2556
2557 /* disable the queue if it's active */
2558 ring->wptr = 0;
2559 mqd->cp_hqd_dequeue_request = 0;
2560 mqd->cp_hqd_pq_rptr = 0;
2561 mqd->cp_hqd_pq_wptr_lo = 0;
2562 mqd->cp_hqd_pq_wptr_hi = 0;
2563
2564 /* set the pointer to the MQD */
33fb8698
AD		 2565 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2566 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 2567
2568 /* set MQD vmid to 0 */
5e78835a 2569 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
464826d6
XY		 2570 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2571 mqd->cp_mqd_control = tmp;
2572
2573 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2574 hqd_gpu_addr = ring->gpu_addr >> 8;
2575 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2576 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2577
2578 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2579 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
464826d6
XY		 2580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2581 (order_base_2(ring->ring_size / 4) - 1));
2582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2583 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2584#ifdef __BIG_ENDIAN
2585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2586#endif
2587 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2588 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2590 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2591 mqd->cp_hqd_pq_control = tmp;
2592
2593 /* set the wb address whether it's enabled or not */
2594 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2595 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2596 mqd->cp_hqd_pq_rptr_report_addr_hi =
2597 upper_32_bits(wb_gpu_addr) & 0xffff;
2598
2599 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2600 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2601 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2602 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2603
2604 tmp = 0;
2605 /* enable the doorbell if requested */
2606 if (ring->use_doorbell) {
5e78835a 2607 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
464826d6
XY		 2608 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2609 DOORBELL_OFFSET, ring->doorbell_index);
2610
2611 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2612 DOORBELL_EN, 1);
2613 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2614 DOORBELL_SOURCE, 0);
2615 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2616 DOORBELL_HIT, 0);
2617 }
2618
2619 mqd->cp_hqd_pq_doorbell_control = tmp;
2620
2621 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2622 ring->wptr = 0;
0274a9c5 2623 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
464826d6
XY		 2624
2625 /* set the vmid for the queue */
2626 mqd->cp_hqd_vmid = 0;
2627
0274a9c5 2628 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
464826d6
XY		 2629 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2630 mqd->cp_hqd_persistent_state = tmp;
2631
fca4ce69
AD		 2632 /* set MIN_IB_AVAIL_SIZE */
2633 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2634 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2635 mqd->cp_hqd_ib_control = tmp;
2636
464826d6
XY		 2637 /* activate the queue */
2638 mqd->cp_hqd_active = 1;
2639
2640 return 0;
2641}
2642
e322edc3 2643static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2644{
33fb8698 2645 struct amdgpu_device *adev = ring->adev;
e322edc3 2646 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2647 int j;
2648
2649 /* disable wptr polling */
72edadd5 2650 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6 2651
5e78835a 2652 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
464826d6 2653 mqd->cp_hqd_eop_base_addr_lo);
5e78835a 2654 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
464826d6
XY		 2655 mqd->cp_hqd_eop_base_addr_hi);
2656
2657 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 2658 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
464826d6
XY		 2659 mqd->cp_hqd_eop_control);
2660
2661 /* enable doorbell? */
5e78835a 2662 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2663 mqd->cp_hqd_pq_doorbell_control);
2664
2665 /* disable the queue if it's active */
5e78835a
TSD		 2666 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2667 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
464826d6 2668 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 2669 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
464826d6
XY		 2670 break;
2671 udelay(1);
2672 }
5e78835a 2673 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
464826d6 2674 mqd->cp_hqd_dequeue_request);
5e78835a 2675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
464826d6 2676 mqd->cp_hqd_pq_rptr);
5e78835a 2677 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2678 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2679 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2680 mqd->cp_hqd_pq_wptr_hi);
2681 }
2682
2683 /* set the pointer to the MQD */
5e78835a 2684 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
464826d6 2685 mqd->cp_mqd_base_addr_lo);
5e78835a 2686 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
464826d6
XY		 2687 mqd->cp_mqd_base_addr_hi);
2688
2689 /* set MQD vmid to 0 */
5e78835a 2690 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
464826d6
XY		 2691 mqd->cp_mqd_control);
2692
2693 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5e78835a 2694 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
464826d6 2695 mqd->cp_hqd_pq_base_lo);
5e78835a 2696 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
464826d6
XY		 2697 mqd->cp_hqd_pq_base_hi);
2698
2699 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 2700 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
464826d6
XY		 2701 mqd->cp_hqd_pq_control);
2702
2703 /* set the wb address whether it's enabled or not */
5e78835a 2704 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
464826d6 2705 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 2706 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
464826d6
XY		 2707 mqd->cp_hqd_pq_rptr_report_addr_hi);
2708
2709 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
5e78835a 2710 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
464826d6 2711 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 2712 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
464826d6
XY		 2713 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2714
2715 /* enable the doorbell if requested */
2716 if (ring->use_doorbell) {
5e78835a 2717 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
464826d6 2718 (AMDGPU_DOORBELL64_KIQ *2) << 2);
5e78835a 2719 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
464826d6
XY		 2720 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2721 }
2722
5e78835a 2723 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
464826d6
XY		 2724 mqd->cp_hqd_pq_doorbell_control);
2725
2726 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a 2727 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
464826d6 2728 mqd->cp_hqd_pq_wptr_lo);
5e78835a 2729 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
464826d6
XY		 2730 mqd->cp_hqd_pq_wptr_hi);
2731
2732 /* set the vmid for the queue */
5e78835a 2733 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
464826d6 2734
5e78835a 2735 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
464826d6
XY		 2736 mqd->cp_hqd_persistent_state);
2737
2738 /* activate the queue */
5e78835a 2739 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
464826d6
XY		 2740 mqd->cp_hqd_active);
2741
72edadd5
TSD		 2742 if (ring->use_doorbell)
2743 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2744
2745 return 0;
2746}
2747
e322edc3 2748static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2749{
2750 struct amdgpu_device *adev = ring->adev;
2751 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
e322edc3 2752 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2753 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
2754 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2fdde9fa 2755 int r;
464826d6
XY		 2756
2757 if (is_kiq) {
464826d6
XY		 2758 gfx_v9_0_kiq_setting(&kiq->ring);
2759 } else {
464826d6
XY		 2760 mqd_idx = ring - &adev->gfx.compute_ring[0];
2761 }
2762
2763 if (!adev->gfx.in_reset) {
2764 memset((void *)mqd, 0, sizeof(*mqd));
2765 mutex_lock(&adev->srbm_mutex);
2766 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2767 gfx_v9_0_mqd_init(ring);
464826d6 2768 if (is_kiq)
e322edc3 2769 gfx_v9_0_kiq_init_register(ring);
464826d6
XY		 2770 soc15_grbm_select(adev, 0, 0, 0, 0);
2771 mutex_unlock(&adev->srbm_mutex);
2772
0ef376ca
AD		 2773 if (adev->gfx.mec.mqd_backup[mqd_idx])
2774 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
464826d6
XY		 2775 } else { /* for GPU_RESET case */
2776 /* reset MQD to a clean status */
0ef376ca
AD		 2777 if (adev->gfx.mec.mqd_backup[mqd_idx])
2778 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
464826d6
XY		 2779
2780 /* reset ring buffer */
2781 ring->wptr = 0;
b98724db 2782 amdgpu_ring_clear_ring(ring);
464826d6
XY		 2783
2784 if (is_kiq) {
2785 mutex_lock(&adev->srbm_mutex);
2786 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2787 gfx_v9_0_kiq_init_register(ring);
464826d6
XY		 2788 soc15_grbm_select(adev, 0, 0, 0, 0);
2789 mutex_unlock(&adev->srbm_mutex);
2790 }
2791 }
2792
2793 if (is_kiq)
2fdde9fa 2794 r = gfx_v9_0_kiq_enable(ring);
464826d6 2795 else
2fdde9fa 2796 r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
464826d6 2797
2fdde9fa 2798 return r;
464826d6
XY		 2799}
2800
2801static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2802{
2803 struct amdgpu_ring *ring = NULL;
2804 int r = 0, i;
2805
2806 gfx_v9_0_cp_compute_enable(adev, true);
2807
2808 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2809
2810 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2811 if (unlikely(r != 0))
2812 goto done;
2813
2814 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2815 if (!r) {
e322edc3 2816 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2817 amdgpu_bo_kunmap(ring->mqd_obj);
2818 ring->mqd_ptr = NULL;
464826d6 2819 }
e1d53aa8
AD		 2820 amdgpu_bo_unreserve(ring->mqd_obj);
2821 if (r)
2822 goto done;
464826d6
XY		 2823
2824 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2825 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2826
2827 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2828 if (unlikely(r != 0))
2829 goto done;
2830 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2831 if (!r) {
e322edc3 2832 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2833 amdgpu_bo_kunmap(ring->mqd_obj);
2834 ring->mqd_ptr = NULL;
464826d6 2835 }
e1d53aa8
AD		 2836 amdgpu_bo_unreserve(ring->mqd_obj);
2837 if (r)
2838 goto done;
464826d6
XY		 2839 }
2840
e1d53aa8
AD		 2841done:
2842 return r;
464826d6
XY		 2843}
2844
b1023571
KW		 2845static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2846{
2847 int r,i;
2848 struct amdgpu_ring *ring;
2849
2850 if (!(adev->flags & AMD_IS_APU))
2851 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2852
2853 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2854 /* legacy firmware loading */
2855 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2856 if (r)
2857 return r;
2858
2859 r = gfx_v9_0_cp_compute_load_microcode(adev);
2860 if (r)
2861 return r;
2862 }
2863
2864 r = gfx_v9_0_cp_gfx_resume(adev);
2865 if (r)
2866 return r;
2867
464826d6
XY		 2868 if (amdgpu_sriov_vf(adev))
2869 r = gfx_v9_0_kiq_resume(adev);
2870 else
2871 r = gfx_v9_0_cp_compute_resume(adev);
b1023571
KW		 2872 if (r)
2873 return r;
2874
2875 ring = &adev->gfx.gfx_ring[0];
2876 r = amdgpu_ring_test_ring(ring);
2877 if (r) {
2878 ring->ready = false;
2879 return r;
2880 }
2881 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2882 ring = &adev->gfx.compute_ring[i];
2883
2884 ring->ready = true;
2885 r = amdgpu_ring_test_ring(ring);
2886 if (r)
2887 ring->ready = false;
2888 }
2889
464826d6
XY		 2890 if (amdgpu_sriov_vf(adev)) {
2891 ring = &adev->gfx.kiq.ring;
2892 ring->ready = true;
2893 r = amdgpu_ring_test_ring(ring);
2894 if (r)
2895 ring->ready = false;
2896 }
2897
b1023571
KW		 2898 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2899
2900 return 0;
2901}
2902
2903static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2904{
2905 gfx_v9_0_cp_gfx_enable(adev, enable);
2906 gfx_v9_0_cp_compute_enable(adev, enable);
2907}
2908
2909static int gfx_v9_0_hw_init(void *handle)
2910{
2911 int r;
2912 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2913
2914 gfx_v9_0_init_golden_registers(adev);
2915
2916 gfx_v9_0_gpu_init(adev);
2917
2918 r = gfx_v9_0_rlc_resume(adev);
2919 if (r)
2920 return r;
2921
2922 r = gfx_v9_0_cp_resume(adev);
2923 if (r)
2924 return r;
2925
2926 r = gfx_v9_0_ngg_en(adev);
2927 if (r)
2928 return r;
2929
2930 return r;
2931}
2932
2933static int gfx_v9_0_hw_fini(void *handle)
2934{
2935 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2936
2937 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2938 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2939 if (amdgpu_sriov_vf(adev)) {
2940 pr_debug("For SRIOV client, shouldn't do anything.\n");
2941 return 0;
2942 }
b1023571
KW		 2943 gfx_v9_0_cp_enable(adev, false);
2944 gfx_v9_0_rlc_stop(adev);
2945 gfx_v9_0_cp_compute_fini(adev);
2946
2947 return 0;
2948}
2949
2950static int gfx_v9_0_suspend(void *handle)
2951{
2952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2953
2954 return gfx_v9_0_hw_fini(adev);
2955}
2956
2957static int gfx_v9_0_resume(void *handle)
2958{
2959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2960
2961 return gfx_v9_0_hw_init(adev);
2962}
2963
2964static bool gfx_v9_0_is_idle(void *handle)
2965{
2966 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2967
5e78835a 2968 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
b1023571
KW		 2969 GRBM_STATUS, GUI_ACTIVE))
2970 return false;
2971 else
2972 return true;
2973}
2974
2975static int gfx_v9_0_wait_for_idle(void *handle)
2976{
2977 unsigned i;
2978 u32 tmp;
2979 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2980
2981 for (i = 0; i < adev->usec_timeout; i++) {
2982 /* read MC_STATUS */
5e78835a 2983 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
b1023571
KW		 2984 GRBM_STATUS__GUI_ACTIVE_MASK;
2985
2986 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2987 return 0;
2988 udelay(1);
2989 }
2990 return -ETIMEDOUT;
2991}
2992
b1023571
KW		 2993static int gfx_v9_0_soft_reset(void *handle)
2994{
2995 u32 grbm_soft_reset = 0;
2996 u32 tmp;
2997 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2998
2999 /* GRBM_STATUS */
5e78835a 3000 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
b1023571
KW		 3001 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3002 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3003 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3004 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3005 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3006 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3007 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3008 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3009 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3010 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3011 }
3012
3013 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3014 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3015 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3016 }
3017
3018 /* GRBM_STATUS2 */
5e78835a 3019 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
b1023571
KW		 3020 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3021 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3022 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3023
3024
75bac5c6 3025 if (grbm_soft_reset) {
b1023571
KW		 3026 /* stop the rlc */
3027 gfx_v9_0_rlc_stop(adev);
3028
3029 /* Disable GFX parsing/prefetching */
3030 gfx_v9_0_cp_gfx_enable(adev, false);
3031
3032 /* Disable MEC parsing/prefetching */
3033 gfx_v9_0_cp_compute_enable(adev, false);
3034
3035 if (grbm_soft_reset) {
5e78835a 3036 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3037 tmp |= grbm_soft_reset;
3038 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5e78835a
TSD		 3039 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3040 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3041
3042 udelay(50);
3043
3044 tmp &= ~grbm_soft_reset;
5e78835a
TSD		 3045 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3046 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
b1023571
KW		 3047 }
3048
3049 /* Wait a little for things to settle down */
3050 udelay(50);
b1023571
KW		 3051 }
3052 return 0;
3053}
3054
3055static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3056{
3057 uint64_t clock;
3058
3059 mutex_lock(&adev->gfx.gpu_clock_mutex);
5e78835a
TSD		 3060 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3061 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3062 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
b1023571
KW		 3063 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3064 return clock;
3065}
3066
3067static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3068 uint32_t vmid,
3069 uint32_t gds_base, uint32_t gds_size,
3070 uint32_t gws_base, uint32_t gws_size,
3071 uint32_t oa_base, uint32_t oa_size)
3072{
3073 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3074 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3075
3076 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3077 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3078
3079 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3080 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3081
3082 /* GDS Base */
3083 gfx_v9_0_write_data_to_reg(ring, 0, false,
3084 amdgpu_gds_reg_offset[vmid].mem_base,
3085 gds_base);
3086
3087 /* GDS Size */
3088 gfx_v9_0_write_data_to_reg(ring, 0, false,
3089 amdgpu_gds_reg_offset[vmid].mem_size,
3090 gds_size);
3091
3092 /* GWS */
3093 gfx_v9_0_write_data_to_reg(ring, 0, false,
3094 amdgpu_gds_reg_offset[vmid].gws,
3095 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3096
3097 /* OA */
3098 gfx_v9_0_write_data_to_reg(ring, 0, false,
3099 amdgpu_gds_reg_offset[vmid].oa,
3100 (1 << (oa_size + oa_base)) - (1 << oa_base));
3101}
3102
3103static int gfx_v9_0_early_init(void *handle)
3104{
3105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3106
3107 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3108 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
3109 gfx_v9_0_set_ring_funcs(adev);
3110 gfx_v9_0_set_irq_funcs(adev);
3111 gfx_v9_0_set_gds_init(adev);
3112 gfx_v9_0_set_rlc_funcs(adev);
3113
3114 return 0;
3115}
3116
3117static int gfx_v9_0_late_init(void *handle)
3118{
3119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3120 int r;
3121
3122 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3123 if (r)
3124 return r;
3125
3126 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3127 if (r)
3128 return r;
3129
3130 return 0;
3131}
3132
3133static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3134{
3135 uint32_t rlc_setting, data;
3136 unsigned i;
3137
3138 if (adev->gfx.rlc.in_safe_mode)
3139 return;
3140
3141 /* if RLC is not enabled, do nothing */
5e78835a 3142 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3143 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3144 return;
3145
3146 if (adev->cg_flags &
3147 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3148 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3149 data = RLC_SAFE_MODE__CMD_MASK;
3150 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5e78835a 3151 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3152
3153 /* wait for RLC_SAFE_MODE */
3154 for (i = 0; i < adev->usec_timeout; i++) {
3155 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3156 break;
3157 udelay(1);
3158 }
3159 adev->gfx.rlc.in_safe_mode = true;
3160 }
3161}
3162
3163static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3164{
3165 uint32_t rlc_setting, data;
3166
3167 if (!adev->gfx.rlc.in_safe_mode)
3168 return;
3169
3170 /* if RLC is not enabled, do nothing */
5e78835a 3171 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
b1023571
KW		 3172 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3173 return;
3174
3175 if (adev->cg_flags &
3176 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3177 /*
3178 * Try to exit safe mode only if it is already in safe
3179 * mode.
3180 */
3181 data = RLC_SAFE_MODE__CMD_MASK;
5e78835a 3182 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
b1023571
KW		 3183 adev->gfx.rlc.in_safe_mode = false;
3184 }
3185}
3186
3187static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3188 bool enable)
3189{
3190 uint32_t data, def;
3191
3192 /* It is disabled by HW by default */
3193 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3194 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
5e78835a 3195 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3196 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3197 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3198 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3199 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3200
3201 /* only for Vega10 & Raven1 */
3202 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3203
3204 if (def != data)
5e78835a 3205 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3206
3207 /* MGLS is a global flag to control all MGLS in GFX */
3208 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3209 /* 2 - RLC memory Light sleep */
3210 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5e78835a 3211 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3212 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3213 if (def != data)
5e78835a 3214 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3215 }
3216 /* 3 - CP memory Light sleep */
3217 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5e78835a 3218 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3219 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3220 if (def != data)
5e78835a 3221 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3222 }
3223 }
3224 } else {
3225 /* 1 - MGCG_OVERRIDE */
5e78835a 3226 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3227 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3228 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3229 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3230 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3231 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3232 if (def != data)
5e78835a 3233 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3234
3235 /* 2 - disable MGLS in RLC */
5e78835a 3236 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
b1023571
KW		 3237 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3238 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5e78835a 3239 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
b1023571
KW		 3240 }
3241
3242 /* 3 - disable MGLS in CP */
5e78835a 3243 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
b1023571
KW		 3244 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3245 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5e78835a 3246 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
b1023571
KW		 3247 }
3248 }
3249}
3250
3251static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3252 bool enable)
3253{
3254 uint32_t data, def;
3255
3256 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3257
3258 /* Enable 3D CGCG/CGLS */
3259 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3260 /* write cmd to clear cgcg/cgls ov */
5e78835a 3261 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3262 /* unset CGCG override */
3263 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3264 /* update CGCG and CGLS override bits */
3265 if (def != data)
5e78835a 3266 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571 3267 /* enable 3Dcgcg FSM(0x0020003f) */
5e78835a 3268 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3269 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3270 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3271 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3272 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3273 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3274 if (def != data)
5e78835a 3275 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3276
3277 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3278 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3279 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3280 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3281 if (def != data)
5e78835a 3282 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571
KW		 3283 } else {
3284 /* Disable CGCG/CGLS */
5e78835a 3285 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
b1023571
KW		 3286 /* disable cgcg, cgls should be disabled */
3287 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3288 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3289 /* disable cgcg and cgls in FSM */
3290 if (def != data)
5e78835a 3291 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
b1023571
KW		 3292 }
3293
3294 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3295}
3296
3297static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3298 bool enable)
3299{
3300 uint32_t def, data;
3301
3302 adev->gfx.rlc.funcs->enter_safe_mode(adev);
3303
3304 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5e78835a 3305 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
b1023571
KW		 3306 /* unset CGCG override */
3307 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3308 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3309 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3310 else
3311 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3312 /* update CGCG and CGLS override bits */
3313 if (def != data)
5e78835a 3314 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
b1023571
KW		 3315
3316 /* enable cgcg FSM(0x0020003F) */
5e78835a 3317 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3318 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3319 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3320 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3321 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3322 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3323 if (def != data)
5e78835a 3324 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3325
3326 /* set IDLE_POLL_COUNT(0x00900100) */
5e78835a 3327 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
b1023571
KW		 3328 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3329 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3330 if (def != data)
5e78835a 3331 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
b1023571 3332 } else {
5e78835a 3333 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
b1023571
KW		 3334 /* reset CGCG/CGLS bits */
3335 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3336 /* disable cgcg and cgls in FSM */
3337 if (def != data)
5e78835a 3338 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
b1023571
KW		 3339 }
3340
3341 adev->gfx.rlc.funcs->exit_safe_mode(adev);
3342}
3343
3344static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3345 bool enable)
3346{
3347 if (enable) {
3348 /* CGCG/CGLS should be enabled after MGCG/MGLS
3349 * === MGCG + MGLS ===
3350 */
3351 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3352 /* === CGCG /CGLS for GFX 3D Only === */
3353 gfx_v9_0_update_3d_clock_gating(adev, enable);
3354 /* === CGCG + CGLS === */
3355 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3356 } else {
3357 /* CGCG/CGLS should be disabled before MGCG/MGLS
3358 * === CGCG + CGLS ===
3359 */
3360 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3361 /* === CGCG /CGLS for GFX 3D Only === */
3362 gfx_v9_0_update_3d_clock_gating(adev, enable);
3363 /* === MGCG + MGLS === */
3364 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3365 }
3366 return 0;
3367}
3368
3369static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3370 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3371 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3372};
3373
3374static int gfx_v9_0_set_powergating_state(void *handle,
3375 enum amd_powergating_state state)
3376{
3377 return 0;
3378}
3379
3380static int gfx_v9_0_set_clockgating_state(void *handle,
3381 enum amd_clockgating_state state)
3382{
3383 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3384
fb82afab
XY		 3385 if (amdgpu_sriov_vf(adev))
3386 return 0;
3387
b1023571
KW		 3388 switch (adev->asic_type) {
3389 case CHIP_VEGA10:
a4dc61f5 3390 case CHIP_RAVEN:
b1023571
KW		 3391 gfx_v9_0_update_gfx_clock_gating(adev,
3392 state == AMD_CG_STATE_GATE ? true : false);
3393 break;
3394 default:
3395 break;
3396 }
3397 return 0;
3398}
3399
12ad27fa
HR		 3400static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3401{
3402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3403 int data;
3404
3405 if (amdgpu_sriov_vf(adev))
3406 *flags = 0;
3407
3408 /* AMD_CG_SUPPORT_GFX_MGCG */
5e78835a 3409 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
12ad27fa
HR		 3410 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3411 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3412
3413 /* AMD_CG_SUPPORT_GFX_CGCG */
5e78835a 3414 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
12ad27fa
HR		 3415 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3416 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3417
3418 /* AMD_CG_SUPPORT_GFX_CGLS */
3419 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3420 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3421
3422 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5e78835a 3423 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
12ad27fa
HR		 3424 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3425 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3426
3427 /* AMD_CG_SUPPORT_GFX_CP_LS */
5e78835a 3428 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
12ad27fa
HR		 3429 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3430 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3431
3432 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5e78835a 3433 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
12ad27fa
HR		 3434 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3435 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3436
3437 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3438 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3439 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3440}
3441
b1023571
KW		 3442static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3443{
3444 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3445}
3446
3447static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3448{
3449 struct amdgpu_device *adev = ring->adev;
3450 u64 wptr;
3451
3452 /* XXX check if swapping is necessary on BE */
3453 if (ring->use_doorbell) {
3454 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3455 } else {
5e78835a
TSD		 3456 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3457 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
b1023571
KW		 3458 }
3459
3460 return wptr;
3461}
3462
3463static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3464{
3465 struct amdgpu_device *adev = ring->adev;
3466
3467 if (ring->use_doorbell) {
3468 /* XXX check if swapping is necessary on BE */
3469 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3470 WDOORBELL64(ring->doorbell_index, ring->wptr);
3471 } else {
5e78835a
TSD		 3472 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3473 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
b1023571
KW		 3474 }
3475}
3476
3477static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3478{
3479 u32 ref_and_mask, reg_mem_engine;
3480 struct nbio_hdp_flush_reg *nbio_hf_reg;
3481
3482 if (ring->adev->asic_type == CHIP_VEGA10)
3483 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3484
3485 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3486 switch (ring->me) {
3487 case 1:
3488 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3489 break;
3490 case 2:
3491 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3492 break;
3493 default:
3494 return;
3495 }
3496 reg_mem_engine = 0;
3497 } else {
3498 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3499 reg_mem_engine = 1; /* pfp */
3500 }
3501
3502 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3503 nbio_hf_reg->hdp_flush_req_offset,
3504 nbio_hf_reg->hdp_flush_done_offset,
3505 ref_and_mask, ref_and_mask, 0x20);
3506}
3507
3508static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3509{
3510 gfx_v9_0_write_data_to_reg(ring, 0, true,
3511 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3512}
3513
3514static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3515 struct amdgpu_ib *ib,
3516 unsigned vm_id, bool ctx_switch)
3517{
eaa05d52 3518 u32 header, control = 0;
b1023571 3519
eaa05d52
ML		 3520 if (ib->flags & AMDGPU_IB_FLAG_CE)
3521 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3522 else
3523 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
b1023571 3524
eaa05d52 3525 control |= ib->length_dw | (vm_id << 24);
b1023571 3526
635e7132 3527 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
eaa05d52 3528 control |= INDIRECT_BUFFER_PRE_ENB(1);
9ccd52eb 3529
635e7132
ML		 3530 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3531 gfx_v9_0_ring_emit_de_meta(ring);
3532 }
3533
eaa05d52
ML		 3534 amdgpu_ring_write(ring, header);
3535BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3536 amdgpu_ring_write(ring,
b1023571 3537#ifdef __BIG_ENDIAN
eaa05d52 3538 (2 << 0) |
b1023571 3539#endif
eaa05d52
ML		 3540 lower_32_bits(ib->gpu_addr));
3541 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3542 amdgpu_ring_write(ring, control);
b1023571
KW		 3543}
3544
b1023571
KW		 3545static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3546 struct amdgpu_ib *ib,
3547 unsigned vm_id, bool ctx_switch)
3548{
3549 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3550
3551 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3552 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3553 amdgpu_ring_write(ring,
3554#ifdef __BIG_ENDIAN
3555 (2 << 0) |
3556#endif
3557 lower_32_bits(ib->gpu_addr));
3558 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3559 amdgpu_ring_write(ring, control);
3560}
3561
3562static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3563 u64 seq, unsigned flags)
3564{
3565 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3566 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3567
3568 /* RELEASE_MEM - flush caches, send int */
3569 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3570 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3571 EOP_TC_ACTION_EN |
3572 EOP_TC_WB_ACTION_EN |
3573 EOP_TC_MD_ACTION_EN |
3574 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3575 EVENT_INDEX(5)));
3576 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3577
3578 /*
3579 * the address should be Qword aligned if 64bit write, Dword
3580 * aligned if only send 32bit data low (discard data high)
3581 */
3582 if (write64bit)
3583 BUG_ON(addr & 0x7);
3584 else
3585 BUG_ON(addr & 0x3);
3586 amdgpu_ring_write(ring, lower_32_bits(addr));
3587 amdgpu_ring_write(ring, upper_32_bits(addr));
3588 amdgpu_ring_write(ring, lower_32_bits(seq));
3589 amdgpu_ring_write(ring, upper_32_bits(seq));
3590 amdgpu_ring_write(ring, 0);
3591}
3592
3593static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3594{
3595 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3596 uint32_t seq = ring->fence_drv.sync_seq;
3597 uint64_t addr = ring->fence_drv.gpu_addr;
3598
3599 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3600 lower_32_bits(addr), upper_32_bits(addr),
3601 seq, 0xffffffff, 4);
3602}
3603
3604static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3605 unsigned vm_id, uint64_t pd_addr)
3606{
2e819849 3607 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
b1023571 3608 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 3609 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 3610 unsigned eng = ring->vm_inv_eng;
b1023571
KW		 3611
3612 pd_addr = pd_addr | 0x1; /* valid bit */
3613 /* now only use physical base address of PDE and valid */
3614 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
3615
2e819849
CK		 3616 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3617 hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3618 lower_32_bits(pd_addr));
b1023571 3619
2e819849
CK		 3620 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3621 hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3622 upper_32_bits(pd_addr));
b1023571 3623
2e819849
CK		 3624 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3625 hub->vm_inv_eng0_req + eng, req);
b1023571 3626
2e819849
CK		 3627 /* wait for the invalidate to complete */
3628 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3629 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
b1023571
KW		 3630
3631 /* compute doesn't have PFP */
3632 if (usepfp) {
3633 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3634 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3635 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3636 }
3637}
3638
3639static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3640{
3641 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3642}
3643
3644static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3645{
3646 u64 wptr;
3647
3648 /* XXX check if swapping is necessary on BE */
3649 if (ring->use_doorbell)
3650 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3651 else
3652 BUG();
3653 return wptr;
3654}
3655
3656static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3657{
3658 struct amdgpu_device *adev = ring->adev;
3659
3660 /* XXX check if swapping is necessary on BE */
3661 if (ring->use_doorbell) {
3662 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3663 WDOORBELL64(ring->doorbell_index, ring->wptr);
3664 } else{
3665 BUG(); /* only DOORBELL method supported on gfx9 now */
3666 }
3667}
3668
aa6faa44
XY		 3669static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3670 u64 seq, unsigned int flags)
3671{
3672 /* we only allocate 32bit for each seq wb address */
3673 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3674
3675 /* write fence seq to the "addr" */
3676 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3677 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3678 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3679 amdgpu_ring_write(ring, lower_32_bits(addr));
3680 amdgpu_ring_write(ring, upper_32_bits(addr));
3681 amdgpu_ring_write(ring, lower_32_bits(seq));
3682
3683 if (flags & AMDGPU_FENCE_FLAG_INT) {
3684 /* set register to trigger INT */
3685 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3686 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3687 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3688 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3689 amdgpu_ring_write(ring, 0);
3690 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3691 }
3692}
3693
b1023571
KW		 3694static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3695{
3696 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3697 amdgpu_ring_write(ring, 0);
3698}
3699
cca02cd3
XY		 3700static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3701{
3702 static struct v9_ce_ib_state ce_payload = {0};
3703 uint64_t csa_addr;
3704 int cnt;
3705
3706 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3707 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3708
3709 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3710 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3711 WRITE_DATA_DST_SEL(8) |
3712 WR_CONFIRM) |
3713 WRITE_DATA_CACHE_POLICY(0));
3714 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3715 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3716 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3717}
3718
3719static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3720{
3721 static struct v9_de_ib_state de_payload = {0};
3722 uint64_t csa_addr, gds_addr;
3723 int cnt;
3724
3725 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3726 gds_addr = csa_addr + 4096;
3727 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3728 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3729
3730 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3731 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3732 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3733 WRITE_DATA_DST_SEL(8) |
3734 WR_CONFIRM) |
3735 WRITE_DATA_CACHE_POLICY(0));
3736 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3737 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3738 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3739}
3740
b1023571
KW		 3741static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3742{
3743 uint32_t dw2 = 0;
3744
cca02cd3
XY		 3745 if (amdgpu_sriov_vf(ring->adev))
3746 gfx_v9_0_ring_emit_ce_meta(ring);
3747
b1023571
KW		 3748 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3749 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3750 /* set load_global_config & load_global_uconfig */
3751 dw2 |= 0x8001;
3752 /* set load_cs_sh_regs */
3753 dw2 |= 0x01000000;
3754 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3755 dw2 |= 0x10002;
3756
3757 /* set load_ce_ram if preamble presented */
3758 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3759 dw2 |= 0x10000000;
3760 } else {
3761 /* still load_ce_ram if this is the first time preamble presented
3762 * although there is no context switch happens.
3763 */
3764 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3765 dw2 |= 0x10000000;
3766 }
3767
3768 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3769 amdgpu_ring_write(ring, dw2);
3770 amdgpu_ring_write(ring, 0);
3771}
3772
9a5e02b5
ML		 3773static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3774{
3775 unsigned ret;
3776 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3777 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3778 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3779 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3780 ret = ring->wptr & ring->buf_mask;
3781 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3782 return ret;
3783}
3784
3785static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3786{
3787 unsigned cur;
3788 BUG_ON(offset > ring->buf_mask);
3789 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3790
3791 cur = (ring->wptr & ring->buf_mask) - 1;
3792 if (likely(cur > offset))
3793 ring->ring[offset] = cur - offset;
3794 else
3795 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3796}
3797
3b4d68e9
ML		 3798static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
3799{
3800 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
3801 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
3802}
3803
aa6faa44
XY		 3804static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3805{
3806 struct amdgpu_device *adev = ring->adev;
3807
3808 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3809 amdgpu_ring_write(ring, 0 | /* src: register*/
3810 (5 << 8) | /* dst: memory */
3811 (1 << 20)); /* write confirm */
3812 amdgpu_ring_write(ring, reg);
3813 amdgpu_ring_write(ring, 0);
3814 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3815 adev->virt.reg_val_offs * 4));
3816 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3817 adev->virt.reg_val_offs * 4));
3818}
3819
3820static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3821 uint32_t val)
3822{
3823 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3824 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3825 amdgpu_ring_write(ring, reg);
3826 amdgpu_ring_write(ring, 0);
3827 amdgpu_ring_write(ring, val);
3828}
3829
b1023571
KW		 3830static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3831 enum amdgpu_interrupt_state state)
3832{
b1023571
KW		 3833 switch (state) {
3834 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3835 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3836 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3837 TIME_STAMP_INT_ENABLE,
3838 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3839 break;
3840 default:
3841 break;
3842 }
3843}
3844
3845static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3846 int me, int pipe,
3847 enum amdgpu_interrupt_state state)
3848{
3849 u32 mec_int_cntl, mec_int_cntl_reg;
3850
3851 /*
3852 * amdgpu controls only pipe 0 of MEC1. That's why this function only
3853 * handles the setting of interrupts for this specific pipe. All other
3854 * pipes' interrupts are set by amdkfd.
3855 */
3856
3857 if (me == 1) {
3858 switch (pipe) {
3859 case 0:
3860 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3861 break;
3862 default:
3863 DRM_DEBUG("invalid pipe %d\n", pipe);
3864 return;
3865 }
3866 } else {
3867 DRM_DEBUG("invalid me %d\n", me);
3868 return;
3869 }
3870
3871 switch (state) {
3872 case AMDGPU_IRQ_STATE_DISABLE:
3873 mec_int_cntl = RREG32(mec_int_cntl_reg);
3874 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3875 TIME_STAMP_INT_ENABLE, 0);
3876 WREG32(mec_int_cntl_reg, mec_int_cntl);
3877 break;
3878 case AMDGPU_IRQ_STATE_ENABLE:
3879 mec_int_cntl = RREG32(mec_int_cntl_reg);
3880 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3881 TIME_STAMP_INT_ENABLE, 1);
3882 WREG32(mec_int_cntl_reg, mec_int_cntl);
3883 break;
3884 default:
3885 break;
3886 }
3887}
3888
3889static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3890 struct amdgpu_irq_src *source,
3891 unsigned type,
3892 enum amdgpu_interrupt_state state)
3893{
b1023571
KW		 3894 switch (state) {
3895 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3896 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3897 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3898 PRIV_REG_INT_ENABLE,
3899 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3900 break;
3901 default:
3902 break;
3903 }
3904
3905 return 0;
3906}
3907
3908static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3909 struct amdgpu_irq_src *source,
3910 unsigned type,
3911 enum amdgpu_interrupt_state state)
3912{
b1023571
KW		 3913 switch (state) {
3914 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3915 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 3916 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3917 PRIV_INSTR_INT_ENABLE,
3918 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3919 default:
3920 break;
3921 }
3922
3923 return 0;
3924}
3925
3926static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3927 struct amdgpu_irq_src *src,
3928 unsigned type,
3929 enum amdgpu_interrupt_state state)
3930{
3931 switch (type) {
3932 case AMDGPU_CP_IRQ_GFX_EOP:
3933 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3934 break;
3935 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3936 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3937 break;
3938 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3939 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3940 break;
3941 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3942 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3943 break;
3944 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3945 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3946 break;
3947 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3948 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3949 break;
3950 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3951 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3952 break;
3953 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3954 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3955 break;
3956 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3957 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3958 break;
3959 default:
3960 break;
3961 }
3962 return 0;
3963}
3964
3965static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
3966 struct amdgpu_irq_src *source,
3967 struct amdgpu_iv_entry *entry)
3968{
3969 int i;
3970 u8 me_id, pipe_id, queue_id;
3971 struct amdgpu_ring *ring;
3972
3973 DRM_DEBUG("IH: CP EOP\n");
3974 me_id = (entry->ring_id & 0x0c) >> 2;
3975 pipe_id = (entry->ring_id & 0x03) >> 0;
3976 queue_id = (entry->ring_id & 0x70) >> 4;
3977
3978 switch (me_id) {
3979 case 0:
3980 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3981 break;
3982 case 1:
3983 case 2:
3984 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3985 ring = &adev->gfx.compute_ring[i];
3986 /* Per-queue interrupt is supported for MEC starting from VI.
3987 * The interrupt can only be enabled/disabled per pipe instead of per queue.
3988 */
3989 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
3990 amdgpu_fence_process(ring);
3991 }
3992 break;
3993 }
3994 return 0;
3995}
3996
3997static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
3998 struct amdgpu_irq_src *source,
3999 struct amdgpu_iv_entry *entry)
4000{
4001 DRM_ERROR("Illegal register access in command stream\n");
4002 schedule_work(&adev->reset_work);
4003 return 0;
4004}
4005
4006static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4007 struct amdgpu_irq_src *source,
4008 struct amdgpu_iv_entry *entry)
4009{
4010 DRM_ERROR("Illegal instruction in command stream\n");
4011 schedule_work(&adev->reset_work);
4012 return 0;
4013}
4014
97031e25
XY		 4015static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4016 struct amdgpu_irq_src *src,
4017 unsigned int type,
4018 enum amdgpu_interrupt_state state)
4019{
4020 uint32_t tmp, target;
1c4ecf48 4021 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4022
4023 if (ring->me == 1)
4024 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4025 else
4026 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4027 target += ring->pipe;
4028
4029 switch (type) {
4030 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4031 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5e78835a 4032 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4033 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4034 GENERIC2_INT_ENABLE, 0);
5e78835a 4035 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4036
4037 tmp = RREG32(target);
4038 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4039 GENERIC2_INT_ENABLE, 0);
4040 WREG32(target, tmp);
4041 } else {
5e78835a 4042 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
97031e25
XY		 4043 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4044 GENERIC2_INT_ENABLE, 1);
5e78835a 4045 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
97031e25
XY		 4046
4047 tmp = RREG32(target);
4048 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4049 GENERIC2_INT_ENABLE, 1);
4050 WREG32(target, tmp);
4051 }
4052 break;
4053 default:
4054 BUG(); /* kiq only support GENERIC2_INT now */
4055 break;
4056 }
4057 return 0;
4058}
4059
4060static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4061 struct amdgpu_irq_src *source,
4062 struct amdgpu_iv_entry *entry)
4063{
4064 u8 me_id, pipe_id, queue_id;
1c4ecf48 4065 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
97031e25
XY		 4066
4067 me_id = (entry->ring_id & 0x0c) >> 2;
4068 pipe_id = (entry->ring_id & 0x03) >> 0;
4069 queue_id = (entry->ring_id & 0x70) >> 4;
4070 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4071 me_id, pipe_id, queue_id);
4072
4073 amdgpu_fence_process(ring);
4074 return 0;
4075}
4076
b1023571
KW		 4077const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4078 .name = "gfx_v9_0",
4079 .early_init = gfx_v9_0_early_init,
4080 .late_init = gfx_v9_0_late_init,
4081 .sw_init = gfx_v9_0_sw_init,
4082 .sw_fini = gfx_v9_0_sw_fini,
4083 .hw_init = gfx_v9_0_hw_init,
4084 .hw_fini = gfx_v9_0_hw_fini,
4085 .suspend = gfx_v9_0_suspend,
4086 .resume = gfx_v9_0_resume,
4087 .is_idle = gfx_v9_0_is_idle,
4088 .wait_for_idle = gfx_v9_0_wait_for_idle,
4089 .soft_reset = gfx_v9_0_soft_reset,
4090 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4091 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 4092 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 4093};
4094
4095static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4096 .type = AMDGPU_RING_TYPE_GFX,
4097 .align_mask = 0xff,
4098 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4099 .support_64bit_ptrs = true,
0eeb68b3 4100 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4101 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4102 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4103 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 4104 .emit_frame_size = /* totally 242 maximum if 16 IBs */
4105 5 + /* COND_EXEC */
4106 7 + /* PIPELINE_SYNC */
2e819849 4107 24 + /* VM_FLUSH */
e9d672b2
ML		 4108 8 + /* FENCE for VM_FLUSH */
4109 20 + /* GDS switch */
4110 4 + /* double SWITCH_BUFFER,
4111 the first COND_EXEC jump to the place just
4112 prior to this double SWITCH_BUFFER */
4113 5 + /* COND_EXEC */
4114 7 + /* HDP_flush */
4115 4 + /* VGT_flush */
4116 14 + /* CE_META */
4117 31 + /* DE_META */
4118 3 + /* CNTX_CTRL */
4119 5 + /* HDP_INVL */
4120 8 + 8 + /* FENCE x2 */
4121 2, /* SWITCH_BUFFER */
b1023571
KW		 4122 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4123 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4124 .emit_fence = gfx_v9_0_ring_emit_fence,
4125 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4126 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4127 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4128 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4129 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4130 .test_ring = gfx_v9_0_ring_test_ring,
4131 .test_ib = gfx_v9_0_ring_test_ib,
4132 .insert_nop = amdgpu_ring_insert_nop,
4133 .pad_ib = amdgpu_ring_generic_pad_ib,
4134 .emit_switch_buffer = gfx_v9_ring_emit_sb,
4135 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 4136 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4137 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
3b4d68e9 4138 .emit_tmz = gfx_v9_0_ring_emit_tmz,
b1023571
KW		 4139};
4140
4141static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4142 .type = AMDGPU_RING_TYPE_COMPUTE,
4143 .align_mask = 0xff,
4144 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4145 .support_64bit_ptrs = true,
0eeb68b3 4146 .vmhub = AMDGPU_GFXHUB,
b1023571
KW		 4147 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4148 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4149 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4150 .emit_frame_size =
4151 20 + /* gfx_v9_0_ring_emit_gds_switch */
4152 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4153 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4154 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4155 24 + /* gfx_v9_0_ring_emit_vm_flush */
b1023571
KW		 4156 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4157 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4158 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4159 .emit_fence = gfx_v9_0_ring_emit_fence,
4160 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4161 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4162 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4163 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4164 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4165 .test_ring = gfx_v9_0_ring_test_ring,
4166 .test_ib = gfx_v9_0_ring_test_ib,
4167 .insert_nop = amdgpu_ring_insert_nop,
4168 .pad_ib = amdgpu_ring_generic_pad_ib,
4169};
4170
aa6faa44
XY		 4171static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4172 .type = AMDGPU_RING_TYPE_KIQ,
4173 .align_mask = 0xff,
4174 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4175 .support_64bit_ptrs = true,
0eeb68b3 4176 .vmhub = AMDGPU_GFXHUB,
aa6faa44
XY		 4177 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4178 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4179 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4180 .emit_frame_size =
4181 20 + /* gfx_v9_0_ring_emit_gds_switch */
4182 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4183 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4184 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2e819849 4185 24 + /* gfx_v9_0_ring_emit_vm_flush */
aa6faa44
XY		 4186 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4187 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4188 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4189 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
aa6faa44
XY		 4190 .test_ring = gfx_v9_0_ring_test_ring,
4191 .test_ib = gfx_v9_0_ring_test_ib,
4192 .insert_nop = amdgpu_ring_insert_nop,
4193 .pad_ib = amdgpu_ring_generic_pad_ib,
4194 .emit_rreg = gfx_v9_0_ring_emit_rreg,
4195 .emit_wreg = gfx_v9_0_ring_emit_wreg,
4196};
b1023571
KW		 4197
4198static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4199{
4200 int i;
4201
aa6faa44
XY		 4202 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4203
b1023571
KW		 4204 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4205 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4206
4207 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4208 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4209}
4210
97031e25
XY		 4211static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4212 .set = gfx_v9_0_kiq_set_interrupt_state,
4213 .process = gfx_v9_0_kiq_irq,
4214};
4215
b1023571
KW		 4216static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4217 .set = gfx_v9_0_set_eop_interrupt_state,
4218 .process = gfx_v9_0_eop_irq,
4219};
4220
4221static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4222 .set = gfx_v9_0_set_priv_reg_fault_state,
4223 .process = gfx_v9_0_priv_reg_irq,
4224};
4225
4226static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4227 .set = gfx_v9_0_set_priv_inst_fault_state,
4228 .process = gfx_v9_0_priv_inst_irq,
4229};
4230
4231static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4232{
4233 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4234 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4235
4236 adev->gfx.priv_reg_irq.num_types = 1;
4237 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4238
4239 adev->gfx.priv_inst_irq.num_types = 1;
4240 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 4241
4242 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4243 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 4244}
4245
4246static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4247{
4248 switch (adev->asic_type) {
4249 case CHIP_VEGA10:
a4dc61f5 4250 case CHIP_RAVEN:
b1023571
KW		 4251 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4252 break;
4253 default:
4254 break;
4255 }
4256}
4257
4258static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4259{
4260 /* init asci gds info */
5e78835a 4261 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
b1023571
KW		 4262 adev->gds.gws.total_size = 64;
4263 adev->gds.oa.total_size = 16;
4264
4265 if (adev->gds.mem.total_size == 64 * 1024) {
4266 adev->gds.mem.gfx_partition_size = 4096;
4267 adev->gds.mem.cs_partition_size = 4096;
4268
4269 adev->gds.gws.gfx_partition_size = 4;
4270 adev->gds.gws.cs_partition_size = 4;
4271
4272 adev->gds.oa.gfx_partition_size = 4;
4273 adev->gds.oa.cs_partition_size = 1;
4274 } else {
4275 adev->gds.mem.gfx_partition_size = 1024;
4276 adev->gds.mem.cs_partition_size = 1024;
4277
4278 adev->gds.gws.gfx_partition_size = 16;
4279 adev->gds.gws.cs_partition_size = 16;
4280
4281 adev->gds.oa.gfx_partition_size = 4;
4282 adev->gds.oa.cs_partition_size = 4;
4283 }
4284}
4285
4286static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4287{
4288 u32 data, mask;
4289
5e78835a
TSD		 4290 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4291 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
b1023571
KW		 4292
4293 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4294 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4295
4296 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
4297
4298 return (~data) & mask;
4299}
4300
4301static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4302 struct amdgpu_cu_info *cu_info)
4303{
4304 int i, j, k, counter, active_cu_number = 0;
4305 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4306
4307 if (!adev || !cu_info)
4308 return -EINVAL;
4309
4310 memset(cu_info, 0, sizeof(*cu_info));
4311
4312 mutex_lock(&adev->grbm_idx_mutex);
4313 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4314 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4315 mask = 1;
4316 ao_bitmap = 0;
4317 counter = 0;
4318 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4319 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4320 cu_info->bitmap[i][j] = bitmap;
4321
fe723cd3 4322 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
b1023571 4323 if (bitmap & mask) {
fe723cd3 4324 if (counter < adev->gfx.config.max_cu_per_sh)
b1023571
KW		 4325 ao_bitmap |= mask;
4326 counter ++;
4327 }
4328 mask <<= 1;
4329 }
4330 active_cu_number += counter;
4331 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4332 }
4333 }
4334 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4335 mutex_unlock(&adev->grbm_idx_mutex);
4336
4337 cu_info->number = active_cu_number;
4338 cu_info->ao_cu_mask = ao_cu_mask;
4339
4340 return 0;
4341}
4342
4343static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
4344{
4345 int r, j;
4346 u32 tmp;
4347 bool use_doorbell = true;
4348 u64 hqd_gpu_addr;
4349 u64 mqd_gpu_addr;
4350 u64 eop_gpu_addr;
4351 u64 wb_gpu_addr;
4352 u32 *buf;
4353 struct v9_mqd *mqd;
4354 struct amdgpu_device *adev;
4355
4356 adev = ring->adev;
4357 if (ring->mqd_obj == NULL) {
4358 r = amdgpu_bo_create(adev,
4359 sizeof(struct v9_mqd),
4360 PAGE_SIZE,true,
4361 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
4362 NULL, &ring->mqd_obj);
4363 if (r) {
4364 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
4365 return r;
4366 }
4367 }
4368
4369 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4370 if (unlikely(r != 0)) {
4371 gfx_v9_0_cp_compute_fini(adev);
4372 return r;
4373 }
4374
4375 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
4376 &mqd_gpu_addr);
4377 if (r) {
4378 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
4379 gfx_v9_0_cp_compute_fini(adev);
4380 return r;
4381 }
4382 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
4383 if (r) {
4384 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
4385 gfx_v9_0_cp_compute_fini(adev);
4386 return r;
4387 }
4388
4389 /* init the mqd struct */
4390 memset(buf, 0, sizeof(struct v9_mqd));
4391
4392 mqd = (struct v9_mqd *)buf;
4393 mqd->header = 0xC0310800;
4394 mqd->compute_pipelinestat_enable = 0x00000001;
4395 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4396 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4397 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4398 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4399 mqd->compute_misc_reserved = 0x00000003;
4400 mutex_lock(&adev->srbm_mutex);
4401 soc15_grbm_select(adev, ring->me,
4402 ring->pipe,
4403 ring->queue, 0);
4404 /* disable wptr polling */
efe53d8a 4405 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
b1023571
KW		 4406
4407 /* write the EOP addr */
4408 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
4409 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
4410 eop_gpu_addr >>= 8;
4411
5e78835a
TSD		 4412 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
4413 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
b1023571
KW		 4414 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
4415 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
4416
4417 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
5e78835a 4418 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
b1023571
KW		 4419 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4420 (order_base_2(MEC_HPD_SIZE / 4) - 1));
5e78835a 4421 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
b1023571
KW		 4422
4423 /* enable doorbell? */
5e78835a 4424 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
b1023571
KW		 4425 if (use_doorbell)
4426 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4427 else
4428 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
4429
5e78835a 4430 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
b1023571
KW		 4431 mqd->cp_hqd_pq_doorbell_control = tmp;
4432
4433 /* disable the queue if it's active */
4434 ring->wptr = 0;
4435 mqd->cp_hqd_dequeue_request = 0;
4436 mqd->cp_hqd_pq_rptr = 0;
4437 mqd->cp_hqd_pq_wptr_lo = 0;
4438 mqd->cp_hqd_pq_wptr_hi = 0;
5e78835a
TSD		 4439 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
4440 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
b1023571 4441 for (j = 0; j < adev->usec_timeout; j++) {
5e78835a 4442 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
b1023571
KW		 4443 break;
4444 udelay(1);
4445 }
5e78835a
TSD		 4446 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
4447 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
4448 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
4449 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
b1023571
KW		 4450 }
4451
4452 /* set the pointer to the MQD */
4453 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
4454 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
5e78835a
TSD		 4455 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
4456 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
b1023571
KW		 4457
4458 /* set MQD vmid to 0 */
5e78835a 4459 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
b1023571 4460 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
5e78835a 4461 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
b1023571
KW		 4462 mqd->cp_mqd_control = tmp;
4463
4464 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4465 hqd_gpu_addr = ring->gpu_addr >> 8;
4466 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4467 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
5e78835a
TSD		 4468 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
4469 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
b1023571
KW		 4470
4471 /* set up the HQD, this is similar to CP_RB0_CNTL */
5e78835a 4472 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
b1023571
KW		 4473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4474 (order_base_2(ring->ring_size / 4) - 1));
4475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4476 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4477#ifdef __BIG_ENDIAN
4478 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4479#endif
4480 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4482 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4483 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
5e78835a 4484 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
b1023571
KW		 4485 mqd->cp_hqd_pq_control = tmp;
4486
4487 /* set the wb address wether it's enabled or not */
4488 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4489 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4490 mqd->cp_hqd_pq_rptr_report_addr_hi =
4491 upper_32_bits(wb_gpu_addr) & 0xffff;
5e78835a 4492 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
b1023571 4493 mqd->cp_hqd_pq_rptr_report_addr_lo);
5e78835a 4494 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
b1023571
KW		 4495 mqd->cp_hqd_pq_rptr_report_addr_hi);
4496
4497 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4498 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4499 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4500 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
5e78835a 4501 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
b1023571 4502 mqd->cp_hqd_pq_wptr_poll_addr_lo);
5e78835a 4503 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
b1023571
KW		 4504 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4505
4506 /* enable the doorbell if requested */
4507 if (use_doorbell) {
5e78835a 4508 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
b1023571 4509 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
5e78835a 4510 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
b1023571 4511 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
5e78835a 4512 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
b1023571
KW		 4513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4514 DOORBELL_OFFSET, ring->doorbell_index);
4515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
4517 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
4518 mqd->cp_hqd_pq_doorbell_control = tmp;
4519
4520 } else {
4521 mqd->cp_hqd_pq_doorbell_control = 0;
4522 }
5e78835a 4523 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
b1023571
KW		 4524 mqd->cp_hqd_pq_doorbell_control);
4525
4526 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5e78835a
TSD		 4527 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
4528 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
b1023571
KW		 4529
4530 /* set the vmid for the queue */
4531 mqd->cp_hqd_vmid = 0;
5e78835a 4532 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
b1023571 4533
5e78835a 4534 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
b1023571 4535 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
5e78835a 4536 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
b1023571
KW		 4537 mqd->cp_hqd_persistent_state = tmp;
4538
4539 /* activate the queue */
4540 mqd->cp_hqd_active = 1;
5e78835a 4541 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
b1023571
KW		 4542
4543 soc15_grbm_select(adev, 0, 0, 0, 0);
4544 mutex_unlock(&adev->srbm_mutex);
4545
4546 amdgpu_bo_kunmap(ring->mqd_obj);
4547 amdgpu_bo_unreserve(ring->mqd_obj);
4548
efe53d8a
TSD		 4549 if (use_doorbell)
4550 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
b1023571
KW		 4551
4552 return 0;
4553}
4554
4555const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4556{
4557 .type = AMD_IP_BLOCK_TYPE_GFX,
4558 .major = 9,
4559 .minor = 0,
4560 .rev = 0,
4561 .funcs = &gfx_v9_0_ip_funcs,
4562};
Linux 6.x block layer and io_uring tree(s)