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drm/amdgpu: implement GFX 9.0 support (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
42#define GFX9_NUM_SE 4
43#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
44
45MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
46MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
47MODULE_FIRMWARE("amdgpu/vega10_me.bin");
48MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
49MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
50MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
51
52static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
53{
54 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
55 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
56 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
57 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
58 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
59 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
60 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
61 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
62 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
63 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
64 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
65 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
66 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
67 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
68 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
69 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
70 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
72 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
73 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
74 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
76 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
77 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
78 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
80 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
81 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
82 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
84 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
85 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
86};
87
88static const u32 golden_settings_gc_9_0[] =
89{
90 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
91 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
93 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
94 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
95 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
96 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
97 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
98 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
99};
100
101static const u32 golden_settings_gc_9_0_vg10[] =
102{
103 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
104 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
105 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
106 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
108 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
109 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
110 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
111};
112
113#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
114
115static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
116static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
117static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
118static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
119static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
120 struct amdgpu_cu_info *cu_info);
121static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
122static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
123
124static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
125{
126 switch (adev->asic_type) {
127 case CHIP_VEGA10:
128 amdgpu_program_register_sequence(adev,
129 golden_settings_gc_9_0,
130 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
131 amdgpu_program_register_sequence(adev,
132 golden_settings_gc_9_0_vg10,
133 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
134 break;
135 default:
136 break;
137 }
138}
139
140static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
141{
142 adev->gfx.scratch.num_reg = 7;
143 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
144 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
145}
146
147static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
148 bool wc, uint32_t reg, uint32_t val)
149{
150 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
151 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
152 WRITE_DATA_DST_SEL(0) |
153 (wc ? WR_CONFIRM : 0));
154 amdgpu_ring_write(ring, reg);
155 amdgpu_ring_write(ring, 0);
156 amdgpu_ring_write(ring, val);
157}
158
159static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
160 int mem_space, int opt, uint32_t addr0,
161 uint32_t addr1, uint32_t ref, uint32_t mask,
162 uint32_t inv)
163{
164 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
165 amdgpu_ring_write(ring,
166 /* memory (1) or register (0) */
167 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
168 WAIT_REG_MEM_OPERATION(opt) | /* wait */
169 WAIT_REG_MEM_FUNCTION(3) | /* equal */
170 WAIT_REG_MEM_ENGINE(eng_sel)));
171
172 if (mem_space)
173 BUG_ON(addr0 & 0x3); /* Dword align */
174 amdgpu_ring_write(ring, addr0);
175 amdgpu_ring_write(ring, addr1);
176 amdgpu_ring_write(ring, ref);
177 amdgpu_ring_write(ring, mask);
178 amdgpu_ring_write(ring, inv); /* poll interval */
179}
180
181static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
182{
183 struct amdgpu_device *adev = ring->adev;
184 uint32_t scratch;
185 uint32_t tmp = 0;
186 unsigned i;
187 int r;
188
189 r = amdgpu_gfx_scratch_get(adev, &scratch);
190 if (r) {
191 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
192 return r;
193 }
194 WREG32(scratch, 0xCAFEDEAD);
195 r = amdgpu_ring_alloc(ring, 3);
196 if (r) {
197 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
198 ring->idx, r);
199 amdgpu_gfx_scratch_free(adev, scratch);
200 return r;
201 }
202 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
203 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
204 amdgpu_ring_write(ring, 0xDEADBEEF);
205 amdgpu_ring_commit(ring);
206
207 for (i = 0; i < adev->usec_timeout; i++) {
208 tmp = RREG32(scratch);
209 if (tmp == 0xDEADBEEF)
210 break;
211 DRM_UDELAY(1);
212 }
213 if (i < adev->usec_timeout) {
214 DRM_INFO("ring test on %d succeeded in %d usecs\n",
215 ring->idx, i);
216 } else {
217 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
218 ring->idx, scratch, tmp);
219 r = -EINVAL;
220 }
221 amdgpu_gfx_scratch_free(adev, scratch);
222 return r;
223}
224
225static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
226{
227 struct amdgpu_device *adev = ring->adev;
228 struct amdgpu_ib ib;
229 struct dma_fence *f = NULL;
230 uint32_t scratch;
231 uint32_t tmp = 0;
232 long r;
233
234 r = amdgpu_gfx_scratch_get(adev, &scratch);
235 if (r) {
236 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
237 return r;
238 }
239 WREG32(scratch, 0xCAFEDEAD);
240 memset(&ib, 0, sizeof(ib));
241 r = amdgpu_ib_get(adev, NULL, 256, &ib);
242 if (r) {
243 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
244 goto err1;
245 }
246 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
247 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
248 ib.ptr[2] = 0xDEADBEEF;
249 ib.length_dw = 3;
250
251 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
252 if (r)
253 goto err2;
254
255 r = dma_fence_wait_timeout(f, false, timeout);
256 if (r == 0) {
257 DRM_ERROR("amdgpu: IB test timed out.\n");
258 r = -ETIMEDOUT;
259 goto err2;
260 } else if (r < 0) {
261 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
262 goto err2;
263 }
264 tmp = RREG32(scratch);
265 if (tmp == 0xDEADBEEF) {
266 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
267 r = 0;
268 } else {
269 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
270 scratch, tmp);
271 r = -EINVAL;
272 }
273err2:
274 amdgpu_ib_free(adev, &ib, NULL);
275 dma_fence_put(f);
276err1:
277 amdgpu_gfx_scratch_free(adev, scratch);
278 return r;
279}
280
281static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
282{
283 const char *chip_name;
284 char fw_name[30];
285 int err;
286 struct amdgpu_firmware_info *info = NULL;
287 const struct common_firmware_header *header = NULL;
288 const struct gfx_firmware_header_v1_0 *cp_hdr;
289
290 DRM_DEBUG("\n");
291
292 switch (adev->asic_type) {
293 case CHIP_VEGA10:
294 chip_name = "vega10";
295 break;
296 default:
297 BUG();
298 }
299
300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
301 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
302 if (err)
303 goto out;
304 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
305 if (err)
306 goto out;
307 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
308 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
309 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
310
311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
312 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
313 if (err)
314 goto out;
315 err = amdgpu_ucode_validate(adev->gfx.me_fw);
316 if (err)
317 goto out;
318 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
319 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
320 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
321
322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
323 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
324 if (err)
325 goto out;
326 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
327 if (err)
328 goto out;
329 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
330 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
331 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
332
333 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
334 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
335 if (err)
336 goto out;
337 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
338 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
339 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
340 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
341
342 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
343 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
344 if (err)
345 goto out;
346 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
347 if (err)
348 goto out;
349 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
350 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
351 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
352
353
354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
355 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
356 if (!err) {
357 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
358 if (err)
359 goto out;
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
361 adev->gfx.mec2_fw->data;
362 adev->gfx.mec2_fw_version =
363 le32_to_cpu(cp_hdr->header.ucode_version);
364 adev->gfx.mec2_feature_version =
365 le32_to_cpu(cp_hdr->ucode_feature_version);
366 } else {
367 err = 0;
368 adev->gfx.mec2_fw = NULL;
369 }
370
371 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
372 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
373 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
374 info->fw = adev->gfx.pfp_fw;
375 header = (const struct common_firmware_header *)info->fw->data;
376 adev->firmware.fw_size +=
377 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
378
379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
380 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
381 info->fw = adev->gfx.me_fw;
382 header = (const struct common_firmware_header *)info->fw->data;
383 adev->firmware.fw_size +=
384 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
385
386 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
387 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
388 info->fw = adev->gfx.ce_fw;
389 header = (const struct common_firmware_header *)info->fw->data;
390 adev->firmware.fw_size +=
391 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
392
393 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
394 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
395 info->fw = adev->gfx.rlc_fw;
396 header = (const struct common_firmware_header *)info->fw->data;
397 adev->firmware.fw_size +=
398 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
399
400 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
401 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
402 info->fw = adev->gfx.mec_fw;
403 header = (const struct common_firmware_header *)info->fw->data;
404 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
405 adev->firmware.fw_size +=
406 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
407
408 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
409 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
410 info->fw = adev->gfx.mec_fw;
411 adev->firmware.fw_size +=
412 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
413
414 if (adev->gfx.mec2_fw) {
415 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
416 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
417 info->fw = adev->gfx.mec2_fw;
418 header = (const struct common_firmware_header *)info->fw->data;
419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
420 adev->firmware.fw_size +=
421 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
422 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
423 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
424 info->fw = adev->gfx.mec2_fw;
425 adev->firmware.fw_size +=
426 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
427 }
428
429 }
430
431out:
432 if (err) {
433 dev_err(adev->dev,
434 "gfx9: Failed to load firmware \"%s\"\n",
435 fw_name);
436 release_firmware(adev->gfx.pfp_fw);
437 adev->gfx.pfp_fw = NULL;
438 release_firmware(adev->gfx.me_fw);
439 adev->gfx.me_fw = NULL;
440 release_firmware(adev->gfx.ce_fw);
441 adev->gfx.ce_fw = NULL;
442 release_firmware(adev->gfx.rlc_fw);
443 adev->gfx.rlc_fw = NULL;
444 release_firmware(adev->gfx.mec_fw);
445 adev->gfx.mec_fw = NULL;
446 release_firmware(adev->gfx.mec2_fw);
447 adev->gfx.mec2_fw = NULL;
448 }
449 return err;
450}
451
452static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
453{
454 int r;
455
456 if (adev->gfx.mec.hpd_eop_obj) {
457 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
458 if (unlikely(r != 0))
459 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
460 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
461 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
462
463 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
464 adev->gfx.mec.hpd_eop_obj = NULL;
465 }
466 if (adev->gfx.mec.mec_fw_obj) {
467 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
468 if (unlikely(r != 0))
469 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
470 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
472
473 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
474 adev->gfx.mec.mec_fw_obj = NULL;
475 }
476}
477
478#define MEC_HPD_SIZE 2048
479
480static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
481{
482 int r;
483 u32 *hpd;
484 const __le32 *fw_data;
485 unsigned fw_size;
486 u32 *fw;
487
488 const struct gfx_firmware_header_v1_0 *mec_hdr;
489
490 /*
491 * we assign only 1 pipe because all other pipes will
492 * be handled by KFD
493 */
494 adev->gfx.mec.num_mec = 1;
495 adev->gfx.mec.num_pipe = 1;
496 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
497
498 if (adev->gfx.mec.hpd_eop_obj == NULL) {
499 r = amdgpu_bo_create(adev,
500 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
501 PAGE_SIZE, true,
502 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
503 &adev->gfx.mec.hpd_eop_obj);
504 if (r) {
505 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
506 return r;
507 }
508 }
509
510 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
511 if (unlikely(r != 0)) {
512 gfx_v9_0_mec_fini(adev);
513 return r;
514 }
515 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
516 &adev->gfx.mec.hpd_eop_gpu_addr);
517 if (r) {
518 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
519 gfx_v9_0_mec_fini(adev);
520 return r;
521 }
522 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
523 if (r) {
524 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
525 gfx_v9_0_mec_fini(adev);
526 return r;
527 }
528
529 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
530
531 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
532 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
533
534 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
535
536 fw_data = (const __le32 *)
537 (adev->gfx.mec_fw->data +
538 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
539 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
540
541 if (adev->gfx.mec.mec_fw_obj == NULL) {
542 r = amdgpu_bo_create(adev,
543 mec_hdr->header.ucode_size_bytes,
544 PAGE_SIZE, true,
545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
546 &adev->gfx.mec.mec_fw_obj);
547 if (r) {
548 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
549 return r;
550 }
551 }
552
553 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
554 if (unlikely(r != 0)) {
555 gfx_v9_0_mec_fini(adev);
556 return r;
557 }
558 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
559 &adev->gfx.mec.mec_fw_gpu_addr);
560 if (r) {
561 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
562 gfx_v9_0_mec_fini(adev);
563 return r;
564 }
565 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
566 if (r) {
567 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
568 gfx_v9_0_mec_fini(adev);
569 return r;
570 }
571 memcpy(fw, fw_data, fw_size);
572
573 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
574 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
575
576
577 return 0;
578}
579
580static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
581{
582 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
583 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
584 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
585 (address << SQ_IND_INDEX__INDEX__SHIFT) |
586 (SQ_IND_INDEX__FORCE_READ_MASK));
587 return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
588}
589
590static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
591 uint32_t wave, uint32_t thread,
592 uint32_t regno, uint32_t num, uint32_t *out)
593{
594 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
595 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
596 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
597 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
598 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
599 (SQ_IND_INDEX__FORCE_READ_MASK) |
600 (SQ_IND_INDEX__AUTO_INCR_MASK));
601 while (num--)
602 *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
603}
604
605static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
606{
607 /* type 1 wave data */
608 dst[(*no_fields)++] = 1;
609 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
610 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
611 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
612 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
613 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
614 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
615 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
616 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
617 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
618 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
619 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
620 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
621 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
622 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
623}
624
625static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
626 uint32_t wave, uint32_t start,
627 uint32_t size, uint32_t *dst)
628{
629 wave_read_regs(
630 adev, simd, wave, 0,
631 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
632}
633
634
635static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
636 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
637 .select_se_sh = &gfx_v9_0_select_se_sh,
638 .read_wave_data = &gfx_v9_0_read_wave_data,
639 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
640};
641
642static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
643{
644 u32 gb_addr_config;
645
646 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
647
648 switch (adev->asic_type) {
649 case CHIP_VEGA10:
650 adev->gfx.config.max_shader_engines = 4;
651 adev->gfx.config.max_tile_pipes = 8; //??
652 adev->gfx.config.max_cu_per_sh = 16;
653 adev->gfx.config.max_sh_per_se = 1;
654 adev->gfx.config.max_backends_per_se = 4;
655 adev->gfx.config.max_texture_channel_caches = 16;
656 adev->gfx.config.max_gprs = 256;
657 adev->gfx.config.max_gs_threads = 32;
658 adev->gfx.config.max_hw_contexts = 8;
659
660 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
661 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
662 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
663 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
664 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
665 break;
666 default:
667 BUG();
668 break;
669 }
670
671 adev->gfx.config.gb_addr_config = gb_addr_config;
672
673 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
674 REG_GET_FIELD(
675 adev->gfx.config.gb_addr_config,
676 GB_ADDR_CONFIG,
677 NUM_PIPES);
678 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
679 REG_GET_FIELD(
680 adev->gfx.config.gb_addr_config,
681 GB_ADDR_CONFIG,
682 NUM_BANKS);
683 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
684 REG_GET_FIELD(
685 adev->gfx.config.gb_addr_config,
686 GB_ADDR_CONFIG,
687 MAX_COMPRESSED_FRAGS);
688 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
689 REG_GET_FIELD(
690 adev->gfx.config.gb_addr_config,
691 GB_ADDR_CONFIG,
692 NUM_RB_PER_SE);
693 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
694 REG_GET_FIELD(
695 adev->gfx.config.gb_addr_config,
696 GB_ADDR_CONFIG,
697 NUM_SHADER_ENGINES);
698 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
699 REG_GET_FIELD(
700 adev->gfx.config.gb_addr_config,
701 GB_ADDR_CONFIG,
702 PIPE_INTERLEAVE_SIZE));
703}
704
705static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
706 struct amdgpu_ngg_buf *ngg_buf,
707 int size_se,
708 int default_size_se)
709{
710 int r;
711
712 if (size_se < 0) {
713 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
714 return -EINVAL;
715 }
716 size_se = size_se ? size_se : default_size_se;
717
718 ngg_buf->size = size_se * GFX9_NUM_SE;
719 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
720 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
721 &ngg_buf->bo,
722 &ngg_buf->gpu_addr,
723 NULL);
724 if (r) {
725 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
726 return r;
727 }
728 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
729
730 return r;
731}
732
733static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
734{
735 int i;
736
737 for (i = 0; i < NGG_BUF_MAX; i++)
738 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
739 &adev->gfx.ngg.buf[i].gpu_addr,
740 NULL);
741
742 memset(&adev->gfx.ngg.buf[0], 0,
743 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
744
745 adev->gfx.ngg.init = false;
746
747 return 0;
748}
749
750static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
751{
752 int r;
753
754 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
755 return 0;
756
757 /* GDS reserve memory: 64 bytes alignment */
758 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
759 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
760 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
761 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
762 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
763
764 /* Primitive Buffer */
765 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
766 amdgpu_prim_buf_per_se,
767 64 * 1024);
768 if (r) {
769 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
770 goto err;
771 }
772
773 /* Position Buffer */
774 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
775 amdgpu_pos_buf_per_se,
776 256 * 1024);
777 if (r) {
778 dev_err(adev->dev, "Failed to create Position Buffer\n");
779 goto err;
780 }
781
782 /* Control Sideband */
783 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
784 amdgpu_cntl_sb_buf_per_se,
785 256);
786 if (r) {
787 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
788 goto err;
789 }
790
791 /* Parameter Cache, not created by default */
792 if (amdgpu_param_buf_per_se <= 0)
793 goto out;
794
795 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
796 amdgpu_param_buf_per_se,
797 512 * 1024);
798 if (r) {
799 dev_err(adev->dev, "Failed to create Parameter Cache\n");
800 goto err;
801 }
802
803out:
804 adev->gfx.ngg.init = true;
805 return 0;
806err:
807 gfx_v9_0_ngg_fini(adev);
808 return r;
809}
810
811static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
812{
813 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
814 int r;
815 u32 data;
816 u32 size;
817 u32 base;
818
819 if (!amdgpu_ngg)
820 return 0;
821
822 /* Program buffer size */
823 data = 0;
824 size = adev->gfx.ngg.buf[PRIM].size / 256;
825 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
826
827 size = adev->gfx.ngg.buf[POS].size / 256;
828 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
829
830 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data);
831
832 data = 0;
833 size = adev->gfx.ngg.buf[CNTL].size / 256;
834 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
835
836 size = adev->gfx.ngg.buf[PARAM].size / 1024;
837 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
838
839 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data);
840
841 /* Program buffer base address */
842 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
843 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
844 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data);
845
846 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
847 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
848 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data);
849
850 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
851 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
852 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data);
853
854 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
855 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
856 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data);
857
858 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
859 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
860 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data);
861
862 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
863 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
864 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data);
865
866 /* Clear GDS reserved memory */
867 r = amdgpu_ring_alloc(ring, 17);
868 if (r) {
869 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
870 ring->idx, r);
871 return r;
872 }
873
874 gfx_v9_0_write_data_to_reg(ring, 0, false,
875 amdgpu_gds_reg_offset[0].mem_size,
876 (adev->gds.mem.total_size +
877 adev->gfx.ngg.gds_reserve_size) >>
878 AMDGPU_GDS_SHIFT);
879
880 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
881 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
882 PACKET3_DMA_DATA_SRC_SEL(2)));
883 amdgpu_ring_write(ring, 0);
884 amdgpu_ring_write(ring, 0);
885 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
886 amdgpu_ring_write(ring, 0);
887 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
888
889
890 gfx_v9_0_write_data_to_reg(ring, 0, false,
891 amdgpu_gds_reg_offset[0].mem_size, 0);
892
893 amdgpu_ring_commit(ring);
894
895 return 0;
896}
897
898static int gfx_v9_0_sw_init(void *handle)
899{
900 int i, r;
901 struct amdgpu_ring *ring;
902 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
903
904 /* EOP Event */
905 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
906 if (r)
907 return r;
908
909 /* Privileged reg */
910 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
911 &adev->gfx.priv_reg_irq);
912 if (r)
913 return r;
914
915 /* Privileged inst */
916 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
917 &adev->gfx.priv_inst_irq);
918 if (r)
919 return r;
920
921 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
922
923 gfx_v9_0_scratch_init(adev);
924
925 r = gfx_v9_0_init_microcode(adev);
926 if (r) {
927 DRM_ERROR("Failed to load gfx firmware!\n");
928 return r;
929 }
930
931 r = gfx_v9_0_mec_init(adev);
932 if (r) {
933 DRM_ERROR("Failed to init MEC BOs!\n");
934 return r;
935 }
936
937 /* set up the gfx ring */
938 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
939 ring = &adev->gfx.gfx_ring[i];
940 ring->ring_obj = NULL;
941 sprintf(ring->name, "gfx");
942 ring->use_doorbell = true;
943 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
944 r = amdgpu_ring_init(adev, ring, 1024,
945 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
946 if (r)
947 return r;
948 }
949
950 /* set up the compute queues */
951 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
952 unsigned irq_type;
953
954 /* max 32 queues per MEC */
955 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
956 DRM_ERROR("Too many (%d) compute rings!\n", i);
957 break;
958 }
959 ring = &adev->gfx.compute_ring[i];
960 ring->ring_obj = NULL;
961 ring->use_doorbell = true;
962 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
963 ring->me = 1; /* first MEC */
964 ring->pipe = i / 8;
965 ring->queue = i % 8;
966 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
967 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
968 /* type-2 packets are deprecated on MEC, use type-3 instead */
969 r = amdgpu_ring_init(adev, ring, 1024,
970 &adev->gfx.eop_irq, irq_type);
971 if (r)
972 return r;
973 }
974
975 /* reserve GDS, GWS and OA resource for gfx */
976 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
977 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
978 &adev->gds.gds_gfx_bo, NULL, NULL);
979 if (r)
980 return r;
981
982 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
983 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
984 &adev->gds.gws_gfx_bo, NULL, NULL);
985 if (r)
986 return r;
987
988 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
989 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
990 &adev->gds.oa_gfx_bo, NULL, NULL);
991 if (r)
992 return r;
993
994 adev->gfx.ce_ram_size = 0x8000;
995
996 gfx_v9_0_gpu_early_init(adev);
997
998 r = gfx_v9_0_ngg_init(adev);
999 if (r)
1000 return r;
1001
1002 return 0;
1003}
1004
1005
1006static int gfx_v9_0_sw_fini(void *handle)
1007{
1008 int i;
1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1010
1011 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1012 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1013 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1014
1015 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1016 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1017 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1018 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1019
1020 gfx_v9_0_mec_fini(adev);
1021 gfx_v9_0_ngg_fini(adev);
1022
1023 return 0;
1024}
1025
1026
1027static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1028{
1029 /* TODO */
1030}
1031
1032static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1033{
1034 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1035
1036 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1037 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1038 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1039 } else if (se_num == 0xffffffff) {
1040 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1041 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1042 } else if (sh_num == 0xffffffff) {
1043 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1044 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1045 } else {
1046 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1047 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1048 }
1049 WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
1050}
1051
1052static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1053{
1054 return (u32)((1ULL << bit_width) - 1);
1055}
1056
1057static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1058{
1059 u32 data, mask;
1060
1061 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE));
1062 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE));
1063
1064 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1065 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1066
1067 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1068 adev->gfx.config.max_sh_per_se);
1069
1070 return (~data) & mask;
1071}
1072
1073static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1074{
1075 int i, j;
1076 u32 data, tmp, num_rbs = 0;
1077 u32 active_rbs = 0;
1078 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1079 adev->gfx.config.max_sh_per_se;
1080
1081 mutex_lock(&adev->grbm_idx_mutex);
1082 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1083 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1084 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1085 data = gfx_v9_0_get_rb_active_bitmap(adev);
1086 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1087 rb_bitmap_width_per_sh);
1088 }
1089 }
1090 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1091 mutex_unlock(&adev->grbm_idx_mutex);
1092
1093 adev->gfx.config.backend_enable_mask = active_rbs;
1094 tmp = active_rbs;
1095 while (tmp >>= 1)
1096 num_rbs++;
1097 adev->gfx.config.num_rbs = num_rbs;
1098}
1099
1100#define DEFAULT_SH_MEM_BASES (0x6000)
1101#define FIRST_COMPUTE_VMID (8)
1102#define LAST_COMPUTE_VMID (16)
1103static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1104{
1105 int i;
1106 uint32_t sh_mem_config;
1107 uint32_t sh_mem_bases;
1108
1109 /*
1110 * Configure apertures:
1111 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1112 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1113 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1114 */
1115 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1116
1117 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1118 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1119 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1120
1121 mutex_lock(&adev->srbm_mutex);
1122 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1123 soc15_grbm_select(adev, 0, 0, 0, i);
1124 /* CP and shaders */
1125 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
1126 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
1127 }
1128 soc15_grbm_select(adev, 0, 0, 0, 0);
1129 mutex_unlock(&adev->srbm_mutex);
1130}
1131
1132static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1133{
1134 u32 tmp;
1135 int i;
1136
1137 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
1138 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
1139 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
1140
1141 gfx_v9_0_tiling_mode_table_init(adev);
1142
1143 gfx_v9_0_setup_rb(adev);
1144 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1145
1146 /* XXX SH_MEM regs */
1147 /* where to put LDS, scratch, GPUVM in FSA64 space */
1148 mutex_lock(&adev->srbm_mutex);
1149 for (i = 0; i < 16; i++) {
1150 soc15_grbm_select(adev, 0, 0, 0, i);
1151 /* CP and shaders */
1152 tmp = 0;
1153 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1154 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1155 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp);
1156 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0);
1157 }
1158 soc15_grbm_select(adev, 0, 0, 0, 0);
1159
1160 mutex_unlock(&adev->srbm_mutex);
1161
1162 gfx_v9_0_init_compute_vmid(adev);
1163
1164 mutex_lock(&adev->grbm_idx_mutex);
1165 /*
1166 * making sure that the following register writes will be broadcasted
1167 * to all the shaders
1168 */
1169 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1170
1171 WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE),
1172 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1173 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1174 (adev->gfx.config.sc_prim_fifo_size_backend <<
1175 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1176 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1177 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1178 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1179 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1180 mutex_unlock(&adev->grbm_idx_mutex);
1181
1182}
1183
1184static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1185{
1186 u32 i, j, k;
1187 u32 mask;
1188
1189 mutex_lock(&adev->grbm_idx_mutex);
1190 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1191 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1192 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1193 for (k = 0; k < adev->usec_timeout; k++) {
1194 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0)
1195 break;
1196 udelay(1);
1197 }
1198 }
1199 }
1200 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1201 mutex_unlock(&adev->grbm_idx_mutex);
1202
1203 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1204 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1205 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1206 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1207 for (k = 0; k < adev->usec_timeout; k++) {
1208 if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0)
1209 break;
1210 udelay(1);
1211 }
1212}
1213
1214static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1215 bool enable)
1216{
1217 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
1218
1219 if (enable)
1220 return;
1221
1222 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1223 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1224 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1225 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1226
1227 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp);
1228}
1229
1230void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1231{
1232 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1233
1234 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1235 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1236
1237 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1238
1239 gfx_v9_0_wait_for_rlc_serdes(adev);
1240}
1241
1242static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1243{
1244 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
1245
1246 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1247 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1248 udelay(50);
1249 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1250 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1251 udelay(50);
1252}
1253
1254static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1255{
1256#ifdef AMDGPU_RLC_DEBUG_RETRY
1257 u32 rlc_ucode_ver;
1258#endif
1259 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1260
1261 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
1262 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1263
1264 /* carrizo do enable cp interrupt after cp inited */
1265 if (!(adev->flags & AMD_IS_APU))
1266 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1267
1268 udelay(50);
1269
1270#ifdef AMDGPU_RLC_DEBUG_RETRY
1271 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1272 rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6));
1273 if(rlc_ucode_ver == 0x108) {
1274 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1275 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1276 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1277 * default is 0x9C4 to create a 100us interval */
1278 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4);
1279 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1280 * to disable the page fault retry interrupts, default is
1281 * 0x100 (256) */
1282 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100);
1283 }
1284#endif
1285}
1286
1287static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1288{
1289 const struct rlc_firmware_header_v2_0 *hdr;
1290 const __le32 *fw_data;
1291 unsigned i, fw_size;
1292
1293 if (!adev->gfx.rlc_fw)
1294 return -EINVAL;
1295
1296 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1297 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1298
1299 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1300 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1301 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1302
1303 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR),
1304 RLCG_UCODE_LOADING_START_ADDRESS);
1305 for (i = 0; i < fw_size; i++)
1306 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++));
1307 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version);
1308
1309 return 0;
1310}
1311
1312static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1313{
1314 int r;
1315
1316 gfx_v9_0_rlc_stop(adev);
1317
1318 /* disable CG */
1319 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0);
1320
1321 /* disable PG */
1322 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0);
1323
1324 gfx_v9_0_rlc_reset(adev);
1325
1326 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1327 /* legacy rlc firmware loading */
1328 r = gfx_v9_0_rlc_load_microcode(adev);
1329 if (r)
1330 return r;
1331 }
1332
1333 gfx_v9_0_rlc_start(adev);
1334
1335 return 0;
1336}
1337
1338static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1339{
1340 int i;
1341 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL));
1342
1343 if (enable) {
1344 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
1345 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
1346 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
1347 } else {
1348 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
1349 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
1350 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
1351 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1352 adev->gfx.gfx_ring[i].ready = false;
1353 }
1354 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp);
1355 udelay(50);
1356}
1357
1358static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1359{
1360 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1361 const struct gfx_firmware_header_v1_0 *ce_hdr;
1362 const struct gfx_firmware_header_v1_0 *me_hdr;
1363 const __le32 *fw_data;
1364 unsigned i, fw_size;
1365
1366 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1367 return -EINVAL;
1368
1369 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1370 adev->gfx.pfp_fw->data;
1371 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1372 adev->gfx.ce_fw->data;
1373 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1374 adev->gfx.me_fw->data;
1375
1376 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1377 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1378 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1379
1380 gfx_v9_0_cp_gfx_enable(adev, false);
1381
1382 /* PFP */
1383 fw_data = (const __le32 *)
1384 (adev->gfx.pfp_fw->data +
1385 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1386 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1387 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0);
1388 for (i = 0; i < fw_size; i++)
1389 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++));
1390 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version);
1391
1392 /* CE */
1393 fw_data = (const __le32 *)
1394 (adev->gfx.ce_fw->data +
1395 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1396 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1397 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0);
1398 for (i = 0; i < fw_size; i++)
1399 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++));
1400 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version);
1401
1402 /* ME */
1403 fw_data = (const __le32 *)
1404 (adev->gfx.me_fw->data +
1405 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1406 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1407 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0);
1408 for (i = 0; i < fw_size; i++)
1409 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++));
1410 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version);
1411
1412 return 0;
1413}
1414
1415static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1416{
1417 u32 count = 0;
1418 const struct cs_section_def *sect = NULL;
1419 const struct cs_extent_def *ext = NULL;
1420
1421 /* begin clear state */
1422 count += 2;
1423 /* context control state */
1424 count += 3;
1425
1426 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1427 for (ext = sect->section; ext->extent != NULL; ++ext) {
1428 if (sect->id == SECT_CONTEXT)
1429 count += 2 + ext->reg_count;
1430 else
1431 return 0;
1432 }
1433 }
1434 /* pa_sc_raster_config/pa_sc_raster_config1 */
1435 count += 4;
1436 /* end clear state */
1437 count += 2;
1438 /* clear state */
1439 count += 2;
1440
1441 return count;
1442}
1443
1444static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1445{
1446 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1447 const struct cs_section_def *sect = NULL;
1448 const struct cs_extent_def *ext = NULL;
1449 int r, i;
1450
1451 /* init the CP */
1452 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1);
1453 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1);
1454
1455 gfx_v9_0_cp_gfx_enable(adev, true);
1456
1457 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1458 if (r) {
1459 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1460 return r;
1461 }
1462
1463 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1464 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1465
1466 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1467 amdgpu_ring_write(ring, 0x80000000);
1468 amdgpu_ring_write(ring, 0x80000000);
1469
1470 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1471 for (ext = sect->section; ext->extent != NULL; ++ext) {
1472 if (sect->id == SECT_CONTEXT) {
1473 amdgpu_ring_write(ring,
1474 PACKET3(PACKET3_SET_CONTEXT_REG,
1475 ext->reg_count));
1476 amdgpu_ring_write(ring,
1477 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1478 for (i = 0; i < ext->reg_count; i++)
1479 amdgpu_ring_write(ring, ext->extent[i]);
1480 }
1481 }
1482 }
1483
1484 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1485 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1486
1487 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1488 amdgpu_ring_write(ring, 0);
1489
1490 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1491 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1492 amdgpu_ring_write(ring, 0x8000);
1493 amdgpu_ring_write(ring, 0x8000);
1494
1495 amdgpu_ring_commit(ring);
1496
1497 return 0;
1498}
1499
1500static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1501{
1502 struct amdgpu_ring *ring;
1503 u32 tmp;
1504 u32 rb_bufsz;
1505 u64 rb_addr, rptr_addr;
1506
1507 /* Set the write pointer delay */
1508 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
1509
1510 /* set the RB to use vmid 0 */
1511 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0);
1512
1513 /* Set ring buffer size */
1514 ring = &adev->gfx.gfx_ring[0];
1515 rb_bufsz = order_base_2(ring->ring_size / 8);
1516 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1517 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1518#ifdef __BIG_ENDIAN
1519 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1520#endif
1521 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1522
1523 /* Initialize the ring buffer's write pointers */
1524 ring->wptr = 0;
1525 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
1526 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
1527
1528 /* set the wb address wether it's enabled or not */
1529 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1530 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr));
1531 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
1532
1533 mdelay(1);
1534 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1535
1536 rb_addr = ring->gpu_addr >> 8;
1537 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr);
1538 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr));
1539
1540 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL));
1541 if (ring->use_doorbell) {
1542 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1543 DOORBELL_OFFSET, ring->doorbell_index);
1544 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1545 DOORBELL_EN, 1);
1546 } else {
1547 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1548 }
1549 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp);
1550
1551 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1552 DOORBELL_RANGE_LOWER, ring->doorbell_index);
1553 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp);
1554
1555 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER),
1556 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1557
1558
1559 /* start the ring */
1560 gfx_v9_0_cp_gfx_start(adev);
1561 ring->ready = true;
1562
1563 return 0;
1564}
1565
1566static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1567{
1568 int i;
1569
1570 if (enable) {
1571 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0);
1572 } else {
1573 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL),
1574 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1575 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1576 adev->gfx.compute_ring[i].ready = false;
1577 }
1578 udelay(50);
1579}
1580
1581static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1582{
1583 gfx_v9_0_cp_compute_enable(adev, true);
1584
1585 return 0;
1586}
1587
1588static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1589{
1590 const struct gfx_firmware_header_v1_0 *mec_hdr;
1591 const __le32 *fw_data;
1592 unsigned i;
1593 u32 tmp;
1594
1595 if (!adev->gfx.mec_fw)
1596 return -EINVAL;
1597
1598 gfx_v9_0_cp_compute_enable(adev, false);
1599
1600 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1601 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1602
1603 fw_data = (const __le32 *)
1604 (adev->gfx.mec_fw->data +
1605 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1606 tmp = 0;
1607 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1608 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1609 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp);
1610
1611 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO),
1612 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1613 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI),
1614 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1615
1616 /* MEC1 */
1617 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1618 mec_hdr->jt_offset);
1619 for (i = 0; i < mec_hdr->jt_size; i++)
1620 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA),
1621 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1622
1623 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1624 adev->gfx.mec_fw_version);
1625 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1626
1627 return 0;
1628}
1629
1630static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1631{
1632 int i, r;
1633
1634 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1635 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1636
1637 if (ring->mqd_obj) {
1638 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1639 if (unlikely(r != 0))
1640 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1641
1642 amdgpu_bo_unpin(ring->mqd_obj);
1643 amdgpu_bo_unreserve(ring->mqd_obj);
1644
1645 amdgpu_bo_unref(&ring->mqd_obj);
1646 ring->mqd_obj = NULL;
1647 }
1648 }
1649}
1650
1651static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1652
1653static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1654{
1655 int i, r;
1656 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1657 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1658 if (gfx_v9_0_init_queue(ring))
1659 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1660 }
1661
1662 r = gfx_v9_0_cp_compute_start(adev);
1663 if (r)
1664 return r;
1665
1666 return 0;
1667}
1668
1669static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
1670{
1671 int r,i;
1672 struct amdgpu_ring *ring;
1673
1674 if (!(adev->flags & AMD_IS_APU))
1675 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1676
1677 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1678 /* legacy firmware loading */
1679 r = gfx_v9_0_cp_gfx_load_microcode(adev);
1680 if (r)
1681 return r;
1682
1683 r = gfx_v9_0_cp_compute_load_microcode(adev);
1684 if (r)
1685 return r;
1686 }
1687
1688 r = gfx_v9_0_cp_gfx_resume(adev);
1689 if (r)
1690 return r;
1691
1692 r = gfx_v9_0_cp_compute_resume(adev);
1693 if (r)
1694 return r;
1695
1696 ring = &adev->gfx.gfx_ring[0];
1697 r = amdgpu_ring_test_ring(ring);
1698 if (r) {
1699 ring->ready = false;
1700 return r;
1701 }
1702 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1703 ring = &adev->gfx.compute_ring[i];
1704
1705 ring->ready = true;
1706 r = amdgpu_ring_test_ring(ring);
1707 if (r)
1708 ring->ready = false;
1709 }
1710
1711 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1712
1713 return 0;
1714}
1715
1716static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
1717{
1718 gfx_v9_0_cp_gfx_enable(adev, enable);
1719 gfx_v9_0_cp_compute_enable(adev, enable);
1720}
1721
1722static int gfx_v9_0_hw_init(void *handle)
1723{
1724 int r;
1725 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1726
1727 gfx_v9_0_init_golden_registers(adev);
1728
1729 gfx_v9_0_gpu_init(adev);
1730
1731 r = gfx_v9_0_rlc_resume(adev);
1732 if (r)
1733 return r;
1734
1735 r = gfx_v9_0_cp_resume(adev);
1736 if (r)
1737 return r;
1738
1739 r = gfx_v9_0_ngg_en(adev);
1740 if (r)
1741 return r;
1742
1743 return r;
1744}
1745
1746static int gfx_v9_0_hw_fini(void *handle)
1747{
1748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1749
1750 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
1751 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
1752 gfx_v9_0_cp_enable(adev, false);
1753 gfx_v9_0_rlc_stop(adev);
1754 gfx_v9_0_cp_compute_fini(adev);
1755
1756 return 0;
1757}
1758
1759static int gfx_v9_0_suspend(void *handle)
1760{
1761 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1762
1763 return gfx_v9_0_hw_fini(adev);
1764}
1765
1766static int gfx_v9_0_resume(void *handle)
1767{
1768 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1769
1770 return gfx_v9_0_hw_init(adev);
1771}
1772
1773static bool gfx_v9_0_is_idle(void *handle)
1774{
1775 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1776
1777 if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)),
1778 GRBM_STATUS, GUI_ACTIVE))
1779 return false;
1780 else
1781 return true;
1782}
1783
1784static int gfx_v9_0_wait_for_idle(void *handle)
1785{
1786 unsigned i;
1787 u32 tmp;
1788 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1789
1790 for (i = 0; i < adev->usec_timeout; i++) {
1791 /* read MC_STATUS */
1792 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) &
1793 GRBM_STATUS__GUI_ACTIVE_MASK;
1794
1795 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
1796 return 0;
1797 udelay(1);
1798 }
1799 return -ETIMEDOUT;
1800}
1801
1802static void gfx_v9_0_print_status(void *handle)
1803{
1804 int i;
1805 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1806
1807 dev_info(adev->dev, "GFX 9.x registers\n");
1808 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
1809 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)));
1810 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
1811 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)));
1812 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1813 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)));
1814 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1815 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)));
1816 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
1817 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)));
1818 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
1819 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)));
1820 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STAT)));
1821 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
1822 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)));
1823 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
1824 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)));
1825 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
1826 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)));
1827 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
1828 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)));
1829 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
1830 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)));
1831 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)));
1832 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT)));
1833 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
1834 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)));
1835 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)));
1836
1837 for (i = 0; i < 32; i++) {
1838 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
1839 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + i*4));
1840 }
1841 for (i = 0; i < 16; i++) {
1842 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
1843 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_MACROTILE_MODE0) + i*4));
1844 }
1845 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1846 dev_info(adev->dev, " se: %d\n", i);
1847 gfx_v9_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1848 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
1849 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG)));
1850 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
1851 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG_1)));
1852 }
1853 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1854
1855 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
1856 RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)));
1857
1858 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
1859 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS)));
1860 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
1861 RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1)));
1862 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
1863 RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX)));
1864 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
1865 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)));
1866 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
1867 RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)));
1868 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
1869 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG)));
1870 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
1871 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)));
1872 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
1873 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3)));
1874 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
1875 RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL)));
1876 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
1877 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1)));
1878 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
1879 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE)));
1880 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
1881 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_NUM_INSTANCES)));
1882 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
1883 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL)));
1884 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
1885 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FORCE_EOV_MAX_CNTS)));
1886 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
1887 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION)));
1888 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
1889 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_GS_VERTEX_REUSE)));
1890 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
1891 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE)));
1892 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
1893 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_CL_ENHANCE)));
1894 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
1895 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE)));
1896
1897 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
1898 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)));
1899 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
1900 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT)));
1901 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
1902 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID)));
1903
1904 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
1905 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_SEM_WAIT_TIMER)));
1906
1907 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
1908 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY)));
1909 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
1910 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID)));
1911 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
1912 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
1913 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
1914 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR)));
1915 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
1916 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR)));
1917 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
1918 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI)));
1919 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
1920 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL)));
1921 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
1922 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE)));
1923 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
1924 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI)));
1925 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
1926 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL)));
1927
1928 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
1929 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_ADDR)));
1930 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
1931 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_UMSK)));
1932
1933 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
1934 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)));
1935 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
1936 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
1937 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
1938 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)));
1939 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
1940 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)));
1941 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
1942 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_INIT)));
1943 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
1944 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_MAX)));
1945 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
1946 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_INIT_CU_MASK)));
1947 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
1948 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_PARAMS)));
1949 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
1950 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL)));
1951 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
1952 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_UCODE_CNTL)));
1953
1954 dev_info(adev->dev, " RLC_GPM_GENERAL_6=0x%08X\n",
1955 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6)));
1956 dev_info(adev->dev, " RLC_GPM_GENERAL_12=0x%08X\n",
1957 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12)));
1958 dev_info(adev->dev, " RLC_GPM_TIMER_INT_3=0x%08X\n",
1959 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3)));
1960 mutex_lock(&adev->srbm_mutex);
1961 for (i = 0; i < 16; i++) {
1962 soc15_grbm_select(adev, 0, 0, 0, i);
1963 dev_info(adev->dev, " VM %d:\n", i);
1964 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
1965 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)));
1966 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
1967 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES)));
1968 }
1969 soc15_grbm_select(adev, 0, 0, 0, 0);
1970 mutex_unlock(&adev->srbm_mutex);
1971}
1972
1973static int gfx_v9_0_soft_reset(void *handle)
1974{
1975 u32 grbm_soft_reset = 0;
1976 u32 tmp;
1977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1978
1979 /* GRBM_STATUS */
1980 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS));
1981 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
1982 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
1983 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
1984 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
1985 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
1986 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
1987 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1988 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
1989 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1990 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
1991 }
1992
1993 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
1994 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
1995 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
1996 }
1997
1998 /* GRBM_STATUS2 */
1999 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2));
2000 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2001 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2002 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2003
2004
2005 if (grbm_soft_reset ) {
2006 gfx_v9_0_print_status((void *)adev);
2007 /* stop the rlc */
2008 gfx_v9_0_rlc_stop(adev);
2009
2010 /* Disable GFX parsing/prefetching */
2011 gfx_v9_0_cp_gfx_enable(adev, false);
2012
2013 /* Disable MEC parsing/prefetching */
2014 gfx_v9_0_cp_compute_enable(adev, false);
2015
2016 if (grbm_soft_reset) {
2017 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2018 tmp |= grbm_soft_reset;
2019 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2020 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2021 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2022
2023 udelay(50);
2024
2025 tmp &= ~grbm_soft_reset;
2026 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2027 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2028 }
2029
2030 /* Wait a little for things to settle down */
2031 udelay(50);
2032 gfx_v9_0_print_status((void *)adev);
2033 }
2034 return 0;
2035}
2036
2037static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2038{
2039 uint64_t clock;
2040
2041 mutex_lock(&adev->gfx.gpu_clock_mutex);
2042 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1);
2043 clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) |
2044 ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL);
2045 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2046 return clock;
2047}
2048
2049static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2050 uint32_t vmid,
2051 uint32_t gds_base, uint32_t gds_size,
2052 uint32_t gws_base, uint32_t gws_size,
2053 uint32_t oa_base, uint32_t oa_size)
2054{
2055 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2056 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2057
2058 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2059 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2060
2061 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2062 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2063
2064 /* GDS Base */
2065 gfx_v9_0_write_data_to_reg(ring, 0, false,
2066 amdgpu_gds_reg_offset[vmid].mem_base,
2067 gds_base);
2068
2069 /* GDS Size */
2070 gfx_v9_0_write_data_to_reg(ring, 0, false,
2071 amdgpu_gds_reg_offset[vmid].mem_size,
2072 gds_size);
2073
2074 /* GWS */
2075 gfx_v9_0_write_data_to_reg(ring, 0, false,
2076 amdgpu_gds_reg_offset[vmid].gws,
2077 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2078
2079 /* OA */
2080 gfx_v9_0_write_data_to_reg(ring, 0, false,
2081 amdgpu_gds_reg_offset[vmid].oa,
2082 (1 << (oa_size + oa_base)) - (1 << oa_base));
2083}
2084
2085static int gfx_v9_0_early_init(void *handle)
2086{
2087 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2088
2089 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2090 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2091 gfx_v9_0_set_ring_funcs(adev);
2092 gfx_v9_0_set_irq_funcs(adev);
2093 gfx_v9_0_set_gds_init(adev);
2094 gfx_v9_0_set_rlc_funcs(adev);
2095
2096 return 0;
2097}
2098
2099static int gfx_v9_0_late_init(void *handle)
2100{
2101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2102 int r;
2103
2104 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2105 if (r)
2106 return r;
2107
2108 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2109 if (r)
2110 return r;
2111
2112 return 0;
2113}
2114
2115static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2116{
2117 uint32_t rlc_setting, data;
2118 unsigned i;
2119
2120 if (adev->gfx.rlc.in_safe_mode)
2121 return;
2122
2123 /* if RLC is not enabled, do nothing */
2124 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2125 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2126 return;
2127
2128 if (adev->cg_flags &
2129 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2130 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2131 data = RLC_SAFE_MODE__CMD_MASK;
2132 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
2133 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2134
2135 /* wait for RLC_SAFE_MODE */
2136 for (i = 0; i < adev->usec_timeout; i++) {
2137 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2138 break;
2139 udelay(1);
2140 }
2141 adev->gfx.rlc.in_safe_mode = true;
2142 }
2143}
2144
2145static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2146{
2147 uint32_t rlc_setting, data;
2148
2149 if (!adev->gfx.rlc.in_safe_mode)
2150 return;
2151
2152 /* if RLC is not enabled, do nothing */
2153 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2154 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2155 return;
2156
2157 if (adev->cg_flags &
2158 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2159 /*
2160 * Try to exit safe mode only if it is already in safe
2161 * mode.
2162 */
2163 data = RLC_SAFE_MODE__CMD_MASK;
2164 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2165 adev->gfx.rlc.in_safe_mode = false;
2166 }
2167}
2168
2169static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2170 bool enable)
2171{
2172 uint32_t data, def;
2173
2174 /* It is disabled by HW by default */
2175 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2176 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2177 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2178 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2179 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2180 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2181 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2182
2183 /* only for Vega10 & Raven1 */
2184 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2185
2186 if (def != data)
2187 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2188
2189 /* MGLS is a global flag to control all MGLS in GFX */
2190 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2191 /* 2 - RLC memory Light sleep */
2192 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2193 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2194 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2195 if (def != data)
2196 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2197 }
2198 /* 3 - CP memory Light sleep */
2199 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2200 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2201 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2202 if (def != data)
2203 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2204 }
2205 }
2206 } else {
2207 /* 1 - MGCG_OVERRIDE */
2208 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2209 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2210 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2211 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2212 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2213 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2214 if (def != data)
2215 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2216
2217 /* 2 - disable MGLS in RLC */
2218 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2219 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2220 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2221 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2222 }
2223
2224 /* 3 - disable MGLS in CP */
2225 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2226 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2227 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2228 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2229 }
2230 }
2231}
2232
2233static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2234 bool enable)
2235{
2236 uint32_t data, def;
2237
2238 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2239
2240 /* Enable 3D CGCG/CGLS */
2241 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2242 /* write cmd to clear cgcg/cgls ov */
2243 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2244 /* unset CGCG override */
2245 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2246 /* update CGCG and CGLS override bits */
2247 if (def != data)
2248 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2249 /* enable 3Dcgcg FSM(0x0020003f) */
2250 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2251 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2252 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2253 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2254 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2255 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2256 if (def != data)
2257 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2258
2259 /* set IDLE_POLL_COUNT(0x00900100) */
2260 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2261 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2262 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2263 if (def != data)
2264 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2265 } else {
2266 /* Disable CGCG/CGLS */
2267 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2268 /* disable cgcg, cgls should be disabled */
2269 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2270 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2271 /* disable cgcg and cgls in FSM */
2272 if (def != data)
2273 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2274 }
2275
2276 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2277}
2278
2279static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2280 bool enable)
2281{
2282 uint32_t def, data;
2283
2284 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2285
2286 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2287 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2288 /* unset CGCG override */
2289 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2290 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2291 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2292 else
2293 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2294 /* update CGCG and CGLS override bits */
2295 if (def != data)
2296 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2297
2298 /* enable cgcg FSM(0x0020003F) */
2299 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2300 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2301 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2302 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2303 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2304 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2305 if (def != data)
2306 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2307
2308 /* set IDLE_POLL_COUNT(0x00900100) */
2309 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2310 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2311 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2312 if (def != data)
2313 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2314 } else {
2315 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2316 /* reset CGCG/CGLS bits */
2317 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2318 /* disable cgcg and cgls in FSM */
2319 if (def != data)
2320 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2321 }
2322
2323 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2324}
2325
2326static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2327 bool enable)
2328{
2329 if (enable) {
2330 /* CGCG/CGLS should be enabled after MGCG/MGLS
2331 * === MGCG + MGLS ===
2332 */
2333 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2334 /* === CGCG /CGLS for GFX 3D Only === */
2335 gfx_v9_0_update_3d_clock_gating(adev, enable);
2336 /* === CGCG + CGLS === */
2337 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2338 } else {
2339 /* CGCG/CGLS should be disabled before MGCG/MGLS
2340 * === CGCG + CGLS ===
2341 */
2342 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2343 /* === CGCG /CGLS for GFX 3D Only === */
2344 gfx_v9_0_update_3d_clock_gating(adev, enable);
2345 /* === MGCG + MGLS === */
2346 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2347 }
2348 return 0;
2349}
2350
2351static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2352 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2353 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2354};
2355
2356static int gfx_v9_0_set_powergating_state(void *handle,
2357 enum amd_powergating_state state)
2358{
2359 return 0;
2360}
2361
2362static int gfx_v9_0_set_clockgating_state(void *handle,
2363 enum amd_clockgating_state state)
2364{
2365 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2366
2367 switch (adev->asic_type) {
2368 case CHIP_VEGA10:
2369 gfx_v9_0_update_gfx_clock_gating(adev,
2370 state == AMD_CG_STATE_GATE ? true : false);
2371 break;
2372 default:
2373 break;
2374 }
2375 return 0;
2376}
2377
2378static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2379{
2380 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2381}
2382
2383static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2384{
2385 struct amdgpu_device *adev = ring->adev;
2386 u64 wptr;
2387
2388 /* XXX check if swapping is necessary on BE */
2389 if (ring->use_doorbell) {
2390 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2391 } else {
2392 wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR));
2393 wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32;
2394 }
2395
2396 return wptr;
2397}
2398
2399static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2400{
2401 struct amdgpu_device *adev = ring->adev;
2402
2403 if (ring->use_doorbell) {
2404 /* XXX check if swapping is necessary on BE */
2405 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2406 WDOORBELL64(ring->doorbell_index, ring->wptr);
2407 } else {
2408 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
2409 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
2410 }
2411}
2412
2413static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2414{
2415 u32 ref_and_mask, reg_mem_engine;
2416 struct nbio_hdp_flush_reg *nbio_hf_reg;
2417
2418 if (ring->adev->asic_type == CHIP_VEGA10)
2419 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2420
2421 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2422 switch (ring->me) {
2423 case 1:
2424 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2425 break;
2426 case 2:
2427 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2428 break;
2429 default:
2430 return;
2431 }
2432 reg_mem_engine = 0;
2433 } else {
2434 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2435 reg_mem_engine = 1; /* pfp */
2436 }
2437
2438 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2439 nbio_hf_reg->hdp_flush_req_offset,
2440 nbio_hf_reg->hdp_flush_done_offset,
2441 ref_and_mask, ref_and_mask, 0x20);
2442}
2443
2444static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2445{
2446 gfx_v9_0_write_data_to_reg(ring, 0, true,
2447 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
2448}
2449
2450static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2451 struct amdgpu_ib *ib,
2452 unsigned vm_id, bool ctx_switch)
2453{
2454 u32 header, control = 0;
2455
2456 if (ib->flags & AMDGPU_IB_FLAG_CE)
2457 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2458 else
2459 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2460
2461 control |= ib->length_dw | (vm_id << 24);
2462
2463 amdgpu_ring_write(ring, header);
2464 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2465 amdgpu_ring_write(ring,
2466#ifdef __BIG_ENDIAN
2467 (2 << 0) |
2468#endif
2469 lower_32_bits(ib->gpu_addr));
2470 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2471 amdgpu_ring_write(ring, control);
2472}
2473
2474#define INDIRECT_BUFFER_VALID (1 << 23)
2475
2476static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2477 struct amdgpu_ib *ib,
2478 unsigned vm_id, bool ctx_switch)
2479{
2480 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2481
2482 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2483 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2484 amdgpu_ring_write(ring,
2485#ifdef __BIG_ENDIAN
2486 (2 << 0) |
2487#endif
2488 lower_32_bits(ib->gpu_addr));
2489 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2490 amdgpu_ring_write(ring, control);
2491}
2492
2493static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2494 u64 seq, unsigned flags)
2495{
2496 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2497 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2498
2499 /* RELEASE_MEM - flush caches, send int */
2500 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2501 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2502 EOP_TC_ACTION_EN |
2503 EOP_TC_WB_ACTION_EN |
2504 EOP_TC_MD_ACTION_EN |
2505 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2506 EVENT_INDEX(5)));
2507 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2508
2509 /*
2510 * the address should be Qword aligned if 64bit write, Dword
2511 * aligned if only send 32bit data low (discard data high)
2512 */
2513 if (write64bit)
2514 BUG_ON(addr & 0x7);
2515 else
2516 BUG_ON(addr & 0x3);
2517 amdgpu_ring_write(ring, lower_32_bits(addr));
2518 amdgpu_ring_write(ring, upper_32_bits(addr));
2519 amdgpu_ring_write(ring, lower_32_bits(seq));
2520 amdgpu_ring_write(ring, upper_32_bits(seq));
2521 amdgpu_ring_write(ring, 0);
2522}
2523
2524static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2525{
2526 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2527 uint32_t seq = ring->fence_drv.sync_seq;
2528 uint64_t addr = ring->fence_drv.gpu_addr;
2529
2530 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
2531 lower_32_bits(addr), upper_32_bits(addr),
2532 seq, 0xffffffff, 4);
2533}
2534
2535static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2536 unsigned vm_id, uint64_t pd_addr)
2537{
2538 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2539 unsigned eng = ring->idx;
2540 unsigned i;
2541
2542 pd_addr = pd_addr | 0x1; /* valid bit */
2543 /* now only use physical base address of PDE and valid */
2544 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
2545
2546 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2547 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
2548 uint32_t req = hub->get_invalidate_req(vm_id);
2549
2550 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2551 hub->ctx0_ptb_addr_lo32
2552 + (2 * vm_id),
2553 lower_32_bits(pd_addr));
2554
2555 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2556 hub->ctx0_ptb_addr_hi32
2557 + (2 * vm_id),
2558 upper_32_bits(pd_addr));
2559
2560 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2561 hub->vm_inv_eng0_req + eng, req);
2562
2563 /* wait for the invalidate to complete */
2564 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
2565 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
2566 }
2567
2568 /* compute doesn't have PFP */
2569 if (usepfp) {
2570 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2571 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2572 amdgpu_ring_write(ring, 0x0);
2573 /* Emits 128 dw nop to prevent CE access VM before vm_flush finish */
2574 amdgpu_ring_insert_nop(ring, 128);
2575 }
2576}
2577
2578static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2579{
2580 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2581}
2582
2583static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2584{
2585 u64 wptr;
2586
2587 /* XXX check if swapping is necessary on BE */
2588 if (ring->use_doorbell)
2589 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2590 else
2591 BUG();
2592 return wptr;
2593}
2594
2595static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2596{
2597 struct amdgpu_device *adev = ring->adev;
2598
2599 /* XXX check if swapping is necessary on BE */
2600 if (ring->use_doorbell) {
2601 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2602 WDOORBELL64(ring->doorbell_index, ring->wptr);
2603 } else{
2604 BUG(); /* only DOORBELL method supported on gfx9 now */
2605 }
2606}
2607
2608static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
2609{
2610 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2611 amdgpu_ring_write(ring, 0);
2612}
2613
2614static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2615{
2616 uint32_t dw2 = 0;
2617
2618 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2619 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2620 /* set load_global_config & load_global_uconfig */
2621 dw2 |= 0x8001;
2622 /* set load_cs_sh_regs */
2623 dw2 |= 0x01000000;
2624 /* set load_per_context_state & load_gfx_sh_regs for GFX */
2625 dw2 |= 0x10002;
2626
2627 /* set load_ce_ram if preamble presented */
2628 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
2629 dw2 |= 0x10000000;
2630 } else {
2631 /* still load_ce_ram if this is the first time preamble presented
2632 * although there is no context switch happens.
2633 */
2634 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
2635 dw2 |= 0x10000000;
2636 }
2637
2638 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2639 amdgpu_ring_write(ring, dw2);
2640 amdgpu_ring_write(ring, 0);
2641}
2642
2643static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
2644 enum amdgpu_interrupt_state state)
2645{
2646 u32 cp_int_cntl;
2647
2648 switch (state) {
2649 case AMDGPU_IRQ_STATE_DISABLE:
2650 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2651 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2652 TIME_STAMP_INT_ENABLE, 0);
2653 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2654 break;
2655 case AMDGPU_IRQ_STATE_ENABLE:
2656 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2657 cp_int_cntl =
2658 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2659 TIME_STAMP_INT_ENABLE, 1);
2660 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2661 break;
2662 default:
2663 break;
2664 }
2665}
2666
2667static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
2668 int me, int pipe,
2669 enum amdgpu_interrupt_state state)
2670{
2671 u32 mec_int_cntl, mec_int_cntl_reg;
2672
2673 /*
2674 * amdgpu controls only pipe 0 of MEC1. That's why this function only
2675 * handles the setting of interrupts for this specific pipe. All other
2676 * pipes' interrupts are set by amdkfd.
2677 */
2678
2679 if (me == 1) {
2680 switch (pipe) {
2681 case 0:
2682 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
2683 break;
2684 default:
2685 DRM_DEBUG("invalid pipe %d\n", pipe);
2686 return;
2687 }
2688 } else {
2689 DRM_DEBUG("invalid me %d\n", me);
2690 return;
2691 }
2692
2693 switch (state) {
2694 case AMDGPU_IRQ_STATE_DISABLE:
2695 mec_int_cntl = RREG32(mec_int_cntl_reg);
2696 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2697 TIME_STAMP_INT_ENABLE, 0);
2698 WREG32(mec_int_cntl_reg, mec_int_cntl);
2699 break;
2700 case AMDGPU_IRQ_STATE_ENABLE:
2701 mec_int_cntl = RREG32(mec_int_cntl_reg);
2702 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2703 TIME_STAMP_INT_ENABLE, 1);
2704 WREG32(mec_int_cntl_reg, mec_int_cntl);
2705 break;
2706 default:
2707 break;
2708 }
2709}
2710
2711static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
2712 struct amdgpu_irq_src *source,
2713 unsigned type,
2714 enum amdgpu_interrupt_state state)
2715{
2716 u32 cp_int_cntl;
2717
2718 switch (state) {
2719 case AMDGPU_IRQ_STATE_DISABLE:
2720 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2721 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2722 PRIV_REG_INT_ENABLE, 0);
2723 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2724 break;
2725 case AMDGPU_IRQ_STATE_ENABLE:
2726 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2727 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2728 PRIV_REG_INT_ENABLE, 1);
2729 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2730 break;
2731 default:
2732 break;
2733 }
2734
2735 return 0;
2736}
2737
2738static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
2739 struct amdgpu_irq_src *source,
2740 unsigned type,
2741 enum amdgpu_interrupt_state state)
2742{
2743 u32 cp_int_cntl;
2744
2745 switch (state) {
2746 case AMDGPU_IRQ_STATE_DISABLE:
2747 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2748 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2749 PRIV_INSTR_INT_ENABLE, 0);
2750 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2751 break;
2752 case AMDGPU_IRQ_STATE_ENABLE:
2753 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
2754 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
2755 PRIV_INSTR_INT_ENABLE, 1);
2756 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl);
2757 break;
2758 default:
2759 break;
2760 }
2761
2762 return 0;
2763}
2764
2765static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
2766 struct amdgpu_irq_src *src,
2767 unsigned type,
2768 enum amdgpu_interrupt_state state)
2769{
2770 switch (type) {
2771 case AMDGPU_CP_IRQ_GFX_EOP:
2772 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
2773 break;
2774 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2775 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
2776 break;
2777 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2778 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
2779 break;
2780 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2781 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
2782 break;
2783 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2784 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
2785 break;
2786 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2787 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
2788 break;
2789 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2790 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
2791 break;
2792 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2793 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
2794 break;
2795 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2796 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
2797 break;
2798 default:
2799 break;
2800 }
2801 return 0;
2802}
2803
2804static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
2805 struct amdgpu_irq_src *source,
2806 struct amdgpu_iv_entry *entry)
2807{
2808 int i;
2809 u8 me_id, pipe_id, queue_id;
2810 struct amdgpu_ring *ring;
2811
2812 DRM_DEBUG("IH: CP EOP\n");
2813 me_id = (entry->ring_id & 0x0c) >> 2;
2814 pipe_id = (entry->ring_id & 0x03) >> 0;
2815 queue_id = (entry->ring_id & 0x70) >> 4;
2816
2817 switch (me_id) {
2818 case 0:
2819 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
2820 break;
2821 case 1:
2822 case 2:
2823 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2824 ring = &adev->gfx.compute_ring[i];
2825 /* Per-queue interrupt is supported for MEC starting from VI.
2826 * The interrupt can only be enabled/disabled per pipe instead of per queue.
2827 */
2828 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2829 amdgpu_fence_process(ring);
2830 }
2831 break;
2832 }
2833 return 0;
2834}
2835
2836static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
2837 struct amdgpu_irq_src *source,
2838 struct amdgpu_iv_entry *entry)
2839{
2840 DRM_ERROR("Illegal register access in command stream\n");
2841 schedule_work(&adev->reset_work);
2842 return 0;
2843}
2844
2845static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
2846 struct amdgpu_irq_src *source,
2847 struct amdgpu_iv_entry *entry)
2848{
2849 DRM_ERROR("Illegal instruction in command stream\n");
2850 schedule_work(&adev->reset_work);
2851 return 0;
2852}
2853
2854const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
2855 .name = "gfx_v9_0",
2856 .early_init = gfx_v9_0_early_init,
2857 .late_init = gfx_v9_0_late_init,
2858 .sw_init = gfx_v9_0_sw_init,
2859 .sw_fini = gfx_v9_0_sw_fini,
2860 .hw_init = gfx_v9_0_hw_init,
2861 .hw_fini = gfx_v9_0_hw_fini,
2862 .suspend = gfx_v9_0_suspend,
2863 .resume = gfx_v9_0_resume,
2864 .is_idle = gfx_v9_0_is_idle,
2865 .wait_for_idle = gfx_v9_0_wait_for_idle,
2866 .soft_reset = gfx_v9_0_soft_reset,
2867 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
2868 .set_powergating_state = gfx_v9_0_set_powergating_state,
2869};
2870
2871static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
2872 .type = AMDGPU_RING_TYPE_GFX,
2873 .align_mask = 0xff,
2874 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
2875 .support_64bit_ptrs = true,
2876 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
2877 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
2878 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
2879 .emit_frame_size =
2880 20 + /* gfx_v9_0_ring_emit_gds_switch */
2881 7 + /* gfx_v9_0_ring_emit_hdp_flush */
2882 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
2883 8 + 8 + 8 +/* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
2884 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2885 128 + 66 + /* gfx_v9_0_ring_emit_vm_flush */
2886 2 + /* gfx_v9_ring_emit_sb */
2887 3, /* gfx_v9_ring_emit_cntxcntl */
2888 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
2889 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
2890 .emit_fence = gfx_v9_0_ring_emit_fence,
2891 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
2892 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
2893 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
2894 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
2895 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
2896 .test_ring = gfx_v9_0_ring_test_ring,
2897 .test_ib = gfx_v9_0_ring_test_ib,
2898 .insert_nop = amdgpu_ring_insert_nop,
2899 .pad_ib = amdgpu_ring_generic_pad_ib,
2900 .emit_switch_buffer = gfx_v9_ring_emit_sb,
2901 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
2902};
2903
2904static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
2905 .type = AMDGPU_RING_TYPE_COMPUTE,
2906 .align_mask = 0xff,
2907 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
2908 .support_64bit_ptrs = true,
2909 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
2910 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
2911 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
2912 .emit_frame_size =
2913 20 + /* gfx_v9_0_ring_emit_gds_switch */
2914 7 + /* gfx_v9_0_ring_emit_hdp_flush */
2915 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
2916 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
2917 64 + /* gfx_v9_0_ring_emit_vm_flush */
2918 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
2919 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
2920 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
2921 .emit_fence = gfx_v9_0_ring_emit_fence,
2922 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
2923 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
2924 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
2925 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
2926 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
2927 .test_ring = gfx_v9_0_ring_test_ring,
2928 .test_ib = gfx_v9_0_ring_test_ib,
2929 .insert_nop = amdgpu_ring_insert_nop,
2930 .pad_ib = amdgpu_ring_generic_pad_ib,
2931};
2932
2933
2934static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
2935{
2936 int i;
2937
2938 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2939 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
2940
2941 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2942 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
2943}
2944
2945static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
2946 .set = gfx_v9_0_set_eop_interrupt_state,
2947 .process = gfx_v9_0_eop_irq,
2948};
2949
2950static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
2951 .set = gfx_v9_0_set_priv_reg_fault_state,
2952 .process = gfx_v9_0_priv_reg_irq,
2953};
2954
2955static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
2956 .set = gfx_v9_0_set_priv_inst_fault_state,
2957 .process = gfx_v9_0_priv_inst_irq,
2958};
2959
2960static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
2961{
2962 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
2963 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
2964
2965 adev->gfx.priv_reg_irq.num_types = 1;
2966 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
2967
2968 adev->gfx.priv_inst_irq.num_types = 1;
2969 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
2970}
2971
2972static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
2973{
2974 switch (adev->asic_type) {
2975 case CHIP_VEGA10:
2976 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
2977 break;
2978 default:
2979 break;
2980 }
2981}
2982
2983static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
2984{
2985 /* init asci gds info */
2986 adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
2987 adev->gds.gws.total_size = 64;
2988 adev->gds.oa.total_size = 16;
2989
2990 if (adev->gds.mem.total_size == 64 * 1024) {
2991 adev->gds.mem.gfx_partition_size = 4096;
2992 adev->gds.mem.cs_partition_size = 4096;
2993
2994 adev->gds.gws.gfx_partition_size = 4;
2995 adev->gds.gws.cs_partition_size = 4;
2996
2997 adev->gds.oa.gfx_partition_size = 4;
2998 adev->gds.oa.cs_partition_size = 1;
2999 } else {
3000 adev->gds.mem.gfx_partition_size = 1024;
3001 adev->gds.mem.cs_partition_size = 1024;
3002
3003 adev->gds.gws.gfx_partition_size = 16;
3004 adev->gds.gws.cs_partition_size = 16;
3005
3006 adev->gds.oa.gfx_partition_size = 4;
3007 adev->gds.oa.cs_partition_size = 4;
3008 }
3009}
3010
3011static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3012{
3013 u32 data, mask;
3014
3015 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG));
3016 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG));
3017
3018 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3019 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3020
3021 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3022
3023 return (~data) & mask;
3024}
3025
3026static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3027 struct amdgpu_cu_info *cu_info)
3028{
3029 int i, j, k, counter, active_cu_number = 0;
3030 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3031
3032 if (!adev || !cu_info)
3033 return -EINVAL;
3034
3035 memset(cu_info, 0, sizeof(*cu_info));
3036
3037 mutex_lock(&adev->grbm_idx_mutex);
3038 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3039 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3040 mask = 1;
3041 ao_bitmap = 0;
3042 counter = 0;
3043 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3044 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3045 cu_info->bitmap[i][j] = bitmap;
3046
3047 for (k = 0; k < 16; k ++) {
3048 if (bitmap & mask) {
3049 if (counter < 2)
3050 ao_bitmap |= mask;
3051 counter ++;
3052 }
3053 mask <<= 1;
3054 }
3055 active_cu_number += counter;
3056 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3057 }
3058 }
3059 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3060 mutex_unlock(&adev->grbm_idx_mutex);
3061
3062 cu_info->number = active_cu_number;
3063 cu_info->ao_cu_mask = ao_cu_mask;
3064
3065 return 0;
3066}
3067
3068static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3069{
3070 int r, j;
3071 u32 tmp;
3072 bool use_doorbell = true;
3073 u64 hqd_gpu_addr;
3074 u64 mqd_gpu_addr;
3075 u64 eop_gpu_addr;
3076 u64 wb_gpu_addr;
3077 u32 *buf;
3078 struct v9_mqd *mqd;
3079 struct amdgpu_device *adev;
3080
3081 adev = ring->adev;
3082 if (ring->mqd_obj == NULL) {
3083 r = amdgpu_bo_create(adev,
3084 sizeof(struct v9_mqd),
3085 PAGE_SIZE,true,
3086 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3087 NULL, &ring->mqd_obj);
3088 if (r) {
3089 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3090 return r;
3091 }
3092 }
3093
3094 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3095 if (unlikely(r != 0)) {
3096 gfx_v9_0_cp_compute_fini(adev);
3097 return r;
3098 }
3099
3100 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3101 &mqd_gpu_addr);
3102 if (r) {
3103 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3104 gfx_v9_0_cp_compute_fini(adev);
3105 return r;
3106 }
3107 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3108 if (r) {
3109 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3110 gfx_v9_0_cp_compute_fini(adev);
3111 return r;
3112 }
3113
3114 /* init the mqd struct */
3115 memset(buf, 0, sizeof(struct v9_mqd));
3116
3117 mqd = (struct v9_mqd *)buf;
3118 mqd->header = 0xC0310800;
3119 mqd->compute_pipelinestat_enable = 0x00000001;
3120 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3121 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3122 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3123 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3124 mqd->compute_misc_reserved = 0x00000003;
3125 mutex_lock(&adev->srbm_mutex);
3126 soc15_grbm_select(adev, ring->me,
3127 ring->pipe,
3128 ring->queue, 0);
3129 /* disable wptr polling */
3130 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
3131 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3132 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
3133
3134 /* write the EOP addr */
3135 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3136 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3137 eop_gpu_addr >>= 8;
3138
3139 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr));
3140 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr));
3141 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3142 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3143
3144 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3145 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
3146 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3147 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3148 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp);
3149
3150 /* enable doorbell? */
3151 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3152 if (use_doorbell)
3153 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3154 else
3155 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3156
3157 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp);
3158 mqd->cp_hqd_pq_doorbell_control = tmp;
3159
3160 /* disable the queue if it's active */
3161 ring->wptr = 0;
3162 mqd->cp_hqd_dequeue_request = 0;
3163 mqd->cp_hqd_pq_rptr = 0;
3164 mqd->cp_hqd_pq_wptr_lo = 0;
3165 mqd->cp_hqd_pq_wptr_hi = 0;
3166 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
3167 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
3168 for (j = 0; j < adev->usec_timeout; j++) {
3169 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
3170 break;
3171 udelay(1);
3172 }
3173 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request);
3174 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr);
3175 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3176 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3177 }
3178
3179 /* set the pointer to the MQD */
3180 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3181 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3182 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo);
3183 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi);
3184
3185 /* set MQD vmid to 0 */
3186 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
3187 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3188 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp);
3189 mqd->cp_mqd_control = tmp;
3190
3191 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3192 hqd_gpu_addr = ring->gpu_addr >> 8;
3193 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3194 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3195 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo);
3196 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi);
3197
3198 /* set up the HQD, this is similar to CP_RB0_CNTL */
3199 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
3200 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3201 (order_base_2(ring->ring_size / 4) - 1));
3202 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3203 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3204#ifdef __BIG_ENDIAN
3205 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3206#endif
3207 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3208 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3209 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3210 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3211 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp);
3212 mqd->cp_hqd_pq_control = tmp;
3213
3214 /* set the wb address wether it's enabled or not */
3215 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3216 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3217 mqd->cp_hqd_pq_rptr_report_addr_hi =
3218 upper_32_bits(wb_gpu_addr) & 0xffff;
3219 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
3220 mqd->cp_hqd_pq_rptr_report_addr_lo);
3221 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
3222 mqd->cp_hqd_pq_rptr_report_addr_hi);
3223
3224 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3225 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3226 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3227 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3228 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
3229 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3230 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
3231 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3232
3233 /* enable the doorbell if requested */
3234 if (use_doorbell) {
3235 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
3236 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
3237 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
3238 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
3239 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3240 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3241 DOORBELL_OFFSET, ring->doorbell_index);
3242 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3243 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3244 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3245 mqd->cp_hqd_pq_doorbell_control = tmp;
3246
3247 } else {
3248 mqd->cp_hqd_pq_doorbell_control = 0;
3249 }
3250 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
3251 mqd->cp_hqd_pq_doorbell_control);
3252
3253 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3254 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3255 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3256
3257 /* set the vmid for the queue */
3258 mqd->cp_hqd_vmid = 0;
3259 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
3260
3261 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE));
3262 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3263 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp);
3264 mqd->cp_hqd_persistent_state = tmp;
3265
3266 /* activate the queue */
3267 mqd->cp_hqd_active = 1;
3268 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active);
3269
3270 soc15_grbm_select(adev, 0, 0, 0, 0);
3271 mutex_unlock(&adev->srbm_mutex);
3272
3273 amdgpu_bo_kunmap(ring->mqd_obj);
3274 amdgpu_bo_unreserve(ring->mqd_obj);
3275
3276 if (use_doorbell) {
3277 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
3278 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3279 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
3280 }
3281
3282 return 0;
3283}
3284
3285const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
3286{
3287 .type = AMD_IP_BLOCK_TYPE_GFX,
3288 .major = 9,
3289 .minor = 0,
3290 .rev = 0,
3291 .funcs = &gfx_v9_0_ip_funcs,
3292};
Linux 6.x block layer and io_uring tree(s)