Commit | Line | Data |
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b1023571 KW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
c366be54 SR |
23 | |
24 | #include <linux/delay.h> | |
c1b24a14 | 25 | #include <linux/kernel.h> |
b1023571 | 26 | #include <linux/firmware.h> |
47b757fb SR |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> | |
c366be54 | 29 | |
b1023571 KW |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_gfx.h" | |
32 | #include "soc15.h" | |
33 | #include "soc15d.h" | |
3251c043 | 34 | #include "amdgpu_atomfirmware.h" |
80f41f84 | 35 | #include "amdgpu_pm.h" |
b1023571 | 36 | |
cde5c34f FX |
37 | #include "gc/gc_9_0_offset.h" |
38 | #include "gc/gc_9_0_sh_mask.h" | |
33294eb8 | 39 | |
fb960bd2 | 40 | #include "vega10_enum.h" |
b1023571 KW |
41 | |
42 | #include "soc15_common.h" | |
43 | #include "clearstate_gfx9.h" | |
44 | #include "v9_structs.h" | |
45 | ||
44a99b65 AG |
46 | #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" |
47 | ||
760a1d55 FX |
48 | #include "amdgpu_ras.h" |
49 | ||
0c97a19a | 50 | #include "amdgpu_ring_mux.h" |
4c461d89 | 51 | #include "gfx_v9_4.h" |
825c91d0 | 52 | #include "gfx_v9_0.h" |
16171a25 | 53 | #include "gfx_v9_4_2.h" |
4c461d89 | 54 | |
c76c1a42 TSD |
55 | #include "asic_reg/pwr/pwr_10_0_offset.h" |
56 | #include "asic_reg/pwr/pwr_10_0_sh_mask.h" | |
0a52a6ca | 57 | #include "asic_reg/gc/gc_9_0_default.h" |
c76c1a42 | 58 | |
b1023571 | 59 | #define GFX9_NUM_GFX_RINGS 1 |
0c97a19a | 60 | #define GFX9_NUM_SW_GFX_RINGS 2 |
17e4bd6c | 61 | #define GFX9_MEC_HPD_SIZE 4096 |
6bce4667 HZ |
62 | #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L |
63 | #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L | |
b1023571 | 64 | |
33294eb8 HR |
65 | #define mmGCEA_PROBE_MAP 0x070c |
66 | #define mmGCEA_PROBE_MAP_BASE_IDX 0 | |
67 | ||
b1023571 KW |
68 | MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); |
69 | MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); | |
70 | MODULE_FIRMWARE("amdgpu/vega10_me.bin"); | |
71 | MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); | |
72 | MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); | |
73 | MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); | |
74 | ||
739ffd9b AD |
75 | MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); |
76 | MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); | |
77 | MODULE_FIRMWARE("amdgpu/vega12_me.bin"); | |
78 | MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); | |
79 | MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); | |
80 | MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); | |
81 | ||
940328fe FX |
82 | MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); |
83 | MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); | |
84 | MODULE_FIRMWARE("amdgpu/vega20_me.bin"); | |
85 | MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); | |
86 | MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); | |
87 | MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); | |
88 | ||
060d124b CZ |
89 | MODULE_FIRMWARE("amdgpu/raven_ce.bin"); |
90 | MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); | |
91 | MODULE_FIRMWARE("amdgpu/raven_me.bin"); | |
92 | MODULE_FIRMWARE("amdgpu/raven_mec.bin"); | |
93 | MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); | |
94 | MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); | |
95 | ||
501a580a LG |
96 | MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); |
97 | MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); | |
98 | MODULE_FIRMWARE("amdgpu/picasso_me.bin"); | |
99 | MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); | |
100 | MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); | |
101 | MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); | |
c50fe0c5 | 102 | MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); |
501a580a | 103 | |
cf4b60c6 FX |
104 | MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); |
105 | MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); | |
106 | MODULE_FIRMWARE("amdgpu/raven2_me.bin"); | |
107 | MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); | |
108 | MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); | |
109 | MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); | |
80f41f84 | 110 | MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); |
cf4b60c6 | 111 | |
84519350 | 112 | MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); |
84519350 LM |
113 | MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); |
114 | ||
1aafd447 HR |
115 | MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); |
116 | MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); | |
117 | MODULE_FIRMWARE("amdgpu/renoir_me.bin"); | |
118 | MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); | |
1aafd447 HR |
119 | MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); |
120 | ||
ad698da3 PL |
121 | MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); |
122 | MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); | |
123 | MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); | |
124 | MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); | |
125 | MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); | |
126 | MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); | |
127 | ||
cdf545f3 LM |
128 | MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); |
129 | MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); | |
130 | MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); | |
1d32af4f | 131 | MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); |
132 | MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); | |
cdf545f3 | 133 | |
582870de HZ |
134 | #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 |
135 | #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 | |
136 | #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 | |
137 | #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 | |
138 | #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 | |
139 | #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 | |
140 | #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a | |
141 | #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 | |
142 | #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b | |
143 | #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 | |
144 | #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c | |
145 | #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 | |
146 | ||
7b37c7f8 AD |
147 | #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 |
148 | #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 | |
149 | #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 | |
150 | #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 | |
151 | ||
dc23a08f DL |
152 | enum ta_ras_gfx_subblock { |
153 | /*CPC*/ | |
154 | TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, | |
155 | TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, | |
156 | TA_RAS_BLOCK__GFX_CPC_UCODE, | |
157 | TA_RAS_BLOCK__GFX_DC_STATE_ME1, | |
158 | TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, | |
159 | TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, | |
160 | TA_RAS_BLOCK__GFX_DC_STATE_ME2, | |
161 | TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, | |
162 | TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, | |
163 | TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, | |
164 | /* CPF*/ | |
165 | TA_RAS_BLOCK__GFX_CPF_INDEX_START, | |
166 | TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, | |
167 | TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, | |
168 | TA_RAS_BLOCK__GFX_CPF_TAG, | |
169 | TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, | |
170 | /* CPG*/ | |
171 | TA_RAS_BLOCK__GFX_CPG_INDEX_START, | |
172 | TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, | |
173 | TA_RAS_BLOCK__GFX_CPG_DMA_TAG, | |
174 | TA_RAS_BLOCK__GFX_CPG_TAG, | |
175 | TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, | |
176 | /* GDS*/ | |
177 | TA_RAS_BLOCK__GFX_GDS_INDEX_START, | |
178 | TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, | |
179 | TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, | |
180 | TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, | |
181 | TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, | |
182 | TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, | |
183 | TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, | |
184 | /* SPI*/ | |
185 | TA_RAS_BLOCK__GFX_SPI_SR_MEM, | |
186 | /* SQ*/ | |
187 | TA_RAS_BLOCK__GFX_SQ_INDEX_START, | |
188 | TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, | |
189 | TA_RAS_BLOCK__GFX_SQ_LDS_D, | |
190 | TA_RAS_BLOCK__GFX_SQ_LDS_I, | |
191 | TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ | |
192 | TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, | |
193 | /* SQC (3 ranges)*/ | |
194 | TA_RAS_BLOCK__GFX_SQC_INDEX_START, | |
195 | /* SQC range 0*/ | |
196 | TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, | |
197 | TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = | |
198 | TA_RAS_BLOCK__GFX_SQC_INDEX0_START, | |
199 | TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, | |
200 | TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, | |
201 | TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, | |
202 | TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, | |
203 | TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, | |
204 | TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, | |
205 | TA_RAS_BLOCK__GFX_SQC_INDEX0_END = | |
206 | TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, | |
207 | /* SQC range 1*/ | |
208 | TA_RAS_BLOCK__GFX_SQC_INDEX1_START, | |
209 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = | |
210 | TA_RAS_BLOCK__GFX_SQC_INDEX1_START, | |
211 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, | |
212 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, | |
213 | TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, | |
214 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, | |
215 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, | |
216 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, | |
217 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, | |
218 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, | |
219 | TA_RAS_BLOCK__GFX_SQC_INDEX1_END = | |
220 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, | |
221 | /* SQC range 2*/ | |
222 | TA_RAS_BLOCK__GFX_SQC_INDEX2_START, | |
223 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = | |
224 | TA_RAS_BLOCK__GFX_SQC_INDEX2_START, | |
225 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, | |
226 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, | |
227 | TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, | |
228 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, | |
229 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, | |
230 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, | |
231 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, | |
232 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, | |
233 | TA_RAS_BLOCK__GFX_SQC_INDEX2_END = | |
234 | TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, | |
235 | TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, | |
236 | /* TA*/ | |
237 | TA_RAS_BLOCK__GFX_TA_INDEX_START, | |
238 | TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, | |
239 | TA_RAS_BLOCK__GFX_TA_FS_AFIFO, | |
240 | TA_RAS_BLOCK__GFX_TA_FL_LFIFO, | |
241 | TA_RAS_BLOCK__GFX_TA_FX_LFIFO, | |
242 | TA_RAS_BLOCK__GFX_TA_FS_CFIFO, | |
243 | TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, | |
244 | /* TCA*/ | |
245 | TA_RAS_BLOCK__GFX_TCA_INDEX_START, | |
246 | TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, | |
247 | TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, | |
248 | TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, | |
249 | /* TCC (5 sub-ranges)*/ | |
250 | TA_RAS_BLOCK__GFX_TCC_INDEX_START, | |
251 | /* TCC range 0*/ | |
252 | TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, | |
253 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, | |
254 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, | |
255 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, | |
256 | TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, | |
257 | TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, | |
258 | TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, | |
259 | TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, | |
260 | TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, | |
261 | TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, | |
262 | /* TCC range 1*/ | |
263 | TA_RAS_BLOCK__GFX_TCC_INDEX1_START, | |
264 | TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, | |
265 | TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, | |
266 | TA_RAS_BLOCK__GFX_TCC_INDEX1_END = | |
267 | TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, | |
268 | /* TCC range 2*/ | |
269 | TA_RAS_BLOCK__GFX_TCC_INDEX2_START, | |
270 | TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, | |
271 | TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, | |
272 | TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, | |
273 | TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, | |
274 | TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, | |
275 | TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, | |
276 | TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, | |
277 | TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, | |
278 | TA_RAS_BLOCK__GFX_TCC_INDEX2_END = | |
279 | TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, | |
280 | /* TCC range 3*/ | |
281 | TA_RAS_BLOCK__GFX_TCC_INDEX3_START, | |
282 | TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, | |
283 | TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, | |
284 | TA_RAS_BLOCK__GFX_TCC_INDEX3_END = | |
285 | TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, | |
286 | /* TCC range 4*/ | |
287 | TA_RAS_BLOCK__GFX_TCC_INDEX4_START, | |
288 | TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = | |
289 | TA_RAS_BLOCK__GFX_TCC_INDEX4_START, | |
290 | TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, | |
291 | TA_RAS_BLOCK__GFX_TCC_INDEX4_END = | |
292 | TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, | |
293 | TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, | |
294 | /* TCI*/ | |
295 | TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, | |
296 | /* TCP*/ | |
297 | TA_RAS_BLOCK__GFX_TCP_INDEX_START, | |
298 | TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, | |
299 | TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, | |
300 | TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, | |
301 | TA_RAS_BLOCK__GFX_TCP_VM_FIFO, | |
302 | TA_RAS_BLOCK__GFX_TCP_DB_RAM, | |
303 | TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, | |
304 | TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, | |
305 | TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, | |
306 | /* TD*/ | |
307 | TA_RAS_BLOCK__GFX_TD_INDEX_START, | |
308 | TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, | |
309 | TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, | |
310 | TA_RAS_BLOCK__GFX_TD_CS_FIFO, | |
311 | TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, | |
312 | /* EA (3 sub-ranges)*/ | |
313 | TA_RAS_BLOCK__GFX_EA_INDEX_START, | |
314 | /* EA range 0*/ | |
315 | TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, | |
316 | TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, | |
317 | TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, | |
318 | TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, | |
319 | TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, | |
320 | TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, | |
321 | TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, | |
322 | TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, | |
323 | TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, | |
324 | TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, | |
325 | /* EA range 1*/ | |
326 | TA_RAS_BLOCK__GFX_EA_INDEX1_START, | |
327 | TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, | |
328 | TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, | |
329 | TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, | |
330 | TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, | |
331 | TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, | |
332 | TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, | |
333 | TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, | |
334 | TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, | |
335 | /* EA range 2*/ | |
336 | TA_RAS_BLOCK__GFX_EA_INDEX2_START, | |
337 | TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, | |
338 | TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, | |
339 | TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, | |
340 | TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, | |
341 | TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, | |
342 | TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, | |
343 | /* UTC VM L2 bank*/ | |
344 | TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, | |
345 | /* UTC VM walker*/ | |
346 | TA_RAS_BLOCK__UTC_VML2_WALKER, | |
347 | /* UTC ATC L2 2MB cache*/ | |
348 | TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, | |
349 | /* UTC ATC L2 4KB cache*/ | |
350 | TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, | |
351 | TA_RAS_BLOCK__GFX_MAX | |
352 | }; | |
2c960ea0 DL |
353 | |
354 | struct ras_gfx_subblock { | |
355 | unsigned char *name; | |
356 | int ta_subblock; | |
dc4d716d DL |
357 | int hw_supported_error_type; |
358 | int sw_supported_error_type; | |
2c960ea0 DL |
359 | }; |
360 | ||
dc4d716d | 361 | #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ |
2c960ea0 DL |
362 | [AMDGPU_RAS_BLOCK__##subblock] = { \ |
363 | #subblock, \ | |
364 | TA_RAS_BLOCK__##subblock, \ | |
365 | ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ | |
dc4d716d | 366 | (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ |
2c960ea0 DL |
367 | } |
368 | ||
369 | static const struct ras_gfx_subblock ras_gfx_subblocks[] = { | |
dc4d716d DL |
370 | AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), |
371 | AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), | |
372 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), | |
373 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), | |
374 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), | |
375 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), | |
376 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), | |
377 | AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), | |
378 | AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), | |
379 | AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), | |
380 | AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), | |
381 | AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), | |
382 | AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), | |
383 | AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), | |
384 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
385 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), | |
386 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, | |
387 | 0), | |
388 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, | |
389 | 0), | |
390 | AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
391 | AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
392 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), | |
393 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), | |
394 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), | |
395 | AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), | |
396 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), | |
397 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, | |
398 | 0, 0), | |
399 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, | |
400 | 0), | |
401 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, | |
402 | 0, 0), | |
403 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, | |
404 | 0), | |
405 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, | |
406 | 0, 0), | |
407 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, | |
408 | 0), | |
409 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, | |
410 | 1), | |
411 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, | |
412 | 0, 0, 0), | |
413 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
414 | 0), | |
415 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, | |
416 | 0), | |
417 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, | |
418 | 0), | |
419 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
420 | 0), | |
421 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
422 | 0), | |
423 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, | |
424 | 0, 0), | |
425 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, | |
426 | 0), | |
427 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, | |
428 | 0), | |
429 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, | |
430 | 0, 0, 0), | |
431 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
432 | 0), | |
433 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, | |
434 | 0), | |
435 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, | |
436 | 0), | |
437 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
438 | 0), | |
439 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
440 | 0), | |
441 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, | |
442 | 0, 0), | |
443 | AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, | |
444 | 0), | |
445 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), | |
446 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
447 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
448 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
449 | AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
450 | AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), | |
451 | AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
452 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), | |
453 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, | |
454 | 1), | |
455 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, | |
456 | 1), | |
457 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, | |
458 | 1), | |
459 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, | |
460 | 0), | |
461 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, | |
462 | 0), | |
463 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), | |
464 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), | |
465 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), | |
466 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), | |
467 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), | |
468 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), | |
469 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
470 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), | |
471 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), | |
472 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), | |
473 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), | |
474 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, | |
475 | 0), | |
476 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
477 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, | |
478 | 0), | |
479 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, | |
480 | 0, 0), | |
481 | AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, | |
482 | 0), | |
483 | AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), | |
484 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), | |
485 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), | |
486 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
487 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), | |
488 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), | |
489 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), | |
490 | AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), | |
491 | AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), | |
492 | AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), | |
493 | AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), | |
494 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), | |
495 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
496 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
497 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
498 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
499 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
500 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
501 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), | |
502 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
503 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
504 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
505 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
506 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
507 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
508 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
509 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
510 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
511 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
512 | AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), | |
513 | AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), | |
514 | AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), | |
515 | AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), | |
516 | AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), | |
2c960ea0 DL |
517 | }; |
518 | ||
946a4d5b SL |
519 | static const struct soc15_reg_golden golden_settings_gc_9_0[] = |
520 | { | |
54d682d9 | 521 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), |
c55045ad | 522 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), |
946a4d5b | 523 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), |
946a4d5b SL |
524 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), |
525 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), | |
526 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), | |
946a4d5b | 527 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), |
c5fb5426 FX |
528 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), |
529 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), | |
25f43a32 OZ |
530 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), |
531 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), | |
946a4d5b SL |
532 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), |
533 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), | |
534 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), | |
535 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), | |
536 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), | |
919a94d8 | 537 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), |
ff9d0971 TY |
538 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), |
539 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), | |
540 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) | |
b1023571 KW |
541 | }; |
542 | ||
946a4d5b | 543 | static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = |
b1023571 | 544 | { |
946a4d5b SL |
545 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), |
546 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), | |
e6d57520 FX |
547 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), |
548 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), | |
549 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), | |
946a4d5b SL |
550 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), |
551 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), | |
e6d57520 | 552 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), |
946a4d5b | 553 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), |
e6d57520 FX |
554 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), |
555 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), | |
556 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), | |
557 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), | |
558 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), | |
946a4d5b | 559 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), |
e6d57520 FX |
560 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), |
561 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), | |
919a94d8 | 562 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) |
b1023571 KW |
563 | }; |
564 | ||
bb5368aa FX |
565 | static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = |
566 | { | |
ac26b0f3 | 567 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), |
bb5368aa FX |
568 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), |
569 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), | |
570 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), | |
571 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), | |
572 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), | |
573 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), | |
574 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), | |
575 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), | |
576 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), | |
577 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) | |
578 | }; | |
579 | ||
946a4d5b SL |
580 | static const struct soc15_reg_golden golden_settings_gc_9_1[] = |
581 | { | |
582 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), | |
583 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), | |
584 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), | |
585 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), | |
586 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), | |
587 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), | |
588 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), | |
589 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), | |
590 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), | |
591 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), | |
592 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), | |
593 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), | |
594 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), | |
595 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), | |
596 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), | |
597 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), | |
598 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), | |
599 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), | |
600 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), | |
601 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), | |
f9f97e3c | 602 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), |
ff9d0971 TY |
603 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), |
604 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), | |
605 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) | |
a5fdb336 CZ |
606 | }; |
607 | ||
946a4d5b | 608 | static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = |
a5fdb336 | 609 | { |
946a4d5b SL |
610 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), |
611 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), | |
612 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), | |
613 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), | |
614 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), | |
615 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), | |
616 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) | |
b1023571 KW |
617 | }; |
618 | ||
28ab1229 FX |
619 | static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = |
620 | { | |
621 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), | |
622 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), | |
623 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), | |
624 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), | |
625 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), | |
626 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), | |
627 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), | |
628 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), | |
629 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), | |
630 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), | |
631 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), | |
632 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), | |
633 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), | |
634 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), | |
635 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), | |
636 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), | |
637 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), | |
638 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), | |
639 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), | |
640 | }; | |
641 | ||
33294eb8 HR |
642 | static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = |
643 | { | |
33294eb8 HR |
644 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), |
645 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), | |
646 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), | |
f13580a9 AL |
647 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), |
648 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), | |
33294eb8 HR |
649 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), |
650 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), | |
651 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), | |
652 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), | |
653 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), | |
654 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), | |
655 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), | |
656 | }; | |
657 | ||
946a4d5b | 658 | static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = |
f5eaffcc | 659 | { |
f7b1844b | 660 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), |
946a4d5b SL |
661 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), |
662 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) | |
f5eaffcc KW |
663 | }; |
664 | ||
62b35f9a HZ |
665 | static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = |
666 | { | |
667 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), | |
668 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), | |
669 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), | |
670 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), | |
671 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), | |
672 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), | |
673 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), | |
674 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), | |
675 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), | |
676 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), | |
677 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), | |
678 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), | |
679 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), | |
680 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), | |
681 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), | |
682 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) | |
683 | }; | |
684 | ||
685 | static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = | |
686 | { | |
687 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), | |
688 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), | |
689 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), | |
690 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), | |
691 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), | |
692 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), | |
693 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), | |
694 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), | |
695 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), | |
f9f97e3c | 696 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), |
ff9d0971 TY |
697 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), |
698 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), | |
699 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) | |
62b35f9a HZ |
700 | }; |
701 | ||
582870de HZ |
702 | static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = |
703 | { | |
704 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), | |
705 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), | |
706 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), | |
707 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), | |
708 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), | |
709 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), | |
710 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), | |
711 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), | |
361d66ed | 712 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), |
6e04b224 | 713 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), |
5a58abf5 | 714 | SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) |
582870de HZ |
715 | }; |
716 | ||
2e0cc4d4 ML |
717 | static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { |
718 | {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, | |
719 | {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, | |
720 | }; | |
721 | ||
727b888f HR |
722 | static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = |
723 | { | |
724 | mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
725 | mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
726 | mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
727 | mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
728 | mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
729 | mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
730 | mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
731 | mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, | |
732 | }; | |
733 | ||
734 | static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = | |
735 | { | |
736 | mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
737 | mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
738 | mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
739 | mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
740 | mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
741 | mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
742 | mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
743 | mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, | |
744 | }; | |
745 | ||
b1023571 | 746 | #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 |
62b35f9a | 747 | #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 |
7b6ba9ea | 748 | #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 |
28ab1229 | 749 | #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 |
b1023571 KW |
750 | |
751 | static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); | |
752 | static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); | |
753 | static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); | |
754 | static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); | |
755 | static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, | |
99dac206 | 756 | struct amdgpu_cu_info *cu_info); |
b1023571 | 757 | static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); |
cfdce594 | 758 | static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds); |
eb03e795 | 759 | static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); |
8b0fb0e9 | 760 | static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, |
2c960ea0 DL |
761 | void *ras_error_status); |
762 | static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, | |
2c22ed0b | 763 | void *inject_if, uint32_t instance_mask); |
279375c3 | 764 | static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); |
08b6e172 AD |
765 | static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, |
766 | unsigned int vmid); | |
b1023571 | 767 | |
f167ea6a AS |
768 | static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, |
769 | uint64_t queue_mask) | |
770 | { | |
771 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); | |
772 | amdgpu_ring_write(kiq_ring, | |
773 | PACKET3_SET_RESOURCES_VMID_MASK(0) | | |
774 | /* vmid_mask:0* queue_type:0 (KIQ) */ | |
775 | PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); | |
776 | amdgpu_ring_write(kiq_ring, | |
777 | lower_32_bits(queue_mask)); /* queue mask lo */ | |
778 | amdgpu_ring_write(kiq_ring, | |
779 | upper_32_bits(queue_mask)); /* queue mask hi */ | |
780 | amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ | |
781 | amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ | |
782 | amdgpu_ring_write(kiq_ring, 0); /* oac mask */ | |
783 | amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ | |
784 | } | |
785 | ||
786 | static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, | |
787 | struct amdgpu_ring *ring) | |
788 | { | |
f167ea6a | 789 | uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); |
3748424b | 790 | uint64_t wptr_addr = ring->wptr_gpu_addr; |
f167ea6a AS |
791 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; |
792 | ||
793 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); | |
794 | /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ | |
795 | amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ | |
796 | PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ | |
797 | PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ | |
798 | PACKET3_MAP_QUEUES_QUEUE(ring->queue) | | |
799 | PACKET3_MAP_QUEUES_PIPE(ring->pipe) | | |
800 | PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | | |
801 | /*queue_type: normal compute queue */ | |
802 | PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | | |
803 | /* alloc format: all_on_one_pipe */ | |
804 | PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | | |
805 | PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | | |
806 | /* num_queues: must be 1 */ | |
807 | PACKET3_MAP_QUEUES_NUM_QUEUES(1)); | |
808 | amdgpu_ring_write(kiq_ring, | |
809 | PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); | |
810 | amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); | |
811 | amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); | |
812 | amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); | |
813 | amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); | |
814 | } | |
815 | ||
816 | static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, | |
817 | struct amdgpu_ring *ring, | |
818 | enum amdgpu_unmap_queues_action action, | |
819 | u64 gpu_addr, u64 seq) | |
820 | { | |
821 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; | |
822 | ||
823 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); | |
824 | amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ | |
825 | PACKET3_UNMAP_QUEUES_ACTION(action) | | |
826 | PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | | |
827 | PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | | |
828 | PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); | |
829 | amdgpu_ring_write(kiq_ring, | |
830 | PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); | |
831 | ||
832 | if (action == PREEMPT_QUEUES_NO_UNMAP) { | |
be254550 JZ |
833 | amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); |
834 | amdgpu_ring_write(kiq_ring, 0); | |
835 | amdgpu_ring_write(kiq_ring, 0); | |
836 | ||
f167ea6a AS |
837 | } else { |
838 | amdgpu_ring_write(kiq_ring, 0); | |
839 | amdgpu_ring_write(kiq_ring, 0); | |
840 | amdgpu_ring_write(kiq_ring, 0); | |
841 | } | |
842 | } | |
843 | ||
844 | static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, | |
845 | struct amdgpu_ring *ring, | |
846 | u64 addr, | |
847 | u64 seq) | |
848 | { | |
849 | uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; | |
850 | ||
851 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); | |
852 | amdgpu_ring_write(kiq_ring, | |
853 | PACKET3_QUERY_STATUS_CONTEXT_ID(0) | | |
854 | PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | | |
855 | PACKET3_QUERY_STATUS_COMMAND(2)); | |
856 | /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ | |
857 | amdgpu_ring_write(kiq_ring, | |
858 | PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | | |
859 | PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); | |
860 | amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); | |
861 | amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); | |
862 | amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); | |
863 | amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); | |
864 | } | |
865 | ||
58e508b6 AS |
866 | static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, |
867 | uint16_t pasid, uint32_t flush_type, | |
868 | bool all_hub) | |
869 | { | |
870 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); | |
871 | amdgpu_ring_write(kiq_ring, | |
872 | PACKET3_INVALIDATE_TLBS_DST_SEL(1) | | |
873 | PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | | |
874 | PACKET3_INVALIDATE_TLBS_PASID(pasid) | | |
875 | PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); | |
876 | } | |
877 | ||
f167ea6a AS |
878 | static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { |
879 | .kiq_set_resources = gfx_v9_0_kiq_set_resources, | |
880 | .kiq_map_queues = gfx_v9_0_kiq_map_queues, | |
881 | .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, | |
882 | .kiq_query_status = gfx_v9_0_kiq_query_status, | |
58e508b6 | 883 | .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, |
f167ea6a AS |
884 | .set_resources_size = 8, |
885 | .map_queues_size = 7, | |
886 | .unmap_queues_size = 6, | |
887 | .query_status_size = 7, | |
36a1707a | 888 | .invalidate_tlbs_size = 2, |
f167ea6a AS |
889 | }; |
890 | ||
891 | static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) | |
892 | { | |
277bd337 | 893 | adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; |
f167ea6a AS |
894 | } |
895 | ||
b1023571 KW |
896 | static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) |
897 | { | |
1d789535 | 898 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 | 899 | case IP_VERSION(9, 0, 1): |
4cd4c5c0 ML |
900 | soc15_program_register_sequence(adev, |
901 | golden_settings_gc_9_0, | |
902 | ARRAY_SIZE(golden_settings_gc_9_0)); | |
903 | soc15_program_register_sequence(adev, | |
904 | golden_settings_gc_9_0_vg10, | |
905 | ARRAY_SIZE(golden_settings_gc_9_0_vg10)); | |
b1023571 | 906 | break; |
9d0cb2c3 | 907 | case IP_VERSION(9, 2, 1): |
62b35f9a HZ |
908 | soc15_program_register_sequence(adev, |
909 | golden_settings_gc_9_2_1, | |
910 | ARRAY_SIZE(golden_settings_gc_9_2_1)); | |
911 | soc15_program_register_sequence(adev, | |
912 | golden_settings_gc_9_2_1_vg12, | |
913 | ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); | |
d5e8ef06 | 914 | break; |
9d0cb2c3 | 915 | case IP_VERSION(9, 4, 0): |
bb5368aa FX |
916 | soc15_program_register_sequence(adev, |
917 | golden_settings_gc_9_0, | |
918 | ARRAY_SIZE(golden_settings_gc_9_0)); | |
919 | soc15_program_register_sequence(adev, | |
920 | golden_settings_gc_9_0_vg20, | |
921 | ARRAY_SIZE(golden_settings_gc_9_0_vg20)); | |
922 | break; | |
9d0cb2c3 | 923 | case IP_VERSION(9, 4, 1): |
582870de HZ |
924 | soc15_program_register_sequence(adev, |
925 | golden_settings_gc_9_4_1_arct, | |
926 | ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); | |
927 | break; | |
9d0cb2c3 AD |
928 | case IP_VERSION(9, 2, 2): |
929 | case IP_VERSION(9, 1, 0): | |
28ab1229 FX |
930 | soc15_program_register_sequence(adev, golden_settings_gc_9_1, |
931 | ARRAY_SIZE(golden_settings_gc_9_1)); | |
54f78a76 | 932 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
28ab1229 FX |
933 | soc15_program_register_sequence(adev, |
934 | golden_settings_gc_9_1_rv2, | |
935 | ARRAY_SIZE(golden_settings_gc_9_1_rv2)); | |
936 | else | |
937 | soc15_program_register_sequence(adev, | |
938 | golden_settings_gc_9_1_rv1, | |
939 | ARRAY_SIZE(golden_settings_gc_9_1_rv1)); | |
940 | break; | |
9d0cb2c3 | 941 | case IP_VERSION(9, 3, 0): |
33294eb8 HR |
942 | soc15_program_register_sequence(adev, |
943 | golden_settings_gc_9_1_rn, | |
944 | ARRAY_SIZE(golden_settings_gc_9_1_rn)); | |
f13580a9 | 945 | return; /* for renoir, don't need common goldensetting */ |
9d0cb2c3 | 946 | case IP_VERSION(9, 4, 2): |
264aef8b HZ |
947 | gfx_v9_4_2_init_golden_registers(adev, |
948 | adev->smuio.funcs->get_die_id(adev)); | |
949 | break; | |
b1023571 KW |
950 | default: |
951 | break; | |
952 | } | |
f5eaffcc | 953 | |
1d789535 AD |
954 | if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && |
955 | (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) | |
f9cf36fc HZ |
956 | soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, |
957 | (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); | |
b1023571 KW |
958 | } |
959 | ||
b1023571 KW |
960 | static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, |
961 | bool wc, uint32_t reg, uint32_t val) | |
962 | { | |
963 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
964 | amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | | |
965 | WRITE_DATA_DST_SEL(0) | | |
966 | (wc ? WR_CONFIRM : 0)); | |
967 | amdgpu_ring_write(ring, reg); | |
968 | amdgpu_ring_write(ring, 0); | |
969 | amdgpu_ring_write(ring, val); | |
970 | } | |
971 | ||
972 | static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, | |
973 | int mem_space, int opt, uint32_t addr0, | |
974 | uint32_t addr1, uint32_t ref, uint32_t mask, | |
975 | uint32_t inv) | |
976 | { | |
977 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); | |
978 | amdgpu_ring_write(ring, | |
979 | /* memory (1) or register (0) */ | |
980 | (WAIT_REG_MEM_MEM_SPACE(mem_space) | | |
981 | WAIT_REG_MEM_OPERATION(opt) | /* wait */ | |
982 | WAIT_REG_MEM_FUNCTION(3) | /* equal */ | |
983 | WAIT_REG_MEM_ENGINE(eng_sel))); | |
984 | ||
985 | if (mem_space) | |
986 | BUG_ON(addr0 & 0x3); /* Dword align */ | |
987 | amdgpu_ring_write(ring, addr0); | |
988 | amdgpu_ring_write(ring, addr1); | |
989 | amdgpu_ring_write(ring, ref); | |
990 | amdgpu_ring_write(ring, mask); | |
991 | amdgpu_ring_write(ring, inv); /* poll interval */ | |
992 | } | |
993 | ||
994 | static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) | |
995 | { | |
996 | struct amdgpu_device *adev = ring->adev; | |
dc2b9c70 | 997 | uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); |
b1023571 KW |
998 | uint32_t tmp = 0; |
999 | unsigned i; | |
1000 | int r; | |
1001 | ||
dc2b9c70 | 1002 | WREG32(scratch, 0xCAFEDEAD); |
b1023571 | 1003 | r = amdgpu_ring_alloc(ring, 3); |
dc9eeff8 | 1004 | if (r) |
d54762cc | 1005 | return r; |
dc9eeff8 | 1006 | |
b1023571 | 1007 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); |
dc2b9c70 | 1008 | amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); |
b1023571 KW |
1009 | amdgpu_ring_write(ring, 0xDEADBEEF); |
1010 | amdgpu_ring_commit(ring); | |
1011 | ||
1012 | for (i = 0; i < adev->usec_timeout; i++) { | |
dc2b9c70 | 1013 | tmp = RREG32(scratch); |
b1023571 KW |
1014 | if (tmp == 0xDEADBEEF) |
1015 | break; | |
c366be54 | 1016 | udelay(1); |
b1023571 | 1017 | } |
dc9eeff8 CK |
1018 | |
1019 | if (i >= adev->usec_timeout) | |
1020 | r = -ETIMEDOUT; | |
b1023571 KW |
1021 | return r; |
1022 | } | |
1023 | ||
1024 | static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) | |
1025 | { | |
ed9324af ML |
1026 | struct amdgpu_device *adev = ring->adev; |
1027 | struct amdgpu_ib ib; | |
1028 | struct dma_fence *f = NULL; | |
1029 | ||
1030 | unsigned index; | |
1031 | uint64_t gpu_addr; | |
1032 | uint32_t tmp; | |
1033 | long r; | |
1034 | ||
1035 | r = amdgpu_device_wb_get(adev, &index); | |
98079389 | 1036 | if (r) |
ed9324af | 1037 | return r; |
ed9324af ML |
1038 | |
1039 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
1040 | adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); | |
1041 | memset(&ib, 0, sizeof(ib)); | |
c8e42d57 | 1042 | r = amdgpu_ib_get(adev, NULL, 16, |
1043 | AMDGPU_IB_POOL_DIRECT, &ib); | |
98079389 | 1044 | if (r) |
ed9324af | 1045 | goto err1; |
98079389 | 1046 | |
ed9324af ML |
1047 | ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); |
1048 | ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; | |
1049 | ib.ptr[2] = lower_32_bits(gpu_addr); | |
1050 | ib.ptr[3] = upper_32_bits(gpu_addr); | |
1051 | ib.ptr[4] = 0xDEADBEEF; | |
1052 | ib.length_dw = 5; | |
b1023571 | 1053 | |
ed9324af ML |
1054 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); |
1055 | if (r) | |
1056 | goto err2; | |
b1023571 | 1057 | |
ed9324af ML |
1058 | r = dma_fence_wait_timeout(f, false, timeout); |
1059 | if (r == 0) { | |
98079389 CK |
1060 | r = -ETIMEDOUT; |
1061 | goto err2; | |
ed9324af | 1062 | } else if (r < 0) { |
98079389 | 1063 | goto err2; |
ed9324af ML |
1064 | } |
1065 | ||
1066 | tmp = adev->wb.wb[index]; | |
98079389 CK |
1067 | if (tmp == 0xDEADBEEF) |
1068 | r = 0; | |
1069 | else | |
1070 | r = -EINVAL; | |
b1023571 | 1071 | |
b1023571 | 1072 | err2: |
ed9324af ML |
1073 | amdgpu_ib_free(adev, &ib, NULL); |
1074 | dma_fence_put(f); | |
b1023571 | 1075 | err1: |
ed9324af ML |
1076 | amdgpu_device_wb_free(adev, index); |
1077 | return r; | |
b1023571 KW |
1078 | } |
1079 | ||
c833d8aa ML |
1080 | |
1081 | static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) | |
1082 | { | |
ec787deb ML |
1083 | amdgpu_ucode_release(&adev->gfx.pfp_fw); |
1084 | amdgpu_ucode_release(&adev->gfx.me_fw); | |
1085 | amdgpu_ucode_release(&adev->gfx.ce_fw); | |
1086 | amdgpu_ucode_release(&adev->gfx.rlc_fw); | |
1087 | amdgpu_ucode_release(&adev->gfx.mec_fw); | |
1088 | amdgpu_ucode_release(&adev->gfx.mec2_fw); | |
c833d8aa ML |
1089 | |
1090 | kfree(adev->gfx.rlc.register_list_format); | |
1091 | } | |
1092 | ||
39b62541 ED |
1093 | static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) |
1094 | { | |
1095 | adev->gfx.me_fw_write_wait = false; | |
1096 | adev->gfx.mec_fw_write_wait = false; | |
1097 | ||
1d789535 | 1098 | if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && |
14008574 | 1099 | ((adev->gfx.mec_fw_version < 0x000001a5) || |
11c61089 | 1100 | (adev->gfx.mec_feature_version < 46) || |
1101 | (adev->gfx.pfp_fw_version < 0x000000b7) || | |
14008574 | 1102 | (adev->gfx.pfp_feature_version < 46))) |
48ccd5ff | 1103 | DRM_WARN_ONCE("CP firmware version too old, please update!"); |
11c61089 | 1104 | |
1d789535 | 1105 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 | 1106 | case IP_VERSION(9, 0, 1): |
39b62541 ED |
1107 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1108 | (adev->gfx.me_feature_version >= 42) && | |
1109 | (adev->gfx.pfp_fw_version >= 0x000000b1) && | |
1110 | (adev->gfx.pfp_feature_version >= 42)) | |
1111 | adev->gfx.me_fw_write_wait = true; | |
1112 | ||
1113 | if ((adev->gfx.mec_fw_version >= 0x00000193) && | |
1114 | (adev->gfx.mec_feature_version >= 42)) | |
1115 | adev->gfx.mec_fw_write_wait = true; | |
1116 | break; | |
9d0cb2c3 | 1117 | case IP_VERSION(9, 2, 1): |
39b62541 ED |
1118 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1119 | (adev->gfx.me_feature_version >= 44) && | |
1120 | (adev->gfx.pfp_fw_version >= 0x000000b2) && | |
1121 | (adev->gfx.pfp_feature_version >= 44)) | |
1122 | adev->gfx.me_fw_write_wait = true; | |
1123 | ||
1124 | if ((adev->gfx.mec_fw_version >= 0x00000196) && | |
1125 | (adev->gfx.mec_feature_version >= 44)) | |
1126 | adev->gfx.mec_fw_write_wait = true; | |
1127 | break; | |
9d0cb2c3 | 1128 | case IP_VERSION(9, 4, 0): |
39b62541 ED |
1129 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1130 | (adev->gfx.me_feature_version >= 44) && | |
1131 | (adev->gfx.pfp_fw_version >= 0x000000b2) && | |
1132 | (adev->gfx.pfp_feature_version >= 44)) | |
1133 | adev->gfx.me_fw_write_wait = true; | |
1134 | ||
1135 | if ((adev->gfx.mec_fw_version >= 0x00000197) && | |
1136 | (adev->gfx.mec_feature_version >= 44)) | |
1137 | adev->gfx.mec_fw_write_wait = true; | |
1138 | break; | |
9d0cb2c3 AD |
1139 | case IP_VERSION(9, 1, 0): |
1140 | case IP_VERSION(9, 2, 2): | |
39b62541 ED |
1141 | if ((adev->gfx.me_fw_version >= 0x0000009c) && |
1142 | (adev->gfx.me_feature_version >= 42) && | |
1143 | (adev->gfx.pfp_fw_version >= 0x000000b1) && | |
1144 | (adev->gfx.pfp_feature_version >= 42)) | |
1145 | adev->gfx.me_fw_write_wait = true; | |
1146 | ||
1147 | if ((adev->gfx.mec_fw_version >= 0x00000192) && | |
1148 | (adev->gfx.mec_feature_version >= 42)) | |
1149 | adev->gfx.mec_fw_write_wait = true; | |
1150 | break; | |
a00ead2b | 1151 | default: |
ba714a56 AL |
1152 | adev->gfx.me_fw_write_wait = true; |
1153 | adev->gfx.mec_fw_write_wait = true; | |
a00ead2b | 1154 | break; |
39b62541 ED |
1155 | } |
1156 | } | |
1157 | ||
7af2a577 AD |
1158 | struct amdgpu_gfxoff_quirk { |
1159 | u16 chip_vendor; | |
1160 | u16 chip_device; | |
1161 | u16 subsys_vendor; | |
1162 | u16 subsys_device; | |
1163 | u8 revision; | |
1164 | }; | |
1165 | ||
1166 | static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { | |
1167 | /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ | |
1168 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, | |
079c72ad AD |
1169 | /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ |
1170 | { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, | |
b0be3c3a TSD |
1171 | /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ |
1172 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, | |
9b6a1ec7 TM |
1173 | /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ |
1174 | { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, | |
7af2a577 AD |
1175 | { 0, 0, 0, 0, 0 }, |
1176 | }; | |
1177 | ||
1178 | static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) | |
1179 | { | |
1180 | const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; | |
1181 | ||
1182 | while (p && p->chip_device != 0) { | |
1183 | if (pdev->vendor == p->chip_vendor && | |
1184 | pdev->device == p->chip_device && | |
1185 | pdev->subsystem_vendor == p->subsys_vendor && | |
1186 | pdev->subsystem_device == p->subsys_device && | |
1187 | pdev->revision == p->revision) { | |
1188 | return true; | |
1189 | } | |
1190 | ++p; | |
1191 | } | |
1192 | return false; | |
1193 | } | |
1194 | ||
f61f01b1 | 1195 | static bool is_raven_kicker(struct amdgpu_device *adev) |
1196 | { | |
1197 | if (adev->pm.fw_version >= 0x41e2b) | |
1198 | return true; | |
1199 | else | |
1200 | return false; | |
1201 | } | |
1202 | ||
198fbe15 YZ |
1203 | static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) |
1204 | { | |
1d789535 | 1205 | if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && |
198fbe15 YZ |
1206 | (adev->gfx.me_fw_version >= 0x000000a5) && |
1207 | (adev->gfx.me_feature_version >= 52)) | |
1208 | return true; | |
1209 | else | |
1210 | return false; | |
1211 | } | |
1212 | ||
00544006 HR |
1213 | static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) |
1214 | { | |
7af2a577 AD |
1215 | if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) |
1216 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; | |
1217 | ||
1d789535 | 1218 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
1219 | case IP_VERSION(9, 0, 1): |
1220 | case IP_VERSION(9, 2, 1): | |
1221 | case IP_VERSION(9, 4, 0): | |
00544006 | 1222 | break; |
9d0cb2c3 AD |
1223 | case IP_VERSION(9, 2, 2): |
1224 | case IP_VERSION(9, 1, 0): | |
54f78a76 AD |
1225 | if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || |
1226 | (adev->apu_flags & AMD_APU_IS_PICASSO)) && | |
f61f01b1 | 1227 | ((!is_raven_kicker(adev) && |
7af2a577 | 1228 | adev->gfx.rlc_fw_version < 531) || |
7af2a577 AD |
1229 | (adev->gfx.rlc_feature_version < 1) || |
1230 | !adev->gfx.rlc.is_rlc_v2_1)) | |
00544006 | 1231 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
c072b0c2 | 1232 | |
ad4d81dc AD |
1233 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
1234 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | | |
1235 | AMD_PG_SUPPORT_CP | | |
1236 | AMD_PG_SUPPORT_RLC_SMU_HS; | |
1237 | break; | |
9d0cb2c3 | 1238 | case IP_VERSION(9, 3, 0): |
b05f65d7 AD |
1239 | if (adev->pm.pp_feature & PP_GFXOFF_MASK) |
1240 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | | |
1241 | AMD_PG_SUPPORT_CP | | |
1242 | AMD_PG_SUPPORT_RLC_SMU_HS; | |
00544006 HR |
1243 | break; |
1244 | default: | |
1245 | break; | |
1246 | } | |
1247 | } | |
1248 | ||
24c44c89 | 1249 | static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, |
1c21885e | 1250 | char *chip_name) |
b1023571 | 1251 | { |
b1023571 KW |
1252 | char fw_name[30]; |
1253 | int err; | |
b1023571 KW |
1254 | |
1255 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); | |
ec787deb | 1256 | err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); |
b1023571 KW |
1257 | if (err) |
1258 | goto out; | |
93cad722 | 1259 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); |
b1023571 KW |
1260 | |
1261 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); | |
ec787deb | 1262 | err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); |
b1023571 KW |
1263 | if (err) |
1264 | goto out; | |
93cad722 | 1265 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); |
b1023571 KW |
1266 | |
1267 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); | |
ec787deb | 1268 | err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); |
b1023571 KW |
1269 | if (err) |
1270 | goto out; | |
93cad722 | 1271 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); |
24c44c89 LM |
1272 | |
1273 | out: | |
1274 | if (err) { | |
ec787deb ML |
1275 | amdgpu_ucode_release(&adev->gfx.pfp_fw); |
1276 | amdgpu_ucode_release(&adev->gfx.me_fw); | |
1277 | amdgpu_ucode_release(&adev->gfx.ce_fw); | |
24c44c89 LM |
1278 | } |
1279 | return err; | |
1280 | } | |
1281 | ||
1282 | static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, | |
1c21885e | 1283 | char *chip_name) |
24c44c89 LM |
1284 | { |
1285 | char fw_name[30]; | |
1286 | int err; | |
24c44c89 | 1287 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
24c44c89 LM |
1288 | uint16_t version_major; |
1289 | uint16_t version_minor; | |
1290 | uint32_t smu_version; | |
1291 | ||
c50fe0c5 AL |
1292 | /* |
1293 | * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin | |
1294 | * instead of picasso_rlc.bin. | |
1295 | * Judgment method: | |
1296 | * PCO AM4: revision >= 0xC8 && revision <= 0xCF | |
1297 | * or revision >= 0xD8 && revision <= 0xDF | |
1298 | * otherwise is PCO FP5 | |
1299 | */ | |
1300 | if (!strcmp(chip_name, "picasso") && | |
1301 | (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || | |
1302 | ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) | |
1303 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); | |
80f41f84 PL |
1304 | else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && |
1305 | (smu_version >= 0x41e2b)) | |
1306 | /** | |
1307 | *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. | |
1308 | */ | |
1309 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); | |
c50fe0c5 AL |
1310 | else |
1311 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); | |
ec787deb | 1312 | err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); |
f6f8bb59 HZ |
1313 | if (err) |
1314 | goto out; | |
a4d41ad0 | 1315 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
621a6318 HR |
1316 | |
1317 | version_major = le16_to_cpu(rlc_hdr->header.header_version_major); | |
1318 | version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); | |
f6f8bb59 | 1319 | err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); |
24c44c89 | 1320 | out: |
ec787deb ML |
1321 | if (err) |
1322 | amdgpu_ucode_release(&adev->gfx.rlc_fw); | |
1323 | ||
24c44c89 LM |
1324 | return err; |
1325 | } | |
1326 | ||
f8f70c13 JC |
1327 | static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) |
1328 | { | |
1d789535 AD |
1329 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || |
1330 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || | |
1331 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) | |
eb28f02b | 1332 | return false; |
f8f70c13 JC |
1333 | |
1334 | return true; | |
1335 | } | |
1336 | ||
24c44c89 | 1337 | static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, |
1c21885e | 1338 | char *chip_name) |
24c44c89 LM |
1339 | { |
1340 | char fw_name[30]; | |
1341 | int err; | |
24c44c89 | 1342 | |
1d32af4f | 1343 | if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) |
1344 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); | |
1345 | else | |
1346 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); | |
1347 | ||
ec787deb | 1348 | err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); |
24c44c89 | 1349 | if (err) |
2b89da46 | 1350 | goto out; |
93cad722 LG |
1351 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); |
1352 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); | |
621a6318 | 1353 | |
f8f70c13 | 1354 | if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { |
1d32af4f | 1355 | if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) |
1356 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); | |
1357 | else | |
1358 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); | |
1359 | ||
2b89da46 | 1360 | /* ignore failures to load */ |
ec787deb | 1361 | err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); |
f8f70c13 | 1362 | if (!err) { |
93cad722 LG |
1363 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); |
1364 | amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); | |
f8f70c13 JC |
1365 | } else { |
1366 | err = 0; | |
2b89da46 | 1367 | amdgpu_ucode_release(&adev->gfx.mec2_fw); |
f8f70c13 | 1368 | } |
47e5d79a JG |
1369 | } else { |
1370 | adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; | |
1371 | adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; | |
24c44c89 LM |
1372 | } |
1373 | ||
00544006 | 1374 | gfx_v9_0_check_if_need_gfxoff(adev); |
39b62541 | 1375 | gfx_v9_0_check_fw_write_wait(adev); |
2b89da46 ML |
1376 | |
1377 | out: | |
1378 | if (err) | |
ec787deb | 1379 | amdgpu_ucode_release(&adev->gfx.mec_fw); |
b1023571 KW |
1380 | return err; |
1381 | } | |
1382 | ||
24c44c89 LM |
1383 | static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) |
1384 | { | |
1c21885e | 1385 | char ucode_prefix[30]; |
24c44c89 LM |
1386 | int r; |
1387 | ||
1388 | DRM_DEBUG("\n"); | |
1c21885e | 1389 | amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); |
24c44c89 | 1390 | |
f8b733b9 | 1391 | /* No CPG in Arcturus */ |
35b14475 | 1392 | if (adev->gfx.num_gfx_rings) { |
1c21885e | 1393 | r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix); |
f8b733b9 LM |
1394 | if (r) |
1395 | return r; | |
1396 | } | |
24c44c89 | 1397 | |
1c21885e | 1398 | r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix); |
24c44c89 LM |
1399 | if (r) |
1400 | return r; | |
1401 | ||
1c21885e | 1402 | r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix); |
24c44c89 LM |
1403 | if (r) |
1404 | return r; | |
1405 | ||
1406 | return r; | |
1407 | } | |
1408 | ||
c9719c69 HZ |
1409 | static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) |
1410 | { | |
1411 | u32 count = 0; | |
1412 | const struct cs_section_def *sect = NULL; | |
1413 | const struct cs_extent_def *ext = NULL; | |
1414 | ||
1415 | /* begin clear state */ | |
1416 | count += 2; | |
1417 | /* context control state */ | |
1418 | count += 3; | |
1419 | ||
1420 | for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { | |
1421 | for (ext = sect->section; ext->extent != NULL; ++ext) { | |
1422 | if (sect->id == SECT_CONTEXT) | |
1423 | count += 2 + ext->reg_count; | |
1424 | else | |
1425 | return 0; | |
1426 | } | |
1427 | } | |
1428 | ||
1429 | /* end clear state */ | |
1430 | count += 2; | |
1431 | /* clear state */ | |
1432 | count += 2; | |
1433 | ||
1434 | return count; | |
1435 | } | |
1436 | ||
1437 | static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, | |
1438 | volatile u32 *buffer) | |
1439 | { | |
1440 | u32 count = 0, i; | |
1441 | const struct cs_section_def *sect = NULL; | |
1442 | const struct cs_extent_def *ext = NULL; | |
1443 | ||
1444 | if (adev->gfx.rlc.cs_data == NULL) | |
1445 | return; | |
1446 | if (buffer == NULL) | |
1447 | return; | |
1448 | ||
1449 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
1450 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
1451 | ||
1452 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); | |
1453 | buffer[count++] = cpu_to_le32(0x80000000); | |
1454 | buffer[count++] = cpu_to_le32(0x80000000); | |
1455 | ||
1456 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { | |
1457 | for (ext = sect->section; ext->extent != NULL; ++ext) { | |
1458 | if (sect->id == SECT_CONTEXT) { | |
1459 | buffer[count++] = | |
1460 | cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); | |
1461 | buffer[count++] = cpu_to_le32(ext->reg_index - | |
1462 | PACKET3_SET_CONTEXT_REG_START); | |
1463 | for (i = 0; i < ext->reg_count; i++) | |
1464 | buffer[count++] = cpu_to_le32(ext->extent[i]); | |
1465 | } else { | |
1466 | return; | |
1467 | } | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
1472 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); | |
1473 | ||
1474 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); | |
1475 | buffer[count++] = cpu_to_le32(0); | |
1476 | } | |
1477 | ||
989b6823 EQ |
1478 | static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) |
1479 | { | |
1480 | struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; | |
1481 | uint32_t pg_always_on_cu_num = 2; | |
1482 | uint32_t always_on_cu_num; | |
1483 | uint32_t i, j, k; | |
1484 | uint32_t mask, cu_bitmap, counter; | |
1485 | ||
1486 | if (adev->flags & AMD_IS_APU) | |
1487 | always_on_cu_num = 4; | |
1d789535 | 1488 | else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)) |
989b6823 EQ |
1489 | always_on_cu_num = 8; |
1490 | else | |
1491 | always_on_cu_num = 12; | |
1492 | ||
1493 | mutex_lock(&adev->grbm_idx_mutex); | |
1494 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
1495 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
1496 | mask = 1; | |
1497 | cu_bitmap = 0; | |
1498 | counter = 0; | |
d51ac6d0 | 1499 | amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); |
989b6823 EQ |
1500 | |
1501 | for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { | |
97e3c6a8 | 1502 | if (cu_info->bitmap[0][i][j] & mask) { |
989b6823 EQ |
1503 | if (counter == pg_always_on_cu_num) |
1504 | WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); | |
1505 | if (counter < always_on_cu_num) | |
1506 | cu_bitmap |= mask; | |
1507 | else | |
1508 | break; | |
1509 | counter++; | |
1510 | } | |
1511 | mask <<= 1; | |
1512 | } | |
1513 | ||
1514 | WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); | |
1515 | cu_info->ao_cu_bitmap[i][j] = cu_bitmap; | |
1516 | } | |
1517 | } | |
d51ac6d0 | 1518 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
989b6823 EQ |
1519 | mutex_unlock(&adev->grbm_idx_mutex); |
1520 | } | |
1521 | ||
ba7bb665 HZ |
1522 | static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) |
1523 | { | |
e5475e16 | 1524 | uint32_t data; |
ba7bb665 HZ |
1525 | |
1526 | /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ | |
1527 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); | |
1528 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); | |
1529 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); | |
1530 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); | |
1531 | ||
1532 | /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ | |
1533 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); | |
1534 | ||
1535 | /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ | |
1536 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); | |
1537 | ||
1538 | mutex_lock(&adev->grbm_idx_mutex); | |
1539 | /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ | |
d51ac6d0 | 1540 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
ba7bb665 HZ |
1541 | WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); |
1542 | ||
1543 | /* set mmRLC_LB_PARAMS = 0x003F_1006 */ | |
e5475e16 TSD |
1544 | data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); |
1545 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); | |
1546 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); | |
ba7bb665 HZ |
1547 | WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); |
1548 | ||
1549 | /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ | |
1550 | data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); | |
1551 | data &= 0x0000FFFF; | |
1552 | data |= 0x00C00000; | |
1553 | WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); | |
1554 | ||
b989531b EQ |
1555 | /* |
1556 | * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), | |
1557 | * programmed in gfx_v9_0_init_always_on_cu_mask() | |
1558 | */ | |
ba7bb665 HZ |
1559 | |
1560 | /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, | |
1561 | * but used for RLC_LB_CNTL configuration */ | |
1562 | data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; | |
e5475e16 TSD |
1563 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); |
1564 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); | |
ba7bb665 HZ |
1565 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); |
1566 | mutex_unlock(&adev->grbm_idx_mutex); | |
b989531b EQ |
1567 | |
1568 | gfx_v9_0_init_always_on_cu_mask(adev); | |
ba7bb665 HZ |
1569 | } |
1570 | ||
989b6823 EQ |
1571 | static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) |
1572 | { | |
1573 | uint32_t data; | |
1574 | ||
1575 | /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ | |
1576 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); | |
1577 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); | |
1578 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); | |
1579 | WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); | |
1580 | ||
1581 | /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ | |
1582 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); | |
1583 | ||
1584 | /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ | |
1585 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); | |
1586 | ||
1587 | mutex_lock(&adev->grbm_idx_mutex); | |
1588 | /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ | |
d51ac6d0 | 1589 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
989b6823 EQ |
1590 | WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); |
1591 | ||
1592 | /* set mmRLC_LB_PARAMS = 0x003F_1006 */ | |
1593 | data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); | |
1594 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); | |
1595 | data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); | |
1596 | WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); | |
1597 | ||
1598 | /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ | |
1599 | data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); | |
1600 | data &= 0x0000FFFF; | |
1601 | data |= 0x00C00000; | |
1602 | WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); | |
1603 | ||
1604 | /* | |
1605 | * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), | |
1606 | * programmed in gfx_v9_0_init_always_on_cu_mask() | |
1607 | */ | |
1608 | ||
1609 | /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, | |
1610 | * but used for RLC_LB_CNTL configuration */ | |
1611 | data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; | |
1612 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); | |
1613 | data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); | |
1614 | WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); | |
1615 | mutex_unlock(&adev->grbm_idx_mutex); | |
1616 | ||
1617 | gfx_v9_0_init_always_on_cu_mask(adev); | |
1618 | } | |
1619 | ||
e8835e0e HZ |
1620 | static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) |
1621 | { | |
e5475e16 | 1622 | WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); |
e8835e0e HZ |
1623 | } |
1624 | ||
106c7d61 | 1625 | static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) |
c9719c69 | 1626 | { |
996aede2 C |
1627 | if (gfx_v9_0_load_mec2_fw_bin_support(adev)) |
1628 | return 5; | |
1629 | else | |
1630 | return 4; | |
c9719c69 HZ |
1631 | } |
1632 | ||
4819732f HZ |
1633 | static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) |
1634 | { | |
1635 | struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; | |
1636 | ||
8ed49dd1 | 1637 | reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; |
4819732f HZ |
1638 | reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); |
1639 | reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); | |
1640 | reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); | |
1641 | reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); | |
1642 | reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); | |
1643 | reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); | |
1644 | reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); | |
1645 | adev->gfx.rlc.rlcg_reg_access_supported = true; | |
1646 | } | |
1647 | ||
c9719c69 HZ |
1648 | static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) |
1649 | { | |
c9719c69 HZ |
1650 | const struct cs_section_def *cs_data; |
1651 | int r; | |
1652 | ||
1653 | adev->gfx.rlc.cs_data = gfx9_cs_data; | |
1654 | ||
1655 | cs_data = adev->gfx.rlc.cs_data; | |
1656 | ||
1657 | if (cs_data) { | |
106c7d61 LG |
1658 | /* init clear state block */ |
1659 | r = amdgpu_gfx_rlc_init_csb(adev); | |
1660 | if (r) | |
a4a02777 | 1661 | return r; |
c9719c69 HZ |
1662 | } |
1663 | ||
70534d1e | 1664 | if (adev->flags & AMD_IS_APU) { |
c9719c69 HZ |
1665 | /* TODO: double check the cp_table_size for RV */ |
1666 | adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ | |
106c7d61 LG |
1667 | r = amdgpu_gfx_rlc_init_cpt(adev); |
1668 | if (r) | |
a4a02777 | 1669 | return r; |
989b6823 | 1670 | } |
ba7bb665 | 1671 | |
c9719c69 HZ |
1672 | return 0; |
1673 | } | |
1674 | ||
b1023571 KW |
1675 | static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) |
1676 | { | |
078af1a3 CK |
1677 | amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); |
1678 | amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); | |
b1023571 KW |
1679 | } |
1680 | ||
b1023571 KW |
1681 | static int gfx_v9_0_mec_init(struct amdgpu_device *adev) |
1682 | { | |
1683 | int r; | |
1684 | u32 *hpd; | |
1685 | const __le32 *fw_data; | |
1686 | unsigned fw_size; | |
1687 | u32 *fw; | |
42794b27 | 1688 | size_t mec_hpd_size; |
b1023571 KW |
1689 | |
1690 | const struct gfx_firmware_header_v1_0 *mec_hdr; | |
1691 | ||
be697aa3 | 1692 | bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
78c16834 | 1693 | |
78c16834 | 1694 | /* take ownership of the relevant compute queues */ |
41f6a99a | 1695 | amdgpu_gfx_compute_queue_acquire(adev); |
78c16834 | 1696 | mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; |
a300de40 ML |
1697 | if (mec_hpd_size) { |
1698 | r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, | |
58ab2c08 CK |
1699 | AMDGPU_GEM_DOMAIN_VRAM | |
1700 | AMDGPU_GEM_DOMAIN_GTT, | |
a300de40 ML |
1701 | &adev->gfx.mec.hpd_eop_obj, |
1702 | &adev->gfx.mec.hpd_eop_gpu_addr, | |
1703 | (void **)&hpd); | |
1704 | if (r) { | |
1705 | dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); | |
1706 | gfx_v9_0_mec_fini(adev); | |
1707 | return r; | |
1708 | } | |
b1023571 | 1709 | |
a300de40 | 1710 | memset(hpd, 0, mec_hpd_size); |
b1023571 | 1711 | |
a300de40 ML |
1712 | amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); |
1713 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); | |
1714 | } | |
b1023571 KW |
1715 | |
1716 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
1717 | ||
1718 | fw_data = (const __le32 *) | |
1719 | (adev->gfx.mec_fw->data + | |
1720 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); | |
74a353ff | 1721 | fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); |
b1023571 | 1722 | |
a4a02777 CK |
1723 | r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, |
1724 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, | |
1725 | &adev->gfx.mec.mec_fw_obj, | |
1726 | &adev->gfx.mec.mec_fw_gpu_addr, | |
1727 | (void **)&fw); | |
b1023571 | 1728 | if (r) { |
a4a02777 | 1729 | dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); |
b1023571 KW |
1730 | gfx_v9_0_mec_fini(adev); |
1731 | return r; | |
1732 | } | |
a4a02777 | 1733 | |
b1023571 KW |
1734 | memcpy(fw, fw_data, fw_size); |
1735 | ||
1736 | amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); | |
1737 | amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); | |
1738 | ||
b1023571 KW |
1739 | return 0; |
1740 | } | |
1741 | ||
1742 | static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) | |
1743 | { | |
2e0cc4d4 | 1744 | WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, |
b1023571 KW |
1745 | (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | |
1746 | (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | | |
1747 | (address << SQ_IND_INDEX__INDEX__SHIFT) | | |
1748 | (SQ_IND_INDEX__FORCE_READ_MASK)); | |
5e78835a | 1749 | return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); |
b1023571 KW |
1750 | } |
1751 | ||
1752 | static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, | |
1753 | uint32_t wave, uint32_t thread, | |
1754 | uint32_t regno, uint32_t num, uint32_t *out) | |
1755 | { | |
2e0cc4d4 | 1756 | WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, |
b1023571 KW |
1757 | (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | |
1758 | (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | | |
1759 | (regno << SQ_IND_INDEX__INDEX__SHIFT) | | |
1760 | (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | | |
1761 | (SQ_IND_INDEX__FORCE_READ_MASK) | | |
1762 | (SQ_IND_INDEX__AUTO_INCR_MASK)); | |
1763 | while (num--) | |
5e78835a | 1764 | *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); |
b1023571 KW |
1765 | } |
1766 | ||
553f973a | 1767 | static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) |
b1023571 KW |
1768 | { |
1769 | /* type 1 wave data */ | |
1770 | dst[(*no_fields)++] = 1; | |
1771 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); | |
1772 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); | |
1773 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); | |
1774 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); | |
1775 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); | |
1776 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); | |
1777 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); | |
1778 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); | |
1779 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); | |
1780 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); | |
1781 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); | |
1782 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); | |
1783 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); | |
1784 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); | |
685967b3 | 1785 | dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); |
b1023571 KW |
1786 | } |
1787 | ||
553f973a | 1788 | static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, |
b1023571 KW |
1789 | uint32_t wave, uint32_t start, |
1790 | uint32_t size, uint32_t *dst) | |
1791 | { | |
1792 | wave_read_regs( | |
1793 | adev, simd, wave, 0, | |
1794 | start + SQIND_WAVE_SGPRS_OFFSET, size, dst); | |
1795 | } | |
1796 | ||
553f973a | 1797 | static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, |
822770ad NH |
1798 | uint32_t wave, uint32_t thread, |
1799 | uint32_t start, uint32_t size, | |
1800 | uint32_t *dst) | |
1801 | { | |
1802 | wave_read_regs( | |
1803 | adev, simd, wave, thread, | |
1804 | start + SQIND_WAVE_VGPRS_OFFSET, size, dst); | |
1805 | } | |
b1023571 | 1806 | |
f7a9ee81 | 1807 | static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, |
553f973a | 1808 | u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) |
f7a9ee81 | 1809 | { |
5aa998ba | 1810 | soc15_grbm_select(adev, me, pipe, q, vm, 0); |
f7a9ee81 AG |
1811 | } |
1812 | ||
b1023571 | 1813 | static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { |
719a9b33 HZ |
1814 | .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, |
1815 | .select_se_sh = &gfx_v9_0_select_se_sh, | |
1816 | .read_wave_data = &gfx_v9_0_read_wave_data, | |
1817 | .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, | |
1818 | .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, | |
1819 | .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, | |
1820 | }; | |
1821 | ||
8b0fb0e9 | 1822 | const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { |
1823 | .ras_error_inject = &gfx_v9_0_ras_error_inject, | |
1824 | .query_ras_error_count = &gfx_v9_0_query_ras_error_count, | |
1825 | .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, | |
1826 | }; | |
1827 | ||
1828 | static struct amdgpu_gfx_ras gfx_v9_0_ras = { | |
1829 | .ras_block = { | |
1830 | .hw_ops = &gfx_v9_0_ras_ops, | |
1831 | }, | |
b1023571 KW |
1832 | }; |
1833 | ||
3251c043 | 1834 | static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) |
b1023571 KW |
1835 | { |
1836 | u32 gb_addr_config; | |
3251c043 | 1837 | int err; |
b1023571 | 1838 | |
1d789535 | 1839 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 | 1840 | case IP_VERSION(9, 0, 1): |
b1023571 | 1841 | adev->gfx.config.max_hw_contexts = 8; |
b1023571 KW |
1842 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1843 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1844 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
1845 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
1846 | gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; | |
1847 | break; | |
9d0cb2c3 | 1848 | case IP_VERSION(9, 2, 1): |
e5c62edd AD |
1849 | adev->gfx.config.max_hw_contexts = 8; |
1850 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
1851 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1852 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
1853 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
62b35f9a | 1854 | gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; |
e5c62edd AD |
1855 | DRM_INFO("fix gfx.config for vega12\n"); |
1856 | break; | |
9d0cb2c3 | 1857 | case IP_VERSION(9, 4, 0): |
8b0fb0e9 | 1858 | adev->gfx.ras = &gfx_v9_0_ras; |
d3adedb4 FX |
1859 | adev->gfx.config.max_hw_contexts = 8; |
1860 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
1861 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1862 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
1863 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
1864 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); | |
1865 | gb_addr_config &= ~0xf3e777ff; | |
1866 | gb_addr_config |= 0x22014042; | |
3251c043 AD |
1867 | /* check vbios table if gpu info is not available */ |
1868 | err = amdgpu_atomfirmware_get_gfx_info(adev); | |
1869 | if (err) | |
1870 | return err; | |
d3adedb4 | 1871 | break; |
9d0cb2c3 AD |
1872 | case IP_VERSION(9, 2, 2): |
1873 | case IP_VERSION(9, 1, 0): | |
5cf7433d CZ |
1874 | adev->gfx.config.max_hw_contexts = 8; |
1875 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
1876 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1877 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
1878 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
54f78a76 | 1879 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
28ab1229 FX |
1880 | gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; |
1881 | else | |
1882 | gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; | |
5cf7433d | 1883 | break; |
9d0cb2c3 | 1884 | case IP_VERSION(9, 4, 1): |
8b0fb0e9 | 1885 | adev->gfx.ras = &gfx_v9_4_ras; |
6155e98a LM |
1886 | adev->gfx.config.max_hw_contexts = 8; |
1887 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
1888 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1889 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
1890 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
1891 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); | |
1892 | gb_addr_config &= ~0xf3e777ff; | |
1893 | gb_addr_config |= 0x22014042; | |
1894 | break; | |
9d0cb2c3 | 1895 | case IP_VERSION(9, 3, 0): |
1aafd447 HR |
1896 | adev->gfx.config.max_hw_contexts = 8; |
1897 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
1898 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1899 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; | |
1900 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
1901 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); | |
1902 | gb_addr_config &= ~0xf3e777ff; | |
1903 | gb_addr_config |= 0x22010042; | |
1904 | break; | |
9d0cb2c3 | 1905 | case IP_VERSION(9, 4, 2): |
8b0fb0e9 | 1906 | adev->gfx.ras = &gfx_v9_4_2_ras; |
cdf545f3 LM |
1907 | adev->gfx.config.max_hw_contexts = 8; |
1908 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; | |
1909 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; | |
1910 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; | |
1911 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; | |
1912 | gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); | |
1913 | gb_addr_config &= ~0xf3e777ff; | |
1914 | gb_addr_config |= 0x22014042; | |
7159a36e HZ |
1915 | /* check vbios table if gpu info is not available */ |
1916 | err = amdgpu_atomfirmware_get_gfx_info(adev); | |
1917 | if (err) | |
1918 | return err; | |
cdf545f3 | 1919 | break; |
b1023571 KW |
1920 | default: |
1921 | BUG(); | |
1922 | break; | |
1923 | } | |
1924 | ||
1925 | adev->gfx.config.gb_addr_config = gb_addr_config; | |
1926 | ||
1927 | adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << | |
1928 | REG_GET_FIELD( | |
1929 | adev->gfx.config.gb_addr_config, | |
1930 | GB_ADDR_CONFIG, | |
1931 | NUM_PIPES); | |
ad7d0ff3 AD |
1932 | |
1933 | adev->gfx.config.max_tile_pipes = | |
1934 | adev->gfx.config.gb_addr_config_fields.num_pipes; | |
1935 | ||
b1023571 KW |
1936 | adev->gfx.config.gb_addr_config_fields.num_banks = 1 << |
1937 | REG_GET_FIELD( | |
1938 | adev->gfx.config.gb_addr_config, | |
1939 | GB_ADDR_CONFIG, | |
1940 | NUM_BANKS); | |
1941 | adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << | |
1942 | REG_GET_FIELD( | |
1943 | adev->gfx.config.gb_addr_config, | |
1944 | GB_ADDR_CONFIG, | |
1945 | MAX_COMPRESSED_FRAGS); | |
1946 | adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << | |
1947 | REG_GET_FIELD( | |
1948 | adev->gfx.config.gb_addr_config, | |
1949 | GB_ADDR_CONFIG, | |
1950 | NUM_RB_PER_SE); | |
1951 | adev->gfx.config.gb_addr_config_fields.num_se = 1 << | |
1952 | REG_GET_FIELD( | |
1953 | adev->gfx.config.gb_addr_config, | |
1954 | GB_ADDR_CONFIG, | |
1955 | NUM_SHADER_ENGINES); | |
1956 | adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + | |
1957 | REG_GET_FIELD( | |
1958 | adev->gfx.config.gb_addr_config, | |
1959 | GB_ADDR_CONFIG, | |
1960 | PIPE_INTERLEAVE_SIZE)); | |
3251c043 AD |
1961 | |
1962 | return 0; | |
b1023571 KW |
1963 | } |
1964 | ||
1361f455 AD |
1965 | static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, |
1966 | int mec, int pipe, int queue) | |
1967 | { | |
1361f455 AD |
1968 | unsigned irq_type; |
1969 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; | |
1c6d567b | 1970 | unsigned int hw_prio; |
1361f455 AD |
1971 | |
1972 | ring = &adev->gfx.compute_ring[ring_id]; | |
1973 | ||
1974 | /* mec0 is me1 */ | |
1975 | ring->me = mec + 1; | |
1976 | ring->pipe = pipe; | |
1977 | ring->queue = queue; | |
1978 | ||
1979 | ring->ring_obj = NULL; | |
1980 | ring->use_doorbell = true; | |
9564f192 | 1981 | ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; |
1361f455 AD |
1982 | ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr |
1983 | + (ring_id * GFX9_MEC_HPD_SIZE); | |
f4caf584 | 1984 | ring->vm_hub = AMDGPU_GFXHUB(0); |
1361f455 AD |
1985 | sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); |
1986 | ||
1987 | irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP | |
1988 | + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) | |
1989 | + ring->pipe; | |
8c0225d7 | 1990 | hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? |
6f90a49b | 1991 | AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; |
1361f455 | 1992 | /* type-2 packets are deprecated on MEC, use type-3 instead */ |
c107171b CK |
1993 | return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, |
1994 | hw_prio, NULL); | |
1361f455 AD |
1995 | } |
1996 | ||
b1023571 KW |
1997 | static int gfx_v9_0_sw_init(void *handle) |
1998 | { | |
1361f455 | 1999 | int i, j, k, r, ring_id; |
b1023571 | 2000 | struct amdgpu_ring *ring; |
ac104e99 | 2001 | struct amdgpu_kiq *kiq; |
b1023571 | 2002 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
0c97a19a | 2003 | unsigned int hw_prio; |
b1023571 | 2004 | |
1d789535 | 2005 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
2006 | case IP_VERSION(9, 0, 1): |
2007 | case IP_VERSION(9, 2, 1): | |
2008 | case IP_VERSION(9, 4, 0): | |
2009 | case IP_VERSION(9, 2, 2): | |
2010 | case IP_VERSION(9, 1, 0): | |
2011 | case IP_VERSION(9, 4, 1): | |
2012 | case IP_VERSION(9, 3, 0): | |
2013 | case IP_VERSION(9, 4, 2): | |
4853bbb6 AD |
2014 | adev->gfx.mec.num_mec = 2; |
2015 | break; | |
2016 | default: | |
2017 | adev->gfx.mec.num_mec = 1; | |
2018 | break; | |
2019 | } | |
2020 | ||
2021 | adev->gfx.mec.num_pipe_per_mec = 4; | |
2022 | adev->gfx.mec.num_queue_per_pipe = 8; | |
2023 | ||
b1023571 | 2024 | /* EOP Event */ |
44a99b65 | 2025 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); |
b1023571 KW |
2026 | if (r) |
2027 | return r; | |
2028 | ||
2029 | /* Privileged reg */ | |
44a99b65 | 2030 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, |
b1023571 KW |
2031 | &adev->gfx.priv_reg_irq); |
2032 | if (r) | |
2033 | return r; | |
2034 | ||
2035 | /* Privileged inst */ | |
44a99b65 | 2036 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, |
b1023571 KW |
2037 | &adev->gfx.priv_inst_irq); |
2038 | if (r) | |
2039 | return r; | |
2040 | ||
760a1d55 FX |
2041 | /* ECC error */ |
2042 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, | |
2043 | &adev->gfx.cp_ecc_error_irq); | |
2044 | if (r) | |
2045 | return r; | |
2046 | ||
2047 | /* FUE error */ | |
2048 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, | |
2049 | &adev->gfx.cp_ecc_error_irq); | |
2050 | if (r) | |
2051 | return r; | |
2052 | ||
b1023571 KW |
2053 | adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; |
2054 | ||
4819732f HZ |
2055 | if (adev->gfx.rlc.funcs) { |
2056 | if (adev->gfx.rlc.funcs->init) { | |
2057 | r = adev->gfx.rlc.funcs->init(adev); | |
2058 | if (r) { | |
2059 | dev_err(adev->dev, "Failed to init rlc BOs!\n"); | |
2060 | return r; | |
2061 | } | |
2062 | } | |
c9719c69 HZ |
2063 | } |
2064 | ||
b1023571 KW |
2065 | r = gfx_v9_0_mec_init(adev); |
2066 | if (r) { | |
2067 | DRM_ERROR("Failed to init MEC BOs!\n"); | |
2068 | return r; | |
2069 | } | |
2070 | ||
2071 | /* set up the gfx ring */ | |
2072 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { | |
2073 | ring = &adev->gfx.gfx_ring[i]; | |
2074 | ring->ring_obj = NULL; | |
f6886c47 TSD |
2075 | if (!i) |
2076 | sprintf(ring->name, "gfx"); | |
2077 | else | |
2078 | sprintf(ring->name, "gfx_%d", i); | |
b1023571 | 2079 | ring->use_doorbell = true; |
9564f192 | 2080 | ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; |
0c97a19a JZ |
2081 | |
2082 | /* disable scheduler on the real ring */ | |
2083 | ring->no_scheduler = true; | |
f4caf584 | 2084 | ring->vm_hub = AMDGPU_GFXHUB(0); |
c107171b | 2085 | r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, |
1c6d567b | 2086 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, |
c107171b | 2087 | AMDGPU_RING_PRIO_DEFAULT, NULL); |
b1023571 KW |
2088 | if (r) |
2089 | return r; | |
2090 | } | |
2091 | ||
0c97a19a JZ |
2092 | /* set up the software rings */ |
2093 | if (adev->gfx.num_gfx_rings) { | |
2094 | for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { | |
2095 | ring = &adev->gfx.sw_gfx_ring[i]; | |
2096 | ring->ring_obj = NULL; | |
2097 | sprintf(ring->name, amdgpu_sw_ring_name(i)); | |
2098 | ring->use_doorbell = true; | |
2099 | ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; | |
2100 | ring->is_sw_ring = true; | |
2101 | hw_prio = amdgpu_sw_ring_priority(i); | |
f4caf584 | 2102 | ring->vm_hub = AMDGPU_GFXHUB(0); |
0c97a19a JZ |
2103 | r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, |
2104 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio, | |
2105 | NULL); | |
2106 | if (r) | |
2107 | return r; | |
2108 | ring->wptr = 0; | |
2109 | } | |
2110 | ||
2111 | /* init the muxer and add software rings */ | |
2112 | r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], | |
2113 | GFX9_NUM_SW_GFX_RINGS); | |
2114 | if (r) { | |
2115 | DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r); | |
2116 | return r; | |
2117 | } | |
2118 | for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { | |
2119 | r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, | |
2120 | &adev->gfx.sw_gfx_ring[i]); | |
2121 | if (r) { | |
2122 | DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r); | |
2123 | return r; | |
2124 | } | |
2125 | } | |
2126 | } | |
2127 | ||
1361f455 AD |
2128 | /* set up the compute queues - allocate horizontally across pipes */ |
2129 | ring_id = 0; | |
2130 | for (i = 0; i < adev->gfx.mec.num_mec; ++i) { | |
2131 | for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { | |
2132 | for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { | |
be697aa3 LM |
2133 | if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, |
2134 | k, j)) | |
1361f455 AD |
2135 | continue; |
2136 | ||
2137 | r = gfx_v9_0_compute_ring_init(adev, | |
2138 | ring_id, | |
2139 | i, k, j); | |
2140 | if (r) | |
2141 | return r; | |
2142 | ||
2143 | ring_id++; | |
2144 | } | |
b1023571 | 2145 | } |
b1023571 KW |
2146 | } |
2147 | ||
def799c6 | 2148 | r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0); |
e30a5223 AD |
2149 | if (r) { |
2150 | DRM_ERROR("Failed to init KIQ BOs!\n"); | |
2151 | return r; | |
2152 | } | |
ac104e99 | 2153 | |
277bd337 | 2154 | kiq = &adev->gfx.kiq[0]; |
def799c6 | 2155 | r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); |
e30a5223 AD |
2156 | if (r) |
2157 | return r; | |
464826d6 | 2158 | |
e30a5223 | 2159 | /* create MQD for all compute queues as wel as KIQ for SRIOV case */ |
def799c6 | 2160 | r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation), 0); |
e30a5223 AD |
2161 | if (r) |
2162 | return r; | |
ac104e99 | 2163 | |
b1023571 KW |
2164 | adev->gfx.ce_ram_size = 0x8000; |
2165 | ||
3251c043 AD |
2166 | r = gfx_v9_0_gpu_early_init(adev); |
2167 | if (r) | |
2168 | return r; | |
b1023571 | 2169 | |
4da9932e YC |
2170 | if (amdgpu_gfx_ras_sw_init(adev)) { |
2171 | dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); | |
2172 | return -EINVAL; | |
2173 | } | |
2174 | ||
b1023571 KW |
2175 | return 0; |
2176 | } | |
2177 | ||
2178 | ||
2179 | static int gfx_v9_0_sw_fini(void *handle) | |
2180 | { | |
2181 | int i; | |
2182 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2183 | ||
0c97a19a JZ |
2184 | if (adev->gfx.num_gfx_rings) { |
2185 | for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) | |
2186 | amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); | |
2187 | amdgpu_ring_mux_fini(&adev->gfx.muxer); | |
2188 | } | |
2189 | ||
b1023571 KW |
2190 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
2191 | amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); | |
2192 | for (i = 0; i < adev->gfx.num_compute_rings; i++) | |
2193 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); | |
2194 | ||
def799c6 | 2195 | amdgpu_gfx_mqd_sw_fini(adev, 0); |
277bd337 | 2196 | amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); |
def799c6 | 2197 | amdgpu_gfx_kiq_fini(adev, 0); |
ac104e99 | 2198 | |
b1023571 | 2199 | gfx_v9_0_mec_fini(adev); |
6ddc0eb7 YW |
2200 | amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, |
2201 | &adev->gfx.rlc.clear_state_gpu_addr, | |
2202 | (void **)&adev->gfx.rlc.cs_ptr); | |
70534d1e | 2203 | if (adev->flags & AMD_IS_APU) { |
9862def9 ML |
2204 | amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, |
2205 | &adev->gfx.rlc.cp_table_gpu_addr, | |
2206 | (void **)&adev->gfx.rlc.cp_table_ptr); | |
2207 | } | |
c833d8aa | 2208 | gfx_v9_0_free_microcode(adev); |
b1023571 KW |
2209 | |
2210 | return 0; | |
2211 | } | |
2212 | ||
2213 | ||
2214 | static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) | |
2215 | { | |
2216 | /* TODO */ | |
2217 | } | |
2218 | ||
825c91d0 | 2219 | void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, |
d51ac6d0 | 2220 | u32 instance, int xcc_id) |
b1023571 | 2221 | { |
be448a4d | 2222 | u32 data; |
b1023571 | 2223 | |
be448a4d NH |
2224 | if (instance == 0xffffffff) |
2225 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); | |
2226 | else | |
2227 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); | |
2228 | ||
2229 | if (se_num == 0xffffffff) | |
b1023571 | 2230 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); |
be448a4d | 2231 | else |
b1023571 | 2232 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); |
be448a4d NH |
2233 | |
2234 | if (sh_num == 0xffffffff) | |
2235 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); | |
2236 | else | |
b1023571 | 2237 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); |
be448a4d | 2238 | |
1bff7f6c | 2239 | WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); |
b1023571 KW |
2240 | } |
2241 | ||
b1023571 KW |
2242 | static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) |
2243 | { | |
2244 | u32 data, mask; | |
2245 | ||
5e78835a TSD |
2246 | data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); |
2247 | data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); | |
b1023571 KW |
2248 | |
2249 | data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; | |
2250 | data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; | |
2251 | ||
378506a7 AD |
2252 | mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / |
2253 | adev->gfx.config.max_sh_per_se); | |
b1023571 KW |
2254 | |
2255 | return (~data) & mask; | |
2256 | } | |
2257 | ||
2258 | static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) | |
2259 | { | |
2260 | int i, j; | |
2572c24c | 2261 | u32 data; |
b1023571 KW |
2262 | u32 active_rbs = 0; |
2263 | u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / | |
2264 | adev->gfx.config.max_sh_per_se; | |
2265 | ||
2266 | mutex_lock(&adev->grbm_idx_mutex); | |
2267 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
2268 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
d51ac6d0 | 2269 | amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); |
b1023571 KW |
2270 | data = gfx_v9_0_get_rb_active_bitmap(adev); |
2271 | active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * | |
2272 | rb_bitmap_width_per_sh); | |
2273 | } | |
2274 | } | |
d51ac6d0 | 2275 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
b1023571 KW |
2276 | mutex_unlock(&adev->grbm_idx_mutex); |
2277 | ||
2278 | adev->gfx.config.backend_enable_mask = active_rbs; | |
2572c24c | 2279 | adev->gfx.config.num_rbs = hweight32(active_rbs); |
b1023571 KW |
2280 | } |
2281 | ||
4504f143 JK |
2282 | static void gfx_v9_0_debug_trap_config_init(struct amdgpu_device *adev, |
2283 | uint32_t first_vmid, | |
2284 | uint32_t last_vmid) | |
2285 | { | |
2286 | uint32_t data; | |
2287 | uint32_t trap_config_vmid_mask = 0; | |
2288 | int i; | |
2289 | ||
2290 | /* Calculate trap config vmid mask */ | |
2291 | for (i = first_vmid; i < last_vmid; i++) | |
2292 | trap_config_vmid_mask |= (1 << i); | |
2293 | ||
2294 | data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, | |
2295 | VMID_SEL, trap_config_vmid_mask); | |
2296 | data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, | |
2297 | TRAP_EN, 1); | |
2298 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); | |
2299 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); | |
2300 | ||
2301 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); | |
2302 | WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); | |
2303 | } | |
2304 | ||
b1023571 | 2305 | #define DEFAULT_SH_MEM_BASES (0x6000) |
b1023571 KW |
2306 | static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) |
2307 | { | |
2308 | int i; | |
2309 | uint32_t sh_mem_config; | |
2310 | uint32_t sh_mem_bases; | |
2311 | ||
2312 | /* | |
2313 | * Configure apertures: | |
2314 | * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) | |
2315 | * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) | |
2316 | * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) | |
2317 | */ | |
2318 | sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); | |
2319 | ||
2320 | sh_mem_config = SH_MEM_ADDRESS_MODE_64 | | |
2321 | SH_MEM_ALIGNMENT_MODE_UNALIGNED << | |
eaa05d52 | 2322 | SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; |
b1023571 KW |
2323 | |
2324 | mutex_lock(&adev->srbm_mutex); | |
40111ec2 | 2325 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { |
5aa998ba | 2326 | soc15_grbm_select(adev, 0, 0, 0, i, 0); |
b1023571 | 2327 | /* CP and shaders */ |
1bff7f6c TH |
2328 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); |
2329 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); | |
b1023571 | 2330 | } |
5aa998ba | 2331 | soc15_grbm_select(adev, 0, 0, 0, 0, 0); |
b1023571 | 2332 | mutex_unlock(&adev->srbm_mutex); |
ad28e024 JG |
2333 | |
2334 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA | |
ab5a7fb6 | 2335 | access. These should be enabled by FW for target VMIDs. */ |
40111ec2 | 2336 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { |
ad28e024 JG |
2337 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); |
2338 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); | |
2339 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); | |
2340 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); | |
2341 | } | |
2c897318 | 2342 | } |
fbdc5d8d | 2343 | |
2c897318 JG |
2344 | static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) |
2345 | { | |
2346 | int vmid; | |
2347 | ||
2348 | /* | |
2349 | * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA | |
2350 | * access. Compute VMIDs should be enabled by FW for target VMIDs, | |
2351 | * the driver can enable them for graphics. VMID0 should maintain | |
2352 | * access so that HWS firmware can save/restore entries. | |
2353 | */ | |
68fce5f0 | 2354 | for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { |
2c897318 JG |
2355 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); |
2356 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); | |
2357 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); | |
2358 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); | |
fbdc5d8d | 2359 | } |
b1023571 KW |
2360 | } |
2361 | ||
18c6b74e JG |
2362 | static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) |
2363 | { | |
2364 | uint32_t tmp; | |
2365 | ||
1d789535 | 2366 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 | 2367 | case IP_VERSION(9, 4, 1): |
18c6b74e | 2368 | tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); |
01f64820 JK |
2369 | tmp = REG_SET_FIELD(tmp, SQ_CONFIG, DISABLE_BARRIER_WAITCNT, |
2370 | !READ_ONCE(adev->barrier_has_auto_waitcnt)); | |
18c6b74e JG |
2371 | WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); |
2372 | break; | |
2373 | default: | |
2374 | break; | |
d18ba57c | 2375 | } |
18c6b74e JG |
2376 | } |
2377 | ||
434e6df2 | 2378 | static void gfx_v9_0_constants_init(struct amdgpu_device *adev) |
b1023571 KW |
2379 | { |
2380 | u32 tmp; | |
2381 | int i; | |
2382 | ||
1bff7f6c | 2383 | WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); |
b1023571 KW |
2384 | |
2385 | gfx_v9_0_tiling_mode_table_init(adev); | |
2386 | ||
4bb5fed1 CL |
2387 | if (adev->gfx.num_gfx_rings) |
2388 | gfx_v9_0_setup_rb(adev); | |
b1023571 | 2389 | gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); |
5eeae247 | 2390 | adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); |
b1023571 KW |
2391 | |
2392 | /* XXX SH_MEM regs */ | |
2393 | /* where to put LDS, scratch, GPUVM in FSA64 space */ | |
2394 | mutex_lock(&adev->srbm_mutex); | |
f4caf584 | 2395 | for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { |
5aa998ba | 2396 | soc15_grbm_select(adev, 0, 0, 0, i, 0); |
b1023571 | 2397 | /* CP and shaders */ |
a7ea6548 AD |
2398 | if (i == 0) { |
2399 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, | |
2400 | SH_MEM_ALIGNMENT_MODE_UNALIGNED); | |
75ee6487 | 2401 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, |
9b498efa | 2402 | !!adev->gmc.noretry); |
bdb50274 ED |
2403 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); |
2404 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); | |
a7ea6548 AD |
2405 | } else { |
2406 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, | |
2407 | SH_MEM_ALIGNMENT_MODE_UNALIGNED); | |
75ee6487 | 2408 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, |
9b498efa | 2409 | !!adev->gmc.noretry); |
bdb50274 | 2410 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); |
bfa8eea2 FC |
2411 | tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, |
2412 | (adev->gmc.private_aperture_start >> 48)); | |
2413 | tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, | |
2414 | (adev->gmc.shared_aperture_start >> 48)); | |
bdb50274 | 2415 | WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); |
a7ea6548 | 2416 | } |
b1023571 | 2417 | } |
5aa998ba | 2418 | soc15_grbm_select(adev, 0, 0, 0, 0, 0); |
b1023571 KW |
2419 | |
2420 | mutex_unlock(&adev->srbm_mutex); | |
2421 | ||
2422 | gfx_v9_0_init_compute_vmid(adev); | |
2c897318 | 2423 | gfx_v9_0_init_gds_vmid(adev); |
18c6b74e | 2424 | gfx_v9_0_init_sq_config(adev); |
b1023571 KW |
2425 | } |
2426 | ||
2427 | static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) | |
2428 | { | |
2429 | u32 i, j, k; | |
2430 | u32 mask; | |
2431 | ||
2432 | mutex_lock(&adev->grbm_idx_mutex); | |
2433 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
2434 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
d51ac6d0 | 2435 | amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); |
b1023571 | 2436 | for (k = 0; k < adev->usec_timeout; k++) { |
5e78835a | 2437 | if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) |
b1023571 KW |
2438 | break; |
2439 | udelay(1); | |
2440 | } | |
1366b2d0 | 2441 | if (k == adev->usec_timeout) { |
cfa61b8f | 2442 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, |
d51ac6d0 | 2443 | 0xffffffff, 0xffffffff, 0); |
1366b2d0 | 2444 | mutex_unlock(&adev->grbm_idx_mutex); |
2445 | DRM_INFO("Timeout wait for RLC serdes %u,%u\n", | |
2446 | i, j); | |
2447 | return; | |
2448 | } | |
b1023571 KW |
2449 | } |
2450 | } | |
d51ac6d0 | 2451 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
b1023571 KW |
2452 | mutex_unlock(&adev->grbm_idx_mutex); |
2453 | ||
2454 | mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | | |
2455 | RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | | |
2456 | RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | | |
2457 | RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; | |
2458 | for (k = 0; k < adev->usec_timeout; k++) { | |
5e78835a | 2459 | if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) |
b1023571 KW |
2460 | break; |
2461 | udelay(1); | |
2462 | } | |
2463 | } | |
2464 | ||
2465 | static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, | |
2466 | bool enable) | |
2467 | { | |
462fbeb1 HZ |
2468 | u32 tmp; |
2469 | ||
8cf3dccb | 2470 | /* These interrupts should be enabled to drive DS clock */ |
462fbeb1 HZ |
2471 | |
2472 | tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); | |
b1023571 | 2473 | |
b1023571 KW |
2474 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); |
2475 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); | |
2476 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); | |
8cf3dccb LL |
2477 | if(adev->gfx.num_gfx_rings) |
2478 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); | |
b1023571 | 2479 | |
5e78835a | 2480 | WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); |
b1023571 KW |
2481 | } |
2482 | ||
6bce4667 HZ |
2483 | static void gfx_v9_0_init_csb(struct amdgpu_device *adev) |
2484 | { | |
82a829dc | 2485 | adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); |
6bce4667 | 2486 | /* csib */ |
1bff7f6c | 2487 | WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), |
6bce4667 | 2488 | adev->gfx.rlc.clear_state_gpu_addr >> 32); |
1bff7f6c | 2489 | WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), |
6bce4667 | 2490 | adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); |
1bff7f6c | 2491 | WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), |
6bce4667 HZ |
2492 | adev->gfx.rlc.clear_state_size); |
2493 | } | |
2494 | ||
727b888f | 2495 | static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, |
6bce4667 HZ |
2496 | int indirect_offset, |
2497 | int list_size, | |
2498 | int *unique_indirect_regs, | |
cb5ed37f | 2499 | int unique_indirect_reg_count, |
6bce4667 | 2500 | int *indirect_start_offsets, |
cb5ed37f EQ |
2501 | int *indirect_start_offsets_count, |
2502 | int max_start_offsets_count) | |
6bce4667 HZ |
2503 | { |
2504 | int idx; | |
6bce4667 HZ |
2505 | |
2506 | for (; indirect_offset < list_size; indirect_offset++) { | |
cb5ed37f | 2507 | WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); |
727b888f HR |
2508 | indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; |
2509 | *indirect_start_offsets_count = *indirect_start_offsets_count + 1; | |
6bce4667 | 2510 | |
727b888f HR |
2511 | while (register_list_format[indirect_offset] != 0xFFFFFFFF) { |
2512 | indirect_offset += 2; | |
6bce4667 | 2513 | |
727b888f | 2514 | /* look for the matching indice */ |
cb5ed37f | 2515 | for (idx = 0; idx < unique_indirect_reg_count; idx++) { |
727b888f HR |
2516 | if (unique_indirect_regs[idx] == |
2517 | register_list_format[indirect_offset] || | |
2518 | !unique_indirect_regs[idx]) | |
2519 | break; | |
2520 | } | |
6bce4667 | 2521 | |
cb5ed37f | 2522 | BUG_ON(idx >= unique_indirect_reg_count); |
6bce4667 | 2523 | |
727b888f HR |
2524 | if (!unique_indirect_regs[idx]) |
2525 | unique_indirect_regs[idx] = register_list_format[indirect_offset]; | |
6bce4667 | 2526 | |
727b888f | 2527 | indirect_offset++; |
6bce4667 | 2528 | } |
6bce4667 HZ |
2529 | } |
2530 | } | |
2531 | ||
727b888f | 2532 | static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) |
6bce4667 HZ |
2533 | { |
2534 | int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; | |
2535 | int unique_indirect_reg_count = 0; | |
2536 | ||
2537 | int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; | |
2538 | int indirect_start_offsets_count = 0; | |
2539 | ||
2540 | int list_size = 0; | |
727b888f | 2541 | int i = 0, j = 0; |
6bce4667 HZ |
2542 | u32 tmp = 0; |
2543 | ||
2544 | u32 *register_list_format = | |
d12c2022 FH |
2545 | kmemdup(adev->gfx.rlc.register_list_format, |
2546 | adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); | |
6bce4667 HZ |
2547 | if (!register_list_format) |
2548 | return -ENOMEM; | |
6bce4667 HZ |
2549 | |
2550 | /* setup unique_indirect_regs array and indirect_start_offsets array */ | |
727b888f HR |
2551 | unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); |
2552 | gfx_v9_1_parse_ind_reg_list(register_list_format, | |
2553 | adev->gfx.rlc.reg_list_format_direct_reg_list_length, | |
2554 | adev->gfx.rlc.reg_list_format_size_bytes >> 2, | |
2555 | unique_indirect_regs, | |
cb5ed37f | 2556 | unique_indirect_reg_count, |
727b888f | 2557 | indirect_start_offsets, |
cb5ed37f EQ |
2558 | &indirect_start_offsets_count, |
2559 | ARRAY_SIZE(indirect_start_offsets)); | |
6bce4667 HZ |
2560 | |
2561 | /* enable auto inc in case it is disabled */ | |
2562 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); | |
2563 | tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; | |
2564 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); | |
2565 | ||
2566 | /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ | |
2567 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), | |
2568 | RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); | |
2569 | for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) | |
2570 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), | |
2571 | adev->gfx.rlc.register_restore[i]); | |
2572 | ||
6bce4667 HZ |
2573 | /* load indirect register */ |
2574 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), | |
2575 | adev->gfx.rlc.reg_list_format_start); | |
727b888f HR |
2576 | |
2577 | /* direct register portion */ | |
2578 | for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) | |
6bce4667 HZ |
2579 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), |
2580 | register_list_format[i]); | |
2581 | ||
727b888f HR |
2582 | /* indirect register portion */ |
2583 | while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { | |
2584 | if (register_list_format[i] == 0xFFFFFFFF) { | |
2585 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); | |
2586 | continue; | |
2587 | } | |
2588 | ||
2589 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); | |
2590 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); | |
2591 | ||
2592 | for (j = 0; j < unique_indirect_reg_count; j++) { | |
2593 | if (register_list_format[i] == unique_indirect_regs[j]) { | |
2594 | WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); | |
2595 | break; | |
2596 | } | |
2597 | } | |
2598 | ||
2599 | BUG_ON(j >= unique_indirect_reg_count); | |
2600 | ||
2601 | i++; | |
2602 | } | |
2603 | ||
6bce4667 HZ |
2604 | /* set save/restore list size */ |
2605 | list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; | |
2606 | list_size = list_size >> 1; | |
2607 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), | |
2608 | adev->gfx.rlc.reg_restore_list_size); | |
2609 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); | |
2610 | ||
2611 | /* write the starting offsets to RLC scratch ram */ | |
2612 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), | |
2613 | adev->gfx.rlc.starting_offsets_start); | |
c1b24a14 | 2614 | for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) |
6bce4667 | 2615 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), |
727b888f | 2616 | indirect_start_offsets[i]); |
6bce4667 HZ |
2617 | |
2618 | /* load unique indirect regs*/ | |
c1b24a14 | 2619 | for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { |
727b888f HR |
2620 | if (unique_indirect_regs[i] != 0) { |
2621 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) | |
2622 | + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], | |
2623 | unique_indirect_regs[i] & 0x3FFFF); | |
2624 | ||
2625 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) | |
2626 | + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], | |
2627 | unique_indirect_regs[i] >> 20); | |
2628 | } | |
6bce4667 HZ |
2629 | } |
2630 | ||
2631 | kfree(register_list_format); | |
2632 | return 0; | |
2633 | } | |
2634 | ||
2635 | static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) | |
2636 | { | |
0e5293d0 | 2637 | WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); |
6bce4667 HZ |
2638 | } |
2639 | ||
91d3130a HZ |
2640 | static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, |
2641 | bool enable) | |
2642 | { | |
2643 | uint32_t data = 0; | |
2644 | uint32_t default_data = 0; | |
2645 | ||
2646 | default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); | |
7b3fa67d | 2647 | if (enable) { |
91d3130a HZ |
2648 | /* enable GFXIP control over CGPG */ |
2649 | data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; | |
2650 | if(default_data != data) | |
2651 | WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); | |
2652 | ||
2653 | /* update status */ | |
2654 | data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; | |
2655 | data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); | |
2656 | if(default_data != data) | |
2657 | WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); | |
2658 | } else { | |
2659 | /* restore GFXIP control over GCPG */ | |
2660 | data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; | |
2661 | if(default_data != data) | |
2662 | WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); | |
2663 | } | |
2664 | } | |
2665 | ||
2666 | static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) | |
2667 | { | |
2668 | uint32_t data = 0; | |
2669 | ||
2670 | if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | | |
2671 | AMD_PG_SUPPORT_GFX_SMG | | |
2672 | AMD_PG_SUPPORT_GFX_DMG)) { | |
2673 | /* init IDLE_POLL_COUNT = 60 */ | |
2674 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); | |
2675 | data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; | |
2676 | data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); | |
2677 | WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); | |
2678 | ||
2679 | /* init RLC PG Delay */ | |
2680 | data = 0; | |
2681 | data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); | |
2682 | data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); | |
2683 | data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); | |
2684 | data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); | |
2685 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); | |
2686 | ||
2687 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); | |
2688 | data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; | |
2689 | data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); | |
2690 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); | |
2691 | ||
2692 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); | |
2693 | data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; | |
2694 | data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); | |
2695 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); | |
2696 | ||
2697 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); | |
2698 | data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; | |
2699 | ||
2700 | /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ | |
2701 | data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); | |
2702 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); | |
1d789535 | 2703 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) |
b6df946e | 2704 | pwr_10_0_gfxip_control_over_cgpg(adev, true); |
91d3130a HZ |
2705 | } |
2706 | } | |
2707 | ||
ed5ad1e4 HZ |
2708 | static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, |
2709 | bool enable) | |
2710 | { | |
2711 | uint32_t data = 0; | |
2712 | uint32_t default_data = 0; | |
2713 | ||
2714 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
e24c7f06 TSD |
2715 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2716 | SMU_CLK_SLOWDOWN_ON_PU_ENABLE, | |
2717 | enable ? 1 : 0); | |
2718 | if (default_data != data) | |
2719 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
ed5ad1e4 HZ |
2720 | } |
2721 | ||
2722 | static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, | |
2723 | bool enable) | |
2724 | { | |
2725 | uint32_t data = 0; | |
2726 | uint32_t default_data = 0; | |
2727 | ||
2728 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
b926fe8e TSD |
2729 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2730 | SMU_CLK_SLOWDOWN_ON_PD_ENABLE, | |
2731 | enable ? 1 : 0); | |
2732 | if(default_data != data) | |
2733 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
ed5ad1e4 HZ |
2734 | } |
2735 | ||
3a6cc477 HZ |
2736 | static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, |
2737 | bool enable) | |
2738 | { | |
2739 | uint32_t data = 0; | |
2740 | uint32_t default_data = 0; | |
2741 | ||
2742 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
54cfe0fc TSD |
2743 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2744 | CP_PG_DISABLE, | |
2745 | enable ? 0 : 1); | |
2746 | if(default_data != data) | |
2747 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
3a6cc477 HZ |
2748 | } |
2749 | ||
197f95c8 HZ |
2750 | static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, |
2751 | bool enable) | |
2752 | { | |
2753 | uint32_t data, default_data; | |
2754 | ||
2755 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
f55ee212 TSD |
2756 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2757 | GFX_POWER_GATING_ENABLE, | |
2758 | enable ? 1 : 0); | |
197f95c8 HZ |
2759 | if(default_data != data) |
2760 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
2761 | } | |
2762 | ||
2763 | static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, | |
2764 | bool enable) | |
2765 | { | |
2766 | uint32_t data, default_data; | |
2767 | ||
2768 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
513f8133 TSD |
2769 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2770 | GFX_PIPELINE_PG_ENABLE, | |
2771 | enable ? 1 : 0); | |
197f95c8 HZ |
2772 | if(default_data != data) |
2773 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
2774 | ||
2775 | if (!enable) | |
2776 | /* read any GFX register to wake up GFX */ | |
2777 | data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); | |
2778 | } | |
2779 | ||
552c8f76 | 2780 | static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, |
2781 | bool enable) | |
18924c71 HZ |
2782 | { |
2783 | uint32_t data, default_data; | |
2784 | ||
2785 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
7915c8fd TSD |
2786 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2787 | STATIC_PER_CU_PG_ENABLE, | |
2788 | enable ? 1 : 0); | |
18924c71 HZ |
2789 | if(default_data != data) |
2790 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
2791 | } | |
2792 | ||
552c8f76 | 2793 | static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, |
18924c71 HZ |
2794 | bool enable) |
2795 | { | |
2796 | uint32_t data, default_data; | |
2797 | ||
2798 | default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); | |
e567fa69 TSD |
2799 | data = REG_SET_FIELD(data, RLC_PG_CNTL, |
2800 | DYN_PER_CU_PG_ENABLE, | |
2801 | enable ? 1 : 0); | |
18924c71 HZ |
2802 | if(default_data != data) |
2803 | WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); | |
2804 | } | |
2805 | ||
6bce4667 HZ |
2806 | static void gfx_v9_0_init_pg(struct amdgpu_device *adev) |
2807 | { | |
af356b6d EQ |
2808 | gfx_v9_0_init_csb(adev); |
2809 | ||
b58b65cf EQ |
2810 | /* |
2811 | * Rlc save restore list is workable since v2_1. | |
2812 | * And it's needed by gfxoff feature. | |
2813 | */ | |
2814 | if (adev->gfx.rlc.is_rlc_v2_1) { | |
1d789535 | 2815 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) || |
54f78a76 | 2816 | (adev->apu_flags & AMD_APU_IS_RAVEN2)) |
58f46d4b | 2817 | gfx_v9_1_init_rlc_save_restore_list(adev); |
b58b65cf EQ |
2818 | gfx_v9_0_enable_save_restore_machine(adev); |
2819 | } | |
a5acf930 | 2820 | |
6bce4667 HZ |
2821 | if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | |
2822 | AMD_PG_SUPPORT_GFX_SMG | | |
2823 | AMD_PG_SUPPORT_GFX_DMG | | |
2824 | AMD_PG_SUPPORT_CP | | |
2825 | AMD_PG_SUPPORT_GDS | | |
2826 | AMD_PG_SUPPORT_RLC_SMU_HS)) { | |
2c113b99 LM |
2827 | WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, |
2828 | adev->gfx.rlc.cp_table_gpu_addr >> 8); | |
a5acf930 | 2829 | gfx_v9_0_init_gfx_power_gating(adev); |
6bce4667 HZ |
2830 | } |
2831 | } | |
2832 | ||
a2ef32c5 | 2833 | static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) |
b1023571 | 2834 | { |
b08796ce | 2835 | WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); |
b1023571 | 2836 | gfx_v9_0_enable_gui_idle_interrupt(adev, false); |
b1023571 KW |
2837 | gfx_v9_0_wait_for_rlc_serdes(adev); |
2838 | } | |
2839 | ||
2840 | static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) | |
2841 | { | |
596c8e8b | 2842 | WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); |
b1023571 | 2843 | udelay(50); |
596c8e8b | 2844 | WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); |
b1023571 KW |
2845 | udelay(50); |
2846 | } | |
2847 | ||
2848 | static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) | |
2849 | { | |
2850 | #ifdef AMDGPU_RLC_DEBUG_RETRY | |
2851 | u32 rlc_ucode_ver; | |
2852 | #endif | |
b1023571 | 2853 | |
342cda25 | 2854 | WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); |
ad97d9de | 2855 | udelay(50); |
b1023571 KW |
2856 | |
2857 | /* carrizo do enable cp interrupt after cp inited */ | |
ad97d9de | 2858 | if (!(adev->flags & AMD_IS_APU)) { |
b1023571 | 2859 | gfx_v9_0_enable_gui_idle_interrupt(adev, true); |
ad97d9de | 2860 | udelay(50); |
2861 | } | |
b1023571 KW |
2862 | |
2863 | #ifdef AMDGPU_RLC_DEBUG_RETRY | |
2864 | /* RLC_GPM_GENERAL_6 : RLC Ucode version */ | |
5e78835a | 2865 | rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); |
b1023571 KW |
2866 | if(rlc_ucode_ver == 0x108) { |
2867 | DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", | |
2868 | rlc_ucode_ver, adev->gfx.rlc_fw_version); | |
2869 | /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, | |
2870 | * default is 0x9C4 to create a 100us interval */ | |
5e78835a | 2871 | WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); |
b1023571 | 2872 | /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr |
eaa05d52 | 2873 | * to disable the page fault retry interrupts, default is |
b1023571 | 2874 | * 0x100 (256) */ |
5e78835a | 2875 | WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); |
b1023571 KW |
2876 | } |
2877 | #endif | |
2878 | } | |
2879 | ||
2880 | static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) | |
2881 | { | |
2882 | const struct rlc_firmware_header_v2_0 *hdr; | |
2883 | const __le32 *fw_data; | |
2884 | unsigned i, fw_size; | |
2885 | ||
2886 | if (!adev->gfx.rlc_fw) | |
2887 | return -EINVAL; | |
2888 | ||
2889 | hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; | |
2890 | amdgpu_ucode_print_rlc_hdr(&hdr->header); | |
2891 | ||
2892 | fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + | |
2893 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2894 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
2895 | ||
5e78835a | 2896 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, |
b1023571 KW |
2897 | RLCG_UCODE_LOADING_START_ADDRESS); |
2898 | for (i = 0; i < fw_size; i++) | |
5e78835a TSD |
2899 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); |
2900 | WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); | |
b1023571 KW |
2901 | |
2902 | return 0; | |
2903 | } | |
2904 | ||
2905 | static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) | |
2906 | { | |
2907 | int r; | |
2908 | ||
f840cc5f ML |
2909 | if (amdgpu_sriov_vf(adev)) { |
2910 | gfx_v9_0_init_csb(adev); | |
cfee05bc | 2911 | return 0; |
f840cc5f | 2912 | } |
cfee05bc | 2913 | |
fdb81fd7 | 2914 | adev->gfx.rlc.funcs->stop(adev); |
b1023571 KW |
2915 | |
2916 | /* disable CG */ | |
5e78835a | 2917 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); |
b1023571 | 2918 | |
6bce4667 HZ |
2919 | gfx_v9_0_init_pg(adev); |
2920 | ||
b1023571 KW |
2921 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
2922 | /* legacy rlc firmware loading */ | |
2923 | r = gfx_v9_0_rlc_load_microcode(adev); | |
2924 | if (r) | |
2925 | return r; | |
2926 | } | |
2927 | ||
1d789535 | 2928 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
2929 | case IP_VERSION(9, 2, 2): |
2930 | case IP_VERSION(9, 1, 0): | |
08b6e172 | 2931 | gfx_v9_0_init_lbpw(adev); |
688be01a AD |
2932 | if (amdgpu_lbpw == 0) |
2933 | gfx_v9_0_enable_lbpw(adev, false); | |
2934 | else | |
2935 | gfx_v9_0_enable_lbpw(adev, true); | |
2936 | break; | |
9d0cb2c3 | 2937 | case IP_VERSION(9, 4, 0): |
08b6e172 | 2938 | gfx_v9_4_init_lbpw(adev); |
688be01a | 2939 | if (amdgpu_lbpw > 0) |
e8835e0e HZ |
2940 | gfx_v9_0_enable_lbpw(adev, true); |
2941 | else | |
2942 | gfx_v9_0_enable_lbpw(adev, false); | |
688be01a AD |
2943 | break; |
2944 | default: | |
2945 | break; | |
e8835e0e HZ |
2946 | } |
2947 | ||
08b6e172 AD |
2948 | gfx_v9_0_update_spm_vmid_internal(adev, 0xf); |
2949 | ||
fdb81fd7 | 2950 | adev->gfx.rlc.funcs->start(adev); |
b1023571 KW |
2951 | |
2952 | return 0; | |
2953 | } | |
2954 | ||
2955 | static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) | |
2956 | { | |
5e78835a | 2957 | u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); |
b1023571 | 2958 | |
ea64468e TSD |
2959 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); |
2960 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); | |
2961 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); | |
1bff7f6c | 2962 | WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); |
b1023571 KW |
2963 | udelay(50); |
2964 | } | |
2965 | ||
2966 | static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) | |
2967 | { | |
2968 | const struct gfx_firmware_header_v1_0 *pfp_hdr; | |
2969 | const struct gfx_firmware_header_v1_0 *ce_hdr; | |
2970 | const struct gfx_firmware_header_v1_0 *me_hdr; | |
2971 | const __le32 *fw_data; | |
2972 | unsigned i, fw_size; | |
2973 | ||
2974 | if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) | |
2975 | return -EINVAL; | |
2976 | ||
2977 | pfp_hdr = (const struct gfx_firmware_header_v1_0 *) | |
2978 | adev->gfx.pfp_fw->data; | |
2979 | ce_hdr = (const struct gfx_firmware_header_v1_0 *) | |
2980 | adev->gfx.ce_fw->data; | |
2981 | me_hdr = (const struct gfx_firmware_header_v1_0 *) | |
2982 | adev->gfx.me_fw->data; | |
2983 | ||
2984 | amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); | |
2985 | amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); | |
2986 | amdgpu_ucode_print_gfx_hdr(&me_hdr->header); | |
2987 | ||
2988 | gfx_v9_0_cp_gfx_enable(adev, false); | |
2989 | ||
2990 | /* PFP */ | |
2991 | fw_data = (const __le32 *) | |
2992 | (adev->gfx.pfp_fw->data + | |
2993 | le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); | |
2994 | fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; | |
5e78835a | 2995 | WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); |
b1023571 | 2996 | for (i = 0; i < fw_size; i++) |
5e78835a TSD |
2997 | WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); |
2998 | WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); | |
b1023571 KW |
2999 | |
3000 | /* CE */ | |
3001 | fw_data = (const __le32 *) | |
3002 | (adev->gfx.ce_fw->data + | |
3003 | le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); | |
3004 | fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; | |
5e78835a | 3005 | WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); |
b1023571 | 3006 | for (i = 0; i < fw_size; i++) |
5e78835a TSD |
3007 | WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); |
3008 | WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); | |
b1023571 KW |
3009 | |
3010 | /* ME */ | |
3011 | fw_data = (const __le32 *) | |
3012 | (adev->gfx.me_fw->data + | |
3013 | le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); | |
3014 | fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; | |
5e78835a | 3015 | WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); |
b1023571 | 3016 | for (i = 0; i < fw_size; i++) |
5e78835a TSD |
3017 | WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); |
3018 | WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); | |
b1023571 KW |
3019 | |
3020 | return 0; | |
3021 | } | |
3022 | ||
b1023571 KW |
3023 | static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) |
3024 | { | |
3025 | struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; | |
3026 | const struct cs_section_def *sect = NULL; | |
3027 | const struct cs_extent_def *ext = NULL; | |
d5de797f | 3028 | int r, i, tmp; |
b1023571 KW |
3029 | |
3030 | /* init the CP */ | |
5e78835a TSD |
3031 | WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); |
3032 | WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); | |
b1023571 KW |
3033 | |
3034 | gfx_v9_0_cp_gfx_enable(adev, true); | |
3035 | ||
d5de797f | 3036 | r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); |
b1023571 KW |
3037 | if (r) { |
3038 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); | |
3039 | return r; | |
3040 | } | |
3041 | ||
3042 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
3043 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
3044 | ||
3045 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); | |
3046 | amdgpu_ring_write(ring, 0x80000000); | |
3047 | amdgpu_ring_write(ring, 0x80000000); | |
3048 | ||
3049 | for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { | |
3050 | for (ext = sect->section; ext->extent != NULL; ++ext) { | |
3051 | if (sect->id == SECT_CONTEXT) { | |
3052 | amdgpu_ring_write(ring, | |
3053 | PACKET3(PACKET3_SET_CONTEXT_REG, | |
3054 | ext->reg_count)); | |
3055 | amdgpu_ring_write(ring, | |
3056 | ext->reg_index - PACKET3_SET_CONTEXT_REG_START); | |
3057 | for (i = 0; i < ext->reg_count; i++) | |
3058 | amdgpu_ring_write(ring, ext->extent[i]); | |
3059 | } | |
3060 | } | |
3061 | } | |
3062 | ||
3063 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
3064 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); | |
3065 | ||
3066 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); | |
3067 | amdgpu_ring_write(ring, 0); | |
3068 | ||
3069 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); | |
3070 | amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); | |
3071 | amdgpu_ring_write(ring, 0x8000); | |
3072 | amdgpu_ring_write(ring, 0x8000); | |
3073 | ||
d5de797f KW |
3074 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); |
3075 | tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | | |
3076 | (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); | |
3077 | amdgpu_ring_write(ring, tmp); | |
3078 | amdgpu_ring_write(ring, 0); | |
3079 | ||
b1023571 KW |
3080 | amdgpu_ring_commit(ring); |
3081 | ||
3082 | return 0; | |
3083 | } | |
3084 | ||
3085 | static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) | |
3086 | { | |
3087 | struct amdgpu_ring *ring; | |
3088 | u32 tmp; | |
3089 | u32 rb_bufsz; | |
3fc08b61 | 3090 | u64 rb_addr, rptr_addr, wptr_gpu_addr; |
b1023571 KW |
3091 | |
3092 | /* Set the write pointer delay */ | |
5e78835a | 3093 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); |
b1023571 KW |
3094 | |
3095 | /* set the RB to use vmid 0 */ | |
5e78835a | 3096 | WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); |
b1023571 KW |
3097 | |
3098 | /* Set ring buffer size */ | |
3099 | ring = &adev->gfx.gfx_ring[0]; | |
3100 | rb_bufsz = order_base_2(ring->ring_size / 8); | |
3101 | tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); | |
3102 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); | |
3103 | #ifdef __BIG_ENDIAN | |
3104 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); | |
3105 | #endif | |
5e78835a | 3106 | WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); |
b1023571 KW |
3107 | |
3108 | /* Initialize the ring buffer's write pointers */ | |
3109 | ring->wptr = 0; | |
5e78835a TSD |
3110 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); |
3111 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); | |
b1023571 KW |
3112 | |
3113 | /* set the wb address wether it's enabled or not */ | |
3748424b | 3114 | rptr_addr = ring->rptr_gpu_addr; |
5e78835a TSD |
3115 | WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); |
3116 | WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); | |
b1023571 | 3117 | |
3748424b | 3118 | wptr_gpu_addr = ring->wptr_gpu_addr; |
5e78835a TSD |
3119 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); |
3120 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); | |
3fc08b61 | 3121 | |
b1023571 | 3122 | mdelay(1); |
5e78835a | 3123 | WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); |
b1023571 KW |
3124 | |
3125 | rb_addr = ring->gpu_addr >> 8; | |
5e78835a TSD |
3126 | WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); |
3127 | WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); | |
b1023571 | 3128 | |
5e78835a | 3129 | tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); |
b1023571 KW |
3130 | if (ring->use_doorbell) { |
3131 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, | |
3132 | DOORBELL_OFFSET, ring->doorbell_index); | |
3133 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, | |
3134 | DOORBELL_EN, 1); | |
3135 | } else { | |
3136 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); | |
3137 | } | |
5e78835a | 3138 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); |
b1023571 KW |
3139 | |
3140 | tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, | |
3141 | DOORBELL_RANGE_LOWER, ring->doorbell_index); | |
5e78835a | 3142 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); |
b1023571 | 3143 | |
5e78835a | 3144 | WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, |
b1023571 KW |
3145 | CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); |
3146 | ||
3147 | ||
3148 | /* start the ring */ | |
3149 | gfx_v9_0_cp_gfx_start(adev); | |
b1023571 KW |
3150 | |
3151 | return 0; | |
3152 | } | |
3153 | ||
3154 | static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) | |
3155 | { | |
b1023571 | 3156 | if (enable) { |
1bff7f6c | 3157 | WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); |
b1023571 | 3158 | } else { |
1bff7f6c | 3159 | WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, |
b1023571 | 3160 | (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); |
277bd337 | 3161 | adev->gfx.kiq[0].ring.sched.ready = false; |
b1023571 KW |
3162 | } |
3163 | udelay(50); | |
3164 | } | |
3165 | ||
b1023571 KW |
3166 | static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) |
3167 | { | |
3168 | const struct gfx_firmware_header_v1_0 *mec_hdr; | |
3169 | const __le32 *fw_data; | |
3170 | unsigned i; | |
3171 | u32 tmp; | |
3172 | ||
3173 | if (!adev->gfx.mec_fw) | |
3174 | return -EINVAL; | |
3175 | ||
3176 | gfx_v9_0_cp_compute_enable(adev, false); | |
3177 | ||
3178 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; | |
3179 | amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); | |
3180 | ||
3181 | fw_data = (const __le32 *) | |
3182 | (adev->gfx.mec_fw->data + | |
3183 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); | |
3184 | tmp = 0; | |
3185 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); | |
3186 | tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); | |
5e78835a | 3187 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); |
b1023571 | 3188 | |
5e78835a | 3189 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, |
b1023571 | 3190 | adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); |
5e78835a | 3191 | WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, |
b1023571 | 3192 | upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); |
eaa05d52 | 3193 | |
b1023571 | 3194 | /* MEC1 */ |
5e78835a | 3195 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, |
b1023571 KW |
3196 | mec_hdr->jt_offset); |
3197 | for (i = 0; i < mec_hdr->jt_size; i++) | |
5e78835a | 3198 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, |
b1023571 KW |
3199 | le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); |
3200 | ||
5e78835a | 3201 | WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, |
b1023571 KW |
3202 | adev->gfx.mec_fw_version); |
3203 | /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ | |
3204 | ||
3205 | return 0; | |
3206 | } | |
3207 | ||
464826d6 XY |
3208 | /* KIQ functions */ |
3209 | static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) | |
b1023571 | 3210 | { |
464826d6 XY |
3211 | uint32_t tmp; |
3212 | struct amdgpu_device *adev = ring->adev; | |
b1023571 | 3213 | |
464826d6 | 3214 | /* tell RLC which is KIQ queue */ |
5e78835a | 3215 | tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); |
464826d6 XY |
3216 | tmp &= 0xffffff00; |
3217 | tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); | |
1bff7f6c | 3218 | WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); |
464826d6 | 3219 | tmp |= 0x80; |
1bff7f6c | 3220 | WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); |
464826d6 | 3221 | } |
b1023571 | 3222 | |
33abcb1f ND |
3223 | static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) |
3224 | { | |
3225 | struct amdgpu_device *adev = ring->adev; | |
3226 | ||
3227 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { | |
8c0225d7 | 3228 | if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { |
33abcb1f | 3229 | mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; |
33abcb1f ND |
3230 | mqd->cp_hqd_queue_priority = |
3231 | AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; | |
33abcb1f ND |
3232 | } |
3233 | } | |
3234 | } | |
3235 | ||
e322edc3 | 3236 | static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) |
464826d6 | 3237 | { |
33fb8698 | 3238 | struct amdgpu_device *adev = ring->adev; |
e322edc3 | 3239 | struct v9_mqd *mqd = ring->mqd_ptr; |
464826d6 XY |
3240 | uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; |
3241 | uint32_t tmp; | |
3242 | ||
3243 | mqd->header = 0xC0310800; | |
3244 | mqd->compute_pipelinestat_enable = 0x00000001; | |
3245 | mqd->compute_static_thread_mgmt_se0 = 0xffffffff; | |
3246 | mqd->compute_static_thread_mgmt_se1 = 0xffffffff; | |
3247 | mqd->compute_static_thread_mgmt_se2 = 0xffffffff; | |
3248 | mqd->compute_static_thread_mgmt_se3 = 0xffffffff; | |
5145d57e JC |
3249 | mqd->compute_static_thread_mgmt_se4 = 0xffffffff; |
3250 | mqd->compute_static_thread_mgmt_se5 = 0xffffffff; | |
3251 | mqd->compute_static_thread_mgmt_se6 = 0xffffffff; | |
3252 | mqd->compute_static_thread_mgmt_se7 = 0xffffffff; | |
464826d6 XY |
3253 | mqd->compute_misc_reserved = 0x00000003; |
3254 | ||
ffe6d881 AD |
3255 | mqd->dynamic_cu_mask_addr_lo = |
3256 | lower_32_bits(ring->mqd_gpu_addr | |
3257 | + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); | |
3258 | mqd->dynamic_cu_mask_addr_hi = | |
3259 | upper_32_bits(ring->mqd_gpu_addr | |
3260 | + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); | |
3261 | ||
d72f2f46 | 3262 | eop_base_addr = ring->eop_gpu_addr >> 8; |
464826d6 XY |
3263 | mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; |
3264 | mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); | |
3265 | ||
3266 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ | |
5e78835a | 3267 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); |
464826d6 | 3268 | tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, |
268cb4c7 | 3269 | (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); |
464826d6 XY |
3270 | |
3271 | mqd->cp_hqd_eop_control = tmp; | |
3272 | ||
3273 | /* enable doorbell? */ | |
5e78835a | 3274 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); |
464826d6 XY |
3275 | |
3276 | if (ring->use_doorbell) { | |
3277 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, | |
3278 | DOORBELL_OFFSET, ring->doorbell_index); | |
3279 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, | |
3280 | DOORBELL_EN, 1); | |
3281 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, | |
3282 | DOORBELL_SOURCE, 0); | |
3283 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, | |
3284 | DOORBELL_HIT, 0); | |
78888cff | 3285 | } else { |
464826d6 XY |
3286 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
3287 | DOORBELL_EN, 0); | |
78888cff | 3288 | } |
464826d6 XY |
3289 | |
3290 | mqd->cp_hqd_pq_doorbell_control = tmp; | |
3291 | ||
3292 | /* disable the queue if it's active */ | |
3293 | ring->wptr = 0; | |
3294 | mqd->cp_hqd_dequeue_request = 0; | |
3295 | mqd->cp_hqd_pq_rptr = 0; | |
3296 | mqd->cp_hqd_pq_wptr_lo = 0; | |
3297 | mqd->cp_hqd_pq_wptr_hi = 0; | |
3298 | ||
3299 | /* set the pointer to the MQD */ | |
33fb8698 AD |
3300 | mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; |
3301 | mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); | |
464826d6 XY |
3302 | |
3303 | /* set MQD vmid to 0 */ | |
5e78835a | 3304 | tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); |
464826d6 XY |
3305 | tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); |
3306 | mqd->cp_mqd_control = tmp; | |
3307 | ||
3308 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ | |
3309 | hqd_gpu_addr = ring->gpu_addr >> 8; | |
3310 | mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; | |
3311 | mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); | |
3312 | ||
3313 | /* set up the HQD, this is similar to CP_RB0_CNTL */ | |
5e78835a | 3314 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); |
464826d6 XY |
3315 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, |
3316 | (order_base_2(ring->ring_size / 4) - 1)); | |
3317 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, | |
84203554 | 3318 | (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); |
464826d6 XY |
3319 | #ifdef __BIG_ENDIAN |
3320 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); | |
3321 | #endif | |
3322 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); | |
3323 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); | |
3324 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); | |
3325 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); | |
3326 | mqd->cp_hqd_pq_control = tmp; | |
3327 | ||
3328 | /* set the wb address whether it's enabled or not */ | |
3748424b | 3329 | wb_gpu_addr = ring->rptr_gpu_addr; |
464826d6 XY |
3330 | mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; |
3331 | mqd->cp_hqd_pq_rptr_report_addr_hi = | |
3332 | upper_32_bits(wb_gpu_addr) & 0xffff; | |
3333 | ||
3334 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ | |
3748424b | 3335 | wb_gpu_addr = ring->wptr_gpu_addr; |
464826d6 XY |
3336 | mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; |
3337 | mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; | |
3338 | ||
464826d6 XY |
3339 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
3340 | ring->wptr = 0; | |
0274a9c5 | 3341 | mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); |
464826d6 XY |
3342 | |
3343 | /* set the vmid for the queue */ | |
3344 | mqd->cp_hqd_vmid = 0; | |
3345 | ||
0274a9c5 | 3346 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); |
464826d6 XY |
3347 | tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); |
3348 | mqd->cp_hqd_persistent_state = tmp; | |
3349 | ||
fca4ce69 AD |
3350 | /* set MIN_IB_AVAIL_SIZE */ |
3351 | tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); | |
3352 | tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); | |
3353 | mqd->cp_hqd_ib_control = tmp; | |
3354 | ||
33abcb1f ND |
3355 | /* set static priority for a queue/ring */ |
3356 | gfx_v9_0_mqd_set_priority(ring, mqd); | |
e7947476 | 3357 | mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); |
33abcb1f | 3358 | |
0e5b7a95 HR |
3359 | /* map_queues packet doesn't need activate the queue, |
3360 | * so only kiq need set this field. | |
3361 | */ | |
3362 | if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) | |
3363 | mqd->cp_hqd_active = 1; | |
464826d6 XY |
3364 | |
3365 | return 0; | |
3366 | } | |
3367 | ||
e322edc3 | 3368 | static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) |
464826d6 | 3369 | { |
33fb8698 | 3370 | struct amdgpu_device *adev = ring->adev; |
e322edc3 | 3371 | struct v9_mqd *mqd = ring->mqd_ptr; |
464826d6 XY |
3372 | int j; |
3373 | ||
3374 | /* disable wptr polling */ | |
72edadd5 | 3375 | WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); |
464826d6 | 3376 | |
1bff7f6c | 3377 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, |
464826d6 | 3378 | mqd->cp_hqd_eop_base_addr_lo); |
1bff7f6c | 3379 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, |
464826d6 XY |
3380 | mqd->cp_hqd_eop_base_addr_hi); |
3381 | ||
3382 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ | |
1bff7f6c | 3383 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, |
464826d6 XY |
3384 | mqd->cp_hqd_eop_control); |
3385 | ||
3386 | /* enable doorbell? */ | |
1bff7f6c | 3387 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, |
464826d6 XY |
3388 | mqd->cp_hqd_pq_doorbell_control); |
3389 | ||
3390 | /* disable the queue if it's active */ | |
5e78835a | 3391 | if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { |
1bff7f6c | 3392 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); |
464826d6 | 3393 | for (j = 0; j < adev->usec_timeout; j++) { |
5e78835a | 3394 | if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) |
464826d6 XY |
3395 | break; |
3396 | udelay(1); | |
3397 | } | |
1bff7f6c | 3398 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, |
464826d6 | 3399 | mqd->cp_hqd_dequeue_request); |
1bff7f6c | 3400 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, |
464826d6 | 3401 | mqd->cp_hqd_pq_rptr); |
1bff7f6c | 3402 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, |
464826d6 | 3403 | mqd->cp_hqd_pq_wptr_lo); |
1bff7f6c | 3404 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, |
464826d6 XY |
3405 | mqd->cp_hqd_pq_wptr_hi); |
3406 | } | |
3407 | ||
3408 | /* set the pointer to the MQD */ | |
1bff7f6c | 3409 | WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, |
464826d6 | 3410 | mqd->cp_mqd_base_addr_lo); |
1bff7f6c | 3411 | WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, |
464826d6 XY |
3412 | mqd->cp_mqd_base_addr_hi); |
3413 | ||
3414 | /* set MQD vmid to 0 */ | |
1bff7f6c | 3415 | WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, |
464826d6 XY |
3416 | mqd->cp_mqd_control); |
3417 | ||
3418 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ | |
1bff7f6c | 3419 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, |
464826d6 | 3420 | mqd->cp_hqd_pq_base_lo); |
1bff7f6c | 3421 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, |
464826d6 XY |
3422 | mqd->cp_hqd_pq_base_hi); |
3423 | ||
3424 | /* set up the HQD, this is similar to CP_RB0_CNTL */ | |
1bff7f6c | 3425 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, |
464826d6 XY |
3426 | mqd->cp_hqd_pq_control); |
3427 | ||
3428 | /* set the wb address whether it's enabled or not */ | |
1bff7f6c | 3429 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, |
464826d6 | 3430 | mqd->cp_hqd_pq_rptr_report_addr_lo); |
1bff7f6c | 3431 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, |
464826d6 XY |
3432 | mqd->cp_hqd_pq_rptr_report_addr_hi); |
3433 | ||
3434 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ | |
1bff7f6c | 3435 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, |
464826d6 | 3436 | mqd->cp_hqd_pq_wptr_poll_addr_lo); |
1bff7f6c | 3437 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, |
464826d6 XY |
3438 | mqd->cp_hqd_pq_wptr_poll_addr_hi); |
3439 | ||
3440 | /* enable the doorbell if requested */ | |
3441 | if (ring->use_doorbell) { | |
5e78835a | 3442 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, |
9564f192 | 3443 | (adev->doorbell_index.kiq * 2) << 2); |
198fbe15 YZ |
3444 | /* If GC has entered CGPG, ringing doorbell > first page |
3445 | * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to | |
3446 | * workaround this issue. And this change has to align with firmware | |
3447 | * update. | |
3448 | */ | |
3449 | if (check_if_enlarge_doorbell_range(adev)) | |
3450 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, | |
3451 | (adev->doorbell.size - 4)); | |
3452 | else | |
3453 | WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, | |
962f2f1a | 3454 | (adev->doorbell_index.userqueue_end * 2) << 2); |
464826d6 XY |
3455 | } |
3456 | ||
bdb50274 | 3457 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, |
464826d6 XY |
3458 | mqd->cp_hqd_pq_doorbell_control); |
3459 | ||
3460 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ | |
1bff7f6c | 3461 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, |
464826d6 | 3462 | mqd->cp_hqd_pq_wptr_lo); |
1bff7f6c | 3463 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, |
464826d6 XY |
3464 | mqd->cp_hqd_pq_wptr_hi); |
3465 | ||
3466 | /* set the vmid for the queue */ | |
1bff7f6c | 3467 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); |
464826d6 | 3468 | |
1bff7f6c | 3469 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, |
464826d6 XY |
3470 | mqd->cp_hqd_persistent_state); |
3471 | ||
3472 | /* activate the queue */ | |
1bff7f6c | 3473 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, |
464826d6 XY |
3474 | mqd->cp_hqd_active); |
3475 | ||
72edadd5 TSD |
3476 | if (ring->use_doorbell) |
3477 | WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); | |
464826d6 XY |
3478 | |
3479 | return 0; | |
3480 | } | |
3481 | ||
326aa996 AG |
3482 | static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) |
3483 | { | |
3484 | struct amdgpu_device *adev = ring->adev; | |
3485 | int j; | |
3486 | ||
3487 | /* disable the queue if it's active */ | |
3488 | if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { | |
3489 | ||
1bff7f6c | 3490 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); |
326aa996 AG |
3491 | |
3492 | for (j = 0; j < adev->usec_timeout; j++) { | |
3493 | if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) | |
3494 | break; | |
3495 | udelay(1); | |
3496 | } | |
3497 | ||
f7a9ee81 | 3498 | if (j == AMDGPU_MAX_USEC_TIMEOUT) { |
326aa996 AG |
3499 | DRM_DEBUG("KIQ dequeue request failed.\n"); |
3500 | ||
f7a9ee81 | 3501 | /* Manual disable if dequeue request times out */ |
1bff7f6c | 3502 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); |
326aa996 AG |
3503 | } |
3504 | ||
1bff7f6c | 3505 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, |
326aa996 AG |
3506 | 0); |
3507 | } | |
3508 | ||
1bff7f6c TH |
3509 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); |
3510 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); | |
3511 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); | |
3512 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); | |
3513 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); | |
3514 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); | |
3515 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); | |
3516 | WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); | |
326aa996 AG |
3517 | |
3518 | return 0; | |
3519 | } | |
3520 | ||
e322edc3 | 3521 | static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) |
464826d6 XY |
3522 | { |
3523 | struct amdgpu_device *adev = ring->adev; | |
e322edc3 | 3524 | struct v9_mqd *mqd = ring->mqd_ptr; |
a330b52a | 3525 | struct v9_mqd *tmp_mqd; |
464826d6 | 3526 | |
898b7893 | 3527 | gfx_v9_0_kiq_setting(ring); |
464826d6 | 3528 | |
a330b52a | 3529 | /* GPU could be in bad state during probe, driver trigger the reset |
3530 | * after load the SMU, in this case , the mqd is not be initialized. | |
3531 | * driver need to re-init the mqd. | |
3532 | * check mqd->cp_hqd_pq_control since this value should not be 0 | |
3533 | */ | |
def799c6 | 3534 | tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup; |
a330b52a | 3535 | if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ |
3536 | /* for GPU_RESET case , reset MQD to a clean status */ | |
def799c6 LM |
3537 | if (adev->gfx.kiq[0].mqd_backup) |
3538 | memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation)); | |
464826d6 XY |
3539 | |
3540 | /* reset ring buffer */ | |
3541 | ring->wptr = 0; | |
b98724db | 3542 | amdgpu_ring_clear_ring(ring); |
464826d6 | 3543 | |
898b7893 | 3544 | mutex_lock(&adev->srbm_mutex); |
5aa998ba | 3545 | soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); |
898b7893 | 3546 | gfx_v9_0_kiq_init_register(ring); |
5aa998ba | 3547 | soc15_grbm_select(adev, 0, 0, 0, 0, 0); |
898b7893 | 3548 | mutex_unlock(&adev->srbm_mutex); |
464826d6 | 3549 | } else { |
ffe6d881 AD |
3550 | memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); |
3551 | ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; | |
3552 | ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; | |
ec4927d4 VZ |
3553 | if (amdgpu_sriov_vf(adev) && adev->in_suspend) |
3554 | amdgpu_ring_clear_ring(ring); | |
ba0c19f5 | 3555 | mutex_lock(&adev->srbm_mutex); |
5aa998ba | 3556 | soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); |
ba0c19f5 AD |
3557 | gfx_v9_0_mqd_init(ring); |
3558 | gfx_v9_0_kiq_init_register(ring); | |
5aa998ba | 3559 | soc15_grbm_select(adev, 0, 0, 0, 0, 0); |
ba0c19f5 AD |
3560 | mutex_unlock(&adev->srbm_mutex); |
3561 | ||
def799c6 LM |
3562 | if (adev->gfx.kiq[0].mqd_backup) |
3563 | memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); | |
464826d6 XY |
3564 | } |
3565 | ||
0f1dfd52 | 3566 | return 0; |
898b7893 AD |
3567 | } |
3568 | ||
3569 | static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) | |
3570 | { | |
3571 | struct amdgpu_device *adev = ring->adev; | |
898b7893 AD |
3572 | struct v9_mqd *mqd = ring->mqd_ptr; |
3573 | int mqd_idx = ring - &adev->gfx.compute_ring[0]; | |
a330b52a | 3574 | struct v9_mqd *tmp_mqd; |
3575 | ||
3576 | /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control | |
3577 | * is not be initialized before | |
3578 | */ | |
3579 | tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; | |
898b7893 | 3580 | |
a330b52a | 3581 | if (!tmp_mqd->cp_hqd_pq_control || |
3582 | (!amdgpu_in_reset(adev) && !adev->in_suspend)) { | |
ffe6d881 AD |
3583 | memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); |
3584 | ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; | |
3585 | ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; | |
464826d6 | 3586 | mutex_lock(&adev->srbm_mutex); |
5aa998ba | 3587 | soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); |
e322edc3 | 3588 | gfx_v9_0_mqd_init(ring); |
5aa998ba | 3589 | soc15_grbm_select(adev, 0, 0, 0, 0, 0); |
464826d6 XY |
3590 | mutex_unlock(&adev->srbm_mutex); |
3591 | ||
898b7893 | 3592 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
ffe6d881 | 3593 | memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); |
45b54a7d AD |
3594 | } else { |
3595 | /* restore MQD to a clean status */ | |
898b7893 | 3596 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
ffe6d881 | 3597 | memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); |
464826d6 XY |
3598 | /* reset ring buffer */ |
3599 | ring->wptr = 0; | |
3748424b | 3600 | atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); |
898b7893 | 3601 | amdgpu_ring_clear_ring(ring); |
464826d6 XY |
3602 | } |
3603 | ||
464826d6 XY |
3604 | return 0; |
3605 | } | |
3606 | ||
3607 | static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) | |
3608 | { | |
a9a8a788 RZ |
3609 | struct amdgpu_ring *ring; |
3610 | int r; | |
464826d6 | 3611 | |
277bd337 | 3612 | ring = &adev->gfx.kiq[0].ring; |
e1d53aa8 AD |
3613 | |
3614 | r = amdgpu_bo_reserve(ring->mqd_obj, false); | |
3615 | if (unlikely(r != 0)) | |
a9a8a788 | 3616 | return r; |
e1d53aa8 AD |
3617 | |
3618 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); | |
1385d88c SB |
3619 | if (unlikely(r != 0)) { |
3620 | amdgpu_bo_unreserve(ring->mqd_obj); | |
a9a8a788 | 3621 | return r; |
1385d88c | 3622 | } |
a9a8a788 RZ |
3623 | |
3624 | gfx_v9_0_kiq_init_queue(ring); | |
3625 | amdgpu_bo_kunmap(ring->mqd_obj); | |
3626 | ring->mqd_ptr = NULL; | |
e1d53aa8 | 3627 | amdgpu_bo_unreserve(ring->mqd_obj); |
a9a8a788 RZ |
3628 | return 0; |
3629 | } | |
3630 | ||
3631 | static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) | |
3632 | { | |
3633 | struct amdgpu_ring *ring = NULL; | |
3634 | int r = 0, i; | |
3635 | ||
3636 | gfx_v9_0_cp_compute_enable(adev, true); | |
464826d6 XY |
3637 | |
3638 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
3639 | ring = &adev->gfx.compute_ring[i]; | |
e1d53aa8 AD |
3640 | |
3641 | r = amdgpu_bo_reserve(ring->mqd_obj, false); | |
3642 | if (unlikely(r != 0)) | |
3643 | goto done; | |
3644 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); | |
3645 | if (!r) { | |
898b7893 | 3646 | r = gfx_v9_0_kcq_init_queue(ring); |
464826d6 XY |
3647 | amdgpu_bo_kunmap(ring->mqd_obj); |
3648 | ring->mqd_ptr = NULL; | |
464826d6 | 3649 | } |
e1d53aa8 AD |
3650 | amdgpu_bo_unreserve(ring->mqd_obj); |
3651 | if (r) | |
3652 | goto done; | |
464826d6 XY |
3653 | } |
3654 | ||
def799c6 | 3655 | r = amdgpu_gfx_enable_kcq(adev, 0); |
e1d53aa8 AD |
3656 | done: |
3657 | return r; | |
464826d6 XY |
3658 | } |
3659 | ||
b1023571 KW |
3660 | static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) |
3661 | { | |
bd3402ea | 3662 | int r, i; |
b1023571 KW |
3663 | struct amdgpu_ring *ring; |
3664 | ||
3665 | if (!(adev->flags & AMD_IS_APU)) | |
3666 | gfx_v9_0_enable_gui_idle_interrupt(adev, false); | |
3667 | ||
3668 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
35b14475 | 3669 | if (adev->gfx.num_gfx_rings) { |
f8b733b9 LM |
3670 | /* legacy firmware loading */ |
3671 | r = gfx_v9_0_cp_gfx_load_microcode(adev); | |
3672 | if (r) | |
3673 | return r; | |
3674 | } | |
b1023571 KW |
3675 | |
3676 | r = gfx_v9_0_cp_compute_load_microcode(adev); | |
3677 | if (r) | |
3678 | return r; | |
3679 | } | |
3680 | ||
a9a8a788 RZ |
3681 | r = gfx_v9_0_kiq_resume(adev); |
3682 | if (r) | |
3683 | return r; | |
3684 | ||
35b14475 | 3685 | if (adev->gfx.num_gfx_rings) { |
f5cdc2da LM |
3686 | r = gfx_v9_0_cp_gfx_resume(adev); |
3687 | if (r) | |
3688 | return r; | |
3689 | } | |
b1023571 | 3690 | |
a9a8a788 | 3691 | r = gfx_v9_0_kcq_resume(adev); |
b1023571 KW |
3692 | if (r) |
3693 | return r; | |
3694 | ||
35b14475 | 3695 | if (adev->gfx.num_gfx_rings) { |
f5cdc2da LM |
3696 | ring = &adev->gfx.gfx_ring[0]; |
3697 | r = amdgpu_ring_test_helper(ring); | |
3698 | if (r) | |
3699 | return r; | |
3700 | } | |
e30a5223 | 3701 | |
b1023571 KW |
3702 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
3703 | ring = &adev->gfx.compute_ring[i]; | |
c66ed765 | 3704 | amdgpu_ring_test_helper(ring); |
b1023571 KW |
3705 | } |
3706 | ||
3707 | gfx_v9_0_enable_gui_idle_interrupt(adev, true); | |
3708 | ||
3709 | return 0; | |
3710 | } | |
3711 | ||
22d39fe7 JG |
3712 | static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) |
3713 | { | |
3714 | u32 tmp; | |
3715 | ||
1d789535 AD |
3716 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) && |
3717 | adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)) | |
22d39fe7 JG |
3718 | return; |
3719 | ||
3720 | tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); | |
3721 | tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, | |
3722 | adev->df.hash_status.hash_64k); | |
3723 | tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, | |
3724 | adev->df.hash_status.hash_2m); | |
3725 | tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, | |
3726 | adev->df.hash_status.hash_1g); | |
3727 | WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); | |
3728 | } | |
3729 | ||
b1023571 KW |
3730 | static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) |
3731 | { | |
35b14475 | 3732 | if (adev->gfx.num_gfx_rings) |
f5cdc2da | 3733 | gfx_v9_0_cp_gfx_enable(adev, enable); |
b1023571 KW |
3734 | gfx_v9_0_cp_compute_enable(adev, enable); |
3735 | } | |
3736 | ||
3737 | static int gfx_v9_0_hw_init(void *handle) | |
3738 | { | |
3739 | int r; | |
3740 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
3741 | ||
4cd4c5c0 ML |
3742 | if (!amdgpu_sriov_vf(adev)) |
3743 | gfx_v9_0_init_golden_registers(adev); | |
b1023571 | 3744 | |
434e6df2 | 3745 | gfx_v9_0_constants_init(adev); |
b1023571 | 3746 | |
22d39fe7 JG |
3747 | gfx_v9_0_init_tcp_config(adev); |
3748 | ||
fdb81fd7 | 3749 | r = adev->gfx.rlc.funcs->resume(adev); |
b1023571 KW |
3750 | if (r) |
3751 | return r; | |
3752 | ||
3753 | r = gfx_v9_0_cp_resume(adev); | |
3754 | if (r) | |
3755 | return r; | |
3756 | ||
1d789535 | 3757 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) |
5217811e KW |
3758 | gfx_v9_4_2_set_power_brake_sequence(adev); |
3759 | ||
b1023571 KW |
3760 | return r; |
3761 | } | |
3762 | ||
3763 | static int gfx_v9_0_hw_fini(void *handle) | |
3764 | { | |
3765 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
3766 | ||
d97b02bb GC |
3767 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
3768 | amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); | |
b1023571 KW |
3769 | amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); |
3770 | amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); | |
85f95ad6 | 3771 | |
bff77e86 LM |
3772 | /* DF freeze and kcq disable will fail */ |
3773 | if (!amdgpu_ras_intr_triggered()) | |
3774 | /* disable KCQ to avoid CPC touch memory not valid anymore */ | |
def799c6 | 3775 | amdgpu_gfx_disable_kcq(adev, 0); |
85f95ad6 | 3776 | |
464826d6 | 3777 | if (amdgpu_sriov_vf(adev)) { |
9f0178fb ML |
3778 | gfx_v9_0_cp_gfx_enable(adev, false); |
3779 | /* must disable polling for SRIOV when hw finished, otherwise | |
3780 | * CPC engine may still keep fetching WB address which is already | |
3781 | * invalid after sw finished and trigger DMAR reading error in | |
3782 | * hypervisor side. | |
3783 | */ | |
3784 | WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); | |
464826d6 XY |
3785 | return 0; |
3786 | } | |
326aa996 AG |
3787 | |
3788 | /* Use deinitialize sequence from CAIL when unbinding device from driver, | |
3789 | * otherwise KIQ is hanging when binding back | |
3790 | */ | |
53b3f8f4 | 3791 | if (!amdgpu_in_reset(adev) && !adev->in_suspend) { |
326aa996 | 3792 | mutex_lock(&adev->srbm_mutex); |
277bd337 LM |
3793 | soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, |
3794 | adev->gfx.kiq[0].ring.pipe, | |
5aa998ba | 3795 | adev->gfx.kiq[0].ring.queue, 0, 0); |
277bd337 | 3796 | gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); |
5aa998ba | 3797 | soc15_grbm_select(adev, 0, 0, 0, 0, 0); |
326aa996 AG |
3798 | mutex_unlock(&adev->srbm_mutex); |
3799 | } | |
3800 | ||
b1023571 | 3801 | gfx_v9_0_cp_enable(adev, false); |
b1023571 | 3802 | |
81d104f4 LL |
3803 | /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ |
3804 | if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || | |
3805 | (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) { | |
3806 | dev_dbg(adev->dev, "Skipping RLC halt\n"); | |
142600e8 LL |
3807 | return 0; |
3808 | } | |
3809 | ||
3810 | adev->gfx.rlc.funcs->stop(adev); | |
b1023571 KW |
3811 | return 0; |
3812 | } | |
3813 | ||
3814 | static int gfx_v9_0_suspend(void *handle) | |
3815 | { | |
44779b43 | 3816 | return gfx_v9_0_hw_fini(handle); |
b1023571 KW |
3817 | } |
3818 | ||
3819 | static int gfx_v9_0_resume(void *handle) | |
3820 | { | |
44779b43 | 3821 | return gfx_v9_0_hw_init(handle); |
b1023571 KW |
3822 | } |
3823 | ||
3824 | static bool gfx_v9_0_is_idle(void *handle) | |
3825 | { | |
3826 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
3827 | ||
5e78835a | 3828 | if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), |
b1023571 KW |
3829 | GRBM_STATUS, GUI_ACTIVE)) |
3830 | return false; | |
3831 | else | |
3832 | return true; | |
3833 | } | |
3834 | ||
3835 | static int gfx_v9_0_wait_for_idle(void *handle) | |
3836 | { | |
3837 | unsigned i; | |
b1023571 KW |
3838 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3839 | ||
3840 | for (i = 0; i < adev->usec_timeout; i++) { | |
2b9bdfa7 | 3841 | if (gfx_v9_0_is_idle(handle)) |
b1023571 KW |
3842 | return 0; |
3843 | udelay(1); | |
3844 | } | |
3845 | return -ETIMEDOUT; | |
3846 | } | |
3847 | ||
b1023571 KW |
3848 | static int gfx_v9_0_soft_reset(void *handle) |
3849 | { | |
3850 | u32 grbm_soft_reset = 0; | |
3851 | u32 tmp; | |
3852 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
3853 | ||
3854 | /* GRBM_STATUS */ | |
5e78835a | 3855 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); |
b1023571 KW |
3856 | if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | |
3857 | GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | | |
3858 | GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | | |
3859 | GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | | |
3860 | GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | | |
3861 | GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { | |
3862 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, | |
3863 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1); | |
3864 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, | |
3865 | GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); | |
3866 | } | |
3867 | ||
3868 | if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { | |
3869 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, | |
3870 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1); | |
3871 | } | |
3872 | ||
3873 | /* GRBM_STATUS2 */ | |
5e78835a | 3874 | tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); |
b1023571 KW |
3875 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) |
3876 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, | |
3877 | GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); | |
3878 | ||
3879 | ||
75bac5c6 | 3880 | if (grbm_soft_reset) { |
b1023571 | 3881 | /* stop the rlc */ |
fdb81fd7 | 3882 | adev->gfx.rlc.funcs->stop(adev); |
b1023571 | 3883 | |
35b14475 | 3884 | if (adev->gfx.num_gfx_rings) |
f5cdc2da LM |
3885 | /* Disable GFX parsing/prefetching */ |
3886 | gfx_v9_0_cp_gfx_enable(adev, false); | |
b1023571 KW |
3887 | |
3888 | /* Disable MEC parsing/prefetching */ | |
3889 | gfx_v9_0_cp_compute_enable(adev, false); | |
3890 | ||
3891 | if (grbm_soft_reset) { | |
5e78835a | 3892 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); |
b1023571 KW |
3893 | tmp |= grbm_soft_reset; |
3894 | dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); | |
5e78835a TSD |
3895 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); |
3896 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); | |
b1023571 KW |
3897 | |
3898 | udelay(50); | |
3899 | ||
3900 | tmp &= ~grbm_soft_reset; | |
5e78835a TSD |
3901 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); |
3902 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); | |
b1023571 KW |
3903 | } |
3904 | ||
3905 | /* Wait a little for things to settle down */ | |
3906 | udelay(50); | |
b1023571 KW |
3907 | } |
3908 | return 0; | |
3909 | } | |
3910 | ||
89510a27 ED |
3911 | static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) |
3912 | { | |
3913 | signed long r, cnt = 0; | |
3914 | unsigned long flags; | |
54208194 YT |
3915 | uint32_t seq, reg_val_offs = 0; |
3916 | uint64_t value = 0; | |
277bd337 | 3917 | struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; |
89510a27 ED |
3918 | struct amdgpu_ring *ring = &kiq->ring; |
3919 | ||
3920 | BUG_ON(!ring->funcs->emit_rreg); | |
3921 | ||
3922 | spin_lock_irqsave(&kiq->ring_lock, flags); | |
54208194 | 3923 | if (amdgpu_device_wb_get(adev, ®_val_offs)) { |
54208194 | 3924 | pr_err("critical bug! too many kiq readers\n"); |
04e4e2e9 | 3925 | goto failed_unlock; |
54208194 | 3926 | } |
89510a27 ED |
3927 | amdgpu_ring_alloc(ring, 32); |
3928 | amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); | |
3929 | amdgpu_ring_write(ring, 9 | /* src: register*/ | |
3930 | (5 << 8) | /* dst: memory */ | |
3931 | (1 << 16) | /* count sel */ | |
3932 | (1 << 20)); /* write confirm */ | |
3933 | amdgpu_ring_write(ring, 0); | |
3934 | amdgpu_ring_write(ring, 0); | |
3935 | amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + | |
54208194 | 3936 | reg_val_offs * 4)); |
89510a27 | 3937 | amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + |
54208194 | 3938 | reg_val_offs * 4)); |
04e4e2e9 YT |
3939 | r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); |
3940 | if (r) | |
3941 | goto failed_undo; | |
3942 | ||
89510a27 ED |
3943 | amdgpu_ring_commit(ring); |
3944 | spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
3945 | ||
3946 | r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
3947 | ||
3948 | /* don't wait anymore for gpu reset case because this way may | |
3949 | * block gpu_recover() routine forever, e.g. this virt_kiq_rreg | |
3950 | * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will | |
3951 | * never return if we keep waiting in virt_kiq_rreg, which cause | |
3952 | * gpu_recover() hang there. | |
3953 | * | |
3954 | * also don't wait anymore for IRQ context | |
3955 | * */ | |
dc1794f0 | 3956 | if (r < 1 && (amdgpu_in_reset(adev))) |
89510a27 ED |
3957 | goto failed_kiq_read; |
3958 | ||
3959 | might_sleep(); | |
3960 | while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { | |
3961 | msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); | |
3962 | r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
3963 | } | |
3964 | ||
3965 | if (cnt > MAX_KIQ_REG_TRY) | |
3966 | goto failed_kiq_read; | |
3967 | ||
54208194 YT |
3968 | mb(); |
3969 | value = (uint64_t)adev->wb.wb[reg_val_offs] | | |
3970 | (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; | |
3971 | amdgpu_device_wb_free(adev, reg_val_offs); | |
3972 | return value; | |
89510a27 | 3973 | |
04e4e2e9 YT |
3974 | failed_undo: |
3975 | amdgpu_ring_undo(ring); | |
3976 | failed_unlock: | |
3977 | spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
89510a27 | 3978 | failed_kiq_read: |
04e4e2e9 YT |
3979 | if (reg_val_offs) |
3980 | amdgpu_device_wb_free(adev, reg_val_offs); | |
89510a27 ED |
3981 | pr_err("failed to read gpu clock\n"); |
3982 | return ~0; | |
3983 | } | |
3984 | ||
b1023571 KW |
3985 | static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) |
3986 | { | |
7b37c7f8 | 3987 | uint64_t clock, clock_lo, clock_hi, hi_check; |
b1023571 | 3988 | |
7b37c7f8 AD |
3989 | switch (adev->ip_versions[GC_HWIP][0]) { |
3990 | case IP_VERSION(9, 3, 0): | |
3991 | preempt_disable(); | |
3992 | clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); | |
3993 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); | |
3994 | hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); | |
3995 | /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over | |
3996 | * roughly every 42 seconds. | |
3997 | */ | |
3998 | if (hi_check != clock_hi) { | |
3999 | clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); | |
4000 | clock_hi = hi_check; | |
4001 | } | |
4002 | preempt_enable(); | |
4003 | clock = clock_lo | (clock_hi << 32ULL); | |
4004 | break; | |
4005 | default: | |
4006 | amdgpu_gfx_off_ctrl(adev, false); | |
4007 | mutex_lock(&adev->gfx.gpu_clock_mutex); | |
4008 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) { | |
4009 | clock = gfx_v9_0_kiq_read_clock(adev); | |
4010 | } else { | |
4011 | WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); | |
4012 | clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | | |
4013 | ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); | |
4014 | } | |
4015 | mutex_unlock(&adev->gfx.gpu_clock_mutex); | |
4016 | amdgpu_gfx_off_ctrl(adev, true); | |
4017 | break; | |
f88e2d1f | 4018 | } |
b1023571 KW |
4019 | return clock; |
4020 | } | |
4021 | ||
4022 | static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, | |
4023 | uint32_t vmid, | |
4024 | uint32_t gds_base, uint32_t gds_size, | |
4025 | uint32_t gws_base, uint32_t gws_size, | |
4026 | uint32_t oa_base, uint32_t oa_size) | |
4027 | { | |
946a4d5b SL |
4028 | struct amdgpu_device *adev = ring->adev; |
4029 | ||
b1023571 KW |
4030 | /* GDS Base */ |
4031 | gfx_v9_0_write_data_to_reg(ring, 0, false, | |
946a4d5b | 4032 | SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, |
b1023571 KW |
4033 | gds_base); |
4034 | ||
4035 | /* GDS Size */ | |
4036 | gfx_v9_0_write_data_to_reg(ring, 0, false, | |
946a4d5b | 4037 | SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, |
b1023571 KW |
4038 | gds_size); |
4039 | ||
4040 | /* GWS */ | |
4041 | gfx_v9_0_write_data_to_reg(ring, 0, false, | |
946a4d5b | 4042 | SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, |
b1023571 KW |
4043 | gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); |
4044 | ||
4045 | /* OA */ | |
4046 | gfx_v9_0_write_data_to_reg(ring, 0, false, | |
946a4d5b | 4047 | SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, |
b1023571 KW |
4048 | (1 << (oa_size + oa_base)) - (1 << oa_base)); |
4049 | } | |
4050 | ||
5326ad54 JZ |
4051 | static const u32 vgpr_init_compute_shader[] = |
4052 | { | |
4053 | 0xb07c0000, 0xbe8000ff, | |
4054 | 0x000000f8, 0xbf110800, | |
4055 | 0x7e000280, 0x7e020280, | |
4056 | 0x7e040280, 0x7e060280, | |
4057 | 0x7e080280, 0x7e0a0280, | |
4058 | 0x7e0c0280, 0x7e0e0280, | |
4059 | 0x80808800, 0xbe803200, | |
4060 | 0xbf84fff5, 0xbf9c0000, | |
4061 | 0xd28c0001, 0x0001007f, | |
4062 | 0xd28d0001, 0x0002027e, | |
4063 | 0x10020288, 0xb8810904, | |
4064 | 0xb7814000, 0xd1196a01, | |
4065 | 0x00000301, 0xbe800087, | |
4066 | 0xbefc00c1, 0xd89c4000, | |
4067 | 0x00020201, 0xd89cc080, | |
4068 | 0x00040401, 0x320202ff, | |
4069 | 0x00000800, 0x80808100, | |
4070 | 0xbf84fff8, 0x7e020280, | |
4071 | 0xbf810000, 0x00000000, | |
4072 | }; | |
4073 | ||
4074 | static const u32 sgpr_init_compute_shader[] = | |
4075 | { | |
4076 | 0xb07c0000, 0xbe8000ff, | |
4077 | 0x0000005f, 0xbee50080, | |
4078 | 0xbe812c65, 0xbe822c65, | |
4079 | 0xbe832c65, 0xbe842c65, | |
4080 | 0xbe852c65, 0xb77c0005, | |
4081 | 0x80808500, 0xbf84fff8, | |
4082 | 0xbe800080, 0xbf810000, | |
4083 | }; | |
4084 | ||
93cdb48e DL |
4085 | static const u32 vgpr_init_compute_shader_arcturus[] = { |
4086 | 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, | |
4087 | 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, | |
4088 | 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, | |
4089 | 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, | |
4090 | 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, | |
4091 | 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, | |
4092 | 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, | |
4093 | 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, | |
4094 | 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, | |
4095 | 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, | |
4096 | 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, | |
4097 | 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, | |
4098 | 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, | |
4099 | 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, | |
4100 | 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, | |
4101 | 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, | |
4102 | 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, | |
4103 | 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, | |
4104 | 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, | |
4105 | 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, | |
4106 | 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, | |
4107 | 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, | |
4108 | 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, | |
4109 | 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, | |
4110 | 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, | |
4111 | 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, | |
4112 | 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, | |
4113 | 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, | |
4114 | 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, | |
4115 | 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, | |
4116 | 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, | |
4117 | 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, | |
4118 | 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, | |
4119 | 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, | |
4120 | 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, | |
4121 | 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, | |
4122 | 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, | |
4123 | 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, | |
4124 | 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, | |
4125 | 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, | |
4126 | 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, | |
4127 | 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, | |
4128 | 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, | |
4129 | 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, | |
4130 | 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, | |
4131 | 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, | |
4132 | 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, | |
4133 | 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, | |
4134 | 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, | |
4135 | 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, | |
4136 | 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, | |
4137 | 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, | |
4138 | 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, | |
4139 | 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, | |
4140 | 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, | |
4141 | 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, | |
4142 | 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, | |
4143 | 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, | |
4144 | 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, | |
4145 | 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, | |
4146 | 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, | |
4147 | 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, | |
4148 | 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, | |
4149 | 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, | |
4150 | 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, | |
4151 | 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, | |
4152 | 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, | |
4153 | 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, | |
4154 | 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, | |
4155 | 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, | |
4156 | 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, | |
4157 | 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, | |
4158 | 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, | |
4159 | 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, | |
4160 | 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, | |
4161 | 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, | |
4162 | 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, | |
4163 | 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, | |
4164 | 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, | |
4165 | 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, | |
4166 | 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, | |
4167 | 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, | |
4168 | 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, | |
4169 | 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, | |
4170 | 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, | |
4171 | 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, | |
4172 | 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, | |
4173 | 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, | |
4174 | 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, | |
4175 | 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, | |
4176 | 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, | |
4177 | 0xbf84fff8, 0xbf810000, | |
4178 | }; | |
4179 | ||
57cb635b JZ |
4180 | /* When below register arrays changed, please update gpr_reg_size, |
4181 | and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, | |
4182 | to cover all gfx9 ASICs */ | |
5326ad54 | 4183 | static const struct soc15_reg_entry vgpr_init_regs[] = { |
f83f5a1e JZ |
4184 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, |
4185 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, | |
4186 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, | |
5326ad54 | 4187 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, |
f83f5a1e | 4188 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, |
5326ad54 | 4189 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ |
107ab061 JZ |
4190 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, |
4191 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, | |
4192 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, | |
4193 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, | |
4194 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, | |
4195 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, | |
4196 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, | |
4197 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, | |
5326ad54 JZ |
4198 | }; |
4199 | ||
93cdb48e DL |
4200 | static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { |
4201 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, | |
4202 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, | |
4203 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, | |
4204 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, | |
10cda519 | 4205 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, |
93cdb48e DL |
4206 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ |
4207 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, | |
4208 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, | |
4209 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, | |
4210 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, | |
4211 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, | |
4212 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, | |
4213 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, | |
4214 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, | |
4215 | }; | |
4216 | ||
f83f5a1e | 4217 | static const struct soc15_reg_entry sgpr1_init_regs[] = { |
f83f5a1e JZ |
4218 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, |
4219 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, | |
4220 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, | |
4221 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, | |
4222 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ | |
4223 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, | |
107ab061 JZ |
4224 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, |
4225 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, | |
4226 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, | |
4227 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, | |
4228 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, | |
4229 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, | |
4230 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, | |
4231 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, | |
f83f5a1e JZ |
4232 | }; |
4233 | ||
4234 | static const struct soc15_reg_entry sgpr2_init_regs[] = { | |
f83f5a1e JZ |
4235 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, |
4236 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, | |
4237 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, | |
5326ad54 | 4238 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, |
f83f5a1e | 4239 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ |
5326ad54 | 4240 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, |
107ab061 JZ |
4241 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, |
4242 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, | |
4243 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, | |
4244 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, | |
4245 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, | |
4246 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, | |
4247 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, | |
4248 | { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, | |
5326ad54 JZ |
4249 | }; |
4250 | ||
504c5e72 | 4251 | static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { |
052af915 JZ |
4252 | { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, |
4253 | { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, | |
4254 | { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, | |
4255 | { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, | |
4256 | { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, | |
4257 | { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, | |
4258 | { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, | |
4259 | { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, | |
4260 | { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, | |
4261 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, | |
4262 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, | |
4263 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, | |
4264 | { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, | |
4265 | { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, | |
4266 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, | |
4267 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, | |
4268 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, | |
4269 | { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, | |
4270 | { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, | |
4271 | { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, | |
13ba0344 | 4272 | { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, |
052af915 JZ |
4273 | { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, |
4274 | { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, | |
4275 | { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, | |
4276 | { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, | |
4277 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, | |
4278 | { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, | |
4279 | { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, | |
4280 | { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, | |
4281 | { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, | |
4282 | { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, | |
4283 | { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, | |
4284 | { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, | |
5326ad54 JZ |
4285 | }; |
4286 | ||
df0a8064 JZ |
4287 | static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) |
4288 | { | |
4289 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; | |
eb03e795 | 4290 | int i, r; |
df0a8064 | 4291 | |
39857252 HZ |
4292 | /* only support when RAS is enabled */ |
4293 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) | |
4294 | return 0; | |
4295 | ||
eb03e795 | 4296 | r = amdgpu_ring_alloc(ring, 7); |
df0a8064 JZ |
4297 | if (r) { |
4298 | DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", | |
4299 | ring->name, r); | |
4300 | return r; | |
4301 | } | |
4302 | ||
eb03e795 JZ |
4303 | WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); |
4304 | WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); | |
df0a8064 JZ |
4305 | |
4306 | amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); | |
4307 | amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | | |
4308 | PACKET3_DMA_DATA_DST_SEL(1) | | |
4309 | PACKET3_DMA_DATA_SRC_SEL(2) | | |
4310 | PACKET3_DMA_DATA_ENGINE(0))); | |
4311 | amdgpu_ring_write(ring, 0); | |
4312 | amdgpu_ring_write(ring, 0); | |
4313 | amdgpu_ring_write(ring, 0); | |
4314 | amdgpu_ring_write(ring, 0); | |
4315 | amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | | |
4316 | adev->gds.gds_size); | |
4317 | ||
df0a8064 JZ |
4318 | amdgpu_ring_commit(ring); |
4319 | ||
eb03e795 JZ |
4320 | for (i = 0; i < adev->usec_timeout; i++) { |
4321 | if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) | |
4322 | break; | |
4323 | udelay(1); | |
4324 | } | |
4325 | ||
4326 | if (i >= adev->usec_timeout) | |
4327 | r = -ETIMEDOUT; | |
4328 | ||
4329 | WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); | |
df0a8064 | 4330 | |
eb03e795 JZ |
4331 | return r; |
4332 | } | |
df0a8064 | 4333 | |
5326ad54 JZ |
4334 | static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) |
4335 | { | |
4336 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; | |
4337 | struct amdgpu_ib ib; | |
4338 | struct dma_fence *f = NULL; | |
504c5e72 | 4339 | int r, i; |
5326ad54 JZ |
4340 | unsigned total_size, vgpr_offset, sgpr_offset; |
4341 | u64 gpu_addr; | |
4342 | ||
d8c61373 JZ |
4343 | int compute_dim_x = adev->gfx.config.max_shader_engines * |
4344 | adev->gfx.config.max_cu_per_sh * | |
4345 | adev->gfx.config.max_sh_per_se; | |
4346 | int sgpr_work_group_size = 5; | |
93cdb48e DL |
4347 | int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; |
4348 | int vgpr_init_shader_size; | |
4349 | const u32 *vgpr_init_shader_ptr; | |
4350 | const struct soc15_reg_entry *vgpr_init_regs_ptr; | |
d8c61373 | 4351 | |
5326ad54 JZ |
4352 | /* only support when RAS is enabled */ |
4353 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) | |
4354 | return 0; | |
4355 | ||
4356 | /* bail if the compute ring is not ready */ | |
4357 | if (!ring->sched.ready) | |
4358 | return 0; | |
4359 | ||
1d789535 | 4360 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { |
93cdb48e DL |
4361 | vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; |
4362 | vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); | |
4363 | vgpr_init_regs_ptr = vgpr_init_regs_arcturus; | |
4364 | } else { | |
4365 | vgpr_init_shader_ptr = vgpr_init_compute_shader; | |
4366 | vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); | |
4367 | vgpr_init_regs_ptr = vgpr_init_regs; | |
4368 | } | |
4369 | ||
5326ad54 | 4370 | total_size = |
d8c61373 | 4371 | (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ |
5326ad54 | 4372 | total_size += |
d8c61373 | 4373 | (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ |
f83f5a1e | 4374 | total_size += |
d8c61373 | 4375 | (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ |
5326ad54 JZ |
4376 | total_size = ALIGN(total_size, 256); |
4377 | vgpr_offset = total_size; | |
93cdb48e | 4378 | total_size += ALIGN(vgpr_init_shader_size, 256); |
5326ad54 JZ |
4379 | sgpr_offset = total_size; |
4380 | total_size += sizeof(sgpr_init_compute_shader); | |
4381 | ||
4382 | /* allocate an indirect buffer to put the commands in */ | |
4383 | memset(&ib, 0, sizeof(ib)); | |
c8e42d57 | 4384 | r = amdgpu_ib_get(adev, NULL, total_size, |
4385 | AMDGPU_IB_POOL_DIRECT, &ib); | |
5326ad54 JZ |
4386 | if (r) { |
4387 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); | |
4388 | return r; | |
4389 | } | |
4390 | ||
4391 | /* load the compute shaders */ | |
93cdb48e DL |
4392 | for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) |
4393 | ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; | |
5326ad54 JZ |
4394 | |
4395 | for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) | |
4396 | ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; | |
4397 | ||
4398 | /* init the ib length to 0 */ | |
4399 | ib.length_dw = 0; | |
4400 | ||
4401 | /* VGPR */ | |
4402 | /* write the register state for the compute dispatch */ | |
d8c61373 | 4403 | for (i = 0; i < gpr_reg_size; i++) { |
5326ad54 | 4404 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); |
93cdb48e | 4405 | ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) |
5326ad54 | 4406 | - PACKET3_SET_SH_REG_START; |
93cdb48e | 4407 | ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; |
5326ad54 JZ |
4408 | } |
4409 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ | |
4410 | gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; | |
4411 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); | |
4412 | ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) | |
4413 | - PACKET3_SET_SH_REG_START; | |
4414 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); | |
4415 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); | |
4416 | ||
4417 | /* write dispatch packet */ | |
4418 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); | |
93cdb48e | 4419 | ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ |
f83f5a1e JZ |
4420 | ib.ptr[ib.length_dw++] = 1; /* y */ |
4421 | ib.ptr[ib.length_dw++] = 1; /* z */ | |
4422 | ib.ptr[ib.length_dw++] = | |
4423 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); | |
4424 | ||
4425 | /* write CS partial flush packet */ | |
4426 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); | |
4427 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); | |
4428 | ||
4429 | /* SGPR1 */ | |
4430 | /* write the register state for the compute dispatch */ | |
d8c61373 | 4431 | for (i = 0; i < gpr_reg_size; i++) { |
f83f5a1e JZ |
4432 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); |
4433 | ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) | |
4434 | - PACKET3_SET_SH_REG_START; | |
4435 | ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; | |
4436 | } | |
4437 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ | |
4438 | gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; | |
4439 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); | |
4440 | ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) | |
4441 | - PACKET3_SET_SH_REG_START; | |
4442 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); | |
4443 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); | |
4444 | ||
4445 | /* write dispatch packet */ | |
4446 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); | |
d8c61373 | 4447 | ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ |
5326ad54 JZ |
4448 | ib.ptr[ib.length_dw++] = 1; /* y */ |
4449 | ib.ptr[ib.length_dw++] = 1; /* z */ | |
4450 | ib.ptr[ib.length_dw++] = | |
4451 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); | |
4452 | ||
4453 | /* write CS partial flush packet */ | |
4454 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); | |
4455 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); | |
4456 | ||
f83f5a1e | 4457 | /* SGPR2 */ |
5326ad54 | 4458 | /* write the register state for the compute dispatch */ |
d8c61373 | 4459 | for (i = 0; i < gpr_reg_size; i++) { |
5326ad54 | 4460 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); |
f83f5a1e | 4461 | ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) |
5326ad54 | 4462 | - PACKET3_SET_SH_REG_START; |
f83f5a1e | 4463 | ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; |
5326ad54 JZ |
4464 | } |
4465 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ | |
4466 | gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; | |
4467 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); | |
4468 | ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) | |
4469 | - PACKET3_SET_SH_REG_START; | |
4470 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); | |
4471 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); | |
4472 | ||
4473 | /* write dispatch packet */ | |
4474 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); | |
d8c61373 | 4475 | ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ |
5326ad54 JZ |
4476 | ib.ptr[ib.length_dw++] = 1; /* y */ |
4477 | ib.ptr[ib.length_dw++] = 1; /* z */ | |
4478 | ib.ptr[ib.length_dw++] = | |
4479 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); | |
4480 | ||
4481 | /* write CS partial flush packet */ | |
4482 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); | |
4483 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); | |
4484 | ||
4485 | /* shedule the ib on the ring */ | |
4486 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); | |
4487 | if (r) { | |
4488 | DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); | |
4489 | goto fail; | |
4490 | } | |
4491 | ||
4492 | /* wait for the GPU to finish processing the IB */ | |
4493 | r = dma_fence_wait(f, false); | |
4494 | if (r) { | |
4495 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); | |
4496 | goto fail; | |
4497 | } | |
4498 | ||
5326ad54 JZ |
4499 | fail: |
4500 | amdgpu_ib_free(adev, &ib, NULL); | |
4501 | dma_fence_put(f); | |
4502 | ||
4503 | return r; | |
4504 | } | |
4505 | ||
b1023571 KW |
4506 | static int gfx_v9_0_early_init(void *handle) |
4507 | { | |
4508 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
4509 | ||
33034c5c AD |
4510 | adev->gfx.funcs = &gfx_v9_0_gfx_funcs; |
4511 | ||
1d789535 AD |
4512 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || |
4513 | adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) | |
f5cdc2da LM |
4514 | adev->gfx.num_gfx_rings = 0; |
4515 | else | |
4516 | adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; | |
8078f1c6 | 4517 | adev->gfx.xcc_mask = 1; |
a3bab325 AD |
4518 | adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), |
4519 | AMDGPU_MAX_COMPUTE_RINGS); | |
f167ea6a | 4520 | gfx_v9_0_set_kiq_pm4_funcs(adev); |
b1023571 KW |
4521 | gfx_v9_0_set_ring_funcs(adev); |
4522 | gfx_v9_0_set_irq_funcs(adev); | |
4523 | gfx_v9_0_set_gds_init(adev); | |
4524 | gfx_v9_0_set_rlc_funcs(adev); | |
4525 | ||
63b5fa9d YW |
4526 | /* init rlcg reg access ctrl */ |
4527 | gfx_v9_0_init_rlcg_reg_access_ctrl(adev); | |
4528 | ||
1c21885e | 4529 | return gfx_v9_0_init_microcode(adev); |
b1023571 KW |
4530 | } |
4531 | ||
760a1d55 FX |
4532 | static int gfx_v9_0_ecc_late_init(void *handle) |
4533 | { | |
4534 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
760a1d55 FX |
4535 | int r; |
4536 | ||
278628fa GC |
4537 | /* |
4538 | * Temp workaround to fix the issue that CP firmware fails to | |
4539 | * update read pointer when CPDMA is writing clearing operation | |
4540 | * to GDS in suspend/resume sequence on several cards. So just | |
4541 | * limit this operation in cold boot sequence. | |
4542 | */ | |
063a1e83 HZ |
4543 | if ((!adev->in_suspend) && |
4544 | (adev->gds.gds_size)) { | |
ea6f0931 GC |
4545 | r = gfx_v9_0_do_edc_gds_workarounds(adev); |
4546 | if (r) | |
4547 | return r; | |
4548 | } | |
df0a8064 | 4549 | |
3058770a | 4550 | /* requires IBs so do in late init after IB pool is initialized */ |
1d789535 | 4551 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) |
6effe779 DL |
4552 | r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); |
4553 | else | |
4554 | r = gfx_v9_0_do_edc_gpr_workarounds(adev); | |
4555 | ||
3058770a JZ |
4556 | if (r) |
4557 | return r; | |
4558 | ||
8b0fb0e9 | 4559 | if (adev->gfx.ras && |
4560 | adev->gfx.ras->enable_watchdog_timer) | |
4561 | adev->gfx.ras->enable_watchdog_timer(adev); | |
761d86d3 | 4562 | |
760a1d55 | 4563 | return 0; |
760a1d55 FX |
4564 | } |
4565 | ||
b1023571 KW |
4566 | static int gfx_v9_0_late_init(void *handle) |
4567 | { | |
4568 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
4569 | int r; | |
4570 | ||
4571 | r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); | |
4572 | if (r) | |
4573 | return r; | |
4574 | ||
4575 | r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); | |
4576 | if (r) | |
4577 | return r; | |
4578 | ||
760a1d55 FX |
4579 | r = gfx_v9_0_ecc_late_init(handle); |
4580 | if (r) | |
4581 | return r; | |
4582 | ||
4504f143 JK |
4583 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) |
4584 | gfx_v9_4_2_debug_trap_config_init(adev, | |
4585 | adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); | |
4586 | else | |
4587 | gfx_v9_0_debug_trap_config_init(adev, | |
4588 | adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); | |
4589 | ||
b1023571 KW |
4590 | return 0; |
4591 | } | |
4592 | ||
106c7d61 | 4593 | static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) |
b1023571 | 4594 | { |
106c7d61 | 4595 | uint32_t rlc_setting; |
b1023571 KW |
4596 | |
4597 | /* if RLC is not enabled, do nothing */ | |
5e78835a | 4598 | rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); |
b1023571 | 4599 | if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) |
106c7d61 | 4600 | return false; |
b1023571 | 4601 | |
106c7d61 | 4602 | return true; |
b1023571 KW |
4603 | } |
4604 | ||
86b20703 | 4605 | static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) |
b1023571 | 4606 | { |
106c7d61 LG |
4607 | uint32_t data; |
4608 | unsigned i; | |
b1023571 | 4609 | |
106c7d61 LG |
4610 | data = RLC_SAFE_MODE__CMD_MASK; |
4611 | data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); | |
4612 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); | |
b1023571 | 4613 | |
106c7d61 LG |
4614 | /* wait for RLC_SAFE_MODE */ |
4615 | for (i = 0; i < adev->usec_timeout; i++) { | |
4616 | if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) | |
4617 | break; | |
4618 | udelay(1); | |
b1023571 KW |
4619 | } |
4620 | } | |
4621 | ||
86b20703 | 4622 | static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) |
106c7d61 LG |
4623 | { |
4624 | uint32_t data; | |
4625 | ||
4626 | data = RLC_SAFE_MODE__CMD_MASK; | |
4627 | WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); | |
4628 | } | |
4629 | ||
197f95c8 HZ |
4630 | static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, |
4631 | bool enable) | |
4632 | { | |
86b20703 | 4633 | amdgpu_gfx_rlc_enter_safe_mode(adev, 0); |
197f95c8 HZ |
4634 | |
4635 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { | |
4636 | gfx_v9_0_enable_gfx_cg_power_gating(adev, true); | |
4637 | if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) | |
4638 | gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); | |
4639 | } else { | |
4640 | gfx_v9_0_enable_gfx_cg_power_gating(adev, false); | |
c8486eef PL |
4641 | if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) |
4642 | gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); | |
197f95c8 HZ |
4643 | } |
4644 | ||
86b20703 | 4645 | amdgpu_gfx_rlc_exit_safe_mode(adev, 0); |
197f95c8 HZ |
4646 | } |
4647 | ||
18924c71 HZ |
4648 | static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, |
4649 | bool enable) | |
4650 | { | |
4651 | /* TODO: double check if we need to perform under safe mode */ | |
4652 | /* gfx_v9_0_enter_rlc_safe_mode(adev); */ | |
4653 | ||
4654 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) | |
4655 | gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); | |
4656 | else | |
4657 | gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); | |
4658 | ||
4659 | if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) | |
4660 | gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); | |
4661 | else | |
4662 | gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); | |
4663 | ||
4664 | /* gfx_v9_0_exit_rlc_safe_mode(adev); */ | |
4665 | } | |
4666 | ||
b1023571 KW |
4667 | static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
4668 | bool enable) | |
4669 | { | |
4670 | uint32_t data, def; | |
4671 | ||
86b20703 | 4672 | amdgpu_gfx_rlc_enter_safe_mode(adev, 0); |
a7a0d543 | 4673 | |
b1023571 KW |
4674 | /* It is disabled by HW by default */ |
4675 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { | |
4676 | /* 1 - RLC_CGTT_MGCG_OVERRIDE */ | |
5e78835a | 4677 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
c3693768 | 4678 | |
1d789535 | 4679 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) |
c3693768 EQ |
4680 | data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; |
4681 | ||
4682 | data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | | |
b1023571 KW |
4683 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | |
4684 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); | |
4685 | ||
4686 | /* only for Vega10 & Raven1 */ | |
4687 | data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; | |
4688 | ||
4689 | if (def != data) | |
5e78835a | 4690 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
b1023571 KW |
4691 | |
4692 | /* MGLS is a global flag to control all MGLS in GFX */ | |
4693 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { | |
4694 | /* 2 - RLC memory Light sleep */ | |
4695 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { | |
5e78835a | 4696 | def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); |
b1023571 KW |
4697 | data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; |
4698 | if (def != data) | |
5e78835a | 4699 | WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); |
b1023571 KW |
4700 | } |
4701 | /* 3 - CP memory Light sleep */ | |
4702 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { | |
5e78835a | 4703 | def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); |
b1023571 KW |
4704 | data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; |
4705 | if (def != data) | |
5e78835a | 4706 | WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); |
b1023571 KW |
4707 | } |
4708 | } | |
4709 | } else { | |
4710 | /* 1 - MGCG_OVERRIDE */ | |
5e78835a | 4711 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
c3693768 | 4712 | |
1d789535 | 4713 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) |
c3693768 EQ |
4714 | data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; |
4715 | ||
4716 | data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | | |
b1023571 KW |
4717 | RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | |
4718 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | | |
4719 | RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); | |
c3693768 | 4720 | |
b1023571 | 4721 | if (def != data) |
5e78835a | 4722 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
b1023571 KW |
4723 | |
4724 | /* 2 - disable MGLS in RLC */ | |
5e78835a | 4725 | data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); |
b1023571 KW |
4726 | if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { |
4727 | data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; | |
5e78835a | 4728 | WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); |
b1023571 KW |
4729 | } |
4730 | ||
4731 | /* 3 - disable MGLS in CP */ | |
5e78835a | 4732 | data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); |
b1023571 KW |
4733 | if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { |
4734 | data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; | |
5e78835a | 4735 | WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); |
b1023571 KW |
4736 | } |
4737 | } | |
a7a0d543 | 4738 | |
86b20703 | 4739 | amdgpu_gfx_rlc_exit_safe_mode(adev, 0); |
b1023571 KW |
4740 | } |
4741 | ||
4742 | static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, | |
4743 | bool enable) | |
4744 | { | |
4745 | uint32_t data, def; | |
4746 | ||
48a6379a | 4747 | if (!adev->gfx.num_gfx_rings) |
f60481a9 LM |
4748 | return; |
4749 | ||
86b20703 | 4750 | amdgpu_gfx_rlc_enter_safe_mode(adev, 0); |
b1023571 KW |
4751 | |
4752 | /* Enable 3D CGCG/CGLS */ | |
8ef4f94a | 4753 | if (enable) { |
b1023571 | 4754 | /* write cmd to clear cgcg/cgls ov */ |
5e78835a | 4755 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
b1023571 KW |
4756 | /* unset CGCG override */ |
4757 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; | |
4758 | /* update CGCG and CGLS override bits */ | |
4759 | if (def != data) | |
5e78835a | 4760 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
a5aedc2d EQ |
4761 | |
4762 | /* enable 3Dcgcg FSM(0x0000363f) */ | |
5e78835a | 4763 | def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); |
a5aedc2d | 4764 | |
8ef4f94a C |
4765 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) |
4766 | data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | | |
4767 | RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; | |
4768 | else | |
4769 | data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; | |
4770 | ||
b1023571 KW |
4771 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) |
4772 | data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | | |
4773 | RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; | |
4774 | if (def != data) | |
5e78835a | 4775 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); |
b1023571 KW |
4776 | |
4777 | /* set IDLE_POLL_COUNT(0x00900100) */ | |
5e78835a | 4778 | def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); |
b1023571 KW |
4779 | data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | |
4780 | (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); | |
4781 | if (def != data) | |
5e78835a | 4782 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); |
b1023571 KW |
4783 | } else { |
4784 | /* Disable CGCG/CGLS */ | |
5e78835a | 4785 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); |
b1023571 KW |
4786 | /* disable cgcg, cgls should be disabled */ |
4787 | data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | | |
4788 | RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); | |
4789 | /* disable cgcg and cgls in FSM */ | |
4790 | if (def != data) | |
5e78835a | 4791 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); |
b1023571 KW |
4792 | } |
4793 | ||
86b20703 | 4794 | amdgpu_gfx_rlc_exit_safe_mode(adev, 0); |
b1023571 KW |
4795 | } |
4796 | ||
4797 | static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, | |
4798 | bool enable) | |
4799 | { | |
4800 | uint32_t def, data; | |
4801 | ||
86b20703 | 4802 | amdgpu_gfx_rlc_enter_safe_mode(adev, 0); |
b1023571 KW |
4803 | |
4804 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { | |
5e78835a | 4805 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); |
b1023571 KW |
4806 | /* unset CGCG override */ |
4807 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; | |
4808 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) | |
4809 | data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; | |
4810 | else | |
4811 | data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; | |
4812 | /* update CGCG and CGLS override bits */ | |
4813 | if (def != data) | |
5e78835a | 4814 | WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); |
b1023571 | 4815 | |
a5aedc2d | 4816 | /* enable cgcg FSM(0x0000363F) */ |
5e78835a | 4817 | def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); |
a5aedc2d | 4818 | |
1d789535 | 4819 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) |
15e2f43a LM |
4820 | data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | |
4821 | RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; | |
4822 | else | |
4823 | data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | | |
4824 | RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; | |
b1023571 KW |
4825 | if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) |
4826 | data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | | |
4827 | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; | |
4828 | if (def != data) | |
5e78835a | 4829 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); |
b1023571 KW |
4830 | |
4831 | /* set IDLE_POLL_COUNT(0x00900100) */ | |
5e78835a | 4832 | def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); |
b1023571 KW |
4833 | data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | |
4834 | (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); | |
4835 | if (def != data) | |
5e78835a | 4836 | WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); |
b1023571 | 4837 | } else { |
5e78835a | 4838 | def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); |
b1023571 KW |
4839 | /* reset CGCG/CGLS bits */ |
4840 | data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); | |
4841 | /* disable cgcg and cgls in FSM */ | |
4842 | if (def != data) | |
5e78835a | 4843 | WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); |
b1023571 KW |
4844 | } |
4845 | ||
86b20703 | 4846 | amdgpu_gfx_rlc_exit_safe_mode(adev, 0); |
b1023571 KW |
4847 | } |
4848 | ||
4849 | static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, | |
4850 | bool enable) | |
4851 | { | |
4852 | if (enable) { | |
4853 | /* CGCG/CGLS should be enabled after MGCG/MGLS | |
4854 | * === MGCG + MGLS === | |
4855 | */ | |
4856 | gfx_v9_0_update_medium_grain_clock_gating(adev, enable); | |
4857 | /* === CGCG /CGLS for GFX 3D Only === */ | |
4858 | gfx_v9_0_update_3d_clock_gating(adev, enable); | |
4859 | /* === CGCG + CGLS === */ | |
4860 | gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); | |
4861 | } else { | |
4862 | /* CGCG/CGLS should be disabled before MGCG/MGLS | |
4863 | * === CGCG + CGLS === | |
4864 | */ | |
4865 | gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); | |
4866 | /* === CGCG /CGLS for GFX 3D Only === */ | |
4867 | gfx_v9_0_update_3d_clock_gating(adev, enable); | |
4868 | /* === MGCG + MGLS === */ | |
4869 | gfx_v9_0_update_medium_grain_clock_gating(adev, enable); | |
4870 | } | |
4871 | return 0; | |
4872 | } | |
4873 | ||
08b6e172 AD |
4874 | static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, |
4875 | unsigned int vmid) | |
460c484f | 4876 | { |
e09d40bd | 4877 | u32 reg, data; |
460c484f | 4878 | |
e09d40bd CK |
4879 | reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); |
4880 | if (amdgpu_sriov_is_pp_one_vf(adev)) | |
4881 | data = RREG32_NO_KIQ(reg); | |
4882 | else | |
d764fb2a | 4883 | data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); |
460c484f JH |
4884 | |
4885 | data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; | |
4886 | data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; | |
4887 | ||
e09d40bd CK |
4888 | if (amdgpu_sriov_is_pp_one_vf(adev)) |
4889 | WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); | |
4890 | else | |
4891 | WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); | |
08b6e172 AD |
4892 | } |
4893 | ||
4894 | static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) | |
4895 | { | |
4896 | amdgpu_gfx_off_ctrl(adev, false); | |
4897 | ||
4898 | gfx_v9_0_update_spm_vmid_internal(adev, vmid); | |
e6ef9b39 EQ |
4899 | |
4900 | amdgpu_gfx_off_ctrl(adev, true); | |
460c484f JH |
4901 | } |
4902 | ||
2e0cc4d4 ML |
4903 | static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, |
4904 | uint32_t offset, | |
4905 | struct soc15_reg_rlcg *entries, int arr_size) | |
4906 | { | |
4907 | int i; | |
4908 | uint32_t reg; | |
4909 | ||
4910 | if (!entries) | |
4911 | return false; | |
4912 | ||
4913 | for (i = 0; i < arr_size; i++) { | |
4914 | const struct soc15_reg_rlcg *entry; | |
4915 | ||
4916 | entry = &entries[i]; | |
4917 | reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; | |
4918 | if (offset == reg) | |
4919 | return true; | |
4920 | } | |
4921 | ||
4922 | return false; | |
4923 | } | |
4924 | ||
4925 | static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) | |
4926 | { | |
4927 | return gfx_v9_0_check_rlcg_range(adev, offset, | |
4928 | (void *)rlcg_access_gc_9_0, | |
4929 | ARRAY_SIZE(rlcg_access_gc_9_0)); | |
4930 | } | |
4931 | ||
b1023571 | 4932 | static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { |
106c7d61 LG |
4933 | .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, |
4934 | .set_safe_mode = gfx_v9_0_set_safe_mode, | |
4935 | .unset_safe_mode = gfx_v9_0_unset_safe_mode, | |
fdb81fd7 | 4936 | .init = gfx_v9_0_rlc_init, |
106c7d61 LG |
4937 | .get_csb_size = gfx_v9_0_get_csb_size, |
4938 | .get_csb_buffer = gfx_v9_0_get_csb_buffer, | |
4939 | .get_cp_table_num = gfx_v9_0_cp_jump_table_num, | |
fdb81fd7 LG |
4940 | .resume = gfx_v9_0_rlc_resume, |
4941 | .stop = gfx_v9_0_rlc_stop, | |
4942 | .reset = gfx_v9_0_rlc_reset, | |
460c484f | 4943 | .start = gfx_v9_0_rlc_start, |
2e0cc4d4 | 4944 | .update_spm_vmid = gfx_v9_0_update_spm_vmid, |
2e0cc4d4 | 4945 | .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, |
b1023571 KW |
4946 | }; |
4947 | ||
4948 | static int gfx_v9_0_set_powergating_state(void *handle, | |
4949 | enum amd_powergating_state state) | |
4950 | { | |
5897c99e | 4951 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a9d4fe2f | 4952 | bool enable = (state == AMD_PG_STATE_GATE); |
5897c99e | 4953 | |
1d789535 | 4954 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
4955 | case IP_VERSION(9, 2, 2): |
4956 | case IP_VERSION(9, 1, 0): | |
4957 | case IP_VERSION(9, 3, 0): | |
47891bf1 | 4958 | if (!enable) |
05df1f01 | 4959 | amdgpu_gfx_off_ctrl(adev, false); |
47891bf1 | 4960 | |
5897c99e HZ |
4961 | if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { |
4962 | gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); | |
4963 | gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); | |
4964 | } else { | |
4965 | gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); | |
4966 | gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); | |
4967 | } | |
4968 | ||
4969 | if (adev->pg_flags & AMD_PG_SUPPORT_CP) | |
4970 | gfx_v9_0_enable_cp_power_gating(adev, true); | |
4971 | else | |
4972 | gfx_v9_0_enable_cp_power_gating(adev, false); | |
197f95c8 HZ |
4973 | |
4974 | /* update gfx cgpg state */ | |
4975 | gfx_v9_0_update_gfx_cg_power_gating(adev, enable); | |
18924c71 HZ |
4976 | |
4977 | /* update mgcg state */ | |
4978 | gfx_v9_0_update_gfx_mg_power_gating(adev, enable); | |
9134c6d7 | 4979 | |
05df1f01 RZ |
4980 | if (enable) |
4981 | amdgpu_gfx_off_ctrl(adev, true); | |
991a6b32 | 4982 | break; |
9d0cb2c3 | 4983 | case IP_VERSION(9, 2, 1): |
47891bf1 | 4984 | amdgpu_gfx_off_ctrl(adev, enable); |
5897c99e HZ |
4985 | break; |
4986 | default: | |
4987 | break; | |
4988 | } | |
4989 | ||
b1023571 KW |
4990 | return 0; |
4991 | } | |
4992 | ||
4993 | static int gfx_v9_0_set_clockgating_state(void *handle, | |
4994 | enum amd_clockgating_state state) | |
4995 | { | |
4996 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
4997 | ||
fb82afab XY |
4998 | if (amdgpu_sriov_vf(adev)) |
4999 | return 0; | |
5000 | ||
1d789535 | 5001 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
5002 | case IP_VERSION(9, 0, 1): |
5003 | case IP_VERSION(9, 2, 1): | |
5004 | case IP_VERSION(9, 4, 0): | |
5005 | case IP_VERSION(9, 2, 2): | |
5006 | case IP_VERSION(9, 1, 0): | |
5007 | case IP_VERSION(9, 4, 1): | |
5008 | case IP_VERSION(9, 3, 0): | |
5009 | case IP_VERSION(9, 4, 2): | |
b1023571 | 5010 | gfx_v9_0_update_gfx_clock_gating(adev, |
a9d4fe2f | 5011 | state == AMD_CG_STATE_GATE); |
b1023571 KW |
5012 | break; |
5013 | default: | |
5014 | break; | |
5015 | } | |
5016 | return 0; | |
5017 | } | |
5018 | ||
25faeddc | 5019 | static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) |
12ad27fa HR |
5020 | { |
5021 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
5022 | int data; | |
5023 | ||
5024 | if (amdgpu_sriov_vf(adev)) | |
5025 | *flags = 0; | |
5026 | ||
5027 | /* AMD_CG_SUPPORT_GFX_MGCG */ | |
e3cd0360 | 5028 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); |
12ad27fa HR |
5029 | if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) |
5030 | *flags |= AMD_CG_SUPPORT_GFX_MGCG; | |
5031 | ||
5032 | /* AMD_CG_SUPPORT_GFX_CGCG */ | |
e3cd0360 | 5033 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); |
12ad27fa HR |
5034 | if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) |
5035 | *flags |= AMD_CG_SUPPORT_GFX_CGCG; | |
5036 | ||
5037 | /* AMD_CG_SUPPORT_GFX_CGLS */ | |
5038 | if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) | |
5039 | *flags |= AMD_CG_SUPPORT_GFX_CGLS; | |
5040 | ||
5041 | /* AMD_CG_SUPPORT_GFX_RLC_LS */ | |
e3cd0360 | 5042 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); |
12ad27fa HR |
5043 | if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) |
5044 | *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; | |
5045 | ||
5046 | /* AMD_CG_SUPPORT_GFX_CP_LS */ | |
e3cd0360 | 5047 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); |
12ad27fa HR |
5048 | if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) |
5049 | *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; | |
5050 | ||
1d789535 | 5051 | if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) { |
2065aa54 | 5052 | /* AMD_CG_SUPPORT_GFX_3D_CGCG */ |
e3cd0360 | 5053 | data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); |
2065aa54 LM |
5054 | if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) |
5055 | *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; | |
5056 | ||
5057 | /* AMD_CG_SUPPORT_GFX_3D_CGLS */ | |
5058 | if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) | |
5059 | *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; | |
5060 | } | |
12ad27fa HR |
5061 | } |
5062 | ||
b1023571 KW |
5063 | static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) |
5064 | { | |
3748424b | 5065 | return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ |
b1023571 KW |
5066 | } |
5067 | ||
5068 | static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) | |
5069 | { | |
5070 | struct amdgpu_device *adev = ring->adev; | |
5071 | u64 wptr; | |
5072 | ||
5073 | /* XXX check if swapping is necessary on BE */ | |
5074 | if (ring->use_doorbell) { | |
3748424b | 5075 | wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); |
b1023571 | 5076 | } else { |
5e78835a TSD |
5077 | wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); |
5078 | wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; | |
b1023571 KW |
5079 | } |
5080 | ||
5081 | return wptr; | |
5082 | } | |
5083 | ||
5084 | static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) | |
5085 | { | |
5086 | struct amdgpu_device *adev = ring->adev; | |
5087 | ||
5088 | if (ring->use_doorbell) { | |
5089 | /* XXX check if swapping is necessary on BE */ | |
3748424b | 5090 | atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); |
b1023571 KW |
5091 | WDOORBELL64(ring->doorbell_index, ring->wptr); |
5092 | } else { | |
5e78835a TSD |
5093 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); |
5094 | WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); | |
b1023571 KW |
5095 | } |
5096 | } | |
5097 | ||
5098 | static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) | |
5099 | { | |
946a4d5b | 5100 | struct amdgpu_device *adev = ring->adev; |
b1023571 | 5101 | u32 ref_and_mask, reg_mem_engine; |
bebc0762 | 5102 | const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; |
b1023571 KW |
5103 | |
5104 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { | |
5105 | switch (ring->me) { | |
5106 | case 1: | |
5107 | ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; | |
5108 | break; | |
5109 | case 2: | |
5110 | ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; | |
5111 | break; | |
5112 | default: | |
5113 | return; | |
5114 | } | |
5115 | reg_mem_engine = 0; | |
5116 | } else { | |
5117 | ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; | |
5118 | reg_mem_engine = 1; /* pfp */ | |
5119 | } | |
5120 | ||
5121 | gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, | |
bebc0762 HZ |
5122 | adev->nbio.funcs->get_hdp_flush_req_offset(adev), |
5123 | adev->nbio.funcs->get_hdp_flush_done_offset(adev), | |
b1023571 KW |
5124 | ref_and_mask, ref_and_mask, 0x20); |
5125 | } | |
5126 | ||
b1023571 | 5127 | static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, |
34955e03 RZ |
5128 | struct amdgpu_job *job, |
5129 | struct amdgpu_ib *ib, | |
c4c905ec | 5130 | uint32_t flags) |
b1023571 | 5131 | { |
34955e03 | 5132 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); |
eaa05d52 | 5133 | u32 header, control = 0; |
b1023571 | 5134 | |
eaa05d52 ML |
5135 | if (ib->flags & AMDGPU_IB_FLAG_CE) |
5136 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); | |
5137 | else | |
5138 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | |
b1023571 | 5139 | |
c4f46f22 | 5140 | control |= ib->length_dw | (vmid << 24); |
b1023571 | 5141 | |
be254550 | 5142 | if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) { |
eaa05d52 | 5143 | control |= INDIRECT_BUFFER_PRE_ENB(1); |
9ccd52eb | 5144 | |
be254550 JZ |
5145 | if (flags & AMDGPU_IB_PREEMPTED) |
5146 | control |= INDIRECT_BUFFER_PRE_RESUME(1); | |
5147 | ||
752c683d | 5148 | if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) |
be254550 JZ |
5149 | gfx_v9_0_ring_emit_de_meta(ring, |
5150 | (!amdgpu_sriov_vf(ring->adev) && | |
5151 | flags & AMDGPU_IB_PREEMPTED) ? | |
cfdce594 JZ |
5152 | true : false, |
5153 | job->gds_size > 0 && job->gds_base != 0); | |
635e7132 ML |
5154 | } |
5155 | ||
eaa05d52 | 5156 | amdgpu_ring_write(ring, header); |
72408a41 | 5157 | BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ |
eaa05d52 | 5158 | amdgpu_ring_write(ring, |
b1023571 | 5159 | #ifdef __BIG_ENDIAN |
eaa05d52 | 5160 | (2 << 0) | |
b1023571 | 5161 | #endif |
eaa05d52 ML |
5162 | lower_32_bits(ib->gpu_addr)); |
5163 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
ea791e70 | 5164 | amdgpu_ring_ib_on_emit_cntl(ring); |
eaa05d52 | 5165 | amdgpu_ring_write(ring, control); |
b1023571 KW |
5166 | } |
5167 | ||
ea791e70 JZ |
5168 | static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring, |
5169 | unsigned offset) | |
5170 | { | |
5171 | u32 control = ring->ring[offset]; | |
5172 | ||
5173 | control |= INDIRECT_BUFFER_PRE_RESUME(1); | |
5174 | ring->ring[offset] = control; | |
5175 | } | |
5176 | ||
5177 | static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring, | |
5178 | unsigned offset) | |
5179 | { | |
5180 | struct amdgpu_device *adev = ring->adev; | |
5181 | void *ce_payload_cpu_addr; | |
5182 | uint64_t payload_offset, payload_size; | |
5183 | ||
5184 | payload_size = sizeof(struct v9_ce_ib_state); | |
5185 | ||
5186 | if (ring->is_mes_queue) { | |
5187 | payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data, | |
5188 | gfx[0].gfx_meta_data) + | |
5189 | offsetof(struct v9_gfx_meta_data, ce_payload); | |
5190 | ce_payload_cpu_addr = | |
5191 | amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset); | |
5192 | } else { | |
5193 | payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload); | |
5194 | ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset; | |
5195 | } | |
5196 | ||
5197 | if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { | |
5198 | memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size); | |
5199 | } else { | |
5200 | memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, | |
5201 | (ring->buf_mask + 1 - offset) << 2); | |
5202 | payload_size -= (ring->buf_mask + 1 - offset) << 2; | |
5203 | memcpy((void *)&ring->ring[0], | |
5204 | ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), | |
5205 | payload_size); | |
5206 | } | |
5207 | } | |
5208 | ||
5209 | static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring, | |
5210 | unsigned offset) | |
5211 | { | |
5212 | struct amdgpu_device *adev = ring->adev; | |
5213 | void *de_payload_cpu_addr; | |
5214 | uint64_t payload_offset, payload_size; | |
5215 | ||
5216 | payload_size = sizeof(struct v9_de_ib_state); | |
5217 | ||
5218 | if (ring->is_mes_queue) { | |
5219 | payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data, | |
5220 | gfx[0].gfx_meta_data) + | |
5221 | offsetof(struct v9_gfx_meta_data, de_payload); | |
5222 | de_payload_cpu_addr = | |
5223 | amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset); | |
5224 | } else { | |
5225 | payload_offset = offsetof(struct v9_gfx_meta_data, de_payload); | |
5226 | de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset; | |
5227 | } | |
5228 | ||
8cbbd115 JZ |
5229 | ((struct v9_de_ib_state *)de_payload_cpu_addr)->ib_completion_status = |
5230 | IB_COMPLETION_STATUS_PREEMPTED; | |
5231 | ||
ea791e70 JZ |
5232 | if (offset + (payload_size >> 2) <= ring->buf_mask + 1) { |
5233 | memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size); | |
5234 | } else { | |
5235 | memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, | |
5236 | (ring->buf_mask + 1 - offset) << 2); | |
5237 | payload_size -= (ring->buf_mask + 1 - offset) << 2; | |
5238 | memcpy((void *)&ring->ring[0], | |
5239 | de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2), | |
5240 | payload_size); | |
5241 | } | |
5242 | } | |
5243 | ||
b1023571 | 5244 | static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, |
34955e03 RZ |
5245 | struct amdgpu_job *job, |
5246 | struct amdgpu_ib *ib, | |
c4c905ec | 5247 | uint32_t flags) |
b1023571 | 5248 | { |
34955e03 RZ |
5249 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); |
5250 | u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); | |
b1023571 | 5251 | |
41cca166 MO |
5252 | /* Currently, there is a high possibility to get wave ID mismatch |
5253 | * between ME and GDS, leading to a hw deadlock, because ME generates | |
5254 | * different wave IDs than the GDS expects. This situation happens | |
5255 | * randomly when at least 5 compute pipes use GDS ordered append. | |
5256 | * The wave IDs generated by ME are also wrong after suspend/resume. | |
5257 | * Those are probably bugs somewhere else in the kernel driver. | |
5258 | * | |
5259 | * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and | |
5260 | * GDS to 0 for this ring (me/pipe). | |
5261 | */ | |
5262 | if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { | |
5263 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
5264 | amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); | |
5265 | amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); | |
5266 | } | |
5267 | ||
34955e03 | 5268 | amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
b1023571 | 5269 | BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ |
34955e03 | 5270 | amdgpu_ring_write(ring, |
b1023571 | 5271 | #ifdef __BIG_ENDIAN |
34955e03 | 5272 | (2 << 0) | |
b1023571 | 5273 | #endif |
34955e03 RZ |
5274 | lower_32_bits(ib->gpu_addr)); |
5275 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
5276 | amdgpu_ring_write(ring, control); | |
b1023571 KW |
5277 | } |
5278 | ||
5279 | static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, | |
5280 | u64 seq, unsigned flags) | |
5281 | { | |
5282 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; | |
5283 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; | |
d240cd9e | 5284 | bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; |
be254550 JZ |
5285 | bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; |
5286 | uint32_t dw2 = 0; | |
b1023571 KW |
5287 | |
5288 | /* RELEASE_MEM - flush caches, send int */ | |
5289 | amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); | |
be254550 JZ |
5290 | |
5291 | if (writeback) { | |
5292 | dw2 = EOP_TC_NC_ACTION_EN; | |
5293 | } else { | |
5294 | dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | | |
5295 | EOP_TC_MD_ACTION_EN; | |
5296 | } | |
5297 | dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | | |
5298 | EVENT_INDEX(5); | |
5299 | if (exec) | |
5300 | dw2 |= EOP_EXEC; | |
5301 | ||
5302 | amdgpu_ring_write(ring, dw2); | |
b1023571 KW |
5303 | amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); |
5304 | ||
5305 | /* | |
5306 | * the address should be Qword aligned if 64bit write, Dword | |
5307 | * aligned if only send 32bit data low (discard data high) | |
5308 | */ | |
5309 | if (write64bit) | |
5310 | BUG_ON(addr & 0x7); | |
5311 | else | |
5312 | BUG_ON(addr & 0x3); | |
5313 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
5314 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
5315 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
5316 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
5317 | amdgpu_ring_write(ring, 0); | |
5318 | } | |
5319 | ||
5320 | static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) | |
5321 | { | |
5322 | int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); | |
5323 | uint32_t seq = ring->fence_drv.sync_seq; | |
5324 | uint64_t addr = ring->fence_drv.gpu_addr; | |
5325 | ||
5326 | gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, | |
5327 | lower_32_bits(addr), upper_32_bits(addr), | |
5328 | seq, 0xffffffff, 4); | |
5329 | } | |
5330 | ||
5331 | static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
c633c00b | 5332 | unsigned vmid, uint64_t pd_addr) |
b1023571 | 5333 | { |
c633c00b | 5334 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
b1023571 | 5335 | |
b1023571 | 5336 | /* compute doesn't have PFP */ |
9096d6e5 | 5337 | if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { |
b1023571 KW |
5338 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
5339 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | |
5340 | amdgpu_ring_write(ring, 0x0); | |
b1023571 KW |
5341 | } |
5342 | } | |
5343 | ||
5344 | static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) | |
5345 | { | |
3748424b | 5346 | return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ |
b1023571 KW |
5347 | } |
5348 | ||
5349 | static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) | |
5350 | { | |
5351 | u64 wptr; | |
5352 | ||
5353 | /* XXX check if swapping is necessary on BE */ | |
5354 | if (ring->use_doorbell) | |
3748424b | 5355 | wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); |
b1023571 KW |
5356 | else |
5357 | BUG(); | |
5358 | return wptr; | |
5359 | } | |
5360 | ||
5361 | static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) | |
5362 | { | |
5363 | struct amdgpu_device *adev = ring->adev; | |
5364 | ||
5365 | /* XXX check if swapping is necessary on BE */ | |
5366 | if (ring->use_doorbell) { | |
3748424b | 5367 | atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); |
b1023571 KW |
5368 | WDOORBELL64(ring->doorbell_index, ring->wptr); |
5369 | } else{ | |
5370 | BUG(); /* only DOORBELL method supported on gfx9 now */ | |
5371 | } | |
5372 | } | |
5373 | ||
aa6faa44 XY |
5374 | static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, |
5375 | u64 seq, unsigned int flags) | |
5376 | { | |
cd29253f SL |
5377 | struct amdgpu_device *adev = ring->adev; |
5378 | ||
aa6faa44 XY |
5379 | /* we only allocate 32bit for each seq wb address */ |
5380 | BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); | |
5381 | ||
5382 | /* write fence seq to the "addr" */ | |
5383 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
5384 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
5385 | WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); | |
5386 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
5387 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
5388 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
5389 | ||
5390 | if (flags & AMDGPU_FENCE_FLAG_INT) { | |
5391 | /* set register to trigger INT */ | |
5392 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); | |
5393 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | | |
5394 | WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); | |
5395 | amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); | |
5396 | amdgpu_ring_write(ring, 0); | |
5397 | amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ | |
5398 | } | |
5399 | } | |
5400 | ||
b1023571 KW |
5401 | static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) |
5402 | { | |
5403 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); | |
5404 | amdgpu_ring_write(ring, 0); | |
5405 | } | |
5406 | ||
be254550 | 5407 | static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) |
cca02cd3 | 5408 | { |
be254550 | 5409 | struct amdgpu_device *adev = ring->adev; |
d81a2209 | 5410 | struct v9_ce_ib_state ce_payload = {0}; |
be254550 JZ |
5411 | uint64_t offset, ce_payload_gpu_addr; |
5412 | void *ce_payload_cpu_addr; | |
cca02cd3 XY |
5413 | int cnt; |
5414 | ||
5415 | cnt = (sizeof(ce_payload) >> 2) + 4 - 2; | |
be254550 JZ |
5416 | |
5417 | if (ring->is_mes_queue) { | |
5418 | offset = offsetof(struct amdgpu_mes_ctx_meta_data, | |
5419 | gfx[0].gfx_meta_data) + | |
5420 | offsetof(struct v9_gfx_meta_data, ce_payload); | |
5421 | ce_payload_gpu_addr = | |
5422 | amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); | |
5423 | ce_payload_cpu_addr = | |
5424 | amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); | |
5425 | } else { | |
5426 | offset = offsetof(struct v9_gfx_meta_data, ce_payload); | |
5427 | ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; | |
5428 | ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; | |
5429 | } | |
cca02cd3 XY |
5430 | |
5431 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); | |
5432 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | | |
5433 | WRITE_DATA_DST_SEL(8) | | |
5434 | WR_CONFIRM) | | |
5435 | WRITE_DATA_CACHE_POLICY(0)); | |
be254550 JZ |
5436 | amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); |
5437 | amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); | |
5438 | ||
ea791e70 JZ |
5439 | amdgpu_ring_ib_on_emit_ce(ring); |
5440 | ||
be254550 JZ |
5441 | if (resume) |
5442 | amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, | |
5443 | sizeof(ce_payload) >> 2); | |
5444 | else | |
5445 | amdgpu_ring_write_multiple(ring, (void *)&ce_payload, | |
5446 | sizeof(ce_payload) >> 2); | |
5447 | } | |
5448 | ||
5449 | static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) | |
5450 | { | |
5451 | int i, r = 0; | |
5452 | struct amdgpu_device *adev = ring->adev; | |
277bd337 | 5453 | struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; |
be254550 JZ |
5454 | struct amdgpu_ring *kiq_ring = &kiq->ring; |
5455 | unsigned long flags; | |
5456 | ||
5457 | if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) | |
5458 | return -EINVAL; | |
5459 | ||
5460 | spin_lock_irqsave(&kiq->ring_lock, flags); | |
5461 | ||
5462 | if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { | |
5463 | spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
5464 | return -ENOMEM; | |
5465 | } | |
5466 | ||
5467 | /* assert preemption condition */ | |
5468 | amdgpu_ring_set_preempt_cond_exec(ring, false); | |
5469 | ||
5470 | ring->trail_seq += 1; | |
5471 | amdgpu_ring_alloc(ring, 13); | |
5472 | gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, | |
3f4c175d | 5473 | ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); |
be254550 JZ |
5474 | |
5475 | /* assert IB preemption, emit the trailing fence */ | |
5476 | kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, | |
5477 | ring->trail_fence_gpu_addr, | |
5478 | ring->trail_seq); | |
5479 | ||
5480 | amdgpu_ring_commit(kiq_ring); | |
5481 | spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
5482 | ||
5483 | /* poll the trailing fence */ | |
5484 | for (i = 0; i < adev->usec_timeout; i++) { | |
5485 | if (ring->trail_seq == | |
5486 | le32_to_cpu(*ring->trail_fence_cpu_addr)) | |
5487 | break; | |
5488 | udelay(1); | |
5489 | } | |
5490 | ||
5491 | if (i >= adev->usec_timeout) { | |
5492 | r = -EINVAL; | |
5493 | DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); | |
5494 | } | |
5495 | ||
b7941e2f JZ |
5496 | /*reset the CP_VMID_PREEMPT after trailing fence*/ |
5497 | amdgpu_ring_emit_wreg(ring, | |
5498 | SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), | |
5499 | 0x0); | |
be254550 JZ |
5500 | amdgpu_ring_commit(ring); |
5501 | ||
5502 | /* deassert preemption condition */ | |
5503 | amdgpu_ring_set_preempt_cond_exec(ring, true); | |
5504 | return r; | |
cca02cd3 XY |
5505 | } |
5506 | ||
cfdce594 | 5507 | static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds) |
cca02cd3 | 5508 | { |
be254550 | 5509 | struct amdgpu_device *adev = ring->adev; |
d81a2209 | 5510 | struct v9_de_ib_state de_payload = {0}; |
be254550 JZ |
5511 | uint64_t offset, gds_addr, de_payload_gpu_addr; |
5512 | void *de_payload_cpu_addr; | |
cca02cd3 XY |
5513 | int cnt; |
5514 | ||
be254550 JZ |
5515 | if (ring->is_mes_queue) { |
5516 | offset = offsetof(struct amdgpu_mes_ctx_meta_data, | |
5517 | gfx[0].gfx_meta_data) + | |
5518 | offsetof(struct v9_gfx_meta_data, de_payload); | |
5519 | de_payload_gpu_addr = | |
5520 | amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); | |
5521 | de_payload_cpu_addr = | |
5522 | amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); | |
5523 | ||
5524 | offset = offsetof(struct amdgpu_mes_ctx_meta_data, | |
5525 | gfx[0].gds_backup) + | |
5526 | offsetof(struct v9_gfx_meta_data, de_payload); | |
5527 | gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); | |
5528 | } else { | |
5529 | offset = offsetof(struct v9_gfx_meta_data, de_payload); | |
5530 | de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; | |
5531 | de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; | |
5532 | ||
5533 | gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + | |
5534 | AMDGPU_CSA_SIZE - adev->gds.gds_size, | |
5535 | PAGE_SIZE); | |
5536 | } | |
5537 | ||
cfdce594 JZ |
5538 | if (usegds) { |
5539 | de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); | |
5540 | de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); | |
5541 | } | |
cca02cd3 XY |
5542 | |
5543 | cnt = (sizeof(de_payload) >> 2) + 4 - 2; | |
5544 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); | |
5545 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | | |
5546 | WRITE_DATA_DST_SEL(8) | | |
5547 | WR_CONFIRM) | | |
5548 | WRITE_DATA_CACHE_POLICY(0)); | |
be254550 JZ |
5549 | amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); |
5550 | amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); | |
5551 | ||
ea791e70 | 5552 | amdgpu_ring_ib_on_emit_de(ring); |
be254550 JZ |
5553 | if (resume) |
5554 | amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, | |
5555 | sizeof(de_payload) >> 2); | |
5556 | else | |
5557 | amdgpu_ring_write_multiple(ring, (void *)&de_payload, | |
5558 | sizeof(de_payload) >> 2); | |
cca02cd3 XY |
5559 | } |
5560 | ||
f77c9aff HR |
5561 | static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, |
5562 | bool secure) | |
2ea6ab27 | 5563 | { |
f77c9aff HR |
5564 | uint32_t v = secure ? FRAME_TMZ : 0; |
5565 | ||
5566 | amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); | |
5567 | amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); | |
2ea6ab27 ML |
5568 | } |
5569 | ||
0bb5d5b0 | 5570 | static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) |
b1023571 KW |
5571 | { |
5572 | uint32_t dw2 = 0; | |
5573 | ||
be254550 JZ |
5574 | gfx_v9_0_ring_emit_ce_meta(ring, |
5575 | (!amdgpu_sriov_vf(ring->adev) && | |
5576 | flags & AMDGPU_IB_PREEMPTED) ? true : false); | |
cca02cd3 | 5577 | |
b1023571 KW |
5578 | dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ |
5579 | if (flags & AMDGPU_HAVE_CTX_SWITCH) { | |
5580 | /* set load_global_config & load_global_uconfig */ | |
5581 | dw2 |= 0x8001; | |
5582 | /* set load_cs_sh_regs */ | |
5583 | dw2 |= 0x01000000; | |
5584 | /* set load_per_context_state & load_gfx_sh_regs for GFX */ | |
5585 | dw2 |= 0x10002; | |
5586 | ||
5587 | /* set load_ce_ram if preamble presented */ | |
5588 | if (AMDGPU_PREAMBLE_IB_PRESENT & flags) | |
5589 | dw2 |= 0x10000000; | |
5590 | } else { | |
5591 | /* still load_ce_ram if this is the first time preamble presented | |
5592 | * although there is no context switch happens. | |
5593 | */ | |
5594 | if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) | |
5595 | dw2 |= 0x10000000; | |
5596 | } | |
5597 | ||
5598 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); | |
5599 | amdgpu_ring_write(ring, dw2); | |
5600 | amdgpu_ring_write(ring, 0); | |
5601 | } | |
5602 | ||
9a5e02b5 ML |
5603 | static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) |
5604 | { | |
5605 | unsigned ret; | |
5606 | amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); | |
5607 | amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); | |
5608 | amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); | |
5609 | amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ | |
5610 | ret = ring->wptr & ring->buf_mask; | |
5611 | amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ | |
5612 | return ret; | |
5613 | } | |
5614 | ||
5615 | static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) | |
5616 | { | |
5617 | unsigned cur; | |
5618 | BUG_ON(offset > ring->buf_mask); | |
5619 | BUG_ON(ring->ring[offset] != 0x55aa55aa); | |
5620 | ||
415be17f | 5621 | cur = (ring->wptr - 1) & ring->buf_mask; |
9a5e02b5 ML |
5622 | if (likely(cur > offset)) |
5623 | ring->ring[offset] = cur - offset; | |
5624 | else | |
5625 | ring->ring[offset] = (ring->ring_size>>2) - offset + cur; | |
5626 | } | |
5627 | ||
54208194 YT |
5628 | static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, |
5629 | uint32_t reg_val_offs) | |
aa6faa44 XY |
5630 | { |
5631 | struct amdgpu_device *adev = ring->adev; | |
5632 | ||
5633 | amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); | |
5634 | amdgpu_ring_write(ring, 0 | /* src: register*/ | |
5635 | (5 << 8) | /* dst: memory */ | |
5636 | (1 << 20)); /* write confirm */ | |
5637 | amdgpu_ring_write(ring, reg); | |
5638 | amdgpu_ring_write(ring, 0); | |
5639 | amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + | |
54208194 | 5640 | reg_val_offs * 4)); |
aa6faa44 | 5641 | amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + |
54208194 | 5642 | reg_val_offs * 4)); |
aa6faa44 XY |
5643 | } |
5644 | ||
5645 | static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, | |
254e825b | 5646 | uint32_t val) |
aa6faa44 | 5647 | { |
254e825b CK |
5648 | uint32_t cmd = 0; |
5649 | ||
5650 | switch (ring->funcs->type) { | |
5651 | case AMDGPU_RING_TYPE_GFX: | |
5652 | cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; | |
5653 | break; | |
5654 | case AMDGPU_RING_TYPE_KIQ: | |
5655 | cmd = (1 << 16); /* no inc addr */ | |
5656 | break; | |
5657 | default: | |
5658 | cmd = WR_CONFIRM; | |
5659 | break; | |
5660 | } | |
aa6faa44 | 5661 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
254e825b | 5662 | amdgpu_ring_write(ring, cmd); |
aa6faa44 XY |
5663 | amdgpu_ring_write(ring, reg); |
5664 | amdgpu_ring_write(ring, 0); | |
5665 | amdgpu_ring_write(ring, val); | |
5666 | } | |
5667 | ||
230fcc34 CK |
5668 | static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, |
5669 | uint32_t val, uint32_t mask) | |
5670 | { | |
5671 | gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); | |
5672 | } | |
5673 | ||
10ed3c31 AD |
5674 | static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, |
5675 | uint32_t reg0, uint32_t reg1, | |
5676 | uint32_t ref, uint32_t mask) | |
5677 | { | |
5678 | int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); | |
39b62541 ED |
5679 | struct amdgpu_device *adev = ring->adev; |
5680 | bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? | |
5681 | adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; | |
10ed3c31 | 5682 | |
39b62541 | 5683 | if (fw_version_ok) |
58cd8fbc CK |
5684 | gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, |
5685 | ref, mask, 0x20); | |
5686 | else | |
5687 | amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, | |
5688 | ref, mask); | |
10ed3c31 AD |
5689 | } |
5690 | ||
80dbea47 CK |
5691 | static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) |
5692 | { | |
5693 | struct amdgpu_device *adev = ring->adev; | |
5694 | uint32_t value = 0; | |
5695 | ||
5696 | value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); | |
5697 | value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); | |
5698 | value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); | |
5699 | value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); | |
62cfcb9e | 5700 | WREG32_SOC15(GC, 0, mmSQ_CMD, value); |
80dbea47 CK |
5701 | } |
5702 | ||
b1023571 KW |
5703 | static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, |
5704 | enum amdgpu_interrupt_state state) | |
5705 | { | |
b1023571 KW |
5706 | switch (state) { |
5707 | case AMDGPU_IRQ_STATE_DISABLE: | |
b1023571 | 5708 | case AMDGPU_IRQ_STATE_ENABLE: |
9da2c652 TSD |
5709 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, |
5710 | TIME_STAMP_INT_ENABLE, | |
5711 | state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); | |
b1023571 KW |
5712 | break; |
5713 | default: | |
5714 | break; | |
5715 | } | |
5716 | } | |
5717 | ||
5718 | static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, | |
5719 | int me, int pipe, | |
5720 | enum amdgpu_interrupt_state state) | |
5721 | { | |
5722 | u32 mec_int_cntl, mec_int_cntl_reg; | |
5723 | ||
5724 | /* | |
d0c55cdf AD |
5725 | * amdgpu controls only the first MEC. That's why this function only |
5726 | * handles the setting of interrupts for this specific MEC. All other | |
b1023571 KW |
5727 | * pipes' interrupts are set by amdkfd. |
5728 | */ | |
5729 | ||
5730 | if (me == 1) { | |
5731 | switch (pipe) { | |
5732 | case 0: | |
5733 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); | |
5734 | break; | |
d0c55cdf AD |
5735 | case 1: |
5736 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); | |
5737 | break; | |
5738 | case 2: | |
5739 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); | |
5740 | break; | |
5741 | case 3: | |
5742 | mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); | |
5743 | break; | |
b1023571 KW |
5744 | default: |
5745 | DRM_DEBUG("invalid pipe %d\n", pipe); | |
5746 | return; | |
5747 | } | |
5748 | } else { | |
5749 | DRM_DEBUG("invalid me %d\n", me); | |
5750 | return; | |
5751 | } | |
5752 | ||
5753 | switch (state) { | |
5754 | case AMDGPU_IRQ_STATE_DISABLE: | |
d764fb2a | 5755 | mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); |
b1023571 KW |
5756 | mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, |
5757 | TIME_STAMP_INT_ENABLE, 0); | |
d764fb2a | 5758 | WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); |
b1023571 KW |
5759 | break; |
5760 | case AMDGPU_IRQ_STATE_ENABLE: | |
d764fb2a | 5761 | mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); |
b1023571 KW |
5762 | mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, |
5763 | TIME_STAMP_INT_ENABLE, 1); | |
d764fb2a | 5764 | WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); |
b1023571 KW |
5765 | break; |
5766 | default: | |
5767 | break; | |
5768 | } | |
5769 | } | |
5770 | ||
5771 | static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, | |
5772 | struct amdgpu_irq_src *source, | |
5773 | unsigned type, | |
5774 | enum amdgpu_interrupt_state state) | |
5775 | { | |
b1023571 KW |
5776 | switch (state) { |
5777 | case AMDGPU_IRQ_STATE_DISABLE: | |
b1023571 | 5778 | case AMDGPU_IRQ_STATE_ENABLE: |
8dd553e1 TSD |
5779 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, |
5780 | PRIV_REG_INT_ENABLE, | |
5781 | state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); | |
b1023571 KW |
5782 | break; |
5783 | default: | |
5784 | break; | |
5785 | } | |
5786 | ||
5787 | return 0; | |
5788 | } | |
5789 | ||
5790 | static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, | |
5791 | struct amdgpu_irq_src *source, | |
5792 | unsigned type, | |
5793 | enum amdgpu_interrupt_state state) | |
5794 | { | |
b1023571 KW |
5795 | switch (state) { |
5796 | case AMDGPU_IRQ_STATE_DISABLE: | |
b1023571 | 5797 | case AMDGPU_IRQ_STATE_ENABLE: |
98709ca6 TSD |
5798 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, |
5799 | PRIV_INSTR_INT_ENABLE, | |
5800 | state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); | |
9304ca4d | 5801 | break; |
b1023571 KW |
5802 | default: |
5803 | break; | |
5804 | } | |
5805 | ||
5806 | return 0; | |
5807 | } | |
5808 | ||
760a1d55 FX |
5809 | #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ |
5810 | WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ | |
5811 | CP_ECC_ERROR_INT_ENABLE, 1) | |
5812 | ||
5813 | #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ | |
5814 | WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ | |
5815 | CP_ECC_ERROR_INT_ENABLE, 0) | |
5816 | ||
5817 | static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, | |
5818 | struct amdgpu_irq_src *source, | |
5819 | unsigned type, | |
5820 | enum amdgpu_interrupt_state state) | |
5821 | { | |
5822 | switch (state) { | |
5823 | case AMDGPU_IRQ_STATE_DISABLE: | |
5824 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, | |
5825 | CP_ECC_ERROR_INT_ENABLE, 0); | |
5826 | DISABLE_ECC_ON_ME_PIPE(1, 0); | |
5827 | DISABLE_ECC_ON_ME_PIPE(1, 1); | |
5828 | DISABLE_ECC_ON_ME_PIPE(1, 2); | |
5829 | DISABLE_ECC_ON_ME_PIPE(1, 3); | |
5830 | break; | |
5831 | ||
5832 | case AMDGPU_IRQ_STATE_ENABLE: | |
5833 | WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, | |
5834 | CP_ECC_ERROR_INT_ENABLE, 1); | |
5835 | ENABLE_ECC_ON_ME_PIPE(1, 0); | |
5836 | ENABLE_ECC_ON_ME_PIPE(1, 1); | |
5837 | ENABLE_ECC_ON_ME_PIPE(1, 2); | |
5838 | ENABLE_ECC_ON_ME_PIPE(1, 3); | |
5839 | break; | |
5840 | default: | |
5841 | break; | |
5842 | } | |
5843 | ||
5844 | return 0; | |
5845 | } | |
5846 | ||
5847 | ||
b1023571 KW |
5848 | static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, |
5849 | struct amdgpu_irq_src *src, | |
5850 | unsigned type, | |
5851 | enum amdgpu_interrupt_state state) | |
5852 | { | |
5853 | switch (type) { | |
53b2fe41 | 5854 | case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: |
b1023571 KW |
5855 | gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); |
5856 | break; | |
5857 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: | |
5858 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); | |
5859 | break; | |
5860 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: | |
5861 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); | |
5862 | break; | |
5863 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: | |
5864 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); | |
5865 | break; | |
5866 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: | |
5867 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); | |
5868 | break; | |
5869 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: | |
5870 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); | |
5871 | break; | |
5872 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: | |
5873 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); | |
5874 | break; | |
5875 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: | |
5876 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); | |
5877 | break; | |
5878 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: | |
5879 | gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); | |
5880 | break; | |
5881 | default: | |
5882 | break; | |
5883 | } | |
5884 | return 0; | |
5885 | } | |
5886 | ||
5887 | static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, | |
5888 | struct amdgpu_irq_src *source, | |
5889 | struct amdgpu_iv_entry *entry) | |
5890 | { | |
5891 | int i; | |
5892 | u8 me_id, pipe_id, queue_id; | |
5893 | struct amdgpu_ring *ring; | |
5894 | ||
5895 | DRM_DEBUG("IH: CP EOP\n"); | |
5896 | me_id = (entry->ring_id & 0x0c) >> 2; | |
5897 | pipe_id = (entry->ring_id & 0x03) >> 0; | |
5898 | queue_id = (entry->ring_id & 0x70) >> 4; | |
5899 | ||
5900 | switch (me_id) { | |
5901 | case 0: | |
3f4c175d JZ |
5902 | if (adev->gfx.num_gfx_rings && |
5903 | !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { | |
5904 | /* Fence signals are handled on the software rings*/ | |
0c97a19a JZ |
5905 | for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) |
5906 | amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); | |
5907 | } | |
b1023571 KW |
5908 | break; |
5909 | case 1: | |
5910 | case 2: | |
5911 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
5912 | ring = &adev->gfx.compute_ring[i]; | |
5913 | /* Per-queue interrupt is supported for MEC starting from VI. | |
5914 | * The interrupt can only be enabled/disabled per pipe instead of per queue. | |
5915 | */ | |
5916 | if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) | |
5917 | amdgpu_fence_process(ring); | |
5918 | } | |
5919 | break; | |
5920 | } | |
5921 | return 0; | |
5922 | } | |
5923 | ||
898c2cb5 CK |
5924 | static void gfx_v9_0_fault(struct amdgpu_device *adev, |
5925 | struct amdgpu_iv_entry *entry) | |
5926 | { | |
5927 | u8 me_id, pipe_id, queue_id; | |
5928 | struct amdgpu_ring *ring; | |
5929 | int i; | |
5930 | ||
5931 | me_id = (entry->ring_id & 0x0c) >> 2; | |
5932 | pipe_id = (entry->ring_id & 0x03) >> 0; | |
5933 | queue_id = (entry->ring_id & 0x70) >> 4; | |
5934 | ||
5935 | switch (me_id) { | |
5936 | case 0: | |
5937 | drm_sched_fault(&adev->gfx.gfx_ring[0].sched); | |
5938 | break; | |
5939 | case 1: | |
5940 | case 2: | |
5941 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { | |
5942 | ring = &adev->gfx.compute_ring[i]; | |
5943 | if (ring->me == me_id && ring->pipe == pipe_id && | |
5944 | ring->queue == queue_id) | |
5945 | drm_sched_fault(&ring->sched); | |
5946 | } | |
5947 | break; | |
5948 | } | |
5949 | } | |
5950 | ||
b1023571 KW |
5951 | static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, |
5952 | struct amdgpu_irq_src *source, | |
5953 | struct amdgpu_iv_entry *entry) | |
5954 | { | |
5955 | DRM_ERROR("Illegal register access in command stream\n"); | |
898c2cb5 | 5956 | gfx_v9_0_fault(adev, entry); |
b1023571 KW |
5957 | return 0; |
5958 | } | |
5959 | ||
5960 | static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, | |
5961 | struct amdgpu_irq_src *source, | |
5962 | struct amdgpu_iv_entry *entry) | |
5963 | { | |
5964 | DRM_ERROR("Illegal instruction in command stream\n"); | |
898c2cb5 | 5965 | gfx_v9_0_fault(adev, entry); |
b1023571 KW |
5966 | return 0; |
5967 | } | |
5968 | ||
13ba0344 | 5969 | |
504c5e72 | 5970 | static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { |
13ba0344 DL |
5971 | { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), |
5972 | SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), | |
5973 | SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) | |
5974 | }, | |
5975 | { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), | |
5976 | SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), | |
5977 | SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) | |
5978 | }, | |
5979 | { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), | |
5980 | SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), | |
5981 | 0, 0 | |
5982 | }, | |
5983 | { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), | |
5984 | SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), | |
5985 | 0, 0 | |
5986 | }, | |
5987 | { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), | |
5988 | SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), | |
5989 | SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) | |
5990 | }, | |
5991 | { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), | |
5992 | SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), | |
5993 | 0, 0 | |
5994 | }, | |
5995 | { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), | |
5996 | SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), | |
5997 | SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) | |
5998 | }, | |
5999 | { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), | |
6000 | SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), | |
6001 | SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) | |
6002 | }, | |
6003 | { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), | |
6004 | SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), | |
6005 | 0, 0 | |
6006 | }, | |
6007 | { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), | |
6008 | SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), | |
6009 | 0, 0 | |
6010 | }, | |
6011 | { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), | |
6012 | SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), | |
6013 | 0, 0 | |
6014 | }, | |
6015 | { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), | |
6016 | SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), | |
6017 | SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) | |
6018 | }, | |
6019 | { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), | |
6020 | SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), | |
6021 | 0, 0 | |
6022 | }, | |
2c960ea0 | 6023 | { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), |
13ba0344 DL |
6024 | SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), |
6025 | SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) | |
6026 | }, | |
2c960ea0 | 6027 | { "GDS_OA_PHY_PHY_CMD_RAM_MEM", |
13ba0344 DL |
6028 | SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), |
6029 | SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), | |
6030 | SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) | |
6031 | }, | |
2c960ea0 | 6032 | { "GDS_OA_PHY_PHY_DATA_RAM_MEM", |
13ba0344 DL |
6033 | SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), |
6034 | SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), | |
6035 | 0, 0 | |
6036 | }, | |
2c960ea0 | 6037 | { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", |
13ba0344 DL |
6038 | SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), |
6039 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), | |
6040 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) | |
6041 | }, | |
2c960ea0 | 6042 | { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", |
13ba0344 DL |
6043 | SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), |
6044 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), | |
6045 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) | |
6046 | }, | |
2c960ea0 | 6047 | { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", |
13ba0344 DL |
6048 | SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), |
6049 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), | |
6050 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) | |
6051 | }, | |
2c960ea0 | 6052 | { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", |
13ba0344 DL |
6053 | SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), |
6054 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), | |
6055 | SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) | |
6056 | }, | |
6057 | { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), | |
6058 | SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), | |
6059 | 0, 0 | |
6060 | }, | |
6061 | { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), | |
6062 | SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), | |
6063 | SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) | |
6064 | }, | |
6065 | { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), | |
6066 | SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), | |
6067 | 0, 0 | |
6068 | }, | |
6069 | { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), | |
6070 | SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), | |
6071 | 0, 0 | |
6072 | }, | |
6073 | { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), | |
6074 | SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), | |
6075 | 0, 0 | |
6076 | }, | |
6077 | { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), | |
6078 | SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), | |
6079 | 0, 0 | |
6080 | }, | |
6081 | { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), | |
6082 | SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), | |
6083 | 0, 0 | |
6084 | }, | |
6085 | { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), | |
6086 | SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), | |
6087 | 0, 0 | |
6088 | }, | |
6089 | { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6090 | SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), | |
6091 | SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) | |
6092 | }, | |
6093 | { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6094 | SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), | |
6095 | SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) | |
6096 | }, | |
6097 | { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6098 | SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), | |
6099 | SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) | |
6100 | }, | |
6101 | { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6102 | SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), | |
6103 | SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) | |
6104 | }, | |
6105 | { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6106 | SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), | |
6107 | SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) | |
6108 | }, | |
6109 | { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6110 | SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), | |
6111 | 0, 0 | |
6112 | }, | |
6113 | { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6114 | SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), | |
6115 | 0, 0 | |
6116 | }, | |
6117 | { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6118 | SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), | |
6119 | 0, 0 | |
6120 | }, | |
6121 | { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6122 | SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), | |
6123 | 0, 0 | |
6124 | }, | |
6125 | { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6126 | SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), | |
6127 | 0, 0 | |
6128 | }, | |
6129 | { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), | |
6130 | SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), | |
6131 | 0, 0 | |
6132 | }, | |
6133 | { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), | |
6134 | SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), | |
6135 | 0, 0 | |
6136 | }, | |
6137 | { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), | |
6138 | SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), | |
6139 | 0, 0 | |
6140 | }, | |
6141 | { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), | |
6142 | SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), | |
6143 | 0, 0 | |
6144 | }, | |
2c960ea0 | 6145 | { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), |
13ba0344 DL |
6146 | SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), |
6147 | 0, 0 | |
6148 | }, | |
6149 | { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), | |
6150 | SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), | |
6151 | 0, 0 | |
6152 | }, | |
2c960ea0 | 6153 | { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), |
13ba0344 DL |
6154 | SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), |
6155 | 0, 0 | |
6156 | }, | |
6157 | { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), | |
6158 | SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), | |
6159 | 0, 0 | |
6160 | }, | |
6161 | { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), | |
6162 | SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), | |
6163 | 0, 0 | |
6164 | }, | |
6165 | { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6166 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), | |
6167 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) | |
6168 | }, | |
6169 | { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6170 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), | |
6171 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) | |
6172 | }, | |
6173 | { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6174 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), | |
6175 | 0, 0 | |
6176 | }, | |
6177 | { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6178 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), | |
6179 | 0, 0 | |
6180 | }, | |
6181 | { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6182 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), | |
6183 | 0, 0 | |
6184 | }, | |
6185 | { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6186 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), | |
6187 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) | |
6188 | }, | |
6189 | { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), | |
6190 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), | |
6191 | SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) | |
6192 | }, | |
6193 | { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), | |
6194 | SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), | |
6195 | SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) | |
6196 | }, | |
6197 | { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), | |
6198 | SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), | |
6199 | SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) | |
6200 | }, | |
6201 | { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), | |
6202 | SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), | |
6203 | 0, 0 | |
6204 | }, | |
6205 | { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6206 | SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), | |
6207 | SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) | |
6208 | }, | |
6209 | { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6210 | SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), | |
6211 | SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) | |
6212 | }, | |
6213 | { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6214 | SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), | |
6215 | SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) | |
6216 | }, | |
6217 | { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6218 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), | |
6219 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) | |
6220 | }, | |
6221 | { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6222 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), | |
6223 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) | |
6224 | }, | |
6225 | { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6226 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), | |
6227 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) | |
6228 | }, | |
6229 | { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), | |
6230 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), | |
6231 | SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) | |
6232 | }, | |
2c960ea0 | 6233 | { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), |
13ba0344 DL |
6234 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), |
6235 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) | |
6236 | }, | |
6237 | { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), | |
6238 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), | |
6239 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) | |
6240 | }, | |
2c960ea0 | 6241 | { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), |
13ba0344 DL |
6242 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), |
6243 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) | |
6244 | }, | |
6245 | { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), | |
6246 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), | |
6247 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) | |
6248 | }, | |
2c960ea0 | 6249 | { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), |
13ba0344 DL |
6250 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), |
6251 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) | |
6252 | }, | |
6253 | { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), | |
6254 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), | |
6255 | SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) | |
6256 | }, | |
6257 | { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6258 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), | |
6259 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) | |
6260 | }, | |
6261 | { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6262 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), | |
6263 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) | |
6264 | }, | |
6265 | { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6266 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), | |
6267 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) | |
6268 | }, | |
6269 | { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6270 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), | |
6271 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) | |
6272 | }, | |
6273 | { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6274 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), | |
6275 | 0, 0 | |
6276 | }, | |
6277 | { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6278 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), | |
6279 | 0, 0 | |
6280 | }, | |
6281 | { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6282 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), | |
6283 | 0, 0 | |
6284 | }, | |
6285 | { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6286 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), | |
6287 | 0, 0 | |
6288 | }, | |
6289 | { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6290 | SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), | |
6291 | 0, 0 | |
6292 | }, | |
6293 | { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), | |
6294 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), | |
6295 | SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) | |
6296 | }, | |
6297 | { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6298 | SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), | |
6299 | SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) | |
6300 | }, | |
6301 | { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6302 | SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), | |
6303 | SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) | |
6304 | }, | |
6305 | { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6306 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), | |
6307 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) | |
6308 | }, | |
6309 | { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6310 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), | |
6311 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) | |
6312 | }, | |
6313 | { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6314 | SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), | |
6315 | 0, 0 | |
6316 | }, | |
6317 | { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6318 | SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), | |
6319 | 0, 0 | |
6320 | }, | |
6321 | { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6322 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), | |
6323 | 0, 0 | |
6324 | }, | |
6325 | { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6326 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), | |
6327 | 0, 0 | |
6328 | }, | |
6329 | { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), | |
6330 | SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), | |
6331 | 0, 0 | |
6332 | }, | |
6333 | { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6334 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), | |
6335 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) | |
6336 | }, | |
6337 | { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6338 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), | |
6339 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) | |
6340 | }, | |
6341 | { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6342 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), | |
6343 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) | |
6344 | }, | |
6345 | { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6346 | SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), | |
6347 | SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) | |
6348 | }, | |
6349 | { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6350 | SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), | |
6351 | SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) | |
6352 | }, | |
6353 | { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6354 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), | |
6355 | 0, 0 | |
6356 | }, | |
6357 | { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6358 | SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), | |
6359 | 0, 0 | |
6360 | }, | |
6361 | { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6362 | SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), | |
6363 | 0, 0 | |
6364 | }, | |
6365 | { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6366 | SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), | |
6367 | 0, 0 | |
6368 | }, | |
6369 | { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), | |
6370 | SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), | |
6371 | 0, 0 | |
6372 | }, | |
6373 | { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6374 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), | |
6375 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) | |
6376 | }, | |
6377 | { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6378 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), | |
6379 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) | |
6380 | }, | |
6381 | { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6382 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), | |
6383 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) | |
6384 | }, | |
6385 | { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6386 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), | |
6387 | 0, 0 | |
6388 | }, | |
6389 | { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6390 | SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), | |
6391 | 0, 0 | |
6392 | }, | |
6393 | { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6394 | SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), | |
6395 | 0, 0 | |
6396 | }, | |
6397 | { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6398 | SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), | |
6399 | 0, 0 | |
6400 | }, | |
6401 | { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6402 | SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), | |
6403 | 0, 0 | |
6404 | }, | |
6405 | { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), | |
6406 | SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), | |
6407 | 0, 0 | |
6408 | } | |
2c960ea0 DL |
6409 | }; |
6410 | ||
6411 | static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, | |
2c22ed0b | 6412 | void *inject_if, uint32_t instance_mask) |
2c960ea0 DL |
6413 | { |
6414 | struct ras_inject_if *info = (struct ras_inject_if *)inject_if; | |
6415 | int ret; | |
6416 | struct ta_ras_trigger_error_input block_info = { 0 }; | |
6417 | ||
5e66403e | 6418 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
2c960ea0 DL |
6419 | return -EINVAL; |
6420 | ||
a2b45994 GC |
6421 | if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) |
6422 | return -EINVAL; | |
6423 | ||
2c960ea0 DL |
6424 | if (!ras_gfx_subblocks[info->head.sub_block_index].name) |
6425 | return -EPERM; | |
6426 | ||
dc4d716d DL |
6427 | if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & |
6428 | info->head.type)) { | |
6429 | DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", | |
6430 | ras_gfx_subblocks[info->head.sub_block_index].name, | |
6431 | info->head.type); | |
2c960ea0 | 6432 | return -EPERM; |
dc4d716d DL |
6433 | } |
6434 | ||
6435 | if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & | |
6436 | info->head.type)) { | |
6437 | DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", | |
6438 | ras_gfx_subblocks[info->head.sub_block_index].name, | |
6439 | info->head.type); | |
6440 | return -EPERM; | |
6441 | } | |
2c960ea0 DL |
6442 | |
6443 | block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); | |
6444 | block_info.sub_block_index = | |
6445 | ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; | |
6446 | block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); | |
6447 | block_info.address = info->address; | |
6448 | block_info.value = info->value; | |
6449 | ||
6450 | mutex_lock(&adev->grbm_idx_mutex); | |
2c22ed0b | 6451 | ret = psp_ras_trigger_error(&adev->psp, &block_info, instance_mask); |
2c960ea0 DL |
6452 | mutex_unlock(&adev->grbm_idx_mutex); |
6453 | ||
6454 | return ret; | |
6455 | } | |
6456 | ||
82092474 DL |
6457 | static const char *vml2_mems[] = { |
6458 | "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", | |
6459 | "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", | |
6460 | "UTC_VML2_BANK_CACHE_0_4K_MEM0", | |
6461 | "UTC_VML2_BANK_CACHE_0_4K_MEM1", | |
6462 | "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", | |
6463 | "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", | |
6464 | "UTC_VML2_BANK_CACHE_1_4K_MEM0", | |
6465 | "UTC_VML2_BANK_CACHE_1_4K_MEM1", | |
6466 | "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", | |
6467 | "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", | |
6468 | "UTC_VML2_BANK_CACHE_2_4K_MEM0", | |
6469 | "UTC_VML2_BANK_CACHE_2_4K_MEM1", | |
6470 | "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", | |
6471 | "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", | |
6472 | "UTC_VML2_BANK_CACHE_3_4K_MEM0", | |
6473 | "UTC_VML2_BANK_CACHE_3_4K_MEM1", | |
6474 | }; | |
6475 | ||
6476 | static const char *vml2_walker_mems[] = { | |
6477 | "UTC_VML2_CACHE_PDE0_MEM0", | |
6478 | "UTC_VML2_CACHE_PDE0_MEM1", | |
6479 | "UTC_VML2_CACHE_PDE1_MEM0", | |
6480 | "UTC_VML2_CACHE_PDE1_MEM1", | |
6481 | "UTC_VML2_CACHE_PDE2_MEM0", | |
6482 | "UTC_VML2_CACHE_PDE2_MEM1", | |
6483 | "UTC_VML2_RDIF_LOG_FIFO", | |
6484 | }; | |
6485 | ||
6486 | static const char *atc_l2_cache_2m_mems[] = { | |
6487 | "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", | |
6488 | "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", | |
6489 | "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", | |
6490 | "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", | |
6491 | }; | |
6492 | ||
6493 | static const char *atc_l2_cache_4k_mems[] = { | |
6494 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", | |
6495 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", | |
6496 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", | |
6497 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", | |
6498 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", | |
6499 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", | |
6500 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", | |
6501 | "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", | |
6502 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", | |
6503 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", | |
6504 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", | |
6505 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", | |
6506 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", | |
6507 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", | |
6508 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", | |
6509 | "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", | |
6510 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", | |
6511 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", | |
6512 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", | |
6513 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", | |
6514 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", | |
6515 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", | |
6516 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", | |
6517 | "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", | |
6518 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", | |
6519 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", | |
6520 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", | |
6521 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", | |
6522 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", | |
6523 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", | |
6524 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", | |
6525 | "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", | |
6526 | }; | |
6527 | ||
6528 | static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, | |
6529 | struct ras_err_data *err_data) | |
6530 | { | |
6531 | uint32_t i, data; | |
6532 | uint32_t sec_count, ded_count; | |
6533 | ||
6534 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); | |
6535 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); | |
6536 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); | |
6537 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); | |
6538 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); | |
6539 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); | |
6540 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); | |
6541 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); | |
6542 | ||
504c5e72 | 6543 | for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { |
82092474 DL |
6544 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); |
6545 | data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); | |
6546 | ||
6547 | sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); | |
6548 | if (sec_count) { | |
ed72aa21 GC |
6549 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6550 | "SEC %d\n", i, vml2_mems[i], sec_count); | |
82092474 DL |
6551 | err_data->ce_count += sec_count; |
6552 | } | |
6553 | ||
6554 | ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); | |
6555 | if (ded_count) { | |
ed72aa21 GC |
6556 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6557 | "DED %d\n", i, vml2_mems[i], ded_count); | |
82092474 DL |
6558 | err_data->ue_count += ded_count; |
6559 | } | |
6560 | } | |
6561 | ||
504c5e72 | 6562 | for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { |
82092474 DL |
6563 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); |
6564 | data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); | |
6565 | ||
6566 | sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, | |
6567 | SEC_COUNT); | |
6568 | if (sec_count) { | |
ed72aa21 GC |
6569 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6570 | "SEC %d\n", i, vml2_walker_mems[i], sec_count); | |
82092474 DL |
6571 | err_data->ce_count += sec_count; |
6572 | } | |
6573 | ||
6574 | ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, | |
6575 | DED_COUNT); | |
6576 | if (ded_count) { | |
ed72aa21 GC |
6577 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6578 | "DED %d\n", i, vml2_walker_mems[i], ded_count); | |
82092474 DL |
6579 | err_data->ue_count += ded_count; |
6580 | } | |
6581 | } | |
6582 | ||
504c5e72 | 6583 | for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { |
82092474 DL |
6584 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); |
6585 | data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); | |
6586 | ||
6587 | sec_count = (data & 0x00006000L) >> 0xd; | |
6588 | if (sec_count) { | |
ed72aa21 GC |
6589 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6590 | "SEC %d\n", i, atc_l2_cache_2m_mems[i], | |
6591 | sec_count); | |
82092474 DL |
6592 | err_data->ce_count += sec_count; |
6593 | } | |
6594 | } | |
6595 | ||
504c5e72 | 6596 | for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { |
82092474 DL |
6597 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); |
6598 | data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); | |
6599 | ||
6600 | sec_count = (data & 0x00006000L) >> 0xd; | |
6601 | if (sec_count) { | |
ed72aa21 GC |
6602 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6603 | "SEC %d\n", i, atc_l2_cache_4k_mems[i], | |
6604 | sec_count); | |
82092474 DL |
6605 | err_data->ce_count += sec_count; |
6606 | } | |
6607 | ||
6608 | ded_count = (data & 0x00018000L) >> 0xf; | |
6609 | if (ded_count) { | |
ed72aa21 GC |
6610 | dev_info(adev->dev, "Instance[%d]: SubBlock %s, " |
6611 | "DED %d\n", i, atc_l2_cache_4k_mems[i], | |
6612 | ded_count); | |
82092474 DL |
6613 | err_data->ue_count += ded_count; |
6614 | } | |
6615 | } | |
6616 | ||
6617 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); | |
6618 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); | |
6619 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); | |
6620 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); | |
6621 | ||
6622 | return 0; | |
6623 | } | |
6624 | ||
ed72aa21 GC |
6625 | static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, |
6626 | const struct soc15_reg_entry *reg, | |
13ba0344 DL |
6627 | uint32_t se_id, uint32_t inst_id, uint32_t value, |
6628 | uint32_t *sec_count, uint32_t *ded_count) | |
6629 | { | |
6630 | uint32_t i; | |
6631 | uint32_t sec_cnt, ded_cnt; | |
6632 | ||
504c5e72 DL |
6633 | for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { |
6634 | if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || | |
6635 | gfx_v9_0_ras_fields[i].seg != reg->seg || | |
6636 | gfx_v9_0_ras_fields[i].inst != reg->inst) | |
13ba0344 DL |
6637 | continue; |
6638 | ||
6639 | sec_cnt = (value & | |
504c5e72 DL |
6640 | gfx_v9_0_ras_fields[i].sec_count_mask) >> |
6641 | gfx_v9_0_ras_fields[i].sec_count_shift; | |
13ba0344 | 6642 | if (sec_cnt) { |
ed72aa21 GC |
6643 | dev_info(adev->dev, "GFX SubBlock %s, " |
6644 | "Instance[%d][%d], SEC %d\n", | |
504c5e72 | 6645 | gfx_v9_0_ras_fields[i].name, |
13ba0344 DL |
6646 | se_id, inst_id, |
6647 | sec_cnt); | |
6648 | *sec_count += sec_cnt; | |
6649 | } | |
6650 | ||
6651 | ded_cnt = (value & | |
504c5e72 DL |
6652 | gfx_v9_0_ras_fields[i].ded_count_mask) >> |
6653 | gfx_v9_0_ras_fields[i].ded_count_shift; | |
13ba0344 | 6654 | if (ded_cnt) { |
ed72aa21 GC |
6655 | dev_info(adev->dev, "GFX SubBlock %s, " |
6656 | "Instance[%d][%d], DED %d\n", | |
504c5e72 | 6657 | gfx_v9_0_ras_fields[i].name, |
13ba0344 DL |
6658 | se_id, inst_id, |
6659 | ded_cnt); | |
6660 | *ded_count += ded_cnt; | |
6661 | } | |
6662 | } | |
6663 | ||
6664 | return 0; | |
6665 | } | |
6666 | ||
279375c3 | 6667 | static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) |
504c5e72 DL |
6668 | { |
6669 | int i, j, k; | |
6670 | ||
06dcd7eb HZ |
6671 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
6672 | return; | |
6673 | ||
504c5e72 DL |
6674 | /* read back registers to clear the counters */ |
6675 | mutex_lock(&adev->grbm_idx_mutex); | |
6676 | for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { | |
6677 | for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { | |
6678 | for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { | |
d51ac6d0 | 6679 | amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0); |
504c5e72 DL |
6680 | RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); |
6681 | } | |
6682 | } | |
6683 | } | |
6684 | WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); | |
6685 | mutex_unlock(&adev->grbm_idx_mutex); | |
6686 | ||
6687 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); | |
6688 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); | |
6689 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); | |
6690 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); | |
6691 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); | |
6692 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); | |
6693 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); | |
6694 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); | |
6695 | ||
6696 | for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { | |
6697 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); | |
6698 | RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); | |
6699 | } | |
6700 | ||
6701 | for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { | |
6702 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); | |
6703 | RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); | |
6704 | } | |
6705 | ||
6706 | for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { | |
6707 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); | |
6708 | RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); | |
6709 | } | |
6710 | ||
6711 | for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { | |
6712 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); | |
6713 | RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); | |
6714 | } | |
6715 | ||
6716 | WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); | |
6717 | WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); | |
6718 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); | |
6719 | WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); | |
6720 | } | |
6721 | ||
8b0fb0e9 | 6722 | static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, |
2c960ea0 DL |
6723 | void *ras_error_status) |
6724 | { | |
6725 | struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; | |
13ba0344 DL |
6726 | uint32_t sec_count = 0, ded_count = 0; |
6727 | uint32_t i, j, k; | |
2c960ea0 | 6728 | uint32_t reg_value; |
2c960ea0 | 6729 | |
5e66403e | 6730 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
8b0fb0e9 | 6731 | return; |
2c960ea0 DL |
6732 | |
6733 | err_data->ue_count = 0; | |
6734 | err_data->ce_count = 0; | |
6735 | ||
6736 | mutex_lock(&adev->grbm_idx_mutex); | |
2c960ea0 | 6737 | |
504c5e72 DL |
6738 | for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { |
6739 | for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { | |
6740 | for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { | |
d51ac6d0 | 6741 | amdgpu_gfx_select_se_sh(adev, j, 0, k, 0); |
13ba0344 | 6742 | reg_value = |
504c5e72 | 6743 | RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); |
13ba0344 | 6744 | if (reg_value) |
ed72aa21 GC |
6745 | gfx_v9_0_ras_error_count(adev, |
6746 | &gfx_v9_0_edc_counter_regs[i], | |
6747 | j, k, reg_value, | |
6748 | &sec_count, &ded_count); | |
2c960ea0 DL |
6749 | } |
6750 | } | |
6751 | } | |
13ba0344 DL |
6752 | |
6753 | err_data->ce_count += sec_count; | |
6754 | err_data->ue_count += ded_count; | |
6755 | ||
d51ac6d0 | 6756 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
2c960ea0 DL |
6757 | mutex_unlock(&adev->grbm_idx_mutex); |
6758 | ||
82092474 | 6759 | gfx_v9_0_query_utc_edc_status(adev, err_data); |
2c960ea0 DL |
6760 | } |
6761 | ||
2f9ce2a3 AG |
6762 | static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) |
6763 | { | |
6764 | const unsigned int cp_coher_cntl = | |
6765 | PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | | |
6766 | PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | | |
6767 | PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | | |
6768 | PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | | |
6769 | PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); | |
6770 | ||
6771 | /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ | |
6772 | amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); | |
6773 | amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ | |
6774 | amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ | |
6775 | amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ | |
6776 | amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ | |
6777 | amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ | |
6778 | amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ | |
6779 | } | |
6780 | ||
f8bf6450 ND |
6781 | static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, |
6782 | uint32_t pipe, bool enable) | |
6783 | { | |
6784 | struct amdgpu_device *adev = ring->adev; | |
6785 | uint32_t val; | |
6786 | uint32_t wcl_cs_reg; | |
6787 | ||
6788 | /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ | |
6789 | val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; | |
6790 | ||
6791 | switch (pipe) { | |
6792 | case 0: | |
6793 | wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); | |
6794 | break; | |
6795 | case 1: | |
6796 | wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); | |
6797 | break; | |
6798 | case 2: | |
6799 | wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); | |
6800 | break; | |
6801 | case 3: | |
6802 | wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); | |
6803 | break; | |
6804 | default: | |
6805 | DRM_DEBUG("invalid pipe %d\n", pipe); | |
6806 | return; | |
6807 | } | |
6808 | ||
6809 | amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); | |
6810 | ||
6811 | } | |
0a52a6ca ND |
6812 | static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) |
6813 | { | |
6814 | struct amdgpu_device *adev = ring->adev; | |
6815 | uint32_t val; | |
f8bf6450 | 6816 | int i; |
0a52a6ca ND |
6817 | |
6818 | ||
6819 | /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit | |
6820 | * number of gfx waves. Setting 5 bit will make sure gfx only gets | |
6821 | * around 25% of gpu resources. | |
6822 | */ | |
6823 | val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; | |
6824 | amdgpu_ring_emit_wreg(ring, | |
6825 | SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), | |
6826 | val); | |
f8bf6450 ND |
6827 | |
6828 | /* Restrict waves for normal/low priority compute queues as well | |
6829 | * to get best QoS for high priority compute jobs. | |
6830 | * | |
6831 | * amdgpu controls only 1st ME(0-3 CS pipes). | |
6832 | */ | |
6833 | for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { | |
6834 | if (i != ring->pipe) | |
6835 | gfx_v9_0_emit_wave_limit_cs(ring, i, enable); | |
6836 | ||
6837 | } | |
0a52a6ca ND |
6838 | } |
6839 | ||
fa04b6ba | 6840 | static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { |
b1023571 KW |
6841 | .name = "gfx_v9_0", |
6842 | .early_init = gfx_v9_0_early_init, | |
6843 | .late_init = gfx_v9_0_late_init, | |
6844 | .sw_init = gfx_v9_0_sw_init, | |
6845 | .sw_fini = gfx_v9_0_sw_fini, | |
6846 | .hw_init = gfx_v9_0_hw_init, | |
6847 | .hw_fini = gfx_v9_0_hw_fini, | |
6848 | .suspend = gfx_v9_0_suspend, | |
6849 | .resume = gfx_v9_0_resume, | |
6850 | .is_idle = gfx_v9_0_is_idle, | |
6851 | .wait_for_idle = gfx_v9_0_wait_for_idle, | |
6852 | .soft_reset = gfx_v9_0_soft_reset, | |
6853 | .set_clockgating_state = gfx_v9_0_set_clockgating_state, | |
6854 | .set_powergating_state = gfx_v9_0_set_powergating_state, | |
12ad27fa | 6855 | .get_clockgating_state = gfx_v9_0_get_clockgating_state, |
b1023571 KW |
6856 | }; |
6857 | ||
6858 | static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { | |
6859 | .type = AMDGPU_RING_TYPE_GFX, | |
6860 | .align_mask = 0xff, | |
6861 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), | |
6862 | .support_64bit_ptrs = true, | |
8c0f11ff | 6863 | .secure_submission_supported = true, |
b1023571 KW |
6864 | .get_rptr = gfx_v9_0_ring_get_rptr_gfx, |
6865 | .get_wptr = gfx_v9_0_ring_get_wptr_gfx, | |
6866 | .set_wptr = gfx_v9_0_ring_set_wptr_gfx, | |
e9d672b2 ML |
6867 | .emit_frame_size = /* totally 242 maximum if 16 IBs */ |
6868 | 5 + /* COND_EXEC */ | |
6869 | 7 + /* PIPELINE_SYNC */ | |
f732b6b3 CK |
6870 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + |
6871 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + | |
6872 | 2 + /* VM_FLUSH */ | |
e9d672b2 ML |
6873 | 8 + /* FENCE for VM_FLUSH */ |
6874 | 20 + /* GDS switch */ | |
6875 | 4 + /* double SWITCH_BUFFER, | |
6876 | the first COND_EXEC jump to the place just | |
6877 | prior to this double SWITCH_BUFFER */ | |
6878 | 5 + /* COND_EXEC */ | |
6879 | 7 + /* HDP_flush */ | |
6880 | 4 + /* VGT_flush */ | |
6881 | 14 + /* CE_META */ | |
6882 | 31 + /* DE_META */ | |
6883 | 3 + /* CNTX_CTRL */ | |
6884 | 5 + /* HDP_INVL */ | |
6885 | 8 + 8 + /* FENCE x2 */ | |
2f9ce2a3 AG |
6886 | 2 + /* SWITCH_BUFFER */ |
6887 | 7, /* gfx_v9_0_emit_mem_sync */ | |
b1023571 KW |
6888 | .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ |
6889 | .emit_ib = gfx_v9_0_ring_emit_ib_gfx, | |
6890 | .emit_fence = gfx_v9_0_ring_emit_fence, | |
6891 | .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, | |
6892 | .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, | |
6893 | .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, | |
6894 | .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, | |
b1023571 | 6895 | .test_ring = gfx_v9_0_ring_test_ring, |
b1023571 KW |
6896 | .insert_nop = amdgpu_ring_insert_nop, |
6897 | .pad_ib = amdgpu_ring_generic_pad_ib, | |
6898 | .emit_switch_buffer = gfx_v9_ring_emit_sb, | |
6899 | .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, | |
9a5e02b5 ML |
6900 | .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, |
6901 | .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, | |
be254550 | 6902 | .preempt_ib = gfx_v9_0_ring_preempt_ib, |
f77c9aff | 6903 | .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, |
254e825b | 6904 | .emit_wreg = gfx_v9_0_ring_emit_wreg, |
230fcc34 | 6905 | .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, |
10ed3c31 | 6906 | .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, |
80dbea47 | 6907 | .soft_recovery = gfx_v9_0_ring_soft_recovery, |
2f9ce2a3 | 6908 | .emit_mem_sync = gfx_v9_0_emit_mem_sync, |
b1023571 KW |
6909 | }; |
6910 | ||
0c97a19a JZ |
6911 | static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { |
6912 | .type = AMDGPU_RING_TYPE_GFX, | |
6913 | .align_mask = 0xff, | |
6914 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), | |
6915 | .support_64bit_ptrs = true, | |
6916 | .secure_submission_supported = true, | |
0c97a19a JZ |
6917 | .get_rptr = amdgpu_sw_ring_get_rptr_gfx, |
6918 | .get_wptr = amdgpu_sw_ring_get_wptr_gfx, | |
6919 | .set_wptr = amdgpu_sw_ring_set_wptr_gfx, | |
6920 | .emit_frame_size = /* totally 242 maximum if 16 IBs */ | |
6921 | 5 + /* COND_EXEC */ | |
6922 | 7 + /* PIPELINE_SYNC */ | |
6923 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + | |
6924 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + | |
6925 | 2 + /* VM_FLUSH */ | |
6926 | 8 + /* FENCE for VM_FLUSH */ | |
6927 | 20 + /* GDS switch */ | |
6928 | 4 + /* double SWITCH_BUFFER, | |
6929 | * the first COND_EXEC jump to the place just | |
6930 | * prior to this double SWITCH_BUFFER | |
6931 | */ | |
6932 | 5 + /* COND_EXEC */ | |
6933 | 7 + /* HDP_flush */ | |
6934 | 4 + /* VGT_flush */ | |
6935 | 14 + /* CE_META */ | |
6936 | 31 + /* DE_META */ | |
6937 | 3 + /* CNTX_CTRL */ | |
6938 | 5 + /* HDP_INVL */ | |
6939 | 8 + 8 + /* FENCE x2 */ | |
6940 | 2 + /* SWITCH_BUFFER */ | |
6941 | 7, /* gfx_v9_0_emit_mem_sync */ | |
6942 | .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ | |
6943 | .emit_ib = gfx_v9_0_ring_emit_ib_gfx, | |
6944 | .emit_fence = gfx_v9_0_ring_emit_fence, | |
6945 | .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, | |
6946 | .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, | |
6947 | .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, | |
6948 | .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, | |
6949 | .test_ring = gfx_v9_0_ring_test_ring, | |
6950 | .test_ib = gfx_v9_0_ring_test_ib, | |
6951 | .insert_nop = amdgpu_sw_ring_insert_nop, | |
6952 | .pad_ib = amdgpu_ring_generic_pad_ib, | |
6953 | .emit_switch_buffer = gfx_v9_ring_emit_sb, | |
6954 | .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, | |
6955 | .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, | |
6956 | .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, | |
6957 | .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, | |
6958 | .emit_wreg = gfx_v9_0_ring_emit_wreg, | |
6959 | .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, | |
6960 | .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, | |
6961 | .soft_recovery = gfx_v9_0_ring_soft_recovery, | |
6962 | .emit_mem_sync = gfx_v9_0_emit_mem_sync, | |
ea791e70 JZ |
6963 | .patch_cntl = gfx_v9_0_ring_patch_cntl, |
6964 | .patch_de = gfx_v9_0_ring_patch_de_meta, | |
6965 | .patch_ce = gfx_v9_0_ring_patch_ce_meta, | |
0c97a19a JZ |
6966 | }; |
6967 | ||
b1023571 KW |
6968 | static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { |
6969 | .type = AMDGPU_RING_TYPE_COMPUTE, | |
6970 | .align_mask = 0xff, | |
6971 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), | |
6972 | .support_64bit_ptrs = true, | |
6973 | .get_rptr = gfx_v9_0_ring_get_rptr_compute, | |
6974 | .get_wptr = gfx_v9_0_ring_get_wptr_compute, | |
6975 | .set_wptr = gfx_v9_0_ring_set_wptr_compute, | |
6976 | .emit_frame_size = | |
6977 | 20 + /* gfx_v9_0_ring_emit_gds_switch */ | |
6978 | 7 + /* gfx_v9_0_ring_emit_hdp_flush */ | |
2ee150cd | 6979 | 5 + /* hdp invalidate */ |
b1023571 | 6980 | 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ |
f732b6b3 CK |
6981 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + |
6982 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + | |
6983 | 2 + /* gfx_v9_0_ring_emit_vm_flush */ | |
d35745bb | 6984 | 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ |
0a52a6ca | 6985 | 7 + /* gfx_v9_0_emit_mem_sync */ |
f8bf6450 ND |
6986 | 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ |
6987 | 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ | |
41cca166 | 6988 | .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ |
b1023571 KW |
6989 | .emit_ib = gfx_v9_0_ring_emit_ib_compute, |
6990 | .emit_fence = gfx_v9_0_ring_emit_fence, | |
6991 | .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, | |
6992 | .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, | |
6993 | .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, | |
6994 | .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, | |
b1023571 KW |
6995 | .test_ring = gfx_v9_0_ring_test_ring, |
6996 | .test_ib = gfx_v9_0_ring_test_ib, | |
6997 | .insert_nop = amdgpu_ring_insert_nop, | |
6998 | .pad_ib = amdgpu_ring_generic_pad_ib, | |
254e825b | 6999 | .emit_wreg = gfx_v9_0_ring_emit_wreg, |
230fcc34 | 7000 | .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, |
10ed3c31 | 7001 | .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, |
d35745bb | 7002 | .emit_mem_sync = gfx_v9_0_emit_mem_sync, |
0a52a6ca | 7003 | .emit_wave_limit = gfx_v9_0_emit_wave_limit, |
b1023571 KW |
7004 | }; |
7005 | ||
aa6faa44 XY |
7006 | static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { |
7007 | .type = AMDGPU_RING_TYPE_KIQ, | |
7008 | .align_mask = 0xff, | |
7009 | .nop = PACKET3(PACKET3_NOP, 0x3FFF), | |
7010 | .support_64bit_ptrs = true, | |
7011 | .get_rptr = gfx_v9_0_ring_get_rptr_compute, | |
7012 | .get_wptr = gfx_v9_0_ring_get_wptr_compute, | |
7013 | .set_wptr = gfx_v9_0_ring_set_wptr_compute, | |
7014 | .emit_frame_size = | |
7015 | 20 + /* gfx_v9_0_ring_emit_gds_switch */ | |
7016 | 7 + /* gfx_v9_0_ring_emit_hdp_flush */ | |
2ee150cd | 7017 | 5 + /* hdp invalidate */ |
aa6faa44 | 7018 | 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ |
f732b6b3 CK |
7019 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + |
7020 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + | |
7021 | 2 + /* gfx_v9_0_ring_emit_vm_flush */ | |
aa6faa44 | 7022 | 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ |
41cca166 | 7023 | .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ |
aa6faa44 | 7024 | .emit_fence = gfx_v9_0_ring_emit_fence_kiq, |
aa6faa44 | 7025 | .test_ring = gfx_v9_0_ring_test_ring, |
aa6faa44 XY |
7026 | .insert_nop = amdgpu_ring_insert_nop, |
7027 | .pad_ib = amdgpu_ring_generic_pad_ib, | |
7028 | .emit_rreg = gfx_v9_0_ring_emit_rreg, | |
7029 | .emit_wreg = gfx_v9_0_ring_emit_wreg, | |
230fcc34 | 7030 | .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, |
10ed3c31 | 7031 | .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, |
aa6faa44 | 7032 | }; |
b1023571 KW |
7033 | |
7034 | static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) | |
7035 | { | |
7036 | int i; | |
7037 | ||
277bd337 | 7038 | adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq; |
aa6faa44 | 7039 | |
b1023571 KW |
7040 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
7041 | adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; | |
7042 | ||
0c97a19a JZ |
7043 | if (adev->gfx.num_gfx_rings) { |
7044 | for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) | |
7045 | adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; | |
7046 | } | |
7047 | ||
b1023571 KW |
7048 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
7049 | adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; | |
7050 | } | |
7051 | ||
7052 | static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { | |
7053 | .set = gfx_v9_0_set_eop_interrupt_state, | |
7054 | .process = gfx_v9_0_eop_irq, | |
7055 | }; | |
7056 | ||
7057 | static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { | |
7058 | .set = gfx_v9_0_set_priv_reg_fault_state, | |
7059 | .process = gfx_v9_0_priv_reg_irq, | |
7060 | }; | |
7061 | ||
7062 | static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { | |
7063 | .set = gfx_v9_0_set_priv_inst_fault_state, | |
7064 | .process = gfx_v9_0_priv_inst_irq, | |
7065 | }; | |
7066 | ||
760a1d55 FX |
7067 | static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { |
7068 | .set = gfx_v9_0_set_cp_ecc_error_state, | |
725253ab | 7069 | .process = amdgpu_gfx_cp_ecc_error_irq, |
760a1d55 FX |
7070 | }; |
7071 | ||
7072 | ||
b1023571 KW |
7073 | static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) |
7074 | { | |
7075 | adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; | |
7076 | adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; | |
7077 | ||
7078 | adev->gfx.priv_reg_irq.num_types = 1; | |
7079 | adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; | |
7080 | ||
7081 | adev->gfx.priv_inst_irq.num_types = 1; | |
7082 | adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; | |
760a1d55 FX |
7083 | |
7084 | adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ | |
7085 | adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; | |
b1023571 KW |
7086 | } |
7087 | ||
7088 | static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) | |
7089 | { | |
1d789535 | 7090 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
7091 | case IP_VERSION(9, 0, 1): |
7092 | case IP_VERSION(9, 2, 1): | |
7093 | case IP_VERSION(9, 4, 0): | |
7094 | case IP_VERSION(9, 2, 2): | |
7095 | case IP_VERSION(9, 1, 0): | |
7096 | case IP_VERSION(9, 4, 1): | |
7097 | case IP_VERSION(9, 3, 0): | |
7098 | case IP_VERSION(9, 4, 2): | |
b1023571 KW |
7099 | adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; |
7100 | break; | |
7101 | default: | |
7102 | break; | |
7103 | } | |
7104 | } | |
7105 | ||
7106 | static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) | |
7107 | { | |
7108 | /* init asci gds info */ | |
1d789535 | 7109 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
7110 | case IP_VERSION(9, 0, 1): |
7111 | case IP_VERSION(9, 2, 1): | |
7112 | case IP_VERSION(9, 4, 0): | |
dca29491 | 7113 | adev->gds.gds_size = 0x10000; |
8bda1013 | 7114 | break; |
9d0cb2c3 AD |
7115 | case IP_VERSION(9, 2, 2): |
7116 | case IP_VERSION(9, 1, 0): | |
7117 | case IP_VERSION(9, 4, 1): | |
dca29491 | 7118 | adev->gds.gds_size = 0x1000; |
8bda1013 | 7119 | break; |
9d0cb2c3 | 7120 | case IP_VERSION(9, 4, 2): |
18c3d45a HZ |
7121 | /* aldebaran removed all the GDS internal memory, |
7122 | * only support GWS opcode in kernel, like barrier | |
7123 | * semaphore.etc */ | |
7124 | adev->gds.gds_size = 0; | |
7125 | break; | |
8bda1013 | 7126 | default: |
dca29491 | 7127 | adev->gds.gds_size = 0x10000; |
8bda1013 ED |
7128 | break; |
7129 | } | |
7130 | ||
1d789535 | 7131 | switch (adev->ip_versions[GC_HWIP][0]) { |
9d0cb2c3 AD |
7132 | case IP_VERSION(9, 0, 1): |
7133 | case IP_VERSION(9, 4, 0): | |
41cca166 MO |
7134 | adev->gds.gds_compute_max_wave_id = 0x7ff; |
7135 | break; | |
9d0cb2c3 | 7136 | case IP_VERSION(9, 2, 1): |
41cca166 MO |
7137 | adev->gds.gds_compute_max_wave_id = 0x27f; |
7138 | break; | |
9d0cb2c3 AD |
7139 | case IP_VERSION(9, 2, 2): |
7140 | case IP_VERSION(9, 1, 0): | |
54f78a76 | 7141 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
41cca166 MO |
7142 | adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ |
7143 | else | |
7144 | adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ | |
7145 | break; | |
9d0cb2c3 | 7146 | case IP_VERSION(9, 4, 1): |
22f5ea4c HZ |
7147 | adev->gds.gds_compute_max_wave_id = 0xfff; |
7148 | break; | |
9d0cb2c3 | 7149 | case IP_VERSION(9, 4, 2): |
18c3d45a HZ |
7150 | /* deprecated for Aldebaran, no usage at all */ |
7151 | adev->gds.gds_compute_max_wave_id = 0; | |
7152 | break; | |
41cca166 MO |
7153 | default: |
7154 | /* this really depends on the chip */ | |
7155 | adev->gds.gds_compute_max_wave_id = 0x7ff; | |
7156 | break; | |
7157 | } | |
7158 | ||
dca29491 CK |
7159 | adev->gds.gws_size = 64; |
7160 | adev->gds.oa_size = 16; | |
b1023571 KW |
7161 | } |
7162 | ||
c94d38f0 NH |
7163 | static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, |
7164 | u32 bitmap) | |
7165 | { | |
7166 | u32 data; | |
7167 | ||
7168 | if (!bitmap) | |
7169 | return; | |
7170 | ||
7171 | data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; | |
7172 | data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; | |
7173 | ||
7174 | WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); | |
7175 | } | |
7176 | ||
b1023571 KW |
7177 | static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) |
7178 | { | |
7179 | u32 data, mask; | |
7180 | ||
5e78835a TSD |
7181 | data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); |
7182 | data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); | |
b1023571 KW |
7183 | |
7184 | data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; | |
7185 | data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; | |
7186 | ||
378506a7 | 7187 | mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); |
b1023571 KW |
7188 | |
7189 | return (~data) & mask; | |
7190 | } | |
7191 | ||
7192 | static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, | |
7193 | struct amdgpu_cu_info *cu_info) | |
7194 | { | |
7195 | int i, j, k, counter, active_cu_number = 0; | |
7196 | u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; | |
857b82d0 | 7197 | unsigned disable_masks[4 * 4]; |
b1023571 KW |
7198 | |
7199 | if (!adev || !cu_info) | |
7200 | return -EINVAL; | |
7201 | ||
857b82d0 LM |
7202 | /* |
7203 | * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs | |
7204 | */ | |
7205 | if (adev->gfx.config.max_shader_engines * | |
7206 | adev->gfx.config.max_sh_per_se > 16) | |
7207 | return -EINVAL; | |
7208 | ||
7209 | amdgpu_gfx_parse_disable_cu(disable_masks, | |
7210 | adev->gfx.config.max_shader_engines, | |
7211 | adev->gfx.config.max_sh_per_se); | |
c94d38f0 | 7212 | |
b1023571 KW |
7213 | mutex_lock(&adev->grbm_idx_mutex); |
7214 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { | |
7215 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { | |
7216 | mask = 1; | |
7217 | ao_bitmap = 0; | |
7218 | counter = 0; | |
d51ac6d0 | 7219 | amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); |
857b82d0 LM |
7220 | gfx_v9_0_set_user_cu_inactive_bitmap( |
7221 | adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); | |
b1023571 | 7222 | bitmap = gfx_v9_0_get_cu_active_bitmap(adev); |
857b82d0 LM |
7223 | |
7224 | /* | |
7225 | * The bitmap(and ao_cu_bitmap) in cu_info structure is | |
7226 | * 4x4 size array, and it's usually suitable for Vega | |
7227 | * ASICs which has 4*2 SE/SH layout. | |
7228 | * But for Arcturus, SE/SH layout is changed to 8*1. | |
7229 | * To mostly reduce the impact, we make it compatible | |
7230 | * with current bitmap array as below: | |
7231 | * SE4,SH0 --> bitmap[0][1] | |
7232 | * SE5,SH0 --> bitmap[1][1] | |
7233 | * SE6,SH0 --> bitmap[2][1] | |
7234 | * SE7,SH0 --> bitmap[3][1] | |
7235 | */ | |
97e3c6a8 | 7236 | cu_info->bitmap[0][i % 4][j + i / 4] = bitmap; |
b1023571 | 7237 | |
fe723cd3 | 7238 | for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { |
b1023571 | 7239 | if (bitmap & mask) { |
fe723cd3 | 7240 | if (counter < adev->gfx.config.max_cu_per_sh) |
b1023571 KW |
7241 | ao_bitmap |= mask; |
7242 | counter ++; | |
7243 | } | |
7244 | mask <<= 1; | |
7245 | } | |
7246 | active_cu_number += counter; | |
dbfe85ea FC |
7247 | if (i < 2 && j < 2) |
7248 | ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); | |
857b82d0 | 7249 | cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; |
b1023571 KW |
7250 | } |
7251 | } | |
d51ac6d0 | 7252 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); |
b1023571 KW |
7253 | mutex_unlock(&adev->grbm_idx_mutex); |
7254 | ||
7255 | cu_info->number = active_cu_number; | |
7256 | cu_info->ao_cu_mask = ao_cu_mask; | |
d5a114a6 | 7257 | cu_info->simd_per_cu = NUM_SIMD_PER_CU; |
b1023571 KW |
7258 | |
7259 | return 0; | |
7260 | } | |
7261 | ||
b1023571 KW |
7262 | const struct amdgpu_ip_block_version gfx_v9_0_ip_block = |
7263 | { | |
7264 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
7265 | .major = 9, | |
7266 | .minor = 0, | |
7267 | .rev = 0, | |
7268 | .funcs = &gfx_v9_0_ip_funcs, | |
7269 | }; |