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drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start()
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v9_0.c
CommitLineData
b1023571
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "soc15.h"
28#include "soc15d.h"
29
30#include "vega10/soc15ip.h"
31#include "vega10/GC/gc_9_0_offset.h"
32#include "vega10/GC/gc_9_0_sh_mask.h"
33#include "vega10/vega10_enum.h"
34#include "vega10/HDP/hdp_4_0_offset.h"
35
36#include "soc15_common.h"
37#include "clearstate_gfx9.h"
38#include "v9_structs.h"
39
40#define GFX9_NUM_GFX_RINGS 1
41#define GFX9_NUM_COMPUTE_RINGS 8
42#define GFX9_NUM_SE 4
43#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
44
45MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
46MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
47MODULE_FIRMWARE("amdgpu/vega10_me.bin");
48MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
49MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
50MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
51
52static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
53{
54 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
55 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
56 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
57 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
58 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
59 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
60 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
61 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
62 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
63 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
64 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
65 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
66 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
67 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
68 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
69 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
70 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
72 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
73 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
74 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
76 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
77 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
78 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
80 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
81 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
82 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
84 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
85 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
86};
87
88static const u32 golden_settings_gc_9_0[] =
89{
90 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
b1023571
KW		 91 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
93 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
94 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
95 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
96 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
97 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
98};
99
100static const u32 golden_settings_gc_9_0_vg10[] =
101{
102 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
103 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
104 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
105 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
106 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
107 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
108 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800,
109 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
110};
111
112#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
113
114static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
115static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
116static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
117static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
118static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
119 struct amdgpu_cu_info *cu_info);
120static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
121static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
122
123static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
124{
125 switch (adev->asic_type) {
126 case CHIP_VEGA10:
127 amdgpu_program_register_sequence(adev,
128 golden_settings_gc_9_0,
129 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
130 amdgpu_program_register_sequence(adev,
131 golden_settings_gc_9_0_vg10,
132 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
133 break;
134 default:
135 break;
136 }
137}
138
139static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
140{
141 adev->gfx.scratch.num_reg = 7;
142 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
143 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
144}
145
146static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
147 bool wc, uint32_t reg, uint32_t val)
148{
149 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
150 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
151 WRITE_DATA_DST_SEL(0) |
152 (wc ? WR_CONFIRM : 0));
153 amdgpu_ring_write(ring, reg);
154 amdgpu_ring_write(ring, 0);
155 amdgpu_ring_write(ring, val);
156}
157
158static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
159 int mem_space, int opt, uint32_t addr0,
160 uint32_t addr1, uint32_t ref, uint32_t mask,
161 uint32_t inv)
162{
163 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
164 amdgpu_ring_write(ring,
165 /* memory (1) or register (0) */
166 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
167 WAIT_REG_MEM_OPERATION(opt) | /* wait */
168 WAIT_REG_MEM_FUNCTION(3) | /* equal */
169 WAIT_REG_MEM_ENGINE(eng_sel)));
170
171 if (mem_space)
172 BUG_ON(addr0 & 0x3); /* Dword align */
173 amdgpu_ring_write(ring, addr0);
174 amdgpu_ring_write(ring, addr1);
175 amdgpu_ring_write(ring, ref);
176 amdgpu_ring_write(ring, mask);
177 amdgpu_ring_write(ring, inv); /* poll interval */
178}
179
180static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
181{
182 struct amdgpu_device *adev = ring->adev;
183 uint32_t scratch;
184 uint32_t tmp = 0;
185 unsigned i;
186 int r;
187
188 r = amdgpu_gfx_scratch_get(adev, &scratch);
189 if (r) {
190 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
191 return r;
192 }
193 WREG32(scratch, 0xCAFEDEAD);
194 r = amdgpu_ring_alloc(ring, 3);
195 if (r) {
196 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
197 ring->idx, r);
198 amdgpu_gfx_scratch_free(adev, scratch);
199 return r;
200 }
201 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
202 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
203 amdgpu_ring_write(ring, 0xDEADBEEF);
204 amdgpu_ring_commit(ring);
205
206 for (i = 0; i < adev->usec_timeout; i++) {
207 tmp = RREG32(scratch);
208 if (tmp == 0xDEADBEEF)
209 break;
210 DRM_UDELAY(1);
211 }
212 if (i < adev->usec_timeout) {
213 DRM_INFO("ring test on %d succeeded in %d usecs\n",
214 ring->idx, i);
215 } else {
216 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
217 ring->idx, scratch, tmp);
218 r = -EINVAL;
219 }
220 amdgpu_gfx_scratch_free(adev, scratch);
221 return r;
222}
223
224static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
225{
226 struct amdgpu_device *adev = ring->adev;
227 struct amdgpu_ib ib;
228 struct dma_fence *f = NULL;
229 uint32_t scratch;
230 uint32_t tmp = 0;
231 long r;
232
233 r = amdgpu_gfx_scratch_get(adev, &scratch);
234 if (r) {
235 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
236 return r;
237 }
238 WREG32(scratch, 0xCAFEDEAD);
239 memset(&ib, 0, sizeof(ib));
240 r = amdgpu_ib_get(adev, NULL, 256, &ib);
241 if (r) {
242 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
243 goto err1;
244 }
245 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
246 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
247 ib.ptr[2] = 0xDEADBEEF;
248 ib.length_dw = 3;
249
250 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
251 if (r)
252 goto err2;
253
254 r = dma_fence_wait_timeout(f, false, timeout);
255 if (r == 0) {
256 DRM_ERROR("amdgpu: IB test timed out.\n");
257 r = -ETIMEDOUT;
258 goto err2;
259 } else if (r < 0) {
260 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
261 goto err2;
262 }
263 tmp = RREG32(scratch);
264 if (tmp == 0xDEADBEEF) {
265 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
266 r = 0;
267 } else {
268 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
269 scratch, tmp);
270 r = -EINVAL;
271 }
272err2:
273 amdgpu_ib_free(adev, &ib, NULL);
274 dma_fence_put(f);
275err1:
276 amdgpu_gfx_scratch_free(adev, scratch);
277 return r;
278}
279
280static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
281{
282 const char *chip_name;
283 char fw_name[30];
284 int err;
285 struct amdgpu_firmware_info *info = NULL;
286 const struct common_firmware_header *header = NULL;
287 const struct gfx_firmware_header_v1_0 *cp_hdr;
288
289 DRM_DEBUG("\n");
290
291 switch (adev->asic_type) {
292 case CHIP_VEGA10:
293 chip_name = "vega10";
294 break;
295 default:
296 BUG();
297 }
298
299 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
300 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
301 if (err)
302 goto out;
303 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
304 if (err)
305 goto out;
306 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
307 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
308 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
309
310 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
311 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
312 if (err)
313 goto out;
314 err = amdgpu_ucode_validate(adev->gfx.me_fw);
315 if (err)
316 goto out;
317 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
318 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
319 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
320
321 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
322 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
323 if (err)
324 goto out;
325 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
326 if (err)
327 goto out;
328 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
329 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
330 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
331
332 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
333 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
334 if (err)
335 goto out;
336 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
337 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
338 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
339 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
340
341 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
342 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
343 if (err)
344 goto out;
345 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
346 if (err)
347 goto out;
348 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
349 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
350 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
351
352
353 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
354 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
355 if (!err) {
356 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
357 if (err)
358 goto out;
359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
360 adev->gfx.mec2_fw->data;
361 adev->gfx.mec2_fw_version =
362 le32_to_cpu(cp_hdr->header.ucode_version);
363 adev->gfx.mec2_feature_version =
364 le32_to_cpu(cp_hdr->ucode_feature_version);
365 } else {
366 err = 0;
367 adev->gfx.mec2_fw = NULL;
368 }
369
370 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
371 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
372 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
373 info->fw = adev->gfx.pfp_fw;
374 header = (const struct common_firmware_header *)info->fw->data;
375 adev->firmware.fw_size +=
376 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
377
378 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
379 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
380 info->fw = adev->gfx.me_fw;
381 header = (const struct common_firmware_header *)info->fw->data;
382 adev->firmware.fw_size +=
383 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
384
385 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
386 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
387 info->fw = adev->gfx.ce_fw;
388 header = (const struct common_firmware_header *)info->fw->data;
389 adev->firmware.fw_size +=
390 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
391
392 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
393 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
394 info->fw = adev->gfx.rlc_fw;
395 header = (const struct common_firmware_header *)info->fw->data;
396 adev->firmware.fw_size +=
397 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
398
399 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
400 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
401 info->fw = adev->gfx.mec_fw;
402 header = (const struct common_firmware_header *)info->fw->data;
403 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
404 adev->firmware.fw_size +=
405 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
406
407 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
408 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
409 info->fw = adev->gfx.mec_fw;
410 adev->firmware.fw_size +=
411 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
412
413 if (adev->gfx.mec2_fw) {
414 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
415 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
416 info->fw = adev->gfx.mec2_fw;
417 header = (const struct common_firmware_header *)info->fw->data;
418 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
419 adev->firmware.fw_size +=
420 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
421 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
422 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
423 info->fw = adev->gfx.mec2_fw;
424 adev->firmware.fw_size +=
425 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
426 }
427
428 }
429
430out:
431 if (err) {
432 dev_err(adev->dev,
433 "gfx9: Failed to load firmware \"%s\"\n",
434 fw_name);
435 release_firmware(adev->gfx.pfp_fw);
436 adev->gfx.pfp_fw = NULL;
437 release_firmware(adev->gfx.me_fw);
438 adev->gfx.me_fw = NULL;
439 release_firmware(adev->gfx.ce_fw);
440 adev->gfx.ce_fw = NULL;
441 release_firmware(adev->gfx.rlc_fw);
442 adev->gfx.rlc_fw = NULL;
443 release_firmware(adev->gfx.mec_fw);
444 adev->gfx.mec_fw = NULL;
445 release_firmware(adev->gfx.mec2_fw);
446 adev->gfx.mec2_fw = NULL;
447 }
448 return err;
449}
450
451static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
452{
453 int r;
454
455 if (adev->gfx.mec.hpd_eop_obj) {
456 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
457 if (unlikely(r != 0))
458 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
459 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
460 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
461
462 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
463 adev->gfx.mec.hpd_eop_obj = NULL;
464 }
465 if (adev->gfx.mec.mec_fw_obj) {
466 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
467 if (unlikely(r != 0))
468 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
469 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
470 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
471
472 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
473 adev->gfx.mec.mec_fw_obj = NULL;
474 }
475}
476
477#define MEC_HPD_SIZE 2048
478
479static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
480{
481 int r;
482 u32 *hpd;
483 const __le32 *fw_data;
484 unsigned fw_size;
485 u32 *fw;
486
487 const struct gfx_firmware_header_v1_0 *mec_hdr;
488
489 /*
490 * we assign only 1 pipe because all other pipes will
491 * be handled by KFD
492 */
493 adev->gfx.mec.num_mec = 1;
494 adev->gfx.mec.num_pipe = 1;
495 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
496
497 if (adev->gfx.mec.hpd_eop_obj == NULL) {
498 r = amdgpu_bo_create(adev,
499 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
500 PAGE_SIZE, true,
501 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
502 &adev->gfx.mec.hpd_eop_obj);
503 if (r) {
504 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
505 return r;
506 }
507 }
508
509 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
510 if (unlikely(r != 0)) {
511 gfx_v9_0_mec_fini(adev);
512 return r;
513 }
514 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
515 &adev->gfx.mec.hpd_eop_gpu_addr);
516 if (r) {
517 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
518 gfx_v9_0_mec_fini(adev);
519 return r;
520 }
521 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
522 if (r) {
523 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
524 gfx_v9_0_mec_fini(adev);
525 return r;
526 }
527
528 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
529
530 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
531 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
532
533 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
534
535 fw_data = (const __le32 *)
536 (adev->gfx.mec_fw->data +
537 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
538 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
539
540 if (adev->gfx.mec.mec_fw_obj == NULL) {
541 r = amdgpu_bo_create(adev,
542 mec_hdr->header.ucode_size_bytes,
543 PAGE_SIZE, true,
544 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
545 &adev->gfx.mec.mec_fw_obj);
546 if (r) {
547 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
548 return r;
549 }
550 }
551
552 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
553 if (unlikely(r != 0)) {
554 gfx_v9_0_mec_fini(adev);
555 return r;
556 }
557 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
558 &adev->gfx.mec.mec_fw_gpu_addr);
559 if (r) {
560 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
561 gfx_v9_0_mec_fini(adev);
562 return r;
563 }
564 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
565 if (r) {
566 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
567 gfx_v9_0_mec_fini(adev);
568 return r;
569 }
570 memcpy(fw, fw_data, fw_size);
571
572 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
573 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
574
575
576 return 0;
577}
578
ac104e99
XY		 579static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
580{
581 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
582
583 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
584}
585
586static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
587{
588 int r;
589 u32 *hpd;
590 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
591
592 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
593 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
594 &kiq->eop_gpu_addr, (void **)&hpd);
595 if (r) {
596 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
597 return r;
598 }
599
600 memset(hpd, 0, MEC_HPD_SIZE);
601
f7618a63
AD		 602 r = amdgpu_bo_reserve(kiq->eop_obj, false);
603 if (unlikely(r != 0))
604 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
ac104e99 605 amdgpu_bo_kunmap(kiq->eop_obj);
f7618a63 606 amdgpu_bo_unreserve(kiq->eop_obj);
ac104e99
XY		 607
608 return 0;
609}
610
611static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
612 struct amdgpu_ring *ring,
613 struct amdgpu_irq_src *irq)
614{
d72f2f46 615 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
ac104e99
XY		 616 int r = 0;
617
618 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
619 if (r)
620 return r;
621
622 ring->adev = NULL;
623 ring->ring_obj = NULL;
624 ring->use_doorbell = true;
625 ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
626 if (adev->gfx.mec2_fw) {
627 ring->me = 2;
628 ring->pipe = 0;
629 } else {
630 ring->me = 1;
631 ring->pipe = 1;
632 }
633
634 irq->data = ring;
635 ring->queue = 0;
d72f2f46 636 ring->eop_gpu_addr = kiq->eop_gpu_addr;
ac104e99
XY		 637 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
638 r = amdgpu_ring_init(adev, ring, 1024,
639 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
640 if (r)
641 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
642
643 return r;
644}
645static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
646 struct amdgpu_irq_src *irq)
647{
648 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
649 amdgpu_ring_fini(ring);
650 irq->data = NULL;
651}
652
464826d6 653/* create MQD for each compute queue */
e935c211 654static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
464826d6
XY		 655{
656 struct amdgpu_ring *ring = NULL;
657 int r, i;
658
659 /* create MQD for KIQ */
660 ring = &adev->gfx.kiq.ring;
661 if (!ring->mqd_obj) {
662 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 663 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
664 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 665 if (r) {
666 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
667 return r;
668 }
669
670 /*TODO: prepare MQD backup */
671 }
672
673 /* create MQD for each KCQ */
b4fcf7f0 674 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
464826d6
XY		 675 ring = &adev->gfx.compute_ring[i];
676 if (!ring->mqd_obj) {
677 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
b4fcf7f0
AD		 678 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
679 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
464826d6
XY		 680 if (r) {
681 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
682 return r;
683 }
684
685 /* TODO: prepare MQD backup */
686 }
687 }
688
689 return 0;
690}
691
e935c211 692static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
464826d6
XY		 693{
694 struct amdgpu_ring *ring = NULL;
695 int i;
696
697 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
698 ring = &adev->gfx.compute_ring[i];
699 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
700 }
701
702 ring = &adev->gfx.kiq.ring;
703 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
704}
705
b1023571
KW		 706static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
707{
708 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
709 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
710 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
711 (address << SQ_IND_INDEX__INDEX__SHIFT) |
712 (SQ_IND_INDEX__FORCE_READ_MASK));
713 return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
714}
715
716static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
717 uint32_t wave, uint32_t thread,
718 uint32_t regno, uint32_t num, uint32_t *out)
719{
720 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
721 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
722 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
723 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
724 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
725 (SQ_IND_INDEX__FORCE_READ_MASK) |
726 (SQ_IND_INDEX__AUTO_INCR_MASK));
727 while (num--)
728 *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA));
729}
730
731static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
732{
733 /* type 1 wave data */
734 dst[(*no_fields)++] = 1;
735 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
736 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
737 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
738 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
739 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
740 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
741 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
742 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
743 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
744 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
745 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
746 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
747 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
748 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
749}
750
751static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
752 uint32_t wave, uint32_t start,
753 uint32_t size, uint32_t *dst)
754{
755 wave_read_regs(
756 adev, simd, wave, 0,
757 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
758}
759
760
761static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
762 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
763 .select_se_sh = &gfx_v9_0_select_se_sh,
764 .read_wave_data = &gfx_v9_0_read_wave_data,
765 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
766};
767
768static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
769{
770 u32 gb_addr_config;
771
772 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
773
774 switch (adev->asic_type) {
775 case CHIP_VEGA10:
776 adev->gfx.config.max_shader_engines = 4;
777 adev->gfx.config.max_tile_pipes = 8; //??
778 adev->gfx.config.max_cu_per_sh = 16;
779 adev->gfx.config.max_sh_per_se = 1;
780 adev->gfx.config.max_backends_per_se = 4;
781 adev->gfx.config.max_texture_channel_caches = 16;
782 adev->gfx.config.max_gprs = 256;
783 adev->gfx.config.max_gs_threads = 32;
784 adev->gfx.config.max_hw_contexts = 8;
785
786 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
787 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
788 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
789 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
790 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
791 break;
792 default:
793 BUG();
794 break;
795 }
796
797 adev->gfx.config.gb_addr_config = gb_addr_config;
798
799 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
800 REG_GET_FIELD(
801 adev->gfx.config.gb_addr_config,
802 GB_ADDR_CONFIG,
803 NUM_PIPES);
804 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
805 REG_GET_FIELD(
806 adev->gfx.config.gb_addr_config,
807 GB_ADDR_CONFIG,
808 NUM_BANKS);
809 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
810 REG_GET_FIELD(
811 adev->gfx.config.gb_addr_config,
812 GB_ADDR_CONFIG,
813 MAX_COMPRESSED_FRAGS);
814 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
815 REG_GET_FIELD(
816 adev->gfx.config.gb_addr_config,
817 GB_ADDR_CONFIG,
818 NUM_RB_PER_SE);
819 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
820 REG_GET_FIELD(
821 adev->gfx.config.gb_addr_config,
822 GB_ADDR_CONFIG,
823 NUM_SHADER_ENGINES);
824 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
825 REG_GET_FIELD(
826 adev->gfx.config.gb_addr_config,
827 GB_ADDR_CONFIG,
828 PIPE_INTERLEAVE_SIZE));
829}
830
831static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
832 struct amdgpu_ngg_buf *ngg_buf,
833 int size_se,
834 int default_size_se)
835{
836 int r;
837
838 if (size_se < 0) {
839 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
840 return -EINVAL;
841 }
842 size_se = size_se ? size_se : default_size_se;
843
844 ngg_buf->size = size_se * GFX9_NUM_SE;
845 r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
846 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
847 &ngg_buf->bo,
848 &ngg_buf->gpu_addr,
849 NULL);
850 if (r) {
851 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
852 return r;
853 }
854 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
855
856 return r;
857}
858
859static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
860{
861 int i;
862
863 for (i = 0; i < NGG_BUF_MAX; i++)
864 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
865 &adev->gfx.ngg.buf[i].gpu_addr,
866 NULL);
867
868 memset(&adev->gfx.ngg.buf[0], 0,
869 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
870
871 adev->gfx.ngg.init = false;
872
873 return 0;
874}
875
876static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
877{
878 int r;
879
880 if (!amdgpu_ngg || adev->gfx.ngg.init == true)
881 return 0;
882
883 /* GDS reserve memory: 64 bytes alignment */
884 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
885 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
886 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
887 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
888 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
889
890 /* Primitive Buffer */
891 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
892 amdgpu_prim_buf_per_se,
893 64 * 1024);
894 if (r) {
895 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
896 goto err;
897 }
898
899 /* Position Buffer */
900 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
901 amdgpu_pos_buf_per_se,
902 256 * 1024);
903 if (r) {
904 dev_err(adev->dev, "Failed to create Position Buffer\n");
905 goto err;
906 }
907
908 /* Control Sideband */
909 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
910 amdgpu_cntl_sb_buf_per_se,
911 256);
912 if (r) {
913 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
914 goto err;
915 }
916
917 /* Parameter Cache, not created by default */
918 if (amdgpu_param_buf_per_se <= 0)
919 goto out;
920
921 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
922 amdgpu_param_buf_per_se,
923 512 * 1024);
924 if (r) {
925 dev_err(adev->dev, "Failed to create Parameter Cache\n");
926 goto err;
927 }
928
929out:
930 adev->gfx.ngg.init = true;
931 return 0;
932err:
933 gfx_v9_0_ngg_fini(adev);
934 return r;
935}
936
937static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
938{
939 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
940 int r;
941 u32 data;
942 u32 size;
943 u32 base;
944
945 if (!amdgpu_ngg)
946 return 0;
947
948 /* Program buffer size */
949 data = 0;
950 size = adev->gfx.ngg.buf[PRIM].size / 256;
951 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
952
953 size = adev->gfx.ngg.buf[POS].size / 256;
954 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
955
956 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data);
957
958 data = 0;
959 size = adev->gfx.ngg.buf[CNTL].size / 256;
960 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
961
962 size = adev->gfx.ngg.buf[PARAM].size / 1024;
963 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
964
965 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data);
966
967 /* Program buffer base address */
968 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
969 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
970 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data);
971
972 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
973 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
974 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data);
975
976 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
977 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
978 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data);
979
980 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
981 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
982 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data);
983
984 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
985 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
986 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data);
987
988 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
989 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
990 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data);
991
992 /* Clear GDS reserved memory */
993 r = amdgpu_ring_alloc(ring, 17);
994 if (r) {
995 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
996 ring->idx, r);
997 return r;
998 }
999
1000 gfx_v9_0_write_data_to_reg(ring, 0, false,
1001 amdgpu_gds_reg_offset[0].mem_size,
1002 (adev->gds.mem.total_size +
1003 adev->gfx.ngg.gds_reserve_size) >>
1004 AMDGPU_GDS_SHIFT);
1005
1006 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1007 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1008 PACKET3_DMA_DATA_SRC_SEL(2)));
1009 amdgpu_ring_write(ring, 0);
1010 amdgpu_ring_write(ring, 0);
1011 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1012 amdgpu_ring_write(ring, 0);
1013 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1014
1015
1016 gfx_v9_0_write_data_to_reg(ring, 0, false,
1017 amdgpu_gds_reg_offset[0].mem_size, 0);
1018
1019 amdgpu_ring_commit(ring);
1020
1021 return 0;
1022}
1023
1024static int gfx_v9_0_sw_init(void *handle)
1025{
1026 int i, r;
1027 struct amdgpu_ring *ring;
ac104e99 1028 struct amdgpu_kiq *kiq;
b1023571
KW		 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1030
97031e25
XY		 1031 /* KIQ event */
1032 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1033 if (r)
1034 return r;
1035
b1023571
KW		 1036 /* EOP Event */
1037 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1038 if (r)
1039 return r;
1040
1041 /* Privileged reg */
1042 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1043 &adev->gfx.priv_reg_irq);
1044 if (r)
1045 return r;
1046
1047 /* Privileged inst */
1048 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1049 &adev->gfx.priv_inst_irq);
1050 if (r)
1051 return r;
1052
1053 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1054
1055 gfx_v9_0_scratch_init(adev);
1056
1057 r = gfx_v9_0_init_microcode(adev);
1058 if (r) {
1059 DRM_ERROR("Failed to load gfx firmware!\n");
1060 return r;
1061 }
1062
1063 r = gfx_v9_0_mec_init(adev);
1064 if (r) {
1065 DRM_ERROR("Failed to init MEC BOs!\n");
1066 return r;
1067 }
1068
1069 /* set up the gfx ring */
1070 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1071 ring = &adev->gfx.gfx_ring[i];
1072 ring->ring_obj = NULL;
1073 sprintf(ring->name, "gfx");
1074 ring->use_doorbell = true;
1075 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1076 r = amdgpu_ring_init(adev, ring, 1024,
1077 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1078 if (r)
1079 return r;
1080 }
1081
1082 /* set up the compute queues */
1083 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1084 unsigned irq_type;
1085
1086 /* max 32 queues per MEC */
1087 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1088 DRM_ERROR("Too many (%d) compute rings!\n", i);
1089 break;
1090 }
1091 ring = &adev->gfx.compute_ring[i];
1092 ring->ring_obj = NULL;
1093 ring->use_doorbell = true;
1094 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1;
1095 ring->me = 1; /* first MEC */
1096 ring->pipe = i / 8;
1097 ring->queue = i % 8;
d72f2f46 1098 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
b1023571
KW		 1099 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1100 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1101 /* type-2 packets are deprecated on MEC, use type-3 instead */
1102 r = amdgpu_ring_init(adev, ring, 1024,
1103 &adev->gfx.eop_irq, irq_type);
1104 if (r)
1105 return r;
1106 }
1107
ac104e99
XY		 1108 if (amdgpu_sriov_vf(adev)) {
1109 r = gfx_v9_0_kiq_init(adev);
1110 if (r) {
1111 DRM_ERROR("Failed to init KIQ BOs!\n");
1112 return r;
1113 }
1114
1115 kiq = &adev->gfx.kiq;
1116 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1117 if (r)
1118 return r;
464826d6
XY		 1119
1120 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
e935c211 1121 r = gfx_v9_0_compute_mqd_sw_init(adev);
464826d6
XY		 1122 if (r)
1123 return r;
ac104e99
XY		 1124 }
1125
b1023571
KW		 1126 /* reserve GDS, GWS and OA resource for gfx */
1127 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1128 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1129 &adev->gds.gds_gfx_bo, NULL, NULL);
1130 if (r)
1131 return r;
1132
1133 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1135 &adev->gds.gws_gfx_bo, NULL, NULL);
1136 if (r)
1137 return r;
1138
1139 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1140 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1141 &adev->gds.oa_gfx_bo, NULL, NULL);
1142 if (r)
1143 return r;
1144
1145 adev->gfx.ce_ram_size = 0x8000;
1146
1147 gfx_v9_0_gpu_early_init(adev);
1148
1149 r = gfx_v9_0_ngg_init(adev);
1150 if (r)
1151 return r;
1152
1153 return 0;
1154}
1155
1156
1157static int gfx_v9_0_sw_fini(void *handle)
1158{
1159 int i;
1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1161
1162 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1163 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1164 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1165
1166 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1167 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1168 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1169 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1170
ac104e99 1171 if (amdgpu_sriov_vf(adev)) {
e935c211 1172 gfx_v9_0_compute_mqd_sw_fini(adev);
ac104e99
XY		 1173 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1174 gfx_v9_0_kiq_fini(adev);
1175 }
1176
b1023571
KW		 1177 gfx_v9_0_mec_fini(adev);
1178 gfx_v9_0_ngg_fini(adev);
1179
1180 return 0;
1181}
1182
1183
1184static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1185{
1186 /* TODO */
1187}
1188
1189static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1190{
1191 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1192
1193 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1194 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1195 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1196 } else if (se_num == 0xffffffff) {
1197 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1198 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1199 } else if (sh_num == 0xffffffff) {
1200 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1201 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1202 } else {
1203 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1204 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1205 }
1206 WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
1207}
1208
1209static u32 gfx_v9_0_create_bitmask(u32 bit_width)
1210{
1211 return (u32)((1ULL << bit_width) - 1);
1212}
1213
1214static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1215{
1216 u32 data, mask;
1217
1218 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE));
1219 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE));
1220
1221 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1222 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1223
1224 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1225 adev->gfx.config.max_sh_per_se);
1226
1227 return (~data) & mask;
1228}
1229
1230static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1231{
1232 int i, j;
2572c24c 1233 u32 data;
b1023571
KW		 1234 u32 active_rbs = 0;
1235 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1236 adev->gfx.config.max_sh_per_se;
1237
1238 mutex_lock(&adev->grbm_idx_mutex);
1239 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1240 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1241 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1242 data = gfx_v9_0_get_rb_active_bitmap(adev);
1243 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1244 rb_bitmap_width_per_sh);
1245 }
1246 }
1247 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1248 mutex_unlock(&adev->grbm_idx_mutex);
1249
1250 adev->gfx.config.backend_enable_mask = active_rbs;
2572c24c 1251 adev->gfx.config.num_rbs = hweight32(active_rbs);
b1023571
KW		 1252}
1253
1254#define DEFAULT_SH_MEM_BASES (0x6000)
1255#define FIRST_COMPUTE_VMID (8)
1256#define LAST_COMPUTE_VMID (16)
1257static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1258{
1259 int i;
1260 uint32_t sh_mem_config;
1261 uint32_t sh_mem_bases;
1262
1263 /*
1264 * Configure apertures:
1265 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1266 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1267 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1268 */
1269 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1270
1271 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1272 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1273 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1274
1275 mutex_lock(&adev->srbm_mutex);
1276 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1277 soc15_grbm_select(adev, 0, 0, 0, i);
1278 /* CP and shaders */
1279 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
1280 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
1281 }
1282 soc15_grbm_select(adev, 0, 0, 0, 0);
1283 mutex_unlock(&adev->srbm_mutex);
1284}
1285
1286static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1287{
1288 u32 tmp;
1289 int i;
1290
1291 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
1292 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
1293 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
1294
1295 gfx_v9_0_tiling_mode_table_init(adev);
1296
1297 gfx_v9_0_setup_rb(adev);
1298 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1299
1300 /* XXX SH_MEM regs */
1301 /* where to put LDS, scratch, GPUVM in FSA64 space */
1302 mutex_lock(&adev->srbm_mutex);
1303 for (i = 0; i < 16; i++) {
1304 soc15_grbm_select(adev, 0, 0, 0, i);
1305 /* CP and shaders */
1306 tmp = 0;
1307 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1308 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1309 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp);
1310 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0);
1311 }
1312 soc15_grbm_select(adev, 0, 0, 0, 0);
1313
1314 mutex_unlock(&adev->srbm_mutex);
1315
1316 gfx_v9_0_init_compute_vmid(adev);
1317
1318 mutex_lock(&adev->grbm_idx_mutex);
1319 /*
1320 * making sure that the following register writes will be broadcasted
1321 * to all the shaders
1322 */
1323 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1324
1325 WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE),
1326 (adev->gfx.config.sc_prim_fifo_size_frontend <<
1327 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1328 (adev->gfx.config.sc_prim_fifo_size_backend <<
1329 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1330 (adev->gfx.config.sc_hiz_tile_fifo_size <<
1331 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1332 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1333 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1334 mutex_unlock(&adev->grbm_idx_mutex);
1335
1336}
1337
1338static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1339{
1340 u32 i, j, k;
1341 u32 mask;
1342
1343 mutex_lock(&adev->grbm_idx_mutex);
1344 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1345 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1346 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1347 for (k = 0; k < adev->usec_timeout; k++) {
1348 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0)
1349 break;
1350 udelay(1);
1351 }
1352 }
1353 }
1354 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1355 mutex_unlock(&adev->grbm_idx_mutex);
1356
1357 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1358 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1359 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1360 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1361 for (k = 0; k < adev->usec_timeout; k++) {
1362 if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0)
1363 break;
1364 udelay(1);
1365 }
1366}
1367
1368static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1369 bool enable)
1370{
1371 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0));
1372
1373 if (enable)
1374 return;
1375
1376 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1377 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1378 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1379 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1380
1381 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp);
1382}
1383
1384void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
1385{
1386 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
1387
1388 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1389 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp);
1390
1391 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
1392
1393 gfx_v9_0_wait_for_rlc_serdes(adev);
1394}
1395
1396static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
1397{
1398 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
1399
1400 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1401 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1402 udelay(50);
1403 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1404 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
1405 udelay(50);
1406}
1407
1408static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
1409{
1410#ifdef AMDGPU_RLC_DEBUG_RETRY
1411 u32 rlc_ucode_ver;
1412#endif
b1023571 1413
342cda25 1414 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
b1023571
KW		 1415
1416 /* carrizo do enable cp interrupt after cp inited */
1417 if (!(adev->flags & AMD_IS_APU))
1418 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
1419
1420 udelay(50);
1421
1422#ifdef AMDGPU_RLC_DEBUG_RETRY
1423 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1424 rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6));
1425 if(rlc_ucode_ver == 0x108) {
1426 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1427 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1428 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1429 * default is 0x9C4 to create a 100us interval */
1430 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4);
1431 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1432 * to disable the page fault retry interrupts, default is
1433 * 0x100 (256) */
1434 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100);
1435 }
1436#endif
1437}
1438
1439static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
1440{
1441 const struct rlc_firmware_header_v2_0 *hdr;
1442 const __le32 *fw_data;
1443 unsigned i, fw_size;
1444
1445 if (!adev->gfx.rlc_fw)
1446 return -EINVAL;
1447
1448 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1449 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1450
1451 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1452 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1453 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1454
1455 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR),
1456 RLCG_UCODE_LOADING_START_ADDRESS);
1457 for (i = 0; i < fw_size; i++)
1458 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++));
1459 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version);
1460
1461 return 0;
1462}
1463
1464static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
1465{
1466 int r;
1467
cfee05bc
ML		 1468 if (amdgpu_sriov_vf(adev))
1469 return 0;
1470
b1023571
KW		 1471 gfx_v9_0_rlc_stop(adev);
1472
1473 /* disable CG */
1474 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0);
1475
1476 /* disable PG */
1477 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0);
1478
1479 gfx_v9_0_rlc_reset(adev);
1480
1481 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1482 /* legacy rlc firmware loading */
1483 r = gfx_v9_0_rlc_load_microcode(adev);
1484 if (r)
1485 return r;
1486 }
1487
1488 gfx_v9_0_rlc_start(adev);
1489
1490 return 0;
1491}
1492
1493static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1494{
1495 int i;
1496 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL));
1497
ea64468e
TSD		 1498 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
1499 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
1500 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
1501 if (!enable) {
b1023571
KW		 1502 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1503 adev->gfx.gfx_ring[i].ready = false;
1504 }
1505 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp);
1506 udelay(50);
1507}
1508
1509static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1510{
1511 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1512 const struct gfx_firmware_header_v1_0 *ce_hdr;
1513 const struct gfx_firmware_header_v1_0 *me_hdr;
1514 const __le32 *fw_data;
1515 unsigned i, fw_size;
1516
1517 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1518 return -EINVAL;
1519
1520 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
1521 adev->gfx.pfp_fw->data;
1522 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
1523 adev->gfx.ce_fw->data;
1524 me_hdr = (const struct gfx_firmware_header_v1_0 *)
1525 adev->gfx.me_fw->data;
1526
1527 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1528 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1529 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1530
1531 gfx_v9_0_cp_gfx_enable(adev, false);
1532
1533 /* PFP */
1534 fw_data = (const __le32 *)
1535 (adev->gfx.pfp_fw->data +
1536 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1537 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1538 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0);
1539 for (i = 0; i < fw_size; i++)
1540 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++));
1541 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version);
1542
1543 /* CE */
1544 fw_data = (const __le32 *)
1545 (adev->gfx.ce_fw->data +
1546 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1547 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1548 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0);
1549 for (i = 0; i < fw_size; i++)
1550 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++));
1551 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version);
1552
1553 /* ME */
1554 fw_data = (const __le32 *)
1555 (adev->gfx.me_fw->data +
1556 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1557 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1558 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0);
1559 for (i = 0; i < fw_size; i++)
1560 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++));
1561 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version);
1562
1563 return 0;
1564}
1565
1566static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1567{
1568 u32 count = 0;
1569 const struct cs_section_def *sect = NULL;
1570 const struct cs_extent_def *ext = NULL;
1571
1572 /* begin clear state */
1573 count += 2;
1574 /* context control state */
1575 count += 3;
1576
1577 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1578 for (ext = sect->section; ext->extent != NULL; ++ext) {
1579 if (sect->id == SECT_CONTEXT)
1580 count += 2 + ext->reg_count;
1581 else
1582 return 0;
1583 }
1584 }
1585 /* pa_sc_raster_config/pa_sc_raster_config1 */
1586 count += 4;
1587 /* end clear state */
1588 count += 2;
1589 /* clear state */
1590 count += 2;
1591
1592 return count;
1593}
1594
1595static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
1596{
1597 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1598 const struct cs_section_def *sect = NULL;
1599 const struct cs_extent_def *ext = NULL;
1600 int r, i;
1601
1602 /* init the CP */
1603 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1);
1604 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1);
1605
1606 gfx_v9_0_cp_gfx_enable(adev, true);
1607
1608 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
1609 if (r) {
1610 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1611 return r;
1612 }
1613
1614 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1615 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1616
1617 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1618 amdgpu_ring_write(ring, 0x80000000);
1619 amdgpu_ring_write(ring, 0x80000000);
1620
1621 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1622 for (ext = sect->section; ext->extent != NULL; ++ext) {
1623 if (sect->id == SECT_CONTEXT) {
1624 amdgpu_ring_write(ring,
1625 PACKET3(PACKET3_SET_CONTEXT_REG,
1626 ext->reg_count));
1627 amdgpu_ring_write(ring,
1628 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
1629 for (i = 0; i < ext->reg_count; i++)
1630 amdgpu_ring_write(ring, ext->extent[i]);
1631 }
1632 }
1633 }
1634
1635 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1636 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1637
1638 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1639 amdgpu_ring_write(ring, 0);
1640
1641 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1642 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1643 amdgpu_ring_write(ring, 0x8000);
1644 amdgpu_ring_write(ring, 0x8000);
1645
1646 amdgpu_ring_commit(ring);
1647
1648 return 0;
1649}
1650
1651static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
1652{
1653 struct amdgpu_ring *ring;
1654 u32 tmp;
1655 u32 rb_bufsz;
3fc08b61 1656 u64 rb_addr, rptr_addr, wptr_gpu_addr;
b1023571
KW		 1657
1658 /* Set the write pointer delay */
1659 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
1660
1661 /* set the RB to use vmid 0 */
1662 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0);
1663
1664 /* Set ring buffer size */
1665 ring = &adev->gfx.gfx_ring[0];
1666 rb_bufsz = order_base_2(ring->ring_size / 8);
1667 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
1668 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
1669#ifdef __BIG_ENDIAN
1670 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
1671#endif
1672 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1673
1674 /* Initialize the ring buffer's write pointers */
1675 ring->wptr = 0;
1676 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
1677 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
1678
1679 /* set the wb address wether it's enabled or not */
1680 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1681 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr));
1682 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
1683
3fc08b61
ML		 1684 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1685 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr));
1686 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr));
1687
b1023571
KW		 1688 mdelay(1);
1689 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
1690
1691 rb_addr = ring->gpu_addr >> 8;
1692 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr);
1693 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr));
1694
1695 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL));
1696 if (ring->use_doorbell) {
1697 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1698 DOORBELL_OFFSET, ring->doorbell_index);
1699 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
1700 DOORBELL_EN, 1);
1701 } else {
1702 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
1703 }
1704 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp);
1705
1706 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
1707 DOORBELL_RANGE_LOWER, ring->doorbell_index);
1708 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp);
1709
1710 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER),
1711 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
1712
1713
1714 /* start the ring */
1715 gfx_v9_0_cp_gfx_start(adev);
1716 ring->ready = true;
1717
1718 return 0;
1719}
1720
1721static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
1722{
1723 int i;
1724
1725 if (enable) {
1726 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0);
1727 } else {
1728 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL),
1729 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1730 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1731 adev->gfx.compute_ring[i].ready = false;
ac104e99 1732 adev->gfx.kiq.ring.ready = false;
b1023571
KW		 1733 }
1734 udelay(50);
1735}
1736
1737static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
1738{
1739 gfx_v9_0_cp_compute_enable(adev, true);
1740
1741 return 0;
1742}
1743
1744static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
1745{
1746 const struct gfx_firmware_header_v1_0 *mec_hdr;
1747 const __le32 *fw_data;
1748 unsigned i;
1749 u32 tmp;
1750
1751 if (!adev->gfx.mec_fw)
1752 return -EINVAL;
1753
1754 gfx_v9_0_cp_compute_enable(adev, false);
1755
1756 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1757 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1758
1759 fw_data = (const __le32 *)
1760 (adev->gfx.mec_fw->data +
1761 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1762 tmp = 0;
1763 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1764 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1765 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp);
1766
1767 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO),
1768 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1769 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI),
1770 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1771
1772 /* MEC1 */
1773 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1774 mec_hdr->jt_offset);
1775 for (i = 0; i < mec_hdr->jt_size; i++)
1776 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA),
1777 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1778
1779 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR),
1780 adev->gfx.mec_fw_version);
1781 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1782
1783 return 0;
1784}
1785
1786static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
1787{
1788 int i, r;
1789
1790 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1791 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1792
1793 if (ring->mqd_obj) {
1794 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1795 if (unlikely(r != 0))
1796 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
1797
1798 amdgpu_bo_unpin(ring->mqd_obj);
1799 amdgpu_bo_unreserve(ring->mqd_obj);
1800
1801 amdgpu_bo_unref(&ring->mqd_obj);
1802 ring->mqd_obj = NULL;
1803 }
1804 }
1805}
1806
1807static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
1808
1809static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
1810{
1811 int i, r;
1812 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1813 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
1814 if (gfx_v9_0_init_queue(ring))
1815 dev_warn(adev->dev, "compute queue %d init failed!\n", i);
1816 }
1817
1818 r = gfx_v9_0_cp_compute_start(adev);
1819 if (r)
1820 return r;
1821
1822 return 0;
1823}
1824
464826d6
XY		 1825/* KIQ functions */
1826static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
1827{
1828 uint32_t tmp;
1829 struct amdgpu_device *adev = ring->adev;
1830
1831 /* tell RLC which is KIQ queue */
1832 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
1833 tmp &= 0xffffff00;
1834 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1835 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp);
1836 tmp |= 0x80;
1837 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp);
1838}
1839
1840static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
1841{
1842 amdgpu_ring_alloc(ring, 8);
1843 /* set resources */
1844 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
1845 amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
1846 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */
1847 amdgpu_ring_write(ring, 0); /* queue mask hi */
1848 amdgpu_ring_write(ring, 0); /* gws mask lo */
1849 amdgpu_ring_write(ring, 0); /* gws mask hi */
1850 amdgpu_ring_write(ring, 0); /* oac mask */
1851 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
1852 amdgpu_ring_commit(ring);
1853 udelay(50);
1854}
1855
1856static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
1857 struct amdgpu_ring *ring)
1858{
1859 struct amdgpu_device *adev = kiq_ring->adev;
1860 uint64_t mqd_addr, wptr_addr;
1861
1862 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
1863 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1864 amdgpu_ring_alloc(kiq_ring, 8);
1865
1866 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
1867 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
1868 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
1869 (0 << 4) | /* Queue_Sel */
1870 (0 << 8) | /* VMID */
1871 (ring->queue << 13 ) |
1872 (ring->pipe << 16) |
1873 ((ring->me == 1 ? 0 : 1) << 18) |
1874 (0 << 21) | /*queue_type: normal compute queue */
1875 (1 << 24) | /* alloc format: all_on_one_pipe */
1876 (0 << 26) | /* engine_sel: compute */
1877 (1 << 29)); /* num_queues: must be 1 */
1878 amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2));
1879 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
1880 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
1881 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
1882 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
1883 amdgpu_ring_commit(kiq_ring);
1884 udelay(50);
1885}
1886
e322edc3 1887static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
464826d6 1888{
33fb8698 1889 struct amdgpu_device *adev = ring->adev;
e322edc3 1890 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 1891 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1892 uint32_t tmp;
1893
1894 mqd->header = 0xC0310800;
1895 mqd->compute_pipelinestat_enable = 0x00000001;
1896 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1897 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1898 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1899 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1900 mqd->compute_misc_reserved = 0x00000003;
1901
d72f2f46 1902 eop_base_addr = ring->eop_gpu_addr >> 8;
464826d6
XY		 1903 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1904 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1905
1906 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1907 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
1908 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1909 (order_base_2(MEC_HPD_SIZE / 4) - 1));
1910
1911 mqd->cp_hqd_eop_control = tmp;
1912
1913 /* enable doorbell? */
1914 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
1915
1916 if (ring->use_doorbell) {
1917 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1918 DOORBELL_OFFSET, ring->doorbell_index);
1919 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1920 DOORBELL_EN, 1);
1921 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1922 DOORBELL_SOURCE, 0);
1923 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1924 DOORBELL_HIT, 0);
1925 }
1926 else
1927 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1928 DOORBELL_EN, 0);
1929
1930 mqd->cp_hqd_pq_doorbell_control = tmp;
1931
1932 /* disable the queue if it's active */
1933 ring->wptr = 0;
1934 mqd->cp_hqd_dequeue_request = 0;
1935 mqd->cp_hqd_pq_rptr = 0;
1936 mqd->cp_hqd_pq_wptr_lo = 0;
1937 mqd->cp_hqd_pq_wptr_hi = 0;
1938
1939 /* set the pointer to the MQD */
33fb8698
AD		 1940 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1941 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
464826d6
XY		 1942
1943 /* set MQD vmid to 0 */
1944 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
1945 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1946 mqd->cp_mqd_control = tmp;
1947
1948 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1949 hqd_gpu_addr = ring->gpu_addr >> 8;
1950 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1951 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1952
1953 /* set up the HQD, this is similar to CP_RB0_CNTL */
1954 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
1955 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1956 (order_base_2(ring->ring_size / 4) - 1));
1957 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1958 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1959#ifdef __BIG_ENDIAN
1960 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1961#endif
1962 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1963 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1964 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1965 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1966 mqd->cp_hqd_pq_control = tmp;
1967
1968 /* set the wb address whether it's enabled or not */
1969 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1970 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1971 mqd->cp_hqd_pq_rptr_report_addr_hi =
1972 upper_32_bits(wb_gpu_addr) & 0xffff;
1973
1974 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1975 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1976 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1977 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1978
1979 tmp = 0;
1980 /* enable the doorbell if requested */
1981 if (ring->use_doorbell) {
1982 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
1983 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1984 DOORBELL_OFFSET, ring->doorbell_index);
1985
1986 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1987 DOORBELL_EN, 1);
1988 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1989 DOORBELL_SOURCE, 0);
1990 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1991 DOORBELL_HIT, 0);
1992 }
1993
1994 mqd->cp_hqd_pq_doorbell_control = tmp;
1995
1996 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1997 ring->wptr = 0;
1998 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
1999
2000 /* set the vmid for the queue */
2001 mqd->cp_hqd_vmid = 0;
2002
2003 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
2004 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2005 mqd->cp_hqd_persistent_state = tmp;
2006
2007 /* activate the queue */
2008 mqd->cp_hqd_active = 1;
2009
2010 return 0;
2011}
2012
e322edc3 2013static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
464826d6 2014{
33fb8698 2015 struct amdgpu_device *adev = ring->adev;
e322edc3 2016 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2017 int j;
2018
2019 /* disable wptr polling */
72edadd5 2020 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
464826d6
XY		 2021
2022 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
2023 mqd->cp_hqd_eop_base_addr_lo);
2024 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
2025 mqd->cp_hqd_eop_base_addr_hi);
2026
2027 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2028 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL),
2029 mqd->cp_hqd_eop_control);
2030
2031 /* enable doorbell? */
2032 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
2033 mqd->cp_hqd_pq_doorbell_control);
2034
2035 /* disable the queue if it's active */
2036 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
2037 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
2038 for (j = 0; j < adev->usec_timeout; j++) {
2039 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
2040 break;
2041 udelay(1);
2042 }
2043 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
2044 mqd->cp_hqd_dequeue_request);
2045 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR),
2046 mqd->cp_hqd_pq_rptr);
2047 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
2048 mqd->cp_hqd_pq_wptr_lo);
2049 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
2050 mqd->cp_hqd_pq_wptr_hi);
2051 }
2052
2053 /* set the pointer to the MQD */
2054 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR),
2055 mqd->cp_mqd_base_addr_lo);
2056 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI),
2057 mqd->cp_mqd_base_addr_hi);
2058
2059 /* set MQD vmid to 0 */
2060 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL),
2061 mqd->cp_mqd_control);
2062
2063 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2064 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE),
2065 mqd->cp_hqd_pq_base_lo);
2066 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI),
2067 mqd->cp_hqd_pq_base_hi);
2068
2069 /* set up the HQD, this is similar to CP_RB0_CNTL */
2070 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL),
2071 mqd->cp_hqd_pq_control);
2072
2073 /* set the wb address whether it's enabled or not */
2074 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
2075 mqd->cp_hqd_pq_rptr_report_addr_lo);
2076 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
2077 mqd->cp_hqd_pq_rptr_report_addr_hi);
2078
2079 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2080 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
2081 mqd->cp_hqd_pq_wptr_poll_addr_lo);
2082 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
2083 mqd->cp_hqd_pq_wptr_poll_addr_hi);
2084
2085 /* enable the doorbell if requested */
2086 if (ring->use_doorbell) {
2087 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
2088 (AMDGPU_DOORBELL64_KIQ *2) << 2);
2089 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
2090 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2091 }
2092
2093 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
2094 mqd->cp_hqd_pq_doorbell_control);
2095
2096 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2097 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
2098 mqd->cp_hqd_pq_wptr_lo);
2099 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
2100 mqd->cp_hqd_pq_wptr_hi);
2101
2102 /* set the vmid for the queue */
2103 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
2104
2105 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE),
2106 mqd->cp_hqd_persistent_state);
2107
2108 /* activate the queue */
2109 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE),
2110 mqd->cp_hqd_active);
2111
72edadd5
TSD		 2112 if (ring->use_doorbell)
2113 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
464826d6
XY		 2114
2115 return 0;
2116}
2117
e322edc3 2118static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
464826d6
XY		 2119{
2120 struct amdgpu_device *adev = ring->adev;
2121 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
e322edc3 2122 struct v9_mqd *mqd = ring->mqd_ptr;
464826d6
XY		 2123 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
2124 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2125
2126 if (is_kiq) {
464826d6
XY		 2127 gfx_v9_0_kiq_setting(&kiq->ring);
2128 } else {
464826d6
XY		 2129 mqd_idx = ring - &adev->gfx.compute_ring[0];
2130 }
2131
2132 if (!adev->gfx.in_reset) {
2133 memset((void *)mqd, 0, sizeof(*mqd));
2134 mutex_lock(&adev->srbm_mutex);
2135 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2136 gfx_v9_0_mqd_init(ring);
464826d6 2137 if (is_kiq)
e322edc3 2138 gfx_v9_0_kiq_init_register(ring);
464826d6
XY		 2139 soc15_grbm_select(adev, 0, 0, 0, 0);
2140 mutex_unlock(&adev->srbm_mutex);
2141
2142 } else { /* for GPU_RESET case */
2143 /* reset MQD to a clean status */
2144
2145 /* reset ring buffer */
2146 ring->wptr = 0;
2147
2148 if (is_kiq) {
2149 mutex_lock(&adev->srbm_mutex);
2150 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
e322edc3 2151 gfx_v9_0_kiq_init_register(ring);
464826d6
XY		 2152 soc15_grbm_select(adev, 0, 0, 0, 0);
2153 mutex_unlock(&adev->srbm_mutex);
2154 }
2155 }
2156
2157 if (is_kiq)
2158 gfx_v9_0_kiq_enable(ring);
2159 else
2160 gfx_v9_0_map_queue_enable(&kiq->ring, ring);
2161
2162 return 0;
2163}
2164
2165static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
2166{
2167 struct amdgpu_ring *ring = NULL;
2168 int r = 0, i;
2169
2170 gfx_v9_0_cp_compute_enable(adev, true);
2171
2172 ring = &adev->gfx.kiq.ring;
e1d53aa8
AD		 2173
2174 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2175 if (unlikely(r != 0))
2176 goto done;
2177
2178 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2179 if (!r) {
e322edc3 2180 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2181 amdgpu_bo_kunmap(ring->mqd_obj);
2182 ring->mqd_ptr = NULL;
464826d6 2183 }
e1d53aa8
AD		 2184 amdgpu_bo_unreserve(ring->mqd_obj);
2185 if (r)
2186 goto done;
464826d6
XY		 2187
2188 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2189 ring = &adev->gfx.compute_ring[i];
e1d53aa8
AD		 2190
2191 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2192 if (unlikely(r != 0))
2193 goto done;
2194 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
2195 if (!r) {
e322edc3 2196 r = gfx_v9_0_kiq_init_queue(ring);
464826d6
XY		 2197 amdgpu_bo_kunmap(ring->mqd_obj);
2198 ring->mqd_ptr = NULL;
464826d6 2199 }
e1d53aa8
AD		 2200 amdgpu_bo_unreserve(ring->mqd_obj);
2201 if (r)
2202 goto done;
464826d6
XY		 2203 }
2204
e1d53aa8
AD		 2205done:
2206 return r;
464826d6
XY		 2207}
2208
b1023571
KW		 2209static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
2210{
2211 int r,i;
2212 struct amdgpu_ring *ring;
2213
2214 if (!(adev->flags & AMD_IS_APU))
2215 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2216
2217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2218 /* legacy firmware loading */
2219 r = gfx_v9_0_cp_gfx_load_microcode(adev);
2220 if (r)
2221 return r;
2222
2223 r = gfx_v9_0_cp_compute_load_microcode(adev);
2224 if (r)
2225 return r;
2226 }
2227
2228 r = gfx_v9_0_cp_gfx_resume(adev);
2229 if (r)
2230 return r;
2231
464826d6
XY		 2232 if (amdgpu_sriov_vf(adev))
2233 r = gfx_v9_0_kiq_resume(adev);
2234 else
2235 r = gfx_v9_0_cp_compute_resume(adev);
b1023571
KW		 2236 if (r)
2237 return r;
2238
2239 ring = &adev->gfx.gfx_ring[0];
2240 r = amdgpu_ring_test_ring(ring);
2241 if (r) {
2242 ring->ready = false;
2243 return r;
2244 }
2245 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2246 ring = &adev->gfx.compute_ring[i];
2247
2248 ring->ready = true;
2249 r = amdgpu_ring_test_ring(ring);
2250 if (r)
2251 ring->ready = false;
2252 }
2253
464826d6
XY		 2254 if (amdgpu_sriov_vf(adev)) {
2255 ring = &adev->gfx.kiq.ring;
2256 ring->ready = true;
2257 r = amdgpu_ring_test_ring(ring);
2258 if (r)
2259 ring->ready = false;
2260 }
2261
b1023571
KW		 2262 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2263
2264 return 0;
2265}
2266
2267static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
2268{
2269 gfx_v9_0_cp_gfx_enable(adev, enable);
2270 gfx_v9_0_cp_compute_enable(adev, enable);
2271}
2272
2273static int gfx_v9_0_hw_init(void *handle)
2274{
2275 int r;
2276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2277
2278 gfx_v9_0_init_golden_registers(adev);
2279
2280 gfx_v9_0_gpu_init(adev);
2281
2282 r = gfx_v9_0_rlc_resume(adev);
2283 if (r)
2284 return r;
2285
2286 r = gfx_v9_0_cp_resume(adev);
2287 if (r)
2288 return r;
2289
2290 r = gfx_v9_0_ngg_en(adev);
2291 if (r)
2292 return r;
2293
2294 return r;
2295}
2296
2297static int gfx_v9_0_hw_fini(void *handle)
2298{
2299 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2300
2301 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2302 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
464826d6
XY		 2303 if (amdgpu_sriov_vf(adev)) {
2304 pr_debug("For SRIOV client, shouldn't do anything.\n");
2305 return 0;
2306 }
b1023571
KW		 2307 gfx_v9_0_cp_enable(adev, false);
2308 gfx_v9_0_rlc_stop(adev);
2309 gfx_v9_0_cp_compute_fini(adev);
2310
2311 return 0;
2312}
2313
2314static int gfx_v9_0_suspend(void *handle)
2315{
2316 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2317
2318 return gfx_v9_0_hw_fini(adev);
2319}
2320
2321static int gfx_v9_0_resume(void *handle)
2322{
2323 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2324
2325 return gfx_v9_0_hw_init(adev);
2326}
2327
2328static bool gfx_v9_0_is_idle(void *handle)
2329{
2330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2331
2332 if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)),
2333 GRBM_STATUS, GUI_ACTIVE))
2334 return false;
2335 else
2336 return true;
2337}
2338
2339static int gfx_v9_0_wait_for_idle(void *handle)
2340{
2341 unsigned i;
2342 u32 tmp;
2343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2344
2345 for (i = 0; i < adev->usec_timeout; i++) {
2346 /* read MC_STATUS */
2347 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) &
2348 GRBM_STATUS__GUI_ACTIVE_MASK;
2349
2350 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
2351 return 0;
2352 udelay(1);
2353 }
2354 return -ETIMEDOUT;
2355}
2356
b1023571
KW		 2357static int gfx_v9_0_soft_reset(void *handle)
2358{
2359 u32 grbm_soft_reset = 0;
2360 u32 tmp;
2361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2362
2363 /* GRBM_STATUS */
2364 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS));
2365 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2366 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2367 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2368 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2369 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2370 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2371 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2372 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2373 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2374 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2375 }
2376
2377 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2378 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2379 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2380 }
2381
2382 /* GRBM_STATUS2 */
2383 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2));
2384 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2385 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2386 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2387
2388
75bac5c6 2389 if (grbm_soft_reset) {
b1023571
KW		 2390 /* stop the rlc */
2391 gfx_v9_0_rlc_stop(adev);
2392
2393 /* Disable GFX parsing/prefetching */
2394 gfx_v9_0_cp_gfx_enable(adev, false);
2395
2396 /* Disable MEC parsing/prefetching */
2397 gfx_v9_0_cp_compute_enable(adev, false);
2398
2399 if (grbm_soft_reset) {
2400 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2401 tmp |= grbm_soft_reset;
2402 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2403 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2404 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2405
2406 udelay(50);
2407
2408 tmp &= ~grbm_soft_reset;
2409 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp);
2410 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET));
2411 }
2412
2413 /* Wait a little for things to settle down */
2414 udelay(50);
b1023571
KW		 2415 }
2416 return 0;
2417}
2418
2419static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2420{
2421 uint64_t clock;
2422
2423 mutex_lock(&adev->gfx.gpu_clock_mutex);
2424 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1);
2425 clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) |
2426 ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL);
2427 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2428 return clock;
2429}
2430
2431static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
2432 uint32_t vmid,
2433 uint32_t gds_base, uint32_t gds_size,
2434 uint32_t gws_base, uint32_t gws_size,
2435 uint32_t oa_base, uint32_t oa_size)
2436{
2437 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
2438 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
2439
2440 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
2441 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
2442
2443 oa_base = oa_base >> AMDGPU_OA_SHIFT;
2444 oa_size = oa_size >> AMDGPU_OA_SHIFT;
2445
2446 /* GDS Base */
2447 gfx_v9_0_write_data_to_reg(ring, 0, false,
2448 amdgpu_gds_reg_offset[vmid].mem_base,
2449 gds_base);
2450
2451 /* GDS Size */
2452 gfx_v9_0_write_data_to_reg(ring, 0, false,
2453 amdgpu_gds_reg_offset[vmid].mem_size,
2454 gds_size);
2455
2456 /* GWS */
2457 gfx_v9_0_write_data_to_reg(ring, 0, false,
2458 amdgpu_gds_reg_offset[vmid].gws,
2459 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2460
2461 /* OA */
2462 gfx_v9_0_write_data_to_reg(ring, 0, false,
2463 amdgpu_gds_reg_offset[vmid].oa,
2464 (1 << (oa_size + oa_base)) - (1 << oa_base));
2465}
2466
2467static int gfx_v9_0_early_init(void *handle)
2468{
2469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2470
2471 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
2472 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS;
2473 gfx_v9_0_set_ring_funcs(adev);
2474 gfx_v9_0_set_irq_funcs(adev);
2475 gfx_v9_0_set_gds_init(adev);
2476 gfx_v9_0_set_rlc_funcs(adev);
2477
2478 return 0;
2479}
2480
2481static int gfx_v9_0_late_init(void *handle)
2482{
2483 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2484 int r;
2485
2486 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2487 if (r)
2488 return r;
2489
2490 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2491 if (r)
2492 return r;
2493
2494 return 0;
2495}
2496
2497static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
2498{
2499 uint32_t rlc_setting, data;
2500 unsigned i;
2501
2502 if (adev->gfx.rlc.in_safe_mode)
2503 return;
2504
2505 /* if RLC is not enabled, do nothing */
2506 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2507 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2508 return;
2509
2510 if (adev->cg_flags &
2511 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
2512 AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2513 data = RLC_SAFE_MODE__CMD_MASK;
2514 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
2515 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2516
2517 /* wait for RLC_SAFE_MODE */
2518 for (i = 0; i < adev->usec_timeout; i++) {
2519 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
2520 break;
2521 udelay(1);
2522 }
2523 adev->gfx.rlc.in_safe_mode = true;
2524 }
2525}
2526
2527static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
2528{
2529 uint32_t rlc_setting, data;
2530
2531 if (!adev->gfx.rlc.in_safe_mode)
2532 return;
2533
2534 /* if RLC is not enabled, do nothing */
2535 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL));
2536 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
2537 return;
2538
2539 if (adev->cg_flags &
2540 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
2541 /*
2542 * Try to exit safe mode only if it is already in safe
2543 * mode.
2544 */
2545 data = RLC_SAFE_MODE__CMD_MASK;
2546 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data);
2547 adev->gfx.rlc.in_safe_mode = false;
2548 }
2549}
2550
2551static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2552 bool enable)
2553{
2554 uint32_t data, def;
2555
2556 /* It is disabled by HW by default */
2557 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2558 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2559 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2560 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2561 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2562 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2563 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2564
2565 /* only for Vega10 & Raven1 */
2566 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
2567
2568 if (def != data)
2569 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2570
2571 /* MGLS is a global flag to control all MGLS in GFX */
2572 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2573 /* 2 - RLC memory Light sleep */
2574 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2575 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2576 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2577 if (def != data)
2578 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2579 }
2580 /* 3 - CP memory Light sleep */
2581 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2582 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2583 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2584 if (def != data)
2585 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2586 }
2587 }
2588 } else {
2589 /* 1 - MGCG_OVERRIDE */
2590 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2591 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
2592 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2593 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2594 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2595 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2596 if (def != data)
2597 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2598
2599 /* 2 - disable MGLS in RLC */
2600 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2601 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2602 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2603 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data);
2604 }
2605
2606 /* 3 - disable MGLS in CP */
2607 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2608 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2609 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2610 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data);
2611 }
2612 }
2613}
2614
2615static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
2616 bool enable)
2617{
2618 uint32_t data, def;
2619
2620 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2621
2622 /* Enable 3D CGCG/CGLS */
2623 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
2624 /* write cmd to clear cgcg/cgls ov */
2625 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2626 /* unset CGCG override */
2627 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
2628 /* update CGCG and CGLS override bits */
2629 if (def != data)
2630 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2631 /* enable 3Dcgcg FSM(0x0020003f) */
2632 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2633 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2634 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
2635 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
2636 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2637 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
2638 if (def != data)
2639 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2640
2641 /* set IDLE_POLL_COUNT(0x00900100) */
2642 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2643 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2644 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2645 if (def != data)
2646 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2647 } else {
2648 /* Disable CGCG/CGLS */
2649 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2650 /* disable cgcg, cgls should be disabled */
2651 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
2652 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
2653 /* disable cgcg and cgls in FSM */
2654 if (def != data)
2655 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data);
2656 }
2657
2658 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2659}
2660
2661static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2662 bool enable)
2663{
2664 uint32_t def, data;
2665
2666 adev->gfx.rlc.funcs->enter_safe_mode(adev);
2667
2668 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2669 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2670 /* unset CGCG override */
2671 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2672 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2673 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2674 else
2675 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2676 /* update CGCG and CGLS override bits */
2677 if (def != data)
2678 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data);
2679
2680 /* enable cgcg FSM(0x0020003F) */
2681 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2682 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2683 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2684 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2685 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2686 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2687 if (def != data)
2688 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2689
2690 /* set IDLE_POLL_COUNT(0x00900100) */
2691 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2692 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2693 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2694 if (def != data)
2695 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2696 } else {
2697 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2698 /* reset CGCG/CGLS bits */
2699 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2700 /* disable cgcg and cgls in FSM */
2701 if (def != data)
2702 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data);
2703 }
2704
2705 adev->gfx.rlc.funcs->exit_safe_mode(adev);
2706}
2707
2708static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
2709 bool enable)
2710{
2711 if (enable) {
2712 /* CGCG/CGLS should be enabled after MGCG/MGLS
2713 * === MGCG + MGLS ===
2714 */
2715 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2716 /* === CGCG /CGLS for GFX 3D Only === */
2717 gfx_v9_0_update_3d_clock_gating(adev, enable);
2718 /* === CGCG + CGLS === */
2719 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2720 } else {
2721 /* CGCG/CGLS should be disabled before MGCG/MGLS
2722 * === CGCG + CGLS ===
2723 */
2724 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
2725 /* === CGCG /CGLS for GFX 3D Only === */
2726 gfx_v9_0_update_3d_clock_gating(adev, enable);
2727 /* === MGCG + MGLS === */
2728 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
2729 }
2730 return 0;
2731}
2732
2733static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
2734 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
2735 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
2736};
2737
2738static int gfx_v9_0_set_powergating_state(void *handle,
2739 enum amd_powergating_state state)
2740{
2741 return 0;
2742}
2743
2744static int gfx_v9_0_set_clockgating_state(void *handle,
2745 enum amd_clockgating_state state)
2746{
2747 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2748
2749 switch (adev->asic_type) {
2750 case CHIP_VEGA10:
2751 gfx_v9_0_update_gfx_clock_gating(adev,
2752 state == AMD_CG_STATE_GATE ? true : false);
2753 break;
2754 default:
2755 break;
2756 }
2757 return 0;
2758}
2759
12ad27fa
HR		 2760static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
2761{
2762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2763 int data;
2764
2765 if (amdgpu_sriov_vf(adev))
2766 *flags = 0;
2767
2768 /* AMD_CG_SUPPORT_GFX_MGCG */
2769 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
2770 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2771 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2772
2773 /* AMD_CG_SUPPORT_GFX_CGCG */
2774 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
2775 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2776 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2777
2778 /* AMD_CG_SUPPORT_GFX_CGLS */
2779 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2780 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2781
2782 /* AMD_CG_SUPPORT_GFX_RLC_LS */
2783 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
2784 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2785 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2786
2787 /* AMD_CG_SUPPORT_GFX_CP_LS */
2788 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
2789 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2790 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2791
2792 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
2793 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
2794 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
2795 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
2796
2797 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
2798 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
2799 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
2800}
2801
b1023571
KW		 2802static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2803{
2804 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
2805}
2806
2807static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2808{
2809 struct amdgpu_device *adev = ring->adev;
2810 u64 wptr;
2811
2812 /* XXX check if swapping is necessary on BE */
2813 if (ring->use_doorbell) {
2814 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
2815 } else {
2816 wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR));
2817 wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32;
2818 }
2819
2820 return wptr;
2821}
2822
2823static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2824{
2825 struct amdgpu_device *adev = ring->adev;
2826
2827 if (ring->use_doorbell) {
2828 /* XXX check if swapping is necessary on BE */
2829 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2830 WDOORBELL64(ring->doorbell_index, ring->wptr);
2831 } else {
2832 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr));
2833 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr));
2834 }
2835}
2836
2837static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2838{
2839 u32 ref_and_mask, reg_mem_engine;
2840 struct nbio_hdp_flush_reg *nbio_hf_reg;
2841
2842 if (ring->adev->asic_type == CHIP_VEGA10)
2843 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
2844
2845 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2846 switch (ring->me) {
2847 case 1:
2848 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2849 break;
2850 case 2:
2851 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2852 break;
2853 default:
2854 return;
2855 }
2856 reg_mem_engine = 0;
2857 } else {
2858 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2859 reg_mem_engine = 1; /* pfp */
2860 }
2861
2862 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2863 nbio_hf_reg->hdp_flush_req_offset,
2864 nbio_hf_reg->hdp_flush_done_offset,
2865 ref_and_mask, ref_and_mask, 0x20);
2866}
2867
2868static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2869{
2870 gfx_v9_0_write_data_to_reg(ring, 0, true,
2871 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
2872}
2873
2874static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2875 struct amdgpu_ib *ib,
2876 unsigned vm_id, bool ctx_switch)
2877{
2878 u32 header, control = 0;
2879
2880 if (ib->flags & AMDGPU_IB_FLAG_CE)
2881 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2882 else
2883 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2884
2885 control |= ib->length_dw | (vm_id << 24);
2886
9ccd52eb
ML		 2887 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
2888 control |= INDIRECT_BUFFER_PRE_ENB(1);
2889
b1023571
KW		 2890 amdgpu_ring_write(ring, header);
2891 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2892 amdgpu_ring_write(ring,
2893#ifdef __BIG_ENDIAN
2894 (2 << 0) |
2895#endif
2896 lower_32_bits(ib->gpu_addr));
2897 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2898 amdgpu_ring_write(ring, control);
2899}
2900
2901#define INDIRECT_BUFFER_VALID (1 << 23)
2902
2903static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2904 struct amdgpu_ib *ib,
2905 unsigned vm_id, bool ctx_switch)
2906{
2907 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2908
2909 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2910 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2911 amdgpu_ring_write(ring,
2912#ifdef __BIG_ENDIAN
2913 (2 << 0) |
2914#endif
2915 lower_32_bits(ib->gpu_addr));
2916 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2917 amdgpu_ring_write(ring, control);
2918}
2919
2920static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2921 u64 seq, unsigned flags)
2922{
2923 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2924 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2925
2926 /* RELEASE_MEM - flush caches, send int */
2927 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2928 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2929 EOP_TC_ACTION_EN |
2930 EOP_TC_WB_ACTION_EN |
2931 EOP_TC_MD_ACTION_EN |
2932 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2933 EVENT_INDEX(5)));
2934 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2935
2936 /*
2937 * the address should be Qword aligned if 64bit write, Dword
2938 * aligned if only send 32bit data low (discard data high)
2939 */
2940 if (write64bit)
2941 BUG_ON(addr & 0x7);
2942 else
2943 BUG_ON(addr & 0x3);
2944 amdgpu_ring_write(ring, lower_32_bits(addr));
2945 amdgpu_ring_write(ring, upper_32_bits(addr));
2946 amdgpu_ring_write(ring, lower_32_bits(seq));
2947 amdgpu_ring_write(ring, upper_32_bits(seq));
2948 amdgpu_ring_write(ring, 0);
2949}
2950
2951static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2952{
2953 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2954 uint32_t seq = ring->fence_drv.sync_seq;
2955 uint64_t addr = ring->fence_drv.gpu_addr;
2956
2957 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
2958 lower_32_bits(addr), upper_32_bits(addr),
2959 seq, 0xffffffff, 4);
2960}
2961
2962static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2963 unsigned vm_id, uint64_t pd_addr)
2964{
2965 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
03f89feb 2966 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
b1023571
KW		 2967 unsigned eng = ring->idx;
2968 unsigned i;
2969
2970 pd_addr = pd_addr | 0x1; /* valid bit */
2971 /* now only use physical base address of PDE and valid */
2972 BUG_ON(pd_addr & 0xFFFF00000000003EULL);
2973
2974 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2975 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
b1023571
KW		 2976
2977 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2978 hub->ctx0_ptb_addr_lo32
2979 + (2 * vm_id),
2980 lower_32_bits(pd_addr));
2981
2982 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2983 hub->ctx0_ptb_addr_hi32
2984 + (2 * vm_id),
2985 upper_32_bits(pd_addr));
2986
2987 gfx_v9_0_write_data_to_reg(ring, usepfp, true,
2988 hub->vm_inv_eng0_req + eng, req);
2989
2990 /* wait for the invalidate to complete */
2991 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
2992 eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
2993 }
2994
2995 /* compute doesn't have PFP */
2996 if (usepfp) {
2997 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2998 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2999 amdgpu_ring_write(ring, 0x0);
b1023571
KW		 3000 }
3001}
3002
3003static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3004{
3005 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3006}
3007
3008static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3009{
3010 u64 wptr;
3011
3012 /* XXX check if swapping is necessary on BE */
3013 if (ring->use_doorbell)
3014 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3015 else
3016 BUG();
3017 return wptr;
3018}
3019
3020static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3021{
3022 struct amdgpu_device *adev = ring->adev;
3023
3024 /* XXX check if swapping is necessary on BE */
3025 if (ring->use_doorbell) {
3026 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3027 WDOORBELL64(ring->doorbell_index, ring->wptr);
3028 } else{
3029 BUG(); /* only DOORBELL method supported on gfx9 now */
3030 }
3031}
3032
aa6faa44
XY		 3033static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3034 u64 seq, unsigned int flags)
3035{
3036 /* we only allocate 32bit for each seq wb address */
3037 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3038
3039 /* write fence seq to the "addr" */
3040 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3041 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3042 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3043 amdgpu_ring_write(ring, lower_32_bits(addr));
3044 amdgpu_ring_write(ring, upper_32_bits(addr));
3045 amdgpu_ring_write(ring, lower_32_bits(seq));
3046
3047 if (flags & AMDGPU_FENCE_FLAG_INT) {
3048 /* set register to trigger INT */
3049 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3050 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3051 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3052 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3053 amdgpu_ring_write(ring, 0);
3054 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3055 }
3056}
3057
b1023571
KW		 3058static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3059{
3060 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3061 amdgpu_ring_write(ring, 0);
3062}
3063
cca02cd3
XY		 3064static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
3065{
3066 static struct v9_ce_ib_state ce_payload = {0};
3067 uint64_t csa_addr;
3068 int cnt;
3069
3070 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
3071 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3072
3073 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3074 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3075 WRITE_DATA_DST_SEL(8) |
3076 WR_CONFIRM) |
3077 WRITE_DATA_CACHE_POLICY(0));
3078 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3079 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
3080 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
3081}
3082
3083static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
3084{
3085 static struct v9_de_ib_state de_payload = {0};
3086 uint64_t csa_addr, gds_addr;
3087 int cnt;
3088
3089 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
3090 gds_addr = csa_addr + 4096;
3091 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
3092 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
3093
3094 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
3095 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
3096 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
3097 WRITE_DATA_DST_SEL(8) |
3098 WR_CONFIRM) |
3099 WRITE_DATA_CACHE_POLICY(0));
3100 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3101 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
3102 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
3103}
3104
b1023571
KW		 3105static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3106{
3107 uint32_t dw2 = 0;
3108
cca02cd3
XY		 3109 if (amdgpu_sriov_vf(ring->adev))
3110 gfx_v9_0_ring_emit_ce_meta(ring);
3111
b1023571
KW		 3112 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
3113 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
3114 /* set load_global_config & load_global_uconfig */
3115 dw2 |= 0x8001;
3116 /* set load_cs_sh_regs */
3117 dw2 |= 0x01000000;
3118 /* set load_per_context_state & load_gfx_sh_regs for GFX */
3119 dw2 |= 0x10002;
3120
3121 /* set load_ce_ram if preamble presented */
3122 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
3123 dw2 |= 0x10000000;
3124 } else {
3125 /* still load_ce_ram if this is the first time preamble presented
3126 * although there is no context switch happens.
3127 */
3128 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
3129 dw2 |= 0x10000000;
3130 }
3131
3132 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3133 amdgpu_ring_write(ring, dw2);
3134 amdgpu_ring_write(ring, 0);
cca02cd3
XY		 3135
3136 if (amdgpu_sriov_vf(ring->adev))
3137 gfx_v9_0_ring_emit_de_meta(ring);
b1023571
KW		 3138}
3139
9a5e02b5
ML		 3140static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
3141{
3142 unsigned ret;
3143 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
3144 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
3145 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
3146 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
3147 ret = ring->wptr & ring->buf_mask;
3148 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
3149 return ret;
3150}
3151
3152static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
3153{
3154 unsigned cur;
3155 BUG_ON(offset > ring->buf_mask);
3156 BUG_ON(ring->ring[offset] != 0x55aa55aa);
3157
3158 cur = (ring->wptr & ring->buf_mask) - 1;
3159 if (likely(cur > offset))
3160 ring->ring[offset] = cur - offset;
3161 else
3162 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
3163}
3164
aa6faa44
XY		 3165static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
3166{
3167 struct amdgpu_device *adev = ring->adev;
3168
3169 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3170 amdgpu_ring_write(ring, 0 | /* src: register*/
3171 (5 << 8) | /* dst: memory */
3172 (1 << 20)); /* write confirm */
3173 amdgpu_ring_write(ring, reg);
3174 amdgpu_ring_write(ring, 0);
3175 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3176 adev->virt.reg_val_offs * 4));
3177 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3178 adev->virt.reg_val_offs * 4));
3179}
3180
3181static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
3182 uint32_t val)
3183{
3184 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3185 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
3186 amdgpu_ring_write(ring, reg);
3187 amdgpu_ring_write(ring, 0);
3188 amdgpu_ring_write(ring, val);
3189}
3190
b1023571
KW		 3191static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3192 enum amdgpu_interrupt_state state)
3193{
b1023571
KW		 3194 switch (state) {
3195 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3196 case AMDGPU_IRQ_STATE_ENABLE:
9da2c652
TSD		 3197 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3198 TIME_STAMP_INT_ENABLE,
3199 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3200 break;
3201 default:
3202 break;
3203 }
3204}
3205
3206static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3207 int me, int pipe,
3208 enum amdgpu_interrupt_state state)
3209{
3210 u32 mec_int_cntl, mec_int_cntl_reg;
3211
3212 /*
3213 * amdgpu controls only pipe 0 of MEC1. That's why this function only
3214 * handles the setting of interrupts for this specific pipe. All other
3215 * pipes' interrupts are set by amdkfd.
3216 */
3217
3218 if (me == 1) {
3219 switch (pipe) {
3220 case 0:
3221 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3222 break;
3223 default:
3224 DRM_DEBUG("invalid pipe %d\n", pipe);
3225 return;
3226 }
3227 } else {
3228 DRM_DEBUG("invalid me %d\n", me);
3229 return;
3230 }
3231
3232 switch (state) {
3233 case AMDGPU_IRQ_STATE_DISABLE:
3234 mec_int_cntl = RREG32(mec_int_cntl_reg);
3235 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3236 TIME_STAMP_INT_ENABLE, 0);
3237 WREG32(mec_int_cntl_reg, mec_int_cntl);
3238 break;
3239 case AMDGPU_IRQ_STATE_ENABLE:
3240 mec_int_cntl = RREG32(mec_int_cntl_reg);
3241 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3242 TIME_STAMP_INT_ENABLE, 1);
3243 WREG32(mec_int_cntl_reg, mec_int_cntl);
3244 break;
3245 default:
3246 break;
3247 }
3248}
3249
3250static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3251 struct amdgpu_irq_src *source,
3252 unsigned type,
3253 enum amdgpu_interrupt_state state)
3254{
b1023571
KW		 3255 switch (state) {
3256 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3257 case AMDGPU_IRQ_STATE_ENABLE:
8dd553e1
TSD		 3258 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3259 PRIV_REG_INT_ENABLE,
3260 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3261 break;
3262 default:
3263 break;
3264 }
3265
3266 return 0;
3267}
3268
3269static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3270 struct amdgpu_irq_src *source,
3271 unsigned type,
3272 enum amdgpu_interrupt_state state)
3273{
b1023571
KW		 3274 switch (state) {
3275 case AMDGPU_IRQ_STATE_DISABLE:
b1023571 3276 case AMDGPU_IRQ_STATE_ENABLE:
98709ca6
TSD		 3277 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
3278 PRIV_INSTR_INT_ENABLE,
3279 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
b1023571
KW		 3280 default:
3281 break;
3282 }
3283
3284 return 0;
3285}
3286
3287static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3288 struct amdgpu_irq_src *src,
3289 unsigned type,
3290 enum amdgpu_interrupt_state state)
3291{
3292 switch (type) {
3293 case AMDGPU_CP_IRQ_GFX_EOP:
3294 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
3295 break;
3296 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3297 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
3298 break;
3299 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3300 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
3301 break;
3302 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
3303 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
3304 break;
3305 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
3306 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
3307 break;
3308 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
3309 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
3310 break;
3311 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
3312 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
3313 break;
3314 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
3315 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
3316 break;
3317 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
3318 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
3319 break;
3320 default:
3321 break;
3322 }
3323 return 0;
3324}
3325
3326static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
3327 struct amdgpu_irq_src *source,
3328 struct amdgpu_iv_entry *entry)
3329{
3330 int i;
3331 u8 me_id, pipe_id, queue_id;
3332 struct amdgpu_ring *ring;
3333
3334 DRM_DEBUG("IH: CP EOP\n");
3335 me_id = (entry->ring_id & 0x0c) >> 2;
3336 pipe_id = (entry->ring_id & 0x03) >> 0;
3337 queue_id = (entry->ring_id & 0x70) >> 4;
3338
3339 switch (me_id) {
3340 case 0:
3341 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3342 break;
3343 case 1:
3344 case 2:
3345 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3346 ring = &adev->gfx.compute_ring[i];
3347 /* Per-queue interrupt is supported for MEC starting from VI.
3348 * The interrupt can only be enabled/disabled per pipe instead of per queue.
3349 */
3350 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
3351 amdgpu_fence_process(ring);
3352 }
3353 break;
3354 }
3355 return 0;
3356}
3357
3358static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361{
3362 DRM_ERROR("Illegal register access in command stream\n");
3363 schedule_work(&adev->reset_work);
3364 return 0;
3365}
3366
3367static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
3368 struct amdgpu_irq_src *source,
3369 struct amdgpu_iv_entry *entry)
3370{
3371 DRM_ERROR("Illegal instruction in command stream\n");
3372 schedule_work(&adev->reset_work);
3373 return 0;
3374}
3375
97031e25
XY		 3376static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
3377 struct amdgpu_irq_src *src,
3378 unsigned int type,
3379 enum amdgpu_interrupt_state state)
3380{
3381 uint32_t tmp, target;
3382 struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data;
3383
3384 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
3385
3386 if (ring->me == 1)
3387 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
3388 else
3389 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
3390 target += ring->pipe;
3391
3392 switch (type) {
3393 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
3394 if (state == AMDGPU_IRQ_STATE_DISABLE) {
3395 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
3396 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3397 GENERIC2_INT_ENABLE, 0);
3398 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
3399
3400 tmp = RREG32(target);
3401 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3402 GENERIC2_INT_ENABLE, 0);
3403 WREG32(target, tmp);
3404 } else {
3405 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
3406 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
3407 GENERIC2_INT_ENABLE, 1);
3408 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
3409
3410 tmp = RREG32(target);
3411 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
3412 GENERIC2_INT_ENABLE, 1);
3413 WREG32(target, tmp);
3414 }
3415 break;
3416 default:
3417 BUG(); /* kiq only support GENERIC2_INT now */
3418 break;
3419 }
3420 return 0;
3421}
3422
3423static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
3424 struct amdgpu_irq_src *source,
3425 struct amdgpu_iv_entry *entry)
3426{
3427 u8 me_id, pipe_id, queue_id;
3428 struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data;
3429
3430 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
3431
3432 me_id = (entry->ring_id & 0x0c) >> 2;
3433 pipe_id = (entry->ring_id & 0x03) >> 0;
3434 queue_id = (entry->ring_id & 0x70) >> 4;
3435 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
3436 me_id, pipe_id, queue_id);
3437
3438 amdgpu_fence_process(ring);
3439 return 0;
3440}
3441
b1023571
KW		 3442const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
3443 .name = "gfx_v9_0",
3444 .early_init = gfx_v9_0_early_init,
3445 .late_init = gfx_v9_0_late_init,
3446 .sw_init = gfx_v9_0_sw_init,
3447 .sw_fini = gfx_v9_0_sw_fini,
3448 .hw_init = gfx_v9_0_hw_init,
3449 .hw_fini = gfx_v9_0_hw_fini,
3450 .suspend = gfx_v9_0_suspend,
3451 .resume = gfx_v9_0_resume,
3452 .is_idle = gfx_v9_0_is_idle,
3453 .wait_for_idle = gfx_v9_0_wait_for_idle,
3454 .soft_reset = gfx_v9_0_soft_reset,
3455 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
3456 .set_powergating_state = gfx_v9_0_set_powergating_state,
12ad27fa 3457 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
b1023571
KW		 3458};
3459
3460static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
3461 .type = AMDGPU_RING_TYPE_GFX,
3462 .align_mask = 0xff,
3463 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3464 .support_64bit_ptrs = true,
3465 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
3466 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
3467 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
e9d672b2
ML		 3468 .emit_frame_size = /* totally 242 maximum if 16 IBs */
3469 5 + /* COND_EXEC */
3470 7 + /* PIPELINE_SYNC */
3471 46 + /* VM_FLUSH */
3472 8 + /* FENCE for VM_FLUSH */
3473 20 + /* GDS switch */
3474 4 + /* double SWITCH_BUFFER,
3475 the first COND_EXEC jump to the place just
3476 prior to this double SWITCH_BUFFER */
3477 5 + /* COND_EXEC */
3478 7 + /* HDP_flush */
3479 4 + /* VGT_flush */
3480 14 + /* CE_META */
3481 31 + /* DE_META */
3482 3 + /* CNTX_CTRL */
3483 5 + /* HDP_INVL */
3484 8 + 8 + /* FENCE x2 */
3485 2, /* SWITCH_BUFFER */
b1023571
KW		 3486 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
3487 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
3488 .emit_fence = gfx_v9_0_ring_emit_fence,
3489 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3490 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3491 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3492 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3493 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3494 .test_ring = gfx_v9_0_ring_test_ring,
3495 .test_ib = gfx_v9_0_ring_test_ib,
3496 .insert_nop = amdgpu_ring_insert_nop,
3497 .pad_ib = amdgpu_ring_generic_pad_ib,
3498 .emit_switch_buffer = gfx_v9_ring_emit_sb,
3499 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
9a5e02b5
ML		 3500 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
3501 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
b1023571
KW		 3502};
3503
3504static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
3505 .type = AMDGPU_RING_TYPE_COMPUTE,
3506 .align_mask = 0xff,
3507 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3508 .support_64bit_ptrs = true,
3509 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3510 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3511 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3512 .emit_frame_size =
3513 20 + /* gfx_v9_0_ring_emit_gds_switch */
3514 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3515 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3516 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3517 64 + /* gfx_v9_0_ring_emit_vm_flush */
3518 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
3519 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3520 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3521 .emit_fence = gfx_v9_0_ring_emit_fence,
3522 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
3523 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
3524 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
3525 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3526 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3527 .test_ring = gfx_v9_0_ring_test_ring,
3528 .test_ib = gfx_v9_0_ring_test_ib,
3529 .insert_nop = amdgpu_ring_insert_nop,
3530 .pad_ib = amdgpu_ring_generic_pad_ib,
3531};
3532
aa6faa44
XY		 3533static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
3534 .type = AMDGPU_RING_TYPE_KIQ,
3535 .align_mask = 0xff,
3536 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
3537 .support_64bit_ptrs = true,
3538 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
3539 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
3540 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
3541 .emit_frame_size =
3542 20 + /* gfx_v9_0_ring_emit_gds_switch */
3543 7 + /* gfx_v9_0_ring_emit_hdp_flush */
3544 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
3545 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
3546 64 + /* gfx_v9_0_ring_emit_vm_flush */
3547 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
3548 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
3549 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
3550 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
3551 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
3552 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
3553 .test_ring = gfx_v9_0_ring_test_ring,
3554 .test_ib = gfx_v9_0_ring_test_ib,
3555 .insert_nop = amdgpu_ring_insert_nop,
3556 .pad_ib = amdgpu_ring_generic_pad_ib,
3557 .emit_rreg = gfx_v9_0_ring_emit_rreg,
3558 .emit_wreg = gfx_v9_0_ring_emit_wreg,
3559};
b1023571
KW		 3560
3561static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
3562{
3563 int i;
3564
aa6faa44
XY		 3565 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
3566
b1023571
KW		 3567 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3568 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
3569
3570 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3571 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
3572}
3573
97031e25
XY		 3574static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
3575 .set = gfx_v9_0_kiq_set_interrupt_state,
3576 .process = gfx_v9_0_kiq_irq,
3577};
3578
b1023571
KW		 3579static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
3580 .set = gfx_v9_0_set_eop_interrupt_state,
3581 .process = gfx_v9_0_eop_irq,
3582};
3583
3584static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
3585 .set = gfx_v9_0_set_priv_reg_fault_state,
3586 .process = gfx_v9_0_priv_reg_irq,
3587};
3588
3589static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
3590 .set = gfx_v9_0_set_priv_inst_fault_state,
3591 .process = gfx_v9_0_priv_inst_irq,
3592};
3593
3594static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
3595{
3596 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3597 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
3598
3599 adev->gfx.priv_reg_irq.num_types = 1;
3600 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
3601
3602 adev->gfx.priv_inst_irq.num_types = 1;
3603 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
97031e25
XY		 3604
3605 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
3606 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
b1023571
KW		 3607}
3608
3609static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
3610{
3611 switch (adev->asic_type) {
3612 case CHIP_VEGA10:
3613 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
3614 break;
3615 default:
3616 break;
3617 }
3618}
3619
3620static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
3621{
3622 /* init asci gds info */
3623 adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
3624 adev->gds.gws.total_size = 64;
3625 adev->gds.oa.total_size = 16;
3626
3627 if (adev->gds.mem.total_size == 64 * 1024) {
3628 adev->gds.mem.gfx_partition_size = 4096;
3629 adev->gds.mem.cs_partition_size = 4096;
3630
3631 adev->gds.gws.gfx_partition_size = 4;
3632 adev->gds.gws.cs_partition_size = 4;
3633
3634 adev->gds.oa.gfx_partition_size = 4;
3635 adev->gds.oa.cs_partition_size = 1;
3636 } else {
3637 adev->gds.mem.gfx_partition_size = 1024;
3638 adev->gds.mem.cs_partition_size = 1024;
3639
3640 adev->gds.gws.gfx_partition_size = 16;
3641 adev->gds.gws.cs_partition_size = 16;
3642
3643 adev->gds.oa.gfx_partition_size = 4;
3644 adev->gds.oa.cs_partition_size = 4;
3645 }
3646}
3647
3648static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3649{
3650 u32 data, mask;
3651
3652 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG));
3653 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG));
3654
3655 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3656 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3657
3658 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3659
3660 return (~data) & mask;
3661}
3662
3663static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
3664 struct amdgpu_cu_info *cu_info)
3665{
3666 int i, j, k, counter, active_cu_number = 0;
3667 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3668
3669 if (!adev || !cu_info)
3670 return -EINVAL;
3671
3672 memset(cu_info, 0, sizeof(*cu_info));
3673
3674 mutex_lock(&adev->grbm_idx_mutex);
3675 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3676 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3677 mask = 1;
3678 ao_bitmap = 0;
3679 counter = 0;
3680 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
3681 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
3682 cu_info->bitmap[i][j] = bitmap;
3683
3684 for (k = 0; k < 16; k ++) {
3685 if (bitmap & mask) {
3686 if (counter < 2)
3687 ao_bitmap |= mask;
3688 counter ++;
3689 }
3690 mask <<= 1;
3691 }
3692 active_cu_number += counter;
3693 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3694 }
3695 }
3696 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3697 mutex_unlock(&adev->grbm_idx_mutex);
3698
3699 cu_info->number = active_cu_number;
3700 cu_info->ao_cu_mask = ao_cu_mask;
3701
3702 return 0;
3703}
3704
3705static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
3706{
3707 int r, j;
3708 u32 tmp;
3709 bool use_doorbell = true;
3710 u64 hqd_gpu_addr;
3711 u64 mqd_gpu_addr;
3712 u64 eop_gpu_addr;
3713 u64 wb_gpu_addr;
3714 u32 *buf;
3715 struct v9_mqd *mqd;
3716 struct amdgpu_device *adev;
3717
3718 adev = ring->adev;
3719 if (ring->mqd_obj == NULL) {
3720 r = amdgpu_bo_create(adev,
3721 sizeof(struct v9_mqd),
3722 PAGE_SIZE,true,
3723 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3724 NULL, &ring->mqd_obj);
3725 if (r) {
3726 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3727 return r;
3728 }
3729 }
3730
3731 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3732 if (unlikely(r != 0)) {
3733 gfx_v9_0_cp_compute_fini(adev);
3734 return r;
3735 }
3736
3737 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3738 &mqd_gpu_addr);
3739 if (r) {
3740 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3741 gfx_v9_0_cp_compute_fini(adev);
3742 return r;
3743 }
3744 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3745 if (r) {
3746 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3747 gfx_v9_0_cp_compute_fini(adev);
3748 return r;
3749 }
3750
3751 /* init the mqd struct */
3752 memset(buf, 0, sizeof(struct v9_mqd));
3753
3754 mqd = (struct v9_mqd *)buf;
3755 mqd->header = 0xC0310800;
3756 mqd->compute_pipelinestat_enable = 0x00000001;
3757 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3758 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3759 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3760 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3761 mqd->compute_misc_reserved = 0x00000003;
3762 mutex_lock(&adev->srbm_mutex);
3763 soc15_grbm_select(adev, ring->me,
3764 ring->pipe,
3765 ring->queue, 0);
3766 /* disable wptr polling */
efe53d8a 3767 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
b1023571
KW		 3768
3769 /* write the EOP addr */
3770 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
3771 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
3772 eop_gpu_addr >>= 8;
3773
3774 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr));
3775 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr));
3776 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
3777 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
3778
3779 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3780 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL));
3781 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3782 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3783 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp);
3784
3785 /* enable doorbell? */
3786 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3787 if (use_doorbell)
3788 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3789 else
3790 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3791
3792 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp);
3793 mqd->cp_hqd_pq_doorbell_control = tmp;
3794
3795 /* disable the queue if it's active */
3796 ring->wptr = 0;
3797 mqd->cp_hqd_dequeue_request = 0;
3798 mqd->cp_hqd_pq_rptr = 0;
3799 mqd->cp_hqd_pq_wptr_lo = 0;
3800 mqd->cp_hqd_pq_wptr_hi = 0;
3801 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) {
3802 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1);
3803 for (j = 0; j < adev->usec_timeout; j++) {
3804 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1))
3805 break;
3806 udelay(1);
3807 }
3808 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request);
3809 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr);
3810 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3811 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3812 }
3813
3814 /* set the pointer to the MQD */
3815 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3816 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3817 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo);
3818 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi);
3819
3820 /* set MQD vmid to 0 */
3821 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL));
3822 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3823 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp);
3824 mqd->cp_mqd_control = tmp;
3825
3826 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3827 hqd_gpu_addr = ring->gpu_addr >> 8;
3828 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3829 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3830 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo);
3831 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi);
3832
3833 /* set up the HQD, this is similar to CP_RB0_CNTL */
3834 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL));
3835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3836 (order_base_2(ring->ring_size / 4) - 1));
3837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3838 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3839#ifdef __BIG_ENDIAN
3840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3841#endif
3842 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3843 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3844 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3846 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp);
3847 mqd->cp_hqd_pq_control = tmp;
3848
3849 /* set the wb address wether it's enabled or not */
3850 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3851 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3852 mqd->cp_hqd_pq_rptr_report_addr_hi =
3853 upper_32_bits(wb_gpu_addr) & 0xffff;
3854 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR),
3855 mqd->cp_hqd_pq_rptr_report_addr_lo);
3856 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI),
3857 mqd->cp_hqd_pq_rptr_report_addr_hi);
3858
3859 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3860 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3861 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3862 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3863 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
3864 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3865 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
3866 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3867
3868 /* enable the doorbell if requested */
3869 if (use_doorbell) {
3870 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER),
3871 (AMDGPU_DOORBELL64_KIQ * 2) << 2);
3872 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER),
3873 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
3874 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL));
3875 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3876 DOORBELL_OFFSET, ring->doorbell_index);
3877 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3878 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3880 mqd->cp_hqd_pq_doorbell_control = tmp;
3881
3882 } else {
3883 mqd->cp_hqd_pq_doorbell_control = 0;
3884 }
3885 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
3886 mqd->cp_hqd_pq_doorbell_control);
3887
3888 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3889 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo);
3890 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi);
3891
3892 /* set the vmid for the queue */
3893 mqd->cp_hqd_vmid = 0;
3894 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid);
3895
3896 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE));
3897 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3898 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp);
3899 mqd->cp_hqd_persistent_state = tmp;
3900
3901 /* activate the queue */
3902 mqd->cp_hqd_active = 1;
3903 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active);
3904
3905 soc15_grbm_select(adev, 0, 0, 0, 0);
3906 mutex_unlock(&adev->srbm_mutex);
3907
3908 amdgpu_bo_kunmap(ring->mqd_obj);
3909 amdgpu_bo_unreserve(ring->mqd_obj);
3910
efe53d8a
TSD		 3911 if (use_doorbell)
3912 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
b1023571
KW		 3913
3914 return 0;
3915}
3916
3917const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
3918{
3919 .type = AMD_IP_BLOCK_TYPE_GFX,
3920 .major = 9,
3921 .minor = 0,
3922 .rev = 0,
3923 .funcs = &gfx_v9_0_ip_funcs,
3924};
Linux 6.x block layer and io_uring tree(s)