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drm/amd/powerplay: rewrite pp_sw_init to make code readable
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
68182d90 30#include "amdgpu_atombios.h"
aaa36a97
AD		 31#include "clearstate_vi.h"
32
33#include "gmc/gmc_8_2_d.h"
34#include "gmc/gmc_8_2_sh_mask.h"
35
36#include "oss/oss_3_0_d.h"
37#include "oss/oss_3_0_sh_mask.h"
38
39#include "bif/bif_5_0_d.h"
40#include "bif/bif_5_0_sh_mask.h"
41
42#include "gca/gfx_8_0_d.h"
43#include "gca/gfx_8_0_enum.h"
44#include "gca/gfx_8_0_sh_mask.h"
45#include "gca/gfx_8_0_enum.h"
46
aaa36a97
AD		 47#include "dce/dce_10_0_d.h"
48#include "dce/dce_10_0_sh_mask.h"
49
50#define GFX8_NUM_GFX_RINGS 1
51#define GFX8_NUM_COMPUTE_RINGS 8
52
53#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
54#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
2cc0c0b5 55#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
aaa36a97
AD		 56#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
57
58#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
59#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
60#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
61#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
62#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
63#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
64#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
65#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
66#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
67
6e378858
EH		 68#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
69#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
70#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
71#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
72#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
73#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
74
75/* BPM SERDES CMD */
76#define SET_BPM_SERDES_CMD 1
77#define CLE_BPM_SERDES_CMD 0
78
79/* BPM Register Address*/
80enum {
81 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
82 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
83 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
84 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
85 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
86 BPM_REG_FGCG_MAX
87};
88
2b6cd977
EH		 89#define RLC_FormatDirectRegListLength 14
90
c65444fe
JZ		 91MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
92MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
93MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
94MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
95MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
96MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
97
e3c7656c
SL		 98MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
99MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
100MODULE_FIRMWARE("amdgpu/stoney_me.bin");
101MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
102MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
103
c65444fe
JZ		 104MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
105MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
106MODULE_FIRMWARE("amdgpu/tonga_me.bin");
107MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
108MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
109MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
110
111MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
112MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
113MODULE_FIRMWARE("amdgpu/topaz_me.bin");
114MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
c65444fe 115MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97 116
af15a2d5
DZ		 117MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
118MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
119MODULE_FIRMWARE("amdgpu/fiji_me.bin");
120MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
121MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
122MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
123
2cc0c0b5
FC		 124MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
125MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
126MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
127MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
128MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
129MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
68182d90 130
2cc0c0b5
FC		 131MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
132MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
133MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
134MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
135MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
68182d90 137
aaa36a97
AD		 138static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
139{
140 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
141 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
142 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
143 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
144 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
145 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
146 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
147 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
148 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
149 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
150 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
151 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
152 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
153 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
154 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
155 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
156};
157
158static const u32 golden_settings_tonga_a11[] =
159{
160 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
161 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
162 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
163 mmGB_GPU_ID, 0x0000000f, 0x00000000,
164 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
165 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
166 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 167 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 168 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
169 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 170 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 171 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
172 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
173 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 174 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 175};
176
177static const u32 tonga_golden_common_all[] =
178{
179 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
180 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
181 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
182 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
183 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
184 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
185 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
186 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
187};
188
189static const u32 tonga_mgcg_cgcg_init[] =
190{
191 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
192 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
193 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
194 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
195 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
196 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
197 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
198 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
199 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
200 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
201 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
202 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
203 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
204 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
205 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
206 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
207 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
208 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
209 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
210 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
211 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
212 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
213 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
214 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
215 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
216 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
217 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
218 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
219 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
220 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
221 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
222 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
223 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
224 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
225 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
226 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
227 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
228 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
229 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
230 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
231 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
232 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
233 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
234 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
235 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
236 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
237 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
238 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
239 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
240 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
241 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
242 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
243 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
244 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
245 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
246 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
247 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
248 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
249 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
250 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
251 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
252 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
253 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
254 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
255 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
256 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
257 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
258 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
259 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
260 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
261 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
262 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
263 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
264 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
265 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
266};
267
2cc0c0b5 268static const u32 golden_settings_polaris11_a11[] =
68182d90
FC		 269{
270 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
271 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
272 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
273 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
274 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
275 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
276 mmSQ_CONFIG, 0x07f80000, 0x07180000,
277 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
278 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
279 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
280 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
281 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
282};
283
2cc0c0b5 284static const u32 polaris11_golden_common_all[] =
68182d90
FC		 285{
286 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
287 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
288 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
289 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
290 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
291 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
292 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
293 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
294};
295
2cc0c0b5 296static const u32 golden_settings_polaris10_a11[] =
68182d90
FC		 297{
298 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
299 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
300 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
301 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
302 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
303 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
304 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
305 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
306 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
307 mmSQ_CONFIG, 0x07f80000, 0x07180000,
308 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
309 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
310 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
311 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
312};
313
2cc0c0b5 314static const u32 polaris10_golden_common_all[] =
68182d90
FC		 315{
316 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
317 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
318 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
319 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
320 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
321 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
322 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
323 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
324};
325
af15a2d5
DZ		 326static const u32 fiji_golden_common_all[] =
327{
328 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
329 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
330 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
a7ca8ef9 331 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
af15a2d5
DZ		 332 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
333 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
a7ca8ef9
FC		 335 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
336 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
337 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
af15a2d5
DZ		 338};
339
340static const u32 golden_settings_fiji_a10[] =
341{
342 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
343 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
344 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
af15a2d5 345 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
a7ca8ef9
FC		 346 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
347 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
af15a2d5 348 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
a7ca8ef9
FC		 349 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
350 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
af15a2d5 351 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
a7ca8ef9 352 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
af15a2d5
DZ		 353};
354
355static const u32 fiji_mgcg_cgcg_init[] =
356{
a7ca8ef9 357 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
af15a2d5
DZ		 358 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
359 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
360 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
361 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
362 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
363 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
364 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
365 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
366 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
367 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
368 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
369 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
370 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
371 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
372 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
373 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
374 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
375 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
376 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
377 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
378 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
379 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
380 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
381 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
382 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
383 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
384 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
385 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
386 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
387 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
388 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
389 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
390 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
391 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
392};
393
aaa36a97
AD		 394static const u32 golden_settings_iceland_a11[] =
395{
396 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
397 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
398 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
399 mmGB_GPU_ID, 0x0000000f, 0x00000000,
400 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
401 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
402 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
403 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
6a00a09e 404 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 405 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
406 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 407 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 408 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
409 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
410 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
411};
412
413static const u32 iceland_golden_common_all[] =
414{
415 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
416 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
417 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
418 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
419 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
420 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
421 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
422 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
423};
424
425static const u32 iceland_mgcg_cgcg_init[] =
426{
427 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
428 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
429 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
430 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
431 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
432 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
433 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
434 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
435 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
436 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
438 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
441 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
445 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
446 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
447 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
448 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
449 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
450 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
452 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
453 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
454 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
455 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
456 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
457 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
458 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
459 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
460 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
461 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
462 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
463 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
464 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
465 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
466 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
467 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
468 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
469 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
470 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
471 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
472 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
473 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
474 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
475 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
476 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
477 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
478 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
479 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
480 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
481 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
482 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
483 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
484 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
485 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
486 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
487 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
488 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
489 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
490 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
491};
492
493static const u32 cz_golden_settings_a11[] =
494{
495 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
496 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
497 mmGB_GPU_ID, 0x0000000f, 0x00000000,
498 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
499 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 500 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 501 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
6a00a09e 502 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 503 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
504 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
505};
506
507static const u32 cz_golden_common_all[] =
508{
509 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
510 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
511 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
512 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
513 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
514 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
515 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
516 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
517};
518
519static const u32 cz_mgcg_cgcg_init[] =
520{
521 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
522 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
523 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
524 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
525 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
526 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
527 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
528 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
531 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
532 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
533 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
534 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
535 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
536 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
537 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
538 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
539 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
540 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
541 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
542 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
543 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
544 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
545 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
546 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
547 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
548 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
549 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
550 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
551 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
552 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
553 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
554 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
555 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
556 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
557 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
558 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
559 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
560 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
561 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
562 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
563 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
564 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
565 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
566 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
567 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
568 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
569 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
570 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
571 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
572 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
573 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
574 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
575 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
576 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
577 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
578 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
579 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
580 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
581 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
582 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
583 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
584 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
585 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
586 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
587 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
588 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
589 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
590 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
591 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
592 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
593 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
594 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
595 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
596};
597
e3c7656c
SL		 598static const u32 stoney_golden_settings_a11[] =
599{
600 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
601 mmGB_GPU_ID, 0x0000000f, 0x00000000,
602 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
603 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
604 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
605 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
edf600da 606 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
e3c7656c
SL		 607 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
608 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
609 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
610};
611
612static const u32 stoney_golden_common_all[] =
613{
614 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
615 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
616 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
617 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
618 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
619 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
620 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
621 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
622};
623
624static const u32 stoney_mgcg_cgcg_init[] =
625{
626 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
627 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
628 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
629 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
630 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
631 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
632};
633
aaa36a97
AD		 634static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
635static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
636static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
dbff57bc 637static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
2b6cd977 638static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
7dae69a2 639static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
aaa36a97
AD		 640
641static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
642{
643 switch (adev->asic_type) {
644 case CHIP_TOPAZ:
645 amdgpu_program_register_sequence(adev,
646 iceland_mgcg_cgcg_init,
647 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
648 amdgpu_program_register_sequence(adev,
649 golden_settings_iceland_a11,
650 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
651 amdgpu_program_register_sequence(adev,
652 iceland_golden_common_all,
653 (const u32)ARRAY_SIZE(iceland_golden_common_all));
654 break;
af15a2d5
DZ		 655 case CHIP_FIJI:
656 amdgpu_program_register_sequence(adev,
657 fiji_mgcg_cgcg_init,
658 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
659 amdgpu_program_register_sequence(adev,
660 golden_settings_fiji_a10,
661 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
662 amdgpu_program_register_sequence(adev,
663 fiji_golden_common_all,
664 (const u32)ARRAY_SIZE(fiji_golden_common_all));
665 break;
666
aaa36a97
AD		 667 case CHIP_TONGA:
668 amdgpu_program_register_sequence(adev,
669 tonga_mgcg_cgcg_init,
670 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
671 amdgpu_program_register_sequence(adev,
672 golden_settings_tonga_a11,
673 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
674 amdgpu_program_register_sequence(adev,
675 tonga_golden_common_all,
676 (const u32)ARRAY_SIZE(tonga_golden_common_all));
677 break;
2cc0c0b5 678 case CHIP_POLARIS11:
68182d90 679 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 680 golden_settings_polaris11_a11,
681 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
68182d90 682 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 683 polaris11_golden_common_all,
684 (const u32)ARRAY_SIZE(polaris11_golden_common_all));
68182d90 685 break;
2cc0c0b5 686 case CHIP_POLARIS10:
68182d90 687 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 688 golden_settings_polaris10_a11,
689 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
68182d90 690 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 691 polaris10_golden_common_all,
692 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
68182d90 693 break;
aaa36a97
AD		 694 case CHIP_CARRIZO:
695 amdgpu_program_register_sequence(adev,
696 cz_mgcg_cgcg_init,
697 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
698 amdgpu_program_register_sequence(adev,
699 cz_golden_settings_a11,
700 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
701 amdgpu_program_register_sequence(adev,
702 cz_golden_common_all,
703 (const u32)ARRAY_SIZE(cz_golden_common_all));
704 break;
e3c7656c
SL		 705 case CHIP_STONEY:
706 amdgpu_program_register_sequence(adev,
707 stoney_mgcg_cgcg_init,
708 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
709 amdgpu_program_register_sequence(adev,
710 stoney_golden_settings_a11,
711 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
712 amdgpu_program_register_sequence(adev,
713 stoney_golden_common_all,
714 (const u32)ARRAY_SIZE(stoney_golden_common_all));
715 break;
aaa36a97
AD		 716 default:
717 break;
718 }
719}
720
721static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
722{
723 int i;
724
725 adev->gfx.scratch.num_reg = 7;
726 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
727 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
728 adev->gfx.scratch.free[i] = true;
729 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
730 }
731}
732
733static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
734{
735 struct amdgpu_device *adev = ring->adev;
736 uint32_t scratch;
737 uint32_t tmp = 0;
738 unsigned i;
739 int r;
740
741 r = amdgpu_gfx_scratch_get(adev, &scratch);
742 if (r) {
743 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
744 return r;
745 }
746 WREG32(scratch, 0xCAFEDEAD);
a27de35c 747 r = amdgpu_ring_alloc(ring, 3);
aaa36a97
AD		 748 if (r) {
749 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
750 ring->idx, r);
751 amdgpu_gfx_scratch_free(adev, scratch);
752 return r;
753 }
754 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
755 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
756 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 757 amdgpu_ring_commit(ring);
aaa36a97
AD		 758
759 for (i = 0; i < adev->usec_timeout; i++) {
760 tmp = RREG32(scratch);
761 if (tmp == 0xDEADBEEF)
762 break;
763 DRM_UDELAY(1);
764 }
765 if (i < adev->usec_timeout) {
766 DRM_INFO("ring test on %d succeeded in %d usecs\n",
767 ring->idx, i);
768 } else {
769 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
770 ring->idx, scratch, tmp);
771 r = -EINVAL;
772 }
773 amdgpu_gfx_scratch_free(adev, scratch);
774 return r;
775}
776
777static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
778{
779 struct amdgpu_device *adev = ring->adev;
780 struct amdgpu_ib ib;
1763552e 781 struct fence *f = NULL;
aaa36a97
AD		 782 uint32_t scratch;
783 uint32_t tmp = 0;
784 unsigned i;
785 int r;
786
787 r = amdgpu_gfx_scratch_get(adev, &scratch);
788 if (r) {
789 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
790 return r;
791 }
792 WREG32(scratch, 0xCAFEDEAD);
b203dd95 793 memset(&ib, 0, sizeof(ib));
b07c60c0 794 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97
AD		 795 if (r) {
796 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 797 goto err1;
aaa36a97
AD		 798 }
799 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
800 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
801 ib.ptr[2] = 0xDEADBEEF;
802 ib.length_dw = 3;
42d13693 803
c5637837 804 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
42d13693
CZ		 805 if (r)
806 goto err2;
807
1763552e 808 r = fence_wait(f, false);
aaa36a97
AD		 809 if (r) {
810 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 811 goto err2;
aaa36a97
AD		 812 }
813 for (i = 0; i < adev->usec_timeout; i++) {
814 tmp = RREG32(scratch);
815 if (tmp == 0xDEADBEEF)
816 break;
817 DRM_UDELAY(1);
818 }
819 if (i < adev->usec_timeout) {
820 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 821 ring->idx, i);
822 goto err2;
aaa36a97
AD		 823 } else {
824 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
825 scratch, tmp);
826 r = -EINVAL;
827 }
42d13693 828err2:
281b4223 829 fence_put(f);
cc55c45d 830 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 831 fence_put(f);
42d13693
CZ		 832err1:
833 amdgpu_gfx_scratch_free(adev, scratch);
aaa36a97
AD		 834 return r;
835}
836
837static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
838{
839 const char *chip_name;
840 char fw_name[30];
841 int err;
842 struct amdgpu_firmware_info *info = NULL;
843 const struct common_firmware_header *header = NULL;
595fd013 844 const struct gfx_firmware_header_v1_0 *cp_hdr;
2b6cd977
EH		 845 const struct rlc_firmware_header_v2_0 *rlc_hdr;
846 unsigned int *tmp = NULL, i;
aaa36a97
AD		 847
848 DRM_DEBUG("\n");
849
850 switch (adev->asic_type) {
851 case CHIP_TOPAZ:
852 chip_name = "topaz";
853 break;
854 case CHIP_TONGA:
855 chip_name = "tonga";
856 break;
857 case CHIP_CARRIZO:
858 chip_name = "carrizo";
859 break;
af15a2d5
DZ		 860 case CHIP_FIJI:
861 chip_name = "fiji";
862 break;
2cc0c0b5
FC		 863 case CHIP_POLARIS11:
864 chip_name = "polaris11";
68182d90 865 break;
2cc0c0b5
FC		 866 case CHIP_POLARIS10:
867 chip_name = "polaris10";
68182d90 868 break;
e3c7656c
SL		 869 case CHIP_STONEY:
870 chip_name = "stoney";
871 break;
aaa36a97
AD		 872 default:
873 BUG();
874 }
875
c65444fe 876 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 877 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
878 if (err)
879 goto out;
880 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
881 if (err)
882 goto out;
595fd013
JZ		 883 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
884 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
885 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 886
c65444fe 887 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 888 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
889 if (err)
890 goto out;
891 err = amdgpu_ucode_validate(adev->gfx.me_fw);
892 if (err)
893 goto out;
595fd013
JZ		 894 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
895 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
896 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 897
c65444fe 898 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 899 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
900 if (err)
901 goto out;
902 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
903 if (err)
904 goto out;
595fd013
JZ		 905 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
906 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
907 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 908
c65444fe 909 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 910 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
911 if (err)
912 goto out;
913 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
2b6cd977
EH		 914 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
915 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
916 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
917
918 adev->gfx.rlc.save_and_restore_offset =
919 le32_to_cpu(rlc_hdr->save_and_restore_offset);
920 adev->gfx.rlc.clear_state_descriptor_offset =
921 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
922 adev->gfx.rlc.avail_scratch_ram_locations =
923 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
924 adev->gfx.rlc.reg_restore_list_size =
925 le32_to_cpu(rlc_hdr->reg_restore_list_size);
926 adev->gfx.rlc.reg_list_format_start =
927 le32_to_cpu(rlc_hdr->reg_list_format_start);
928 adev->gfx.rlc.reg_list_format_separate_start =
929 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
930 adev->gfx.rlc.starting_offsets_start =
931 le32_to_cpu(rlc_hdr->starting_offsets_start);
932 adev->gfx.rlc.reg_list_format_size_bytes =
933 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
934 adev->gfx.rlc.reg_list_size_bytes =
935 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
936
937 adev->gfx.rlc.register_list_format =
938 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
939 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
940
941 if (!adev->gfx.rlc.register_list_format) {
942 err = -ENOMEM;
943 goto out;
944 }
945
ae17c999 946 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
2b6cd977
EH		 947 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
948 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
949 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
950
951 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
952
ae17c999 953 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
2b6cd977
EH		 954 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
955 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
956 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
aaa36a97 957
c65444fe 958 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 959 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
963 if (err)
964 goto out;
595fd013
JZ		 965 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
966 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
967 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 968
97dde76a
AD		 969 if ((adev->asic_type != CHIP_STONEY) &&
970 (adev->asic_type != CHIP_TOPAZ)) {
e3c7656c
SL		 971 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
972 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
973 if (!err) {
974 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
975 if (err)
976 goto out;
977 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
978 adev->gfx.mec2_fw->data;
979 adev->gfx.mec2_fw_version =
980 le32_to_cpu(cp_hdr->header.ucode_version);
981 adev->gfx.mec2_feature_version =
982 le32_to_cpu(cp_hdr->ucode_feature_version);
983 } else {
984 err = 0;
985 adev->gfx.mec2_fw = NULL;
986 }
aaa36a97
AD		 987 }
988
989 if (adev->firmware.smu_load) {
990 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
991 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
992 info->fw = adev->gfx.pfp_fw;
993 header = (const struct common_firmware_header *)info->fw->data;
994 adev->firmware.fw_size +=
995 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
996
997 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
998 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
999 info->fw = adev->gfx.me_fw;
1000 header = (const struct common_firmware_header *)info->fw->data;
1001 adev->firmware.fw_size +=
1002 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1003
1004 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1005 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1006 info->fw = adev->gfx.ce_fw;
1007 header = (const struct common_firmware_header *)info->fw->data;
1008 adev->firmware.fw_size +=
1009 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1010
1011 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1012 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1013 info->fw = adev->gfx.rlc_fw;
1014 header = (const struct common_firmware_header *)info->fw->data;
1015 adev->firmware.fw_size +=
1016 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1017
1018 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1019 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1020 info->fw = adev->gfx.mec_fw;
1021 header = (const struct common_firmware_header *)info->fw->data;
1022 adev->firmware.fw_size +=
1023 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1024
1025 if (adev->gfx.mec2_fw) {
1026 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1027 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1028 info->fw = adev->gfx.mec2_fw;
1029 header = (const struct common_firmware_header *)info->fw->data;
1030 adev->firmware.fw_size +=
1031 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1032 }
1033
1034 }
1035
1036out:
1037 if (err) {
1038 dev_err(adev->dev,
1039 "gfx8: Failed to load firmware \"%s\"\n",
1040 fw_name);
1041 release_firmware(adev->gfx.pfp_fw);
1042 adev->gfx.pfp_fw = NULL;
1043 release_firmware(adev->gfx.me_fw);
1044 adev->gfx.me_fw = NULL;
1045 release_firmware(adev->gfx.ce_fw);
1046 adev->gfx.ce_fw = NULL;
1047 release_firmware(adev->gfx.rlc_fw);
1048 adev->gfx.rlc_fw = NULL;
1049 release_firmware(adev->gfx.mec_fw);
1050 adev->gfx.mec_fw = NULL;
1051 release_firmware(adev->gfx.mec2_fw);
1052 adev->gfx.mec2_fw = NULL;
1053 }
1054 return err;
1055}
1056
2b6cd977
EH		 1057static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1058 volatile u32 *buffer)
1059{
1060 u32 count = 0, i;
1061 const struct cs_section_def *sect = NULL;
1062 const struct cs_extent_def *ext = NULL;
1063
1064 if (adev->gfx.rlc.cs_data == NULL)
1065 return;
1066 if (buffer == NULL)
1067 return;
1068
1069 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1070 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1071
1072 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1073 buffer[count++] = cpu_to_le32(0x80000000);
1074 buffer[count++] = cpu_to_le32(0x80000000);
1075
1076 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1077 for (ext = sect->section; ext->extent != NULL; ++ext) {
1078 if (sect->id == SECT_CONTEXT) {
1079 buffer[count++] =
1080 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1081 buffer[count++] = cpu_to_le32(ext->reg_index -
1082 PACKET3_SET_CONTEXT_REG_START);
1083 for (i = 0; i < ext->reg_count; i++)
1084 buffer[count++] = cpu_to_le32(ext->extent[i]);
1085 } else {
1086 return;
1087 }
1088 }
1089 }
1090
1091 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1092 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1093 PACKET3_SET_CONTEXT_REG_START);
1094 switch (adev->asic_type) {
1095 case CHIP_TONGA:
2cc0c0b5 1096 case CHIP_POLARIS10:
2b6cd977
EH		 1097 buffer[count++] = cpu_to_le32(0x16000012);
1098 buffer[count++] = cpu_to_le32(0x0000002A);
1099 break;
2cc0c0b5 1100 case CHIP_POLARIS11:
f4bfffdd
EH		 1101 buffer[count++] = cpu_to_le32(0x16000012);
1102 buffer[count++] = cpu_to_le32(0x00000000);
1103 break;
2b6cd977
EH		 1104 case CHIP_FIJI:
1105 buffer[count++] = cpu_to_le32(0x3a00161a);
1106 buffer[count++] = cpu_to_le32(0x0000002e);
1107 break;
1108 case CHIP_TOPAZ:
1109 case CHIP_CARRIZO:
1110 buffer[count++] = cpu_to_le32(0x00000002);
1111 buffer[count++] = cpu_to_le32(0x00000000);
1112 break;
1113 case CHIP_STONEY:
1114 buffer[count++] = cpu_to_le32(0x00000000);
1115 buffer[count++] = cpu_to_le32(0x00000000);
1116 break;
1117 default:
1118 buffer[count++] = cpu_to_le32(0x00000000);
1119 buffer[count++] = cpu_to_le32(0x00000000);
1120 break;
1121 }
1122
1123 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1124 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1125
1126 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1127 buffer[count++] = cpu_to_le32(0);
1128}
1129
1130static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
1131{
1132 int r;
1133
1134 /* clear state block */
1135 if (adev->gfx.rlc.clear_state_obj) {
1136 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1137 if (unlikely(r != 0))
1138 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
1139 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1140 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1141
1142 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
1143 adev->gfx.rlc.clear_state_obj = NULL;
1144 }
1145}
1146
1147static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1148{
1149 volatile u32 *dst_ptr;
1150 u32 dws;
1151 const struct cs_section_def *cs_data;
1152 int r;
1153
1154 adev->gfx.rlc.cs_data = vi_cs_data;
1155
1156 cs_data = adev->gfx.rlc.cs_data;
1157
1158 if (cs_data) {
1159 /* clear state block */
1160 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev);
1161
1162 if (adev->gfx.rlc.clear_state_obj == NULL) {
1163 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
1164 AMDGPU_GEM_DOMAIN_VRAM,
1165 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1166 NULL, NULL,
1167 &adev->gfx.rlc.clear_state_obj);
1168 if (r) {
1169 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
1170 gfx_v8_0_rlc_fini(adev);
1171 return r;
1172 }
1173 }
1174 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1175 if (unlikely(r != 0)) {
1176 gfx_v8_0_rlc_fini(adev);
1177 return r;
1178 }
1179 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
1180 &adev->gfx.rlc.clear_state_gpu_addr);
1181 if (r) {
1182 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1183 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
1184 gfx_v8_0_rlc_fini(adev);
1185 return r;
1186 }
1187
1188 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
1189 if (r) {
1190 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
1191 gfx_v8_0_rlc_fini(adev);
1192 return r;
1193 }
1194 /* set up the cs buffer */
1195 dst_ptr = adev->gfx.rlc.cs_ptr;
1196 gfx_v8_0_get_csb_buffer(adev, dst_ptr);
1197 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1198 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1199 }
1200
1201 return 0;
1202}
1203
aaa36a97
AD		 1204static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1205{
1206 int r;
1207
1208 if (adev->gfx.mec.hpd_eop_obj) {
1209 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1210 if (unlikely(r != 0))
1211 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
1212 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
1213 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1214
1215 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
1216 adev->gfx.mec.hpd_eop_obj = NULL;
1217 }
1218}
1219
1220#define MEC_HPD_SIZE 2048
1221
1222static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1223{
1224 int r;
1225 u32 *hpd;
1226
1227 /*
1228 * we assign only 1 pipe because all other pipes will
1229 * be handled by KFD
1230 */
1231 adev->gfx.mec.num_mec = 1;
1232 adev->gfx.mec.num_pipe = 1;
1233 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
1234
1235 if (adev->gfx.mec.hpd_eop_obj == NULL) {
1236 r = amdgpu_bo_create(adev,
1237 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
1238 PAGE_SIZE, true,
72d7668b 1239 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
aaa36a97
AD		 1240 &adev->gfx.mec.hpd_eop_obj);
1241 if (r) {
1242 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1243 return r;
1244 }
1245 }
1246
1247 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
1248 if (unlikely(r != 0)) {
1249 gfx_v8_0_mec_fini(adev);
1250 return r;
1251 }
1252 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
1253 &adev->gfx.mec.hpd_eop_gpu_addr);
1254 if (r) {
1255 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
1256 gfx_v8_0_mec_fini(adev);
1257 return r;
1258 }
1259 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
1260 if (r) {
1261 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
1262 gfx_v8_0_mec_fini(adev);
1263 return r;
1264 }
1265
1266 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
1267
1268 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1269 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1270
1271 return 0;
1272}
1273
ccba7691
AD		 1274static const u32 vgpr_init_compute_shader[] =
1275{
1276 0x7e000209, 0x7e020208,
1277 0x7e040207, 0x7e060206,
1278 0x7e080205, 0x7e0a0204,
1279 0x7e0c0203, 0x7e0e0202,
1280 0x7e100201, 0x7e120200,
1281 0x7e140209, 0x7e160208,
1282 0x7e180207, 0x7e1a0206,
1283 0x7e1c0205, 0x7e1e0204,
1284 0x7e200203, 0x7e220202,
1285 0x7e240201, 0x7e260200,
1286 0x7e280209, 0x7e2a0208,
1287 0x7e2c0207, 0x7e2e0206,
1288 0x7e300205, 0x7e320204,
1289 0x7e340203, 0x7e360202,
1290 0x7e380201, 0x7e3a0200,
1291 0x7e3c0209, 0x7e3e0208,
1292 0x7e400207, 0x7e420206,
1293 0x7e440205, 0x7e460204,
1294 0x7e480203, 0x7e4a0202,
1295 0x7e4c0201, 0x7e4e0200,
1296 0x7e500209, 0x7e520208,
1297 0x7e540207, 0x7e560206,
1298 0x7e580205, 0x7e5a0204,
1299 0x7e5c0203, 0x7e5e0202,
1300 0x7e600201, 0x7e620200,
1301 0x7e640209, 0x7e660208,
1302 0x7e680207, 0x7e6a0206,
1303 0x7e6c0205, 0x7e6e0204,
1304 0x7e700203, 0x7e720202,
1305 0x7e740201, 0x7e760200,
1306 0x7e780209, 0x7e7a0208,
1307 0x7e7c0207, 0x7e7e0206,
1308 0xbf8a0000, 0xbf810000,
1309};
1310
1311static const u32 sgpr_init_compute_shader[] =
1312{
1313 0xbe8a0100, 0xbe8c0102,
1314 0xbe8e0104, 0xbe900106,
1315 0xbe920108, 0xbe940100,
1316 0xbe960102, 0xbe980104,
1317 0xbe9a0106, 0xbe9c0108,
1318 0xbe9e0100, 0xbea00102,
1319 0xbea20104, 0xbea40106,
1320 0xbea60108, 0xbea80100,
1321 0xbeaa0102, 0xbeac0104,
1322 0xbeae0106, 0xbeb00108,
1323 0xbeb20100, 0xbeb40102,
1324 0xbeb60104, 0xbeb80106,
1325 0xbeba0108, 0xbebc0100,
1326 0xbebe0102, 0xbec00104,
1327 0xbec20106, 0xbec40108,
1328 0xbec60100, 0xbec80102,
1329 0xbee60004, 0xbee70005,
1330 0xbeea0006, 0xbeeb0007,
1331 0xbee80008, 0xbee90009,
1332 0xbefc0000, 0xbf8a0000,
1333 0xbf810000, 0x00000000,
1334};
1335
1336static const u32 vgpr_init_regs[] =
1337{
1338 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1339 mmCOMPUTE_RESOURCE_LIMITS, 0,
1340 mmCOMPUTE_NUM_THREAD_X, 256*4,
1341 mmCOMPUTE_NUM_THREAD_Y, 1,
1342 mmCOMPUTE_NUM_THREAD_Z, 1,
1343 mmCOMPUTE_PGM_RSRC2, 20,
1344 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1345 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1346 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1347 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1348 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1349 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1350 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1351 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1352 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1353 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1354};
1355
1356static const u32 sgpr1_init_regs[] =
1357{
1358 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1359 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1360 mmCOMPUTE_NUM_THREAD_X, 256*5,
1361 mmCOMPUTE_NUM_THREAD_Y, 1,
1362 mmCOMPUTE_NUM_THREAD_Z, 1,
1363 mmCOMPUTE_PGM_RSRC2, 20,
1364 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1365 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1366 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1367 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1368 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1369 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1370 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1371 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1372 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1373 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1374};
1375
1376static const u32 sgpr2_init_regs[] =
1377{
1378 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1379 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1380 mmCOMPUTE_NUM_THREAD_X, 256*5,
1381 mmCOMPUTE_NUM_THREAD_Y, 1,
1382 mmCOMPUTE_NUM_THREAD_Z, 1,
1383 mmCOMPUTE_PGM_RSRC2, 20,
1384 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1385 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1386 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1387 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1388 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1389 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1390 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1391 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1392 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1393 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1394};
1395
1396static const u32 sec_ded_counter_registers[] =
1397{
1398 mmCPC_EDC_ATC_CNT,
1399 mmCPC_EDC_SCRATCH_CNT,
1400 mmCPC_EDC_UCODE_CNT,
1401 mmCPF_EDC_ATC_CNT,
1402 mmCPF_EDC_ROQ_CNT,
1403 mmCPF_EDC_TAG_CNT,
1404 mmCPG_EDC_ATC_CNT,
1405 mmCPG_EDC_DMA_CNT,
1406 mmCPG_EDC_TAG_CNT,
1407 mmDC_EDC_CSINVOC_CNT,
1408 mmDC_EDC_RESTORE_CNT,
1409 mmDC_EDC_STATE_CNT,
1410 mmGDS_EDC_CNT,
1411 mmGDS_EDC_GRBM_CNT,
1412 mmGDS_EDC_OA_DED,
1413 mmSPI_EDC_CNT,
1414 mmSQC_ATC_EDC_GATCL1_CNT,
1415 mmSQC_EDC_CNT,
1416 mmSQ_EDC_DED_CNT,
1417 mmSQ_EDC_INFO,
1418 mmSQ_EDC_SEC_CNT,
1419 mmTCC_EDC_CNT,
1420 mmTCP_ATC_EDC_GATCL1_CNT,
1421 mmTCP_EDC_CNT,
1422 mmTD_EDC_CNT
1423};
1424
1425static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1426{
1427 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1428 struct amdgpu_ib ib;
1429 struct fence *f = NULL;
1430 int r, i;
1431 u32 tmp;
1432 unsigned total_size, vgpr_offset, sgpr_offset;
1433 u64 gpu_addr;
1434
1435 /* only supported on CZ */
1436 if (adev->asic_type != CHIP_CARRIZO)
1437 return 0;
1438
1439 /* bail if the compute ring is not ready */
1440 if (!ring->ready)
1441 return 0;
1442
1443 tmp = RREG32(mmGB_EDC_MODE);
1444 WREG32(mmGB_EDC_MODE, 0);
1445
1446 total_size =
1447 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1448 total_size +=
1449 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1450 total_size +=
1451 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1452 total_size = ALIGN(total_size, 256);
1453 vgpr_offset = total_size;
1454 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1455 sgpr_offset = total_size;
1456 total_size += sizeof(sgpr_init_compute_shader);
1457
1458 /* allocate an indirect buffer to put the commands in */
1459 memset(&ib, 0, sizeof(ib));
b07c60c0 1460 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
ccba7691
AD		 1461 if (r) {
1462 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1463 return r;
1464 }
1465
1466 /* load the compute shaders */
1467 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1468 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1469
1470 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1471 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1472
1473 /* init the ib length to 0 */
1474 ib.length_dw = 0;
1475
1476 /* VGPR */
1477 /* write the register state for the compute dispatch */
1478 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1479 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1480 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1481 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1482 }
1483 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1484 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1485 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1486 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1487 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1488 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1489
1490 /* write dispatch packet */
1491 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1492 ib.ptr[ib.length_dw++] = 8; /* x */
1493 ib.ptr[ib.length_dw++] = 1; /* y */
1494 ib.ptr[ib.length_dw++] = 1; /* z */
1495 ib.ptr[ib.length_dw++] =
1496 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1497
1498 /* write CS partial flush packet */
1499 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1500 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1501
1502 /* SGPR1 */
1503 /* write the register state for the compute dispatch */
1504 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1505 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1506 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1507 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1508 }
1509 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1510 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1511 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1512 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1513 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1514 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1515
1516 /* write dispatch packet */
1517 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1518 ib.ptr[ib.length_dw++] = 8; /* x */
1519 ib.ptr[ib.length_dw++] = 1; /* y */
1520 ib.ptr[ib.length_dw++] = 1; /* z */
1521 ib.ptr[ib.length_dw++] =
1522 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1523
1524 /* write CS partial flush packet */
1525 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1526 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1527
1528 /* SGPR2 */
1529 /* write the register state for the compute dispatch */
1530 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1531 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1532 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1533 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1534 }
1535 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1536 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1537 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1538 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1539 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1540 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1541
1542 /* write dispatch packet */
1543 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1544 ib.ptr[ib.length_dw++] = 8; /* x */
1545 ib.ptr[ib.length_dw++] = 1; /* y */
1546 ib.ptr[ib.length_dw++] = 1; /* z */
1547 ib.ptr[ib.length_dw++] =
1548 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1549
1550 /* write CS partial flush packet */
1551 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1552 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1553
1554 /* shedule the ib on the ring */
c5637837 1555 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
ccba7691
AD		 1556 if (r) {
1557 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1558 goto fail;
1559 }
1560
1561 /* wait for the GPU to finish processing the IB */
1562 r = fence_wait(f, false);
1563 if (r) {
1564 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1565 goto fail;
1566 }
1567
1568 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1569 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1570 WREG32(mmGB_EDC_MODE, tmp);
1571
1572 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1573 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1574 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1575
1576
1577 /* read back registers to clear the counters */
1578 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1579 RREG32(sec_ded_counter_registers[i]);
1580
1581fail:
1582 fence_put(f);
cc55c45d 1583 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 1584 fence_put(f);
ccba7691
AD		 1585
1586 return r;
1587}
1588
68182d90 1589static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
0bde3a95
AD		 1590{
1591 u32 gb_addr_config;
1592 u32 mc_shared_chmap, mc_arb_ramcfg;
1593 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1594 u32 tmp;
68182d90 1595 int ret;
0bde3a95
AD		 1596
1597 switch (adev->asic_type) {
1598 case CHIP_TOPAZ:
1599 adev->gfx.config.max_shader_engines = 1;
1600 adev->gfx.config.max_tile_pipes = 2;
1601 adev->gfx.config.max_cu_per_sh = 6;
1602 adev->gfx.config.max_sh_per_se = 1;
1603 adev->gfx.config.max_backends_per_se = 2;
1604 adev->gfx.config.max_texture_channel_caches = 2;
1605 adev->gfx.config.max_gprs = 256;
1606 adev->gfx.config.max_gs_threads = 32;
1607 adev->gfx.config.max_hw_contexts = 8;
1608
1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1613 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1614 break;
1615 case CHIP_FIJI:
1616 adev->gfx.config.max_shader_engines = 4;
1617 adev->gfx.config.max_tile_pipes = 16;
1618 adev->gfx.config.max_cu_per_sh = 16;
1619 adev->gfx.config.max_sh_per_se = 1;
1620 adev->gfx.config.max_backends_per_se = 4;
5f2e816b 1621 adev->gfx.config.max_texture_channel_caches = 16;
0bde3a95
AD		 1622 adev->gfx.config.max_gprs = 256;
1623 adev->gfx.config.max_gs_threads = 32;
1624 adev->gfx.config.max_hw_contexts = 8;
1625
68182d90
FC		 1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1630 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1631 break;
2cc0c0b5 1632 case CHIP_POLARIS11:
68182d90
FC		 1633 ret = amdgpu_atombios_get_gfx_info(adev);
1634 if (ret)
1635 return ret;
1636 adev->gfx.config.max_gprs = 256;
1637 adev->gfx.config.max_gs_threads = 32;
1638 adev->gfx.config.max_hw_contexts = 8;
1639
1640 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1641 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1642 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1643 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2cc0c0b5 1644 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
68182d90 1645 break;
2cc0c0b5 1646 case CHIP_POLARIS10:
68182d90
FC		 1647 ret = amdgpu_atombios_get_gfx_info(adev);
1648 if (ret)
1649 return ret;
1650 adev->gfx.config.max_gprs = 256;
1651 adev->gfx.config.max_gs_threads = 32;
1652 adev->gfx.config.max_hw_contexts = 8;
1653
0bde3a95
AD		 1654 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1655 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1656 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1657 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1658 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1659 break;
1660 case CHIP_TONGA:
1661 adev->gfx.config.max_shader_engines = 4;
1662 adev->gfx.config.max_tile_pipes = 8;
1663 adev->gfx.config.max_cu_per_sh = 8;
1664 adev->gfx.config.max_sh_per_se = 1;
1665 adev->gfx.config.max_backends_per_se = 2;
1666 adev->gfx.config.max_texture_channel_caches = 8;
1667 adev->gfx.config.max_gprs = 256;
1668 adev->gfx.config.max_gs_threads = 32;
1669 adev->gfx.config.max_hw_contexts = 8;
1670
1671 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1672 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1673 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1674 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1675 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1676 break;
1677 case CHIP_CARRIZO:
1678 adev->gfx.config.max_shader_engines = 1;
1679 adev->gfx.config.max_tile_pipes = 2;
1680 adev->gfx.config.max_sh_per_se = 1;
1681 adev->gfx.config.max_backends_per_se = 2;
1682
1683 switch (adev->pdev->revision) {
1684 case 0xc4:
1685 case 0x84:
1686 case 0xc8:
1687 case 0xcc:
b8b339ea
AD		 1688 case 0xe1:
1689 case 0xe3:
0bde3a95
AD		 1690 /* B10 */
1691 adev->gfx.config.max_cu_per_sh = 8;
1692 break;
1693 case 0xc5:
1694 case 0x81:
1695 case 0x85:
1696 case 0xc9:
1697 case 0xcd:
b8b339ea
AD		 1698 case 0xe2:
1699 case 0xe4:
0bde3a95
AD		 1700 /* B8 */
1701 adev->gfx.config.max_cu_per_sh = 6;
1702 break;
1703 case 0xc6:
1704 case 0xca:
1705 case 0xce:
b8b339ea 1706 case 0x88:
0bde3a95
AD		 1707 /* B6 */
1708 adev->gfx.config.max_cu_per_sh = 6;
1709 break;
1710 case 0xc7:
1711 case 0x87:
1712 case 0xcb:
b8b339ea
AD		 1713 case 0xe5:
1714 case 0x89:
0bde3a95
AD		 1715 default:
1716 /* B4 */
1717 adev->gfx.config.max_cu_per_sh = 4;
1718 break;
1719 }
1720
1721 adev->gfx.config.max_texture_channel_caches = 2;
1722 adev->gfx.config.max_gprs = 256;
1723 adev->gfx.config.max_gs_threads = 32;
1724 adev->gfx.config.max_hw_contexts = 8;
1725
e3c7656c
SL		 1726 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1727 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1728 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1729 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1730 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1731 break;
1732 case CHIP_STONEY:
1733 adev->gfx.config.max_shader_engines = 1;
1734 adev->gfx.config.max_tile_pipes = 2;
1735 adev->gfx.config.max_sh_per_se = 1;
1736 adev->gfx.config.max_backends_per_se = 1;
1737
1738 switch (adev->pdev->revision) {
1739 case 0xc0:
1740 case 0xc1:
1741 case 0xc2:
1742 case 0xc4:
1743 case 0xc8:
1744 case 0xc9:
1745 adev->gfx.config.max_cu_per_sh = 3;
1746 break;
1747 case 0xd0:
1748 case 0xd1:
1749 case 0xd2:
1750 default:
1751 adev->gfx.config.max_cu_per_sh = 2;
1752 break;
1753 }
1754
1755 adev->gfx.config.max_texture_channel_caches = 2;
1756 adev->gfx.config.max_gprs = 256;
1757 adev->gfx.config.max_gs_threads = 16;
1758 adev->gfx.config.max_hw_contexts = 8;
1759
0bde3a95
AD		 1760 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1761 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1762 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1763 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1764 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1765 break;
1766 default:
1767 adev->gfx.config.max_shader_engines = 2;
1768 adev->gfx.config.max_tile_pipes = 4;
1769 adev->gfx.config.max_cu_per_sh = 2;
1770 adev->gfx.config.max_sh_per_se = 1;
1771 adev->gfx.config.max_backends_per_se = 2;
1772 adev->gfx.config.max_texture_channel_caches = 4;
1773 adev->gfx.config.max_gprs = 256;
1774 adev->gfx.config.max_gs_threads = 32;
1775 adev->gfx.config.max_hw_contexts = 8;
1776
1777 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1778 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1779 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1780 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1781 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1782 break;
1783 }
1784
1785 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1786 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1787 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1788
1789 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1790 adev->gfx.config.mem_max_burst_length_bytes = 256;
1791 if (adev->flags & AMD_IS_APU) {
1792 /* Get memory bank mapping mode. */
1793 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1794 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1795 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1796
1797 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1798 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1799 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1800
1801 /* Validate settings in case only one DIMM installed. */
1802 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1803 dimm00_addr_map = 0;
1804 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1805 dimm01_addr_map = 0;
1806 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1807 dimm10_addr_map = 0;
1808 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1809 dimm11_addr_map = 0;
1810
1811 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1812 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1813 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1814 adev->gfx.config.mem_row_size_in_kb = 2;
1815 else
1816 adev->gfx.config.mem_row_size_in_kb = 1;
1817 } else {
1818 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1819 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1820 if (adev->gfx.config.mem_row_size_in_kb > 4)
1821 adev->gfx.config.mem_row_size_in_kb = 4;
1822 }
1823
1824 adev->gfx.config.shader_engine_tile_size = 32;
1825 adev->gfx.config.num_gpus = 1;
1826 adev->gfx.config.multi_gpu_tile_size = 64;
1827
1828 /* fix up row size */
1829 switch (adev->gfx.config.mem_row_size_in_kb) {
1830 case 1:
1831 default:
1832 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1833 break;
1834 case 2:
1835 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1836 break;
1837 case 4:
1838 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1839 break;
1840 }
1841 adev->gfx.config.gb_addr_config = gb_addr_config;
68182d90
FC		 1842
1843 return 0;
0bde3a95
AD		 1844}
1845
5fc3aeeb 1846static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 1847{
1848 int i, r;
1849 struct amdgpu_ring *ring;
5fc3aeeb 1850 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1851
1852 /* EOP Event */
1853 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1854 if (r)
1855 return r;
1856
1857 /* Privileged reg */
1858 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1859 if (r)
1860 return r;
1861
1862 /* Privileged inst */
1863 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1864 if (r)
1865 return r;
1866
1867 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1868
1869 gfx_v8_0_scratch_init(adev);
1870
1871 r = gfx_v8_0_init_microcode(adev);
1872 if (r) {
1873 DRM_ERROR("Failed to load gfx firmware!\n");
1874 return r;
1875 }
1876
2b6cd977
EH		 1877 r = gfx_v8_0_rlc_init(adev);
1878 if (r) {
1879 DRM_ERROR("Failed to init rlc BOs!\n");
1880 return r;
1881 }
1882
aaa36a97
AD		 1883 r = gfx_v8_0_mec_init(adev);
1884 if (r) {
1885 DRM_ERROR("Failed to init MEC BOs!\n");
1886 return r;
1887 }
1888
aaa36a97
AD		 1889 /* set up the gfx ring */
1890 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1891 ring = &adev->gfx.gfx_ring[i];
1892 ring->ring_obj = NULL;
1893 sprintf(ring->name, "gfx");
1894 /* no gfx doorbells on iceland */
1895 if (adev->asic_type != CHIP_TOPAZ) {
1896 ring->use_doorbell = true;
1897 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1898 }
1899
2800de2e 1900 r = amdgpu_ring_init(adev, ring, 1024,
aaa36a97
AD		 1901 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1902 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1903 AMDGPU_RING_TYPE_GFX);
1904 if (r)
1905 return r;
1906 }
1907
1908 /* set up the compute queues */
1909 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1910 unsigned irq_type;
1911
1912 /* max 32 queues per MEC */
1913 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1914 DRM_ERROR("Too many (%d) compute rings!\n", i);
1915 break;
1916 }
1917 ring = &adev->gfx.compute_ring[i];
1918 ring->ring_obj = NULL;
1919 ring->use_doorbell = true;
1920 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1921 ring->me = 1; /* first MEC */
1922 ring->pipe = i / 8;
1923 ring->queue = i % 8;
771c8ec1 1924 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
aaa36a97
AD		 1925 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1926 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 1927 r = amdgpu_ring_init(adev, ring, 1024,
aaa36a97
AD		 1928 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1929 &adev->gfx.eop_irq, irq_type,
1930 AMDGPU_RING_TYPE_COMPUTE);
1931 if (r)
1932 return r;
1933 }
1934
1935 /* reserve GDS, GWS and OA resource for gfx */
1936 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1937 PAGE_SIZE, true,
72d7668b 1938 AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
aaa36a97
AD		 1939 NULL, &adev->gds.gds_gfx_bo);
1940 if (r)
1941 return r;
1942
1943 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1944 PAGE_SIZE, true,
72d7668b 1945 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
aaa36a97
AD		 1946 NULL, &adev->gds.gws_gfx_bo);
1947 if (r)
1948 return r;
1949
1950 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1951 PAGE_SIZE, true,
72d7668b 1952 AMDGPU_GEM_DOMAIN_OA, 0, NULL,
aaa36a97
AD		 1953 NULL, &adev->gds.oa_gfx_bo);
1954 if (r)
1955 return r;
1956
a101a899
KW		 1957 adev->gfx.ce_ram_size = 0x8000;
1958
68182d90
FC		 1959 r = gfx_v8_0_gpu_early_init(adev);
1960 if (r)
1961 return r;
0bde3a95 1962
aaa36a97
AD		 1963 return 0;
1964}
1965
5fc3aeeb 1966static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 1967{
1968 int i;
5fc3aeeb 1969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1970
1971 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1972 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1973 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1974
1975 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1976 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1977 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1978 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1979
aaa36a97
AD		 1980 gfx_v8_0_mec_fini(adev);
1981
2b6cd977
EH		 1982 gfx_v8_0_rlc_fini(adev);
1983
1984 kfree(adev->gfx.rlc.register_list_format);
1985
aaa36a97
AD		 1986 return 0;
1987}
1988
1989static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1990{
90bea0ab 1991 uint32_t *modearray, *mod2array;
eb64526f
TSD		 1992 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1993 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
90bea0ab 1994 u32 reg_offset;
aaa36a97 1995
90bea0ab
TSD		 1996 modearray = adev->gfx.config.tile_mode_array;
1997 mod2array = adev->gfx.config.macrotile_mode_array;
1998
1999 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2000 modearray[reg_offset] = 0;
2001
2002 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2003 mod2array[reg_offset] = 0;
aaa36a97
AD		 2004
2005 switch (adev->asic_type) {
2006 case CHIP_TOPAZ:
90bea0ab
TSD		 2007 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2008 PIPE_CONFIG(ADDR_SURF_P2) |
2009 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2010 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2011 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2012 PIPE_CONFIG(ADDR_SURF_P2) |
2013 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2014 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2015 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2016 PIPE_CONFIG(ADDR_SURF_P2) |
2017 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2018 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2019 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2020 PIPE_CONFIG(ADDR_SURF_P2) |
2021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2022 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2023 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2024 PIPE_CONFIG(ADDR_SURF_P2) |
2025 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2026 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2027 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2028 PIPE_CONFIG(ADDR_SURF_P2) |
2029 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2030 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2031 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2032 PIPE_CONFIG(ADDR_SURF_P2) |
2033 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2034 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2035 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2036 PIPE_CONFIG(ADDR_SURF_P2));
2037 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2038 PIPE_CONFIG(ADDR_SURF_P2) |
2039 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2040 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2041 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2042 PIPE_CONFIG(ADDR_SURF_P2) |
2043 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2044 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2045 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2046 PIPE_CONFIG(ADDR_SURF_P2) |
2047 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2048 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2049 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2050 PIPE_CONFIG(ADDR_SURF_P2) |
2051 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2052 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2053 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2054 PIPE_CONFIG(ADDR_SURF_P2) |
2055 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2056 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2057 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2058 PIPE_CONFIG(ADDR_SURF_P2) |
2059 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2060 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2061 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2062 PIPE_CONFIG(ADDR_SURF_P2) |
2063 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2064 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2065 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2066 PIPE_CONFIG(ADDR_SURF_P2) |
2067 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2068 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2069 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2070 PIPE_CONFIG(ADDR_SURF_P2) |
2071 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2072 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2073 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2074 PIPE_CONFIG(ADDR_SURF_P2) |
2075 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2076 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2077 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2078 PIPE_CONFIG(ADDR_SURF_P2) |
2079 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2080 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2081 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2082 PIPE_CONFIG(ADDR_SURF_P2) |
2083 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2084 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2085 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2086 PIPE_CONFIG(ADDR_SURF_P2) |
2087 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2089 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2090 PIPE_CONFIG(ADDR_SURF_P2) |
2091 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2093 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2094 PIPE_CONFIG(ADDR_SURF_P2) |
2095 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2096 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2097 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2098 PIPE_CONFIG(ADDR_SURF_P2) |
2099 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2101 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2102 PIPE_CONFIG(ADDR_SURF_P2) |
2103 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2105 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2106 PIPE_CONFIG(ADDR_SURF_P2) |
2107 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2109
2110 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2113 NUM_BANKS(ADDR_SURF_8_BANK));
2114 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2115 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2116 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2117 NUM_BANKS(ADDR_SURF_8_BANK));
2118 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2121 NUM_BANKS(ADDR_SURF_8_BANK));
2122 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2123 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2124 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2125 NUM_BANKS(ADDR_SURF_8_BANK));
2126 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2129 NUM_BANKS(ADDR_SURF_8_BANK));
2130 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2133 NUM_BANKS(ADDR_SURF_8_BANK));
2134 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2137 NUM_BANKS(ADDR_SURF_8_BANK));
2138 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2139 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2140 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2141 NUM_BANKS(ADDR_SURF_16_BANK));
2142 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2145 NUM_BANKS(ADDR_SURF_16_BANK));
2146 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2149 NUM_BANKS(ADDR_SURF_16_BANK));
2150 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2151 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2152 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2153 NUM_BANKS(ADDR_SURF_16_BANK));
2154 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2157 NUM_BANKS(ADDR_SURF_16_BANK));
2158 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2161 NUM_BANKS(ADDR_SURF_16_BANK));
2162 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2165 NUM_BANKS(ADDR_SURF_8_BANK));
2166
2167 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2168 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2169 reg_offset != 23)
2170 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2171
2172 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2173 if (reg_offset != 7)
2174 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2175
8cdacf44 2176 break;
af15a2d5 2177 case CHIP_FIJI:
90bea0ab
TSD		 2178 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2179 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2180 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2181 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2182 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2183 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2184 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2185 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2186 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2187 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2188 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2189 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2190 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2191 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2192 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2193 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2194 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2195 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2197 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2198 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2199 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2200 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2201 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2202 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2203 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2205 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2206 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2207 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2208 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2209 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2210 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2211 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2212 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2214 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2215 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2216 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2218 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2219 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2220 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2222 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2223 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2224 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2225 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2226 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2227 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2228 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2230 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2231 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2232 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2234 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2235 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2236 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2238 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2239 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2240 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2242 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2243 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2244 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2245 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2246 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2247 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2248 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2249 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2250 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2251 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2252 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2254 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2255 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2256 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2258 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2260 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2262 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2264 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2266 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2268 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2269 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2270 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2272 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2276 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2280 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2282 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2284 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2285 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2286 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2288 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2290 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2292 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2294 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2295 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2296 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2297 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2298 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2299 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2300
2301 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2302 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2303 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2304 NUM_BANKS(ADDR_SURF_8_BANK));
2305 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2306 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2307 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2308 NUM_BANKS(ADDR_SURF_8_BANK));
2309 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2310 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2311 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2312 NUM_BANKS(ADDR_SURF_8_BANK));
2313 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2314 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2315 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2316 NUM_BANKS(ADDR_SURF_8_BANK));
2317 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2318 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2319 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2320 NUM_BANKS(ADDR_SURF_8_BANK));
2321 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2322 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2323 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2324 NUM_BANKS(ADDR_SURF_8_BANK));
2325 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2326 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2327 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2328 NUM_BANKS(ADDR_SURF_8_BANK));
2329 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2330 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2331 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2332 NUM_BANKS(ADDR_SURF_8_BANK));
2333 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2334 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2335 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2336 NUM_BANKS(ADDR_SURF_8_BANK));
2337 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2338 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2339 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2340 NUM_BANKS(ADDR_SURF_8_BANK));
2341 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2342 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2343 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2344 NUM_BANKS(ADDR_SURF_8_BANK));
2345 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2346 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2347 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2348 NUM_BANKS(ADDR_SURF_8_BANK));
2349 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2352 NUM_BANKS(ADDR_SURF_8_BANK));
2353 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2355 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2356 NUM_BANKS(ADDR_SURF_4_BANK));
2357
2358 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2359 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2360
2361 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2362 if (reg_offset != 7)
2363 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2364
5f2e816b 2365 break;
aaa36a97 2366 case CHIP_TONGA:
90bea0ab
TSD		 2367 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2368 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2369 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2371 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2372 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2373 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2375 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2376 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2379 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2380 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2381 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2383 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2384 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2385 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2387 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2388 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2389 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2391 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2392 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2393 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2395 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2396 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2397 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2399 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2400 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2401 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2402 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2403 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2404 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2405 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2406 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2407 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2408 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2409 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2410 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2411 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2412 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2413 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2414 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2415 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2416 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2417 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2418 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2419 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2420 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2421 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2422 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2423 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2424 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2425 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2426 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2427 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2428 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2429 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2430 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2431 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2432 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2433 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2434 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2435 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2436 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2437 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2438 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2439 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2440 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2441 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2442 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2443 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2444 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2445 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2446 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2447 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2448 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2449 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2450 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2451 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2452 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2453 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2454 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2455 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2456 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2457 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2458 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2459 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2461 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2462 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2463 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2464 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2465 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2466 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2467 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2468 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2469 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2470 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2471 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2473 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2474 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2475 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2476 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2477 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2478 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2479 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2480 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2481 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2482 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2483 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2484 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2485 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2486 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2487 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2488 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2489
2490 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2493 NUM_BANKS(ADDR_SURF_16_BANK));
2494 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2495 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2496 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2497 NUM_BANKS(ADDR_SURF_16_BANK));
2498 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2501 NUM_BANKS(ADDR_SURF_16_BANK));
2502 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2504 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2505 NUM_BANKS(ADDR_SURF_16_BANK));
2506 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2509 NUM_BANKS(ADDR_SURF_16_BANK));
2510 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2513 NUM_BANKS(ADDR_SURF_16_BANK));
2514 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2517 NUM_BANKS(ADDR_SURF_16_BANK));
2518 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2521 NUM_BANKS(ADDR_SURF_16_BANK));
2522 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2525 NUM_BANKS(ADDR_SURF_16_BANK));
2526 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2529 NUM_BANKS(ADDR_SURF_16_BANK));
2530 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2533 NUM_BANKS(ADDR_SURF_16_BANK));
2534 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2537 NUM_BANKS(ADDR_SURF_8_BANK));
2538 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2541 NUM_BANKS(ADDR_SURF_4_BANK));
2542 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2543 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2544 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2545 NUM_BANKS(ADDR_SURF_4_BANK));
2546
2547 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2548 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2549
2550 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2551 if (reg_offset != 7)
2552 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2553
68182d90 2554 break;
2cc0c0b5 2555 case CHIP_POLARIS11:
68182d90
FC		 2556 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2557 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2558 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2560 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2561 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2562 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2564 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2565 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2566 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2568 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2569 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2570 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2572 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2573 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2574 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2576 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2577 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2578 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2580 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2581 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2582 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2584 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2585 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2586 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2588 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2589 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2590 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2591 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2592 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2593 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2594 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2595 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2596 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2597 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2598 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2599 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2600 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2601 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2602 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2603 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2604 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2605 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2606 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2607 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2608 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2609 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2610 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2611 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2612 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2613 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2614 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2615 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2616 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2617 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2618 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2619 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2620 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2621 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2622 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2623 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2624 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2625 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2626 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2627 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2628 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2629 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2630 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2631 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2632 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2633 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2634 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2635 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2636 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2637 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2638 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2639 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2640 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2641 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2642 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2643 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2644 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2645 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2646 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2647 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2648 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2649 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2650 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2651 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2652 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2653 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2654 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2655 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2656 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2657 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2658 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2659 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2660 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2661 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2662 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2663 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2664 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2665 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2666 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2667 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2668 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2669 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2670 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2671 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2672 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2673 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2674 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2675 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2676 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2677 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2678
2679 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2680 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2681 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2682 NUM_BANKS(ADDR_SURF_16_BANK));
2683
2684 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2686 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2687 NUM_BANKS(ADDR_SURF_16_BANK));
2688
2689 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2690 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2691 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2692 NUM_BANKS(ADDR_SURF_16_BANK));
2693
2694 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2697 NUM_BANKS(ADDR_SURF_16_BANK));
2698
2699 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2700 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2701 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2702 NUM_BANKS(ADDR_SURF_16_BANK));
2703
2704 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2705 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2706 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2707 NUM_BANKS(ADDR_SURF_16_BANK));
2708
2709 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2711 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2712 NUM_BANKS(ADDR_SURF_16_BANK));
2713
2714 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2716 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2717 NUM_BANKS(ADDR_SURF_16_BANK));
2718
2719 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2720 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2721 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2722 NUM_BANKS(ADDR_SURF_16_BANK));
2723
2724 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2727 NUM_BANKS(ADDR_SURF_16_BANK));
2728
2729 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2730 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2731 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2732 NUM_BANKS(ADDR_SURF_16_BANK));
2733
2734 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2737 NUM_BANKS(ADDR_SURF_16_BANK));
2738
2739 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2740 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2741 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2742 NUM_BANKS(ADDR_SURF_8_BANK));
2743
2744 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2747 NUM_BANKS(ADDR_SURF_4_BANK));
2748
2749 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2750 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2751
2752 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2753 if (reg_offset != 7)
2754 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2755
2756 break;
2cc0c0b5 2757 case CHIP_POLARIS10:
68182d90
FC		 2758 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2759 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2760 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2762 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2763 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2765 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2766 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2767 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2768 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2769 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2770 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2771 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2773 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2774 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2775 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2776 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2777 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2778 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2779 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2780 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2781 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2782 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2783 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2784 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2786 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2787 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2790 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2791 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2792 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2793 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2794 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2795 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2796 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2797 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2798 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2799 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2800 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2801 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2802 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2803 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2804 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2805 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2806 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2807 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2808 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2809 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2810 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2811 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2812 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2813 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2814 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2815 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2816 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2817 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2818 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2819 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2820 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2821 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2822 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2823 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2824 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2825 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2826 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2827 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2828 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2829 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2830 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2831 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2832 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2833 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2834 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2835 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2836 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2837 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2838 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2839 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2840 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2841 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2842 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2843 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2844 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2845 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2846 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2847 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2848 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2849 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2850 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2851 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2852 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2853 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2854 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2855 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2856 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2857 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2858 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2859 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2860 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2861 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2862 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2863 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2864 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2865 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2866 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2867 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2868 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2869 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2870 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2871 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2872 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2873 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2874 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2875 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2876 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2877 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2878 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2879 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2880
2881 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2884 NUM_BANKS(ADDR_SURF_16_BANK));
2885
2886 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2887 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2888 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2889 NUM_BANKS(ADDR_SURF_16_BANK));
2890
2891 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2892 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2893 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2894 NUM_BANKS(ADDR_SURF_16_BANK));
2895
2896 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2897 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2898 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2899 NUM_BANKS(ADDR_SURF_16_BANK));
2900
2901 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2902 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2903 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2904 NUM_BANKS(ADDR_SURF_16_BANK));
2905
2906 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2907 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2908 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2909 NUM_BANKS(ADDR_SURF_16_BANK));
2910
2911 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2914 NUM_BANKS(ADDR_SURF_16_BANK));
2915
2916 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2917 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2918 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2919 NUM_BANKS(ADDR_SURF_16_BANK));
2920
2921 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2922 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2923 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2924 NUM_BANKS(ADDR_SURF_16_BANK));
2925
2926 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2927 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2928 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2929 NUM_BANKS(ADDR_SURF_16_BANK));
2930
2931 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2932 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2933 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2934 NUM_BANKS(ADDR_SURF_16_BANK));
2935
2936 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2939 NUM_BANKS(ADDR_SURF_8_BANK));
2940
2941 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2942 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2943 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2944 NUM_BANKS(ADDR_SURF_4_BANK));
2945
2946 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2947 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2948 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2949 NUM_BANKS(ADDR_SURF_4_BANK));
2950
2951 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2952 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2953
2954 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2955 if (reg_offset != 7)
2956 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2957
aaa36a97 2958 break;
e3c7656c 2959 case CHIP_STONEY:
90bea0ab
TSD		 2960 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2961 PIPE_CONFIG(ADDR_SURF_P2) |
2962 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2963 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2964 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2965 PIPE_CONFIG(ADDR_SURF_P2) |
2966 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2967 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2968 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2969 PIPE_CONFIG(ADDR_SURF_P2) |
2970 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2971 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2972 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2973 PIPE_CONFIG(ADDR_SURF_P2) |
2974 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2975 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2976 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2977 PIPE_CONFIG(ADDR_SURF_P2) |
2978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2979 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2980 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2981 PIPE_CONFIG(ADDR_SURF_P2) |
2982 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2983 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2984 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2985 PIPE_CONFIG(ADDR_SURF_P2) |
2986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2987 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2988 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2989 PIPE_CONFIG(ADDR_SURF_P2));
2990 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2991 PIPE_CONFIG(ADDR_SURF_P2) |
2992 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2993 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2994 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2995 PIPE_CONFIG(ADDR_SURF_P2) |
2996 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2997 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2998 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2999 PIPE_CONFIG(ADDR_SURF_P2) |
3000 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3001 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3002 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3003 PIPE_CONFIG(ADDR_SURF_P2) |
3004 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3005 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3006 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3007 PIPE_CONFIG(ADDR_SURF_P2) |
3008 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3009 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3010 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3011 PIPE_CONFIG(ADDR_SURF_P2) |
3012 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3013 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3014 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3015 PIPE_CONFIG(ADDR_SURF_P2) |
3016 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3017 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3018 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3019 PIPE_CONFIG(ADDR_SURF_P2) |
3020 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3021 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3022 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3023 PIPE_CONFIG(ADDR_SURF_P2) |
3024 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3025 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3026 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3027 PIPE_CONFIG(ADDR_SURF_P2) |
3028 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3029 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3030 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3031 PIPE_CONFIG(ADDR_SURF_P2) |
3032 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3033 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3034 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3035 PIPE_CONFIG(ADDR_SURF_P2) |
3036 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3037 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3038 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3039 PIPE_CONFIG(ADDR_SURF_P2) |
3040 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3041 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3042 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3043 PIPE_CONFIG(ADDR_SURF_P2) |
3044 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3045 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3046 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3047 PIPE_CONFIG(ADDR_SURF_P2) |
3048 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3049 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3050 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3051 PIPE_CONFIG(ADDR_SURF_P2) |
3052 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3053 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3054 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3055 PIPE_CONFIG(ADDR_SURF_P2) |
3056 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3057 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3058 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3059 PIPE_CONFIG(ADDR_SURF_P2) |
3060 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3061 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3062
3063 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3066 NUM_BANKS(ADDR_SURF_8_BANK));
3067 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3068 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3069 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3070 NUM_BANKS(ADDR_SURF_8_BANK));
3071 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3074 NUM_BANKS(ADDR_SURF_8_BANK));
3075 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3078 NUM_BANKS(ADDR_SURF_8_BANK));
3079 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3082 NUM_BANKS(ADDR_SURF_8_BANK));
3083 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3084 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3085 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3086 NUM_BANKS(ADDR_SURF_8_BANK));
3087 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3088 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3089 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3090 NUM_BANKS(ADDR_SURF_8_BANK));
3091 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3094 NUM_BANKS(ADDR_SURF_16_BANK));
3095 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3096 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3097 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3098 NUM_BANKS(ADDR_SURF_16_BANK));
3099 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3102 NUM_BANKS(ADDR_SURF_16_BANK));
3103 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3104 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3105 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3106 NUM_BANKS(ADDR_SURF_16_BANK));
3107 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3110 NUM_BANKS(ADDR_SURF_16_BANK));
3111 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3112 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3113 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3114 NUM_BANKS(ADDR_SURF_16_BANK));
3115 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3116 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3117 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3118 NUM_BANKS(ADDR_SURF_8_BANK));
3119
3120 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3121 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3122 reg_offset != 23)
3123 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3124
3125 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3126 if (reg_offset != 7)
3127 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3128
e3c7656c 3129 break;
aaa36a97 3130 default:
90bea0ab
TSD		 3131 dev_warn(adev->dev,
3132 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3133 adev->asic_type);
3134
3135 case CHIP_CARRIZO:
3136 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3137 PIPE_CONFIG(ADDR_SURF_P2) |
3138 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3139 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3140 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3141 PIPE_CONFIG(ADDR_SURF_P2) |
3142 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3143 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3144 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3145 PIPE_CONFIG(ADDR_SURF_P2) |
3146 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3147 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3148 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3149 PIPE_CONFIG(ADDR_SURF_P2) |
3150 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3151 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3152 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3153 PIPE_CONFIG(ADDR_SURF_P2) |
3154 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3155 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3156 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3157 PIPE_CONFIG(ADDR_SURF_P2) |
3158 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3159 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3160 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3161 PIPE_CONFIG(ADDR_SURF_P2) |
3162 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3163 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3164 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3165 PIPE_CONFIG(ADDR_SURF_P2));
3166 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3167 PIPE_CONFIG(ADDR_SURF_P2) |
3168 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3169 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3170 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3171 PIPE_CONFIG(ADDR_SURF_P2) |
3172 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3173 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3174 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3175 PIPE_CONFIG(ADDR_SURF_P2) |
3176 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3177 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3178 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3179 PIPE_CONFIG(ADDR_SURF_P2) |
3180 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3181 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3182 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3183 PIPE_CONFIG(ADDR_SURF_P2) |
3184 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3185 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3186 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3187 PIPE_CONFIG(ADDR_SURF_P2) |
3188 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3189 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3190 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3191 PIPE_CONFIG(ADDR_SURF_P2) |
3192 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3193 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3194 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3195 PIPE_CONFIG(ADDR_SURF_P2) |
3196 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3197 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3198 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3199 PIPE_CONFIG(ADDR_SURF_P2) |
3200 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3201 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3202 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3203 PIPE_CONFIG(ADDR_SURF_P2) |
3204 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3205 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3206 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3207 PIPE_CONFIG(ADDR_SURF_P2) |
3208 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3209 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3210 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3211 PIPE_CONFIG(ADDR_SURF_P2) |
3212 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3213 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3214 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3215 PIPE_CONFIG(ADDR_SURF_P2) |
3216 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3217 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3218 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3219 PIPE_CONFIG(ADDR_SURF_P2) |
3220 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3221 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3222 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3223 PIPE_CONFIG(ADDR_SURF_P2) |
3224 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3225 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3226 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3227 PIPE_CONFIG(ADDR_SURF_P2) |
3228 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3229 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3230 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3231 PIPE_CONFIG(ADDR_SURF_P2) |
3232 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3233 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3234 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3235 PIPE_CONFIG(ADDR_SURF_P2) |
3236 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3237 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3238
3239 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3242 NUM_BANKS(ADDR_SURF_8_BANK));
3243 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3246 NUM_BANKS(ADDR_SURF_8_BANK));
3247 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3250 NUM_BANKS(ADDR_SURF_8_BANK));
3251 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3252 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3253 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3254 NUM_BANKS(ADDR_SURF_8_BANK));
3255 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3256 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3257 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3258 NUM_BANKS(ADDR_SURF_8_BANK));
3259 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3262 NUM_BANKS(ADDR_SURF_8_BANK));
3263 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3264 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3265 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3266 NUM_BANKS(ADDR_SURF_8_BANK));
3267 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3270 NUM_BANKS(ADDR_SURF_16_BANK));
3271 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3272 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3273 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3274 NUM_BANKS(ADDR_SURF_16_BANK));
3275 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3276 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3277 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3278 NUM_BANKS(ADDR_SURF_16_BANK));
3279 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3282 NUM_BANKS(ADDR_SURF_16_BANK));
3283 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3284 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3285 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3286 NUM_BANKS(ADDR_SURF_16_BANK));
3287 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3290 NUM_BANKS(ADDR_SURF_16_BANK));
3291 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3292 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3293 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3294 NUM_BANKS(ADDR_SURF_8_BANK));
3295
3296 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3297 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3298 reg_offset != 23)
3299 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3300
3301 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3302 if (reg_offset != 7)
3303 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3304
3305 break;
aaa36a97
AD		 3306 }
3307}
3308
aaa36a97
AD		 3309void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
3310{
3311 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3312
3313 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
3314 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3315 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3316 } else if (se_num == 0xffffffff) {
3317 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3318 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3319 } else if (sh_num == 0xffffffff) {
3320 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3321 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3322 } else {
3323 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3324 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3325 }
3326 WREG32(mmGRBM_GFX_INDEX, data);
3327}
3328
8f8e00c1
AD		 3329static u32 gfx_v8_0_create_bitmask(u32 bit_width)
3330{
3331 return (u32)((1ULL << bit_width) - 1);
3332}
3333
3334static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
aaa36a97
AD		 3335{
3336 u32 data, mask;
3337
3338 data = RREG32(mmCC_RB_BACKEND_DISABLE);
aaa36a97
AD		 3339 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3340
8f8e00c1 3341 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
aaa36a97
AD		 3342 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
3343
8f8e00c1
AD		 3344 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
3345 adev->gfx.config.max_sh_per_se);
aaa36a97 3346
8f8e00c1 3347 return (~data) & mask;
aaa36a97
AD		 3348}
3349
8f8e00c1 3350static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
aaa36a97
AD		 3351{
3352 int i, j;
aac1e3ca 3353 u32 data;
8f8e00c1 3354 u32 active_rbs = 0;
6157bd7a
FC		 3355 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3356 adev->gfx.config.max_sh_per_se;
aaa36a97
AD		 3357
3358 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 3359 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3360 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
aaa36a97 3361 gfx_v8_0_select_se_sh(adev, i, j);
8f8e00c1
AD		 3362 data = gfx_v8_0_get_rb_active_bitmap(adev);
3363 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
6157bd7a 3364 rb_bitmap_width_per_sh);
aaa36a97
AD		 3365 }
3366 }
3367 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3368 mutex_unlock(&adev->grbm_idx_mutex);
3369
8f8e00c1 3370 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 3371 adev->gfx.config.num_rbs = hweight32(active_rbs);
aaa36a97
AD		 3372}
3373
cd06bf68 3374/**
35c7a952 3375 * gfx_v8_0_init_compute_vmid - gart enable
cd06bf68
BG		 3376 *
3377 * @rdev: amdgpu_device pointer
3378 *
3379 * Initialize compute vmid sh_mem registers
3380 *
3381 */
3382#define DEFAULT_SH_MEM_BASES (0x6000)
3383#define FIRST_COMPUTE_VMID (8)
3384#define LAST_COMPUTE_VMID (16)
35c7a952 3385static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
cd06bf68
BG		 3386{
3387 int i;
3388 uint32_t sh_mem_config;
3389 uint32_t sh_mem_bases;
3390
3391 /*
3392 * Configure apertures:
3393 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3394 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3395 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3396 */
3397 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3398
3399 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3400 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3401 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3402 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3403 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3404 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3405
3406 mutex_lock(&adev->srbm_mutex);
3407 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3408 vi_srbm_select(adev, 0, 0, 0, i);
3409 /* CP and shaders */
3410 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3411 WREG32(mmSH_MEM_APE1_BASE, 1);
3412 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3413 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3414 }
3415 vi_srbm_select(adev, 0, 0, 0, 0);
3416 mutex_unlock(&adev->srbm_mutex);
3417}
3418
aaa36a97
AD		 3419static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
3420{
aaa36a97
AD		 3421 u32 tmp;
3422 int i;
3423
aaa36a97
AD		 3424 tmp = RREG32(mmGRBM_CNTL);
3425 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
3426 WREG32(mmGRBM_CNTL, tmp);
3427
0bde3a95
AD		 3428 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3429 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3430 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
aaa36a97
AD		 3431
3432 gfx_v8_0_tiling_mode_table_init(adev);
3433
8f8e00c1 3434 gfx_v8_0_setup_rb(adev);
7dae69a2 3435 gfx_v8_0_get_cu_info(adev);
aaa36a97
AD		 3436
3437 /* XXX SH_MEM regs */
3438 /* where to put LDS, scratch, GPUVM in FSA64 space */
3439 mutex_lock(&adev->srbm_mutex);
3440 for (i = 0; i < 16; i++) {
3441 vi_srbm_select(adev, 0, 0, 0, i);
3442 /* CP and shaders */
3443 if (i == 0) {
3444 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3445 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
0bde3a95 3446 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3447 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3448 WREG32(mmSH_MEM_CONFIG, tmp);
3449 } else {
3450 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3451 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
0bde3a95 3452 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 3453 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 3454 WREG32(mmSH_MEM_CONFIG, tmp);
3455 }
3456
3457 WREG32(mmSH_MEM_APE1_BASE, 1);
3458 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3459 WREG32(mmSH_MEM_BASES, 0);
3460 }
3461 vi_srbm_select(adev, 0, 0, 0, 0);
3462 mutex_unlock(&adev->srbm_mutex);
3463
35c7a952 3464 gfx_v8_0_init_compute_vmid(adev);
cd06bf68 3465
aaa36a97
AD		 3466 mutex_lock(&adev->grbm_idx_mutex);
3467 /*
3468 * making sure that the following register writes will be broadcasted
3469 * to all the shaders
3470 */
3471 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3472
3473 WREG32(mmPA_SC_FIFO_SIZE,
3474 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3475 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3476 (adev->gfx.config.sc_prim_fifo_size_backend <<
3477 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3478 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3479 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3480 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3481 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3482 mutex_unlock(&adev->grbm_idx_mutex);
3483
3484}
3485
3486static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3487{
3488 u32 i, j, k;
3489 u32 mask;
3490
3491 mutex_lock(&adev->grbm_idx_mutex);
3492 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3493 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3494 gfx_v8_0_select_se_sh(adev, i, j);
3495 for (k = 0; k < adev->usec_timeout; k++) {
3496 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3497 break;
3498 udelay(1);
3499 }
3500 }
3501 }
3502 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3503 mutex_unlock(&adev->grbm_idx_mutex);
3504
3505 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3506 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3507 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3508 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3509 for (k = 0; k < adev->usec_timeout; k++) {
3510 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3511 break;
3512 udelay(1);
3513 }
3514}
3515
3516static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3517 bool enable)
3518{
3519 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3520
0d07db7e
TSD		 3521 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3522 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3523 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3524 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3525
aaa36a97
AD		 3526 WREG32(mmCP_INT_CNTL_RING0, tmp);
3527}
3528
2b6cd977
EH		 3529static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3530{
3531 /* csib */
3532 WREG32(mmRLC_CSIB_ADDR_HI,
3533 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3534 WREG32(mmRLC_CSIB_ADDR_LO,
3535 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3536 WREG32(mmRLC_CSIB_LENGTH,
3537 adev->gfx.rlc.clear_state_size);
3538}
3539
3540static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3541 int ind_offset,
3542 int list_size,
3543 int *unique_indices,
3544 int *indices_count,
3545 int max_indices,
3546 int *ind_start_offsets,
3547 int *offset_count,
3548 int max_offset)
3549{
3550 int indices;
3551 bool new_entry = true;
3552
3553 for (; ind_offset < list_size; ind_offset++) {
3554
3555 if (new_entry) {
3556 new_entry = false;
3557 ind_start_offsets[*offset_count] = ind_offset;
3558 *offset_count = *offset_count + 1;
3559 BUG_ON(*offset_count >= max_offset);
3560 }
3561
3562 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3563 new_entry = true;
3564 continue;
3565 }
3566
3567 ind_offset += 2;
3568
3569 /* look for the matching indice */
3570 for (indices = 0;
3571 indices < *indices_count;
3572 indices++) {
3573 if (unique_indices[indices] ==
3574 register_list_format[ind_offset])
3575 break;
3576 }
3577
3578 if (indices >= *indices_count) {
3579 unique_indices[*indices_count] =
3580 register_list_format[ind_offset];
3581 indices = *indices_count;
3582 *indices_count = *indices_count + 1;
3583 BUG_ON(*indices_count >= max_indices);
3584 }
3585
3586 register_list_format[ind_offset] = indices;
3587 }
3588}
3589
3590static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3591{
3592 int i, temp, data;
3593 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3594 int indices_count = 0;
3595 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3596 int offset_count = 0;
3597
3598 int list_size;
3599 unsigned int *register_list_format =
3600 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3601 if (register_list_format == NULL)
3602 return -ENOMEM;
3603 memcpy(register_list_format, adev->gfx.rlc.register_list_format,
3604 adev->gfx.rlc.reg_list_format_size_bytes);
3605
3606 gfx_v8_0_parse_ind_reg_list(register_list_format,
3607 RLC_FormatDirectRegListLength,
3608 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3609 unique_indices,
3610 &indices_count,
3611 sizeof(unique_indices) / sizeof(int),
3612 indirect_start_offsets,
3613 &offset_count,
3614 sizeof(indirect_start_offsets)/sizeof(int));
3615
3616 /* save and restore list */
3617 temp = RREG32(mmRLC_SRM_CNTL);
3618 temp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
3619 WREG32(mmRLC_SRM_CNTL, temp);
3620
3621 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3622 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3623 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3624
3625 /* indirect list */
3626 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3627 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3628 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3629
3630 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3631 list_size = list_size >> 1;
3632 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3633 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3634
3635 /* starting offsets starts */
3636 WREG32(mmRLC_GPM_SCRATCH_ADDR,
3637 adev->gfx.rlc.starting_offsets_start);
3638 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
3639 WREG32(mmRLC_GPM_SCRATCH_DATA,
3640 indirect_start_offsets[i]);
3641
3642 /* unique indices */
3643 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3644 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3645 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
3646 amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
3647 amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
3648 }
3649 kfree(register_list_format);
3650
3651 return 0;
3652}
3653
3654static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3655{
3656 uint32_t data;
3657
3658 data = RREG32(mmRLC_SRM_CNTL);
3659 data |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
3660 WREG32(mmRLC_SRM_CNTL, data);
3661}
3662
2cc0c0b5 3663static void polaris11_init_power_gating(struct amdgpu_device *adev)
f4bfffdd
EH		 3664{
3665 uint32_t data;
3666
3667 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3668 AMD_PG_SUPPORT_GFX_SMG |
3669 AMD_PG_SUPPORT_GFX_DMG)) {
3670 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3671 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3672 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3673 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3674
3675 data = 0;
3676 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
3677 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
3678 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
3679 data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
3680 WREG32(mmRLC_PG_DELAY, data);
3681
3682 data = RREG32(mmRLC_PG_DELAY_2);
3683 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
3684 data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
3685 WREG32(mmRLC_PG_DELAY_2, data);
3686
3687 data = RREG32(mmRLC_AUTO_PG_CTRL);
3688 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3689 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3690 WREG32(mmRLC_AUTO_PG_CTRL, data);
3691 }
3692}
3693
2b6cd977
EH		 3694static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
3695{
3696 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3697 AMD_PG_SUPPORT_GFX_SMG |
3698 AMD_PG_SUPPORT_GFX_DMG |
3699 AMD_PG_SUPPORT_CP |
3700 AMD_PG_SUPPORT_GDS |
3701 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3702 gfx_v8_0_init_csb(adev);
3703 gfx_v8_0_init_save_restore_list(adev);
3704 gfx_v8_0_enable_save_restore_machine(adev);
f4bfffdd 3705
2cc0c0b5
FC		 3706 if (adev->asic_type == CHIP_POLARIS11)
3707 polaris11_init_power_gating(adev);
2b6cd977
EH		 3708 }
3709}
3710
aaa36a97
AD		 3711void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
3712{
3713 u32 tmp = RREG32(mmRLC_CNTL);
3714
3715 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
3716 WREG32(mmRLC_CNTL, tmp);
3717
3718 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3719
3720 gfx_v8_0_wait_for_rlc_serdes(adev);
3721}
3722
3723static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
3724{
3725 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3726
3727 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3728 WREG32(mmGRBM_SOFT_RESET, tmp);
3729 udelay(50);
3730 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3731 WREG32(mmGRBM_SOFT_RESET, tmp);
3732 udelay(50);
3733}
3734
3735static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
3736{
3737 u32 tmp = RREG32(mmRLC_CNTL);
3738
3739 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
3740 WREG32(mmRLC_CNTL, tmp);
3741
3742 /* carrizo do enable cp interrupt after cp inited */
e3c7656c 3743 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 3744 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3745
3746 udelay(50);
3747}
3748
3749static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
3750{
3751 const struct rlc_firmware_header_v2_0 *hdr;
3752 const __le32 *fw_data;
3753 unsigned i, fw_size;
3754
3755 if (!adev->gfx.rlc_fw)
3756 return -EINVAL;
3757
3758 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3759 amdgpu_ucode_print_rlc_hdr(&hdr->header);
aaa36a97
AD		 3760
3761 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
3762 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3763 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3764
3765 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3766 for (i = 0; i < fw_size; i++)
3767 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3768 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3769
3770 return 0;
3771}
3772
3773static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
3774{
3775 int r;
3776
3777 gfx_v8_0_rlc_stop(adev);
3778
3779 /* disable CG */
3780 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2cc0c0b5
FC		 3781 if (adev->asic_type == CHIP_POLARIS11 ||
3782 adev->asic_type == CHIP_POLARIS10)
68182d90 3783 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
aaa36a97
AD		 3784
3785 /* disable PG */
3786 WREG32(mmRLC_PG_CNTL, 0);
3787
3788 gfx_v8_0_rlc_reset(adev);
3789
2b6cd977
EH		 3790 gfx_v8_0_init_pg(adev);
3791
e61710c5 3792 if (!adev->pp_enabled) {
ba5c2a87
RZ		 3793 if (!adev->firmware.smu_load) {
3794 /* legacy rlc firmware loading */
3795 r = gfx_v8_0_rlc_load_microcode(adev);
3796 if (r)
3797 return r;
3798 } else {
3799 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3800 AMDGPU_UCODE_ID_RLC_G);
3801 if (r)
3802 return -EINVAL;
3803 }
aaa36a97
AD		 3804 }
3805
3806 gfx_v8_0_rlc_start(adev);
3807
3808 return 0;
3809}
3810
3811static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
3812{
3813 int i;
3814 u32 tmp = RREG32(mmCP_ME_CNTL);
3815
3816 if (enable) {
3817 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
3818 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
3819 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
3820 } else {
3821 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
3822 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
3823 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
3824 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3825 adev->gfx.gfx_ring[i].ready = false;
3826 }
3827 WREG32(mmCP_ME_CNTL, tmp);
3828 udelay(50);
3829}
3830
3831static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3832{
3833 const struct gfx_firmware_header_v1_0 *pfp_hdr;
3834 const struct gfx_firmware_header_v1_0 *ce_hdr;
3835 const struct gfx_firmware_header_v1_0 *me_hdr;
3836 const __le32 *fw_data;
3837 unsigned i, fw_size;
3838
3839 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
3840 return -EINVAL;
3841
3842 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3843 adev->gfx.pfp_fw->data;
3844 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
3845 adev->gfx.ce_fw->data;
3846 me_hdr = (const struct gfx_firmware_header_v1_0 *)
3847 adev->gfx.me_fw->data;
3848
3849 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3850 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
3851 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
aaa36a97
AD		 3852
3853 gfx_v8_0_cp_gfx_enable(adev, false);
3854
3855 /* PFP */
3856 fw_data = (const __le32 *)
3857 (adev->gfx.pfp_fw->data +
3858 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3859 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3860 WREG32(mmCP_PFP_UCODE_ADDR, 0);
3861 for (i = 0; i < fw_size; i++)
3862 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3863 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3864
3865 /* CE */
3866 fw_data = (const __le32 *)
3867 (adev->gfx.ce_fw->data +
3868 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3869 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3870 WREG32(mmCP_CE_UCODE_ADDR, 0);
3871 for (i = 0; i < fw_size; i++)
3872 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3873 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3874
3875 /* ME */
3876 fw_data = (const __le32 *)
3877 (adev->gfx.me_fw->data +
3878 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3879 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3880 WREG32(mmCP_ME_RAM_WADDR, 0);
3881 for (i = 0; i < fw_size; i++)
3882 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3883 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3884
3885 return 0;
3886}
3887
3888static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
3889{
3890 u32 count = 0;
3891 const struct cs_section_def *sect = NULL;
3892 const struct cs_extent_def *ext = NULL;
3893
3894 /* begin clear state */
3895 count += 2;
3896 /* context control state */
3897 count += 3;
3898
3899 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3900 for (ext = sect->section; ext->extent != NULL; ++ext) {
3901 if (sect->id == SECT_CONTEXT)
3902 count += 2 + ext->reg_count;
3903 else
3904 return 0;
3905 }
3906 }
3907 /* pa_sc_raster_config/pa_sc_raster_config1 */
3908 count += 4;
3909 /* end clear state */
3910 count += 2;
3911 /* clear state */
3912 count += 2;
3913
3914 return count;
3915}
3916
3917static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
3918{
3919 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3920 const struct cs_section_def *sect = NULL;
3921 const struct cs_extent_def *ext = NULL;
3922 int r, i;
3923
3924 /* init the CP */
3925 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3926 WREG32(mmCP_ENDIAN_SWAP, 0);
3927 WREG32(mmCP_DEVICE_ID, 1);
3928
3929 gfx_v8_0_cp_gfx_enable(adev, true);
3930
a27de35c 3931 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
aaa36a97
AD		 3932 if (r) {
3933 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3934 return r;
3935 }
3936
3937 /* clear state buffer */
3938 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3939 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3940
3941 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3942 amdgpu_ring_write(ring, 0x80000000);
3943 amdgpu_ring_write(ring, 0x80000000);
3944
3945 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
3946 for (ext = sect->section; ext->extent != NULL; ++ext) {
3947 if (sect->id == SECT_CONTEXT) {
3948 amdgpu_ring_write(ring,
3949 PACKET3(PACKET3_SET_CONTEXT_REG,
3950 ext->reg_count));
3951 amdgpu_ring_write(ring,
3952 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3953 for (i = 0; i < ext->reg_count; i++)
3954 amdgpu_ring_write(ring, ext->extent[i]);
3955 }
3956 }
3957 }
3958
3959 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3960 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3961 switch (adev->asic_type) {
3962 case CHIP_TONGA:
2cc0c0b5 3963 case CHIP_POLARIS10:
aaa36a97
AD		 3964 amdgpu_ring_write(ring, 0x16000012);
3965 amdgpu_ring_write(ring, 0x0000002A);
3966 break;
2cc0c0b5 3967 case CHIP_POLARIS11:
68182d90
FC		 3968 amdgpu_ring_write(ring, 0x16000012);
3969 amdgpu_ring_write(ring, 0x00000000);
3970 break;
fa676048
FC		 3971 case CHIP_FIJI:
3972 amdgpu_ring_write(ring, 0x3a00161a);
3973 amdgpu_ring_write(ring, 0x0000002e);
3974 break;
aaa36a97
AD		 3975 case CHIP_TOPAZ:
3976 case CHIP_CARRIZO:
3977 amdgpu_ring_write(ring, 0x00000002);
3978 amdgpu_ring_write(ring, 0x00000000);
3979 break;
e3c7656c
SL		 3980 case CHIP_STONEY:
3981 amdgpu_ring_write(ring, 0x00000000);
3982 amdgpu_ring_write(ring, 0x00000000);
3983 break;
aaa36a97
AD		 3984 default:
3985 BUG();
3986 }
3987
3988 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3989 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3990
3991 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3992 amdgpu_ring_write(ring, 0);
3993
3994 /* init the CE partitions */
3995 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3996 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3997 amdgpu_ring_write(ring, 0x8000);
3998 amdgpu_ring_write(ring, 0x8000);
3999
a27de35c 4000 amdgpu_ring_commit(ring);
aaa36a97
AD		 4001
4002 return 0;
4003}
4004
4005static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4006{
4007 struct amdgpu_ring *ring;
4008 u32 tmp;
4009 u32 rb_bufsz;
4010 u64 rb_addr, rptr_addr;
4011 int r;
4012
4013 /* Set the write pointer delay */
4014 WREG32(mmCP_RB_WPTR_DELAY, 0);
4015
4016 /* set the RB to use vmid 0 */
4017 WREG32(mmCP_RB_VMID, 0);
4018
4019 /* Set ring buffer size */
4020 ring = &adev->gfx.gfx_ring[0];
4021 rb_bufsz = order_base_2(ring->ring_size / 8);
4022 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4023 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4024 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4025 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4026#ifdef __BIG_ENDIAN
4027 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4028#endif
4029 WREG32(mmCP_RB0_CNTL, tmp);
4030
4031 /* Initialize the ring buffer's read and write pointers */
4032 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4033 ring->wptr = 0;
4034 WREG32(mmCP_RB0_WPTR, ring->wptr);
4035
4036 /* set the wb address wether it's enabled or not */
4037 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4038 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4039 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4040
4041 mdelay(1);
4042 WREG32(mmCP_RB0_CNTL, tmp);
4043
4044 rb_addr = ring->gpu_addr >> 8;
4045 WREG32(mmCP_RB0_BASE, rb_addr);
4046 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4047
4048 /* no gfx doorbells on iceland */
4049 if (adev->asic_type != CHIP_TOPAZ) {
4050 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4051 if (ring->use_doorbell) {
4052 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4053 DOORBELL_OFFSET, ring->doorbell_index);
68182d90
FC		 4054 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4055 DOORBELL_HIT, 0);
aaa36a97
AD		 4056 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4057 DOORBELL_EN, 1);
4058 } else {
4059 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4060 DOORBELL_EN, 0);
4061 }
4062 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4063
4064 if (adev->asic_type == CHIP_TONGA) {
4065 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4066 DOORBELL_RANGE_LOWER,
4067 AMDGPU_DOORBELL_GFX_RING0);
4068 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4069
4070 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4071 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4072 }
4073
4074 }
4075
4076 /* start the ring */
4077 gfx_v8_0_cp_gfx_start(adev);
4078 ring->ready = true;
4079 r = amdgpu_ring_test_ring(ring);
4080 if (r) {
4081 ring->ready = false;
4082 return r;
4083 }
4084
4085 return 0;
4086}
4087
4088static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4089{
4090 int i;
4091
4092 if (enable) {
4093 WREG32(mmCP_MEC_CNTL, 0);
4094 } else {
4095 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4096 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4097 adev->gfx.compute_ring[i].ready = false;
4098 }
4099 udelay(50);
4100}
4101
aaa36a97
AD		 4102static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
4103{
4104 const struct gfx_firmware_header_v1_0 *mec_hdr;
4105 const __le32 *fw_data;
4106 unsigned i, fw_size;
4107
4108 if (!adev->gfx.mec_fw)
4109 return -EINVAL;
4110
4111 gfx_v8_0_cp_compute_enable(adev, false);
4112
4113 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4114 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
aaa36a97
AD		 4115
4116 fw_data = (const __le32 *)
4117 (adev->gfx.mec_fw->data +
4118 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4119 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4120
4121 /* MEC1 */
4122 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
4123 for (i = 0; i < fw_size; i++)
4124 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
4125 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
4126
4127 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
4128 if (adev->gfx.mec2_fw) {
4129 const struct gfx_firmware_header_v1_0 *mec2_hdr;
4130
4131 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4132 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
aaa36a97
AD		 4133
4134 fw_data = (const __le32 *)
4135 (adev->gfx.mec2_fw->data +
4136 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4137 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4138
4139 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
4140 for (i = 0; i < fw_size; i++)
4141 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
4142 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
4143 }
4144
4145 return 0;
4146}
4147
4148struct vi_mqd {
4149 uint32_t header; /* ordinal0 */
4150 uint32_t compute_dispatch_initiator; /* ordinal1 */
4151 uint32_t compute_dim_x; /* ordinal2 */
4152 uint32_t compute_dim_y; /* ordinal3 */
4153 uint32_t compute_dim_z; /* ordinal4 */
4154 uint32_t compute_start_x; /* ordinal5 */
4155 uint32_t compute_start_y; /* ordinal6 */
4156 uint32_t compute_start_z; /* ordinal7 */
4157 uint32_t compute_num_thread_x; /* ordinal8 */
4158 uint32_t compute_num_thread_y; /* ordinal9 */
4159 uint32_t compute_num_thread_z; /* ordinal10 */
4160 uint32_t compute_pipelinestat_enable; /* ordinal11 */
4161 uint32_t compute_perfcount_enable; /* ordinal12 */
4162 uint32_t compute_pgm_lo; /* ordinal13 */
4163 uint32_t compute_pgm_hi; /* ordinal14 */
4164 uint32_t compute_tba_lo; /* ordinal15 */
4165 uint32_t compute_tba_hi; /* ordinal16 */
4166 uint32_t compute_tma_lo; /* ordinal17 */
4167 uint32_t compute_tma_hi; /* ordinal18 */
4168 uint32_t compute_pgm_rsrc1; /* ordinal19 */
4169 uint32_t compute_pgm_rsrc2; /* ordinal20 */
4170 uint32_t compute_vmid; /* ordinal21 */
4171 uint32_t compute_resource_limits; /* ordinal22 */
4172 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
4173 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
4174 uint32_t compute_tmpring_size; /* ordinal25 */
4175 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
4176 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
4177 uint32_t compute_restart_x; /* ordinal28 */
4178 uint32_t compute_restart_y; /* ordinal29 */
4179 uint32_t compute_restart_z; /* ordinal30 */
4180 uint32_t compute_thread_trace_enable; /* ordinal31 */
4181 uint32_t compute_misc_reserved; /* ordinal32 */
4182 uint32_t compute_dispatch_id; /* ordinal33 */
4183 uint32_t compute_threadgroup_id; /* ordinal34 */
4184 uint32_t compute_relaunch; /* ordinal35 */
4185 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
4186 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
4187 uint32_t compute_wave_restore_control; /* ordinal38 */
4188 uint32_t reserved9; /* ordinal39 */
4189 uint32_t reserved10; /* ordinal40 */
4190 uint32_t reserved11; /* ordinal41 */
4191 uint32_t reserved12; /* ordinal42 */
4192 uint32_t reserved13; /* ordinal43 */
4193 uint32_t reserved14; /* ordinal44 */
4194 uint32_t reserved15; /* ordinal45 */
4195 uint32_t reserved16; /* ordinal46 */
4196 uint32_t reserved17; /* ordinal47 */
4197 uint32_t reserved18; /* ordinal48 */
4198 uint32_t reserved19; /* ordinal49 */
4199 uint32_t reserved20; /* ordinal50 */
4200 uint32_t reserved21; /* ordinal51 */
4201 uint32_t reserved22; /* ordinal52 */
4202 uint32_t reserved23; /* ordinal53 */
4203 uint32_t reserved24; /* ordinal54 */
4204 uint32_t reserved25; /* ordinal55 */
4205 uint32_t reserved26; /* ordinal56 */
4206 uint32_t reserved27; /* ordinal57 */
4207 uint32_t reserved28; /* ordinal58 */
4208 uint32_t reserved29; /* ordinal59 */
4209 uint32_t reserved30; /* ordinal60 */
4210 uint32_t reserved31; /* ordinal61 */
4211 uint32_t reserved32; /* ordinal62 */
4212 uint32_t reserved33; /* ordinal63 */
4213 uint32_t reserved34; /* ordinal64 */
4214 uint32_t compute_user_data_0; /* ordinal65 */
4215 uint32_t compute_user_data_1; /* ordinal66 */
4216 uint32_t compute_user_data_2; /* ordinal67 */
4217 uint32_t compute_user_data_3; /* ordinal68 */
4218 uint32_t compute_user_data_4; /* ordinal69 */
4219 uint32_t compute_user_data_5; /* ordinal70 */
4220 uint32_t compute_user_data_6; /* ordinal71 */
4221 uint32_t compute_user_data_7; /* ordinal72 */
4222 uint32_t compute_user_data_8; /* ordinal73 */
4223 uint32_t compute_user_data_9; /* ordinal74 */
4224 uint32_t compute_user_data_10; /* ordinal75 */
4225 uint32_t compute_user_data_11; /* ordinal76 */
4226 uint32_t compute_user_data_12; /* ordinal77 */
4227 uint32_t compute_user_data_13; /* ordinal78 */
4228 uint32_t compute_user_data_14; /* ordinal79 */
4229 uint32_t compute_user_data_15; /* ordinal80 */
4230 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
4231 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
4232 uint32_t reserved35; /* ordinal83 */
4233 uint32_t reserved36; /* ordinal84 */
4234 uint32_t reserved37; /* ordinal85 */
4235 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
4236 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
4237 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
4238 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
4239 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
4240 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
4241 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
4242 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
4243 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
4244 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
4245 uint32_t reserved38; /* ordinal96 */
4246 uint32_t reserved39; /* ordinal97 */
4247 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
4248 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
4249 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
4250 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
4251 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
4252 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
4253 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
4254 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
4255 uint32_t reserved40; /* ordinal106 */
4256 uint32_t reserved41; /* ordinal107 */
4257 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
4258 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
4259 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
4260 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
4261 uint32_t reserved42; /* ordinal112 */
4262 uint32_t reserved43; /* ordinal113 */
4263 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
4264 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
4265 uint32_t cp_packet_id_lo; /* ordinal116 */
4266 uint32_t cp_packet_id_hi; /* ordinal117 */
4267 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
4268 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
4269 uint32_t gds_save_base_addr_lo; /* ordinal120 */
4270 uint32_t gds_save_base_addr_hi; /* ordinal121 */
4271 uint32_t gds_save_mask_lo; /* ordinal122 */
4272 uint32_t gds_save_mask_hi; /* ordinal123 */
4273 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
4274 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
4275 uint32_t reserved44; /* ordinal126 */
4276 uint32_t reserved45; /* ordinal127 */
4277 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
4278 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
4279 uint32_t cp_hqd_active; /* ordinal130 */
4280 uint32_t cp_hqd_vmid; /* ordinal131 */
4281 uint32_t cp_hqd_persistent_state; /* ordinal132 */
4282 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
4283 uint32_t cp_hqd_queue_priority; /* ordinal134 */
4284 uint32_t cp_hqd_quantum; /* ordinal135 */
4285 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
4286 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
4287 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
4288 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
4289 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
4290 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
4291 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
4292 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
4293 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
4294 uint32_t cp_hqd_pq_control; /* ordinal145 */
4295 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
4296 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
4297 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
4298 uint32_t cp_hqd_ib_control; /* ordinal149 */
4299 uint32_t cp_hqd_iq_timer; /* ordinal150 */
4300 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
4301 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
4302 uint32_t cp_hqd_dma_offload; /* ordinal153 */
4303 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
4304 uint32_t cp_hqd_msg_type; /* ordinal155 */
4305 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
4306 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
4307 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
4308 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
4309 uint32_t cp_hqd_hq_status0; /* ordinal160 */
4310 uint32_t cp_hqd_hq_control0; /* ordinal161 */
4311 uint32_t cp_mqd_control; /* ordinal162 */
4312 uint32_t cp_hqd_hq_status1; /* ordinal163 */
4313 uint32_t cp_hqd_hq_control1; /* ordinal164 */
4314 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
4315 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
4316 uint32_t cp_hqd_eop_control; /* ordinal167 */
4317 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
4318 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
4319 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
4320 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
4321 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
4322 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
4323 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
4324 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
4325 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
4326 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
4327 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
4328 uint32_t cp_hqd_error; /* ordinal179 */
4329 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
4330 uint32_t cp_hqd_eop_dones; /* ordinal181 */
4331 uint32_t reserved46; /* ordinal182 */
4332 uint32_t reserved47; /* ordinal183 */
4333 uint32_t reserved48; /* ordinal184 */
4334 uint32_t reserved49; /* ordinal185 */
4335 uint32_t reserved50; /* ordinal186 */
4336 uint32_t reserved51; /* ordinal187 */
4337 uint32_t reserved52; /* ordinal188 */
4338 uint32_t reserved53; /* ordinal189 */
4339 uint32_t reserved54; /* ordinal190 */
4340 uint32_t reserved55; /* ordinal191 */
4341 uint32_t iqtimer_pkt_header; /* ordinal192 */
4342 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
4343 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
4344 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
4345 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
4346 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
4347 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
4348 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
4349 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
4350 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
4351 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
4352 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
4353 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
4354 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
4355 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
4356 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
4357 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
4358 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
4359 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
4360 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
4361 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
4362 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
4363 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
4364 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
4365 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
4366 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
4367 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
4368 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
4369 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
4370 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
4371 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
4372 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
4373 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
4374 uint32_t reserved56; /* ordinal225 */
4375 uint32_t reserved57; /* ordinal226 */
4376 uint32_t reserved58; /* ordinal227 */
4377 uint32_t set_resources_header; /* ordinal228 */
4378 uint32_t set_resources_dw1; /* ordinal229 */
4379 uint32_t set_resources_dw2; /* ordinal230 */
4380 uint32_t set_resources_dw3; /* ordinal231 */
4381 uint32_t set_resources_dw4; /* ordinal232 */
4382 uint32_t set_resources_dw5; /* ordinal233 */
4383 uint32_t set_resources_dw6; /* ordinal234 */
4384 uint32_t set_resources_dw7; /* ordinal235 */
4385 uint32_t reserved59; /* ordinal236 */
4386 uint32_t reserved60; /* ordinal237 */
4387 uint32_t reserved61; /* ordinal238 */
4388 uint32_t reserved62; /* ordinal239 */
4389 uint32_t reserved63; /* ordinal240 */
4390 uint32_t reserved64; /* ordinal241 */
4391 uint32_t reserved65; /* ordinal242 */
4392 uint32_t reserved66; /* ordinal243 */
4393 uint32_t reserved67; /* ordinal244 */
4394 uint32_t reserved68; /* ordinal245 */
4395 uint32_t reserved69; /* ordinal246 */
4396 uint32_t reserved70; /* ordinal247 */
4397 uint32_t reserved71; /* ordinal248 */
4398 uint32_t reserved72; /* ordinal249 */
4399 uint32_t reserved73; /* ordinal250 */
4400 uint32_t reserved74; /* ordinal251 */
4401 uint32_t reserved75; /* ordinal252 */
4402 uint32_t reserved76; /* ordinal253 */
4403 uint32_t reserved77; /* ordinal254 */
4404 uint32_t reserved78; /* ordinal255 */
4405
4406 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
4407};
4408
4409static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
4410{
4411 int i, r;
4412
4413 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4414 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4415
4416 if (ring->mqd_obj) {
4417 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4418 if (unlikely(r != 0))
4419 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
4420
4421 amdgpu_bo_unpin(ring->mqd_obj);
4422 amdgpu_bo_unreserve(ring->mqd_obj);
4423
4424 amdgpu_bo_unref(&ring->mqd_obj);
4425 ring->mqd_obj = NULL;
4426 }
4427 }
4428}
4429
4430static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4431{
4432 int r, i, j;
4433 u32 tmp;
4434 bool use_doorbell = true;
4435 u64 hqd_gpu_addr;
4436 u64 mqd_gpu_addr;
4437 u64 eop_gpu_addr;
4438 u64 wb_gpu_addr;
4439 u32 *buf;
4440 struct vi_mqd *mqd;
4441
4442 /* init the pipes */
4443 mutex_lock(&adev->srbm_mutex);
4444 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4445 int me = (i < 4) ? 1 : 2;
4446 int pipe = (i < 4) ? i : (i - 4);
4447
4448 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
4449 eop_gpu_addr >>= 8;
4450
4451 vi_srbm_select(adev, me, pipe, 0, 0);
4452
4453 /* write the EOP addr */
4454 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
4455 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
4456
4457 /* set the VMID assigned */
4458 WREG32(mmCP_HQD_VMID, 0);
4459
4460 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4461 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4462 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4463 (order_base_2(MEC_HPD_SIZE / 4) - 1));
4464 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
4465 }
4466 vi_srbm_select(adev, 0, 0, 0, 0);
4467 mutex_unlock(&adev->srbm_mutex);
4468
4469 /* init the queues. Just two for now. */
4470 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4471 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4472
4473 if (ring->mqd_obj == NULL) {
4474 r = amdgpu_bo_create(adev,
4475 sizeof(struct vi_mqd),
4476 PAGE_SIZE, true,
4477 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
72d7668b 4478 NULL, &ring->mqd_obj);
aaa36a97
AD		 4479 if (r) {
4480 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
4481 return r;
4482 }
4483 }
4484
4485 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4486 if (unlikely(r != 0)) {
4487 gfx_v8_0_cp_compute_fini(adev);
4488 return r;
4489 }
4490 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
4491 &mqd_gpu_addr);
4492 if (r) {
4493 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
4494 gfx_v8_0_cp_compute_fini(adev);
4495 return r;
4496 }
4497 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
4498 if (r) {
4499 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
4500 gfx_v8_0_cp_compute_fini(adev);
4501 return r;
4502 }
4503
4504 /* init the mqd struct */
4505 memset(buf, 0, sizeof(struct vi_mqd));
4506
4507 mqd = (struct vi_mqd *)buf;
4508 mqd->header = 0xC0310800;
4509 mqd->compute_pipelinestat_enable = 0x00000001;
4510 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4511 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4512 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4513 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4514 mqd->compute_misc_reserved = 0x00000003;
4515
4516 mutex_lock(&adev->srbm_mutex);
4517 vi_srbm_select(adev, ring->me,
4518 ring->pipe,
4519 ring->queue, 0);
4520
4521 /* disable wptr polling */
4522 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
4523 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
4524 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
4525
4526 mqd->cp_hqd_eop_base_addr_lo =
4527 RREG32(mmCP_HQD_EOP_BASE_ADDR);
4528 mqd->cp_hqd_eop_base_addr_hi =
4529 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
4530
4531 /* enable doorbell? */
4532 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4533 if (use_doorbell) {
4534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4535 } else {
4536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
4537 }
4538 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
4539 mqd->cp_hqd_pq_doorbell_control = tmp;
4540
4541 /* disable the queue if it's active */
4542 mqd->cp_hqd_dequeue_request = 0;
4543 mqd->cp_hqd_pq_rptr = 0;
4544 mqd->cp_hqd_pq_wptr= 0;
4545 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
4546 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
4547 for (j = 0; j < adev->usec_timeout; j++) {
4548 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
4549 break;
4550 udelay(1);
4551 }
4552 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
4553 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
4554 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4555 }
4556
4557 /* set the pointer to the MQD */
4558 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
4559 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4560 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
4561 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
4562
4563 /* set MQD vmid to 0 */
4564 tmp = RREG32(mmCP_MQD_CONTROL);
4565 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4566 WREG32(mmCP_MQD_CONTROL, tmp);
4567 mqd->cp_mqd_control = tmp;
4568
4569 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4570 hqd_gpu_addr = ring->gpu_addr >> 8;
4571 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4572 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4573 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
4574 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
4575
4576 /* set up the HQD, this is similar to CP_RB0_CNTL */
4577 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4579 (order_base_2(ring->ring_size / 4) - 1));
4580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4581 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4582#ifdef __BIG_ENDIAN
4583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4584#endif
4585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4587 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4588 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4589 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
4590 mqd->cp_hqd_pq_control = tmp;
4591
4592 /* set the wb address wether it's enabled or not */
4593 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4594 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4595 mqd->cp_hqd_pq_rptr_report_addr_hi =
4596 upper_32_bits(wb_gpu_addr) & 0xffff;
4597 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
4598 mqd->cp_hqd_pq_rptr_report_addr_lo);
4599 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4600 mqd->cp_hqd_pq_rptr_report_addr_hi);
4601
4602 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4603 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4604 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4605 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4606 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
4607 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
4608 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4609
4610 /* enable the doorbell if requested */
4611 if (use_doorbell) {
bddf8026 4612 if ((adev->asic_type == CHIP_CARRIZO) ||
e3c7656c 4613 (adev->asic_type == CHIP_FIJI) ||
68182d90 4614 (adev->asic_type == CHIP_STONEY) ||
2cc0c0b5
FC		 4615 (adev->asic_type == CHIP_POLARIS11) ||
4616 (adev->asic_type == CHIP_POLARIS10)) {
aaa36a97
AD		 4617 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
4618 AMDGPU_DOORBELL_KIQ << 2);
4619 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
b8826b0c 4620 AMDGPU_DOORBELL_MEC_RING7 << 2);
aaa36a97
AD		 4621 }
4622 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4624 DOORBELL_OFFSET, ring->doorbell_index);
4625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
4626 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
4627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
4628 mqd->cp_hqd_pq_doorbell_control = tmp;
4629
4630 } else {
4631 mqd->cp_hqd_pq_doorbell_control = 0;
4632 }
4633 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
4634 mqd->cp_hqd_pq_doorbell_control);
4635
845253e7
SJ		 4636 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4637 ring->wptr = 0;
4638 mqd->cp_hqd_pq_wptr = ring->wptr;
4639 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4640 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4641
aaa36a97
AD		 4642 /* set the vmid for the queue */
4643 mqd->cp_hqd_vmid = 0;
4644 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
4645
4646 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4647 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4648 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
4649 mqd->cp_hqd_persistent_state = tmp;
68182d90 4650 if (adev->asic_type == CHIP_STONEY ||
2cc0c0b5
FC		 4651 adev->asic_type == CHIP_POLARIS11 ||
4652 adev->asic_type == CHIP_POLARIS10) {
3b55ddad
FC		 4653 tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
4654 tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
4655 WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
4656 }
aaa36a97
AD		 4657
4658 /* activate the queue */
4659 mqd->cp_hqd_active = 1;
4660 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
4661
4662 vi_srbm_select(adev, 0, 0, 0, 0);
4663 mutex_unlock(&adev->srbm_mutex);
4664
4665 amdgpu_bo_kunmap(ring->mqd_obj);
4666 amdgpu_bo_unreserve(ring->mqd_obj);
4667 }
4668
4669 if (use_doorbell) {
4670 tmp = RREG32(mmCP_PQ_STATUS);
4671 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4672 WREG32(mmCP_PQ_STATUS, tmp);
4673 }
4674
6e9821b2 4675 gfx_v8_0_cp_compute_enable(adev, true);
aaa36a97
AD		 4676
4677 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4678 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4679
4680 ring->ready = true;
4681 r = amdgpu_ring_test_ring(ring);
4682 if (r)
4683 ring->ready = false;
4684 }
4685
4686 return 0;
4687}
4688
4689static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4690{
4691 int r;
4692
e3c7656c 4693 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 4694 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4695
e61710c5 4696 if (!adev->pp_enabled) {
ba5c2a87
RZ		 4697 if (!adev->firmware.smu_load) {
4698 /* legacy firmware loading */
4699 r = gfx_v8_0_cp_gfx_load_microcode(adev);
4700 if (r)
4701 return r;
aaa36a97 4702
ba5c2a87
RZ		 4703 r = gfx_v8_0_cp_compute_load_microcode(adev);
4704 if (r)
4705 return r;
4706 } else {
4707 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4708 AMDGPU_UCODE_ID_CP_CE);
4709 if (r)
4710 return -EINVAL;
4711
4712 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4713 AMDGPU_UCODE_ID_CP_PFP);
4714 if (r)
4715 return -EINVAL;
4716
4717 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4718 AMDGPU_UCODE_ID_CP_ME);
4719 if (r)
4720 return -EINVAL;
4721
951e0962
AD		 4722 if (adev->asic_type == CHIP_TOPAZ) {
4723 r = gfx_v8_0_cp_compute_load_microcode(adev);
4724 if (r)
4725 return r;
4726 } else {
4727 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
4728 AMDGPU_UCODE_ID_CP_MEC1);
4729 if (r)
4730 return -EINVAL;
4731 }
ba5c2a87 4732 }
aaa36a97
AD		 4733 }
4734
4735 r = gfx_v8_0_cp_gfx_resume(adev);
4736 if (r)
4737 return r;
4738
4739 r = gfx_v8_0_cp_compute_resume(adev);
4740 if (r)
4741 return r;
4742
4743 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4744
4745 return 0;
4746}
4747
4748static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4749{
4750 gfx_v8_0_cp_gfx_enable(adev, enable);
4751 gfx_v8_0_cp_compute_enable(adev, enable);
4752}
4753
5fc3aeeb 4754static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 4755{
4756 int r;
5fc3aeeb 4757 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4758
4759 gfx_v8_0_init_golden_registers(adev);
4760
4761 gfx_v8_0_gpu_init(adev);
4762
4763 r = gfx_v8_0_rlc_resume(adev);
4764 if (r)
4765 return r;
4766
4767 r = gfx_v8_0_cp_resume(adev);
4768 if (r)
4769 return r;
4770
4771 return r;
4772}
4773
5fc3aeeb 4774static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 4775{
5fc3aeeb 4776 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4777
1d22a454
AD		 4778 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4779 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
aaa36a97
AD		 4780 gfx_v8_0_cp_enable(adev, false);
4781 gfx_v8_0_rlc_stop(adev);
4782 gfx_v8_0_cp_compute_fini(adev);
4783
62a86fc2
EH		 4784 amdgpu_set_powergating_state(adev,
4785 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE);
4786
aaa36a97
AD		 4787 return 0;
4788}
4789
5fc3aeeb 4790static int gfx_v8_0_suspend(void *handle)
aaa36a97 4791{
5fc3aeeb 4792 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4793
aaa36a97
AD		 4794 return gfx_v8_0_hw_fini(adev);
4795}
4796
5fc3aeeb 4797static int gfx_v8_0_resume(void *handle)
aaa36a97 4798{
5fc3aeeb 4799 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4800
aaa36a97
AD		 4801 return gfx_v8_0_hw_init(adev);
4802}
4803
5fc3aeeb 4804static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 4805{
5fc3aeeb 4806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4807
aaa36a97
AD		 4808 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
4809 return false;
4810 else
4811 return true;
4812}
4813
5fc3aeeb 4814static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 4815{
4816 unsigned i;
4817 u32 tmp;
5fc3aeeb 4818 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4819
4820 for (i = 0; i < adev->usec_timeout; i++) {
4821 /* read MC_STATUS */
4822 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4823
4824 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4825 return 0;
4826 udelay(1);
4827 }
4828 return -ETIMEDOUT;
4829}
4830
5fc3aeeb 4831static int gfx_v8_0_soft_reset(void *handle)
aaa36a97
AD		 4832{
4833 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4834 u32 tmp;
5fc3aeeb 4835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 4836
4837 /* GRBM_STATUS */
4838 tmp = RREG32(mmGRBM_STATUS);
4839 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4840 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4841 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4842 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4843 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4844 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4845 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4846 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4847 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4848 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4849 }
4850
4851 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4852 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4853 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4854 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4855 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4856 }
4857
4858 /* GRBM_STATUS2 */
4859 tmp = RREG32(mmGRBM_STATUS2);
4860 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4861 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4862 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4863
4864 /* SRBM_STATUS */
4865 tmp = RREG32(mmSRBM_STATUS);
4866 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4867 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4868 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4869
4870 if (grbm_soft_reset || srbm_soft_reset) {
aaa36a97
AD		 4871 /* stop the rlc */
4872 gfx_v8_0_rlc_stop(adev);
4873
4874 /* Disable GFX parsing/prefetching */
4875 gfx_v8_0_cp_gfx_enable(adev, false);
4876
4877 /* Disable MEC parsing/prefetching */
7776a693
AD		 4878 gfx_v8_0_cp_compute_enable(adev, false);
4879
4880 if (grbm_soft_reset || srbm_soft_reset) {
4881 tmp = RREG32(mmGMCON_DEBUG);
4882 tmp = REG_SET_FIELD(tmp,
4883 GMCON_DEBUG, GFX_STALL, 1);
4884 tmp = REG_SET_FIELD(tmp,
4885 GMCON_DEBUG, GFX_CLEAR, 1);
4886 WREG32(mmGMCON_DEBUG, tmp);
4887
4888 udelay(50);
4889 }
aaa36a97
AD		 4890
4891 if (grbm_soft_reset) {
4892 tmp = RREG32(mmGRBM_SOFT_RESET);
4893 tmp |= grbm_soft_reset;
4894 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4895 WREG32(mmGRBM_SOFT_RESET, tmp);
4896 tmp = RREG32(mmGRBM_SOFT_RESET);
4897
4898 udelay(50);
4899
4900 tmp &= ~grbm_soft_reset;
4901 WREG32(mmGRBM_SOFT_RESET, tmp);
4902 tmp = RREG32(mmGRBM_SOFT_RESET);
4903 }
4904
4905 if (srbm_soft_reset) {
4906 tmp = RREG32(mmSRBM_SOFT_RESET);
4907 tmp |= srbm_soft_reset;
4908 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4909 WREG32(mmSRBM_SOFT_RESET, tmp);
4910 tmp = RREG32(mmSRBM_SOFT_RESET);
4911
4912 udelay(50);
4913
4914 tmp &= ~srbm_soft_reset;
4915 WREG32(mmSRBM_SOFT_RESET, tmp);
4916 tmp = RREG32(mmSRBM_SOFT_RESET);
4917 }
7776a693
AD		 4918
4919 if (grbm_soft_reset || srbm_soft_reset) {
4920 tmp = RREG32(mmGMCON_DEBUG);
4921 tmp = REG_SET_FIELD(tmp,
4922 GMCON_DEBUG, GFX_STALL, 0);
4923 tmp = REG_SET_FIELD(tmp,
4924 GMCON_DEBUG, GFX_CLEAR, 0);
4925 WREG32(mmGMCON_DEBUG, tmp);
4926 }
4927
aaa36a97
AD		 4928 /* Wait a little for things to settle down */
4929 udelay(50);
aaa36a97
AD		 4930 }
4931 return 0;
4932}
4933
4934/**
4935 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
4936 *
4937 * @adev: amdgpu_device pointer
4938 *
4939 * Fetches a GPU clock counter snapshot.
4940 * Returns the 64 bit clock counter snapshot.
4941 */
4942uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4943{
4944 uint64_t clock;
4945
4946 mutex_lock(&adev->gfx.gpu_clock_mutex);
4947 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4948 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4949 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4950 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4951 return clock;
4952}
4953
4954static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4955 uint32_t vmid,
4956 uint32_t gds_base, uint32_t gds_size,
4957 uint32_t gws_base, uint32_t gws_size,
4958 uint32_t oa_base, uint32_t oa_size)
4959{
4960 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4961 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4962
4963 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4964 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4965
4966 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4967 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4968
4969 /* GDS Base */
4970 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4971 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4972 WRITE_DATA_DST_SEL(0)));
4973 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4974 amdgpu_ring_write(ring, 0);
4975 amdgpu_ring_write(ring, gds_base);
4976
4977 /* GDS Size */
4978 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4979 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4980 WRITE_DATA_DST_SEL(0)));
4981 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4982 amdgpu_ring_write(ring, 0);
4983 amdgpu_ring_write(ring, gds_size);
4984
4985 /* GWS */
4986 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4987 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4988 WRITE_DATA_DST_SEL(0)));
4989 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4990 amdgpu_ring_write(ring, 0);
4991 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4992
4993 /* OA */
4994 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4995 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4996 WRITE_DATA_DST_SEL(0)));
4997 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4998 amdgpu_ring_write(ring, 0);
4999 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5000}
5001
5fc3aeeb 5002static int gfx_v8_0_early_init(void *handle)
aaa36a97 5003{
5fc3aeeb 5004 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 5005
5006 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5007 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
5008 gfx_v8_0_set_ring_funcs(adev);
5009 gfx_v8_0_set_irq_funcs(adev);
5010 gfx_v8_0_set_gds_init(adev);
dbff57bc 5011 gfx_v8_0_set_rlc_funcs(adev);
aaa36a97
AD		 5012
5013 return 0;
5014}
5015
ccba7691
AD		 5016static int gfx_v8_0_late_init(void *handle)
5017{
5018 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5019 int r;
5020
1d22a454
AD		 5021 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5022 if (r)
5023 return r;
5024
5025 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5026 if (r)
5027 return r;
5028
ccba7691
AD		 5029 /* requires IBs so do in late init after IB pool is initialized */
5030 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5031 if (r)
5032 return r;
5033
62a86fc2
EH		 5034 amdgpu_set_powergating_state(adev,
5035 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE);
5036
ccba7691
AD		 5037 return 0;
5038}
5039
2cc0c0b5 5040static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
62a86fc2
EH		 5041 bool enable)
5042{
5043 uint32_t data, temp;
5044
5045 /* Send msg to SMU via Powerplay */
5046 amdgpu_set_powergating_state(adev,
5047 AMD_IP_BLOCK_TYPE_SMC,
5048 enable ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
5049
5050 if (enable) {
5051 /* Enable static MGPG */
5052 temp = data = RREG32(mmRLC_PG_CNTL);
5053 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
5054
5055 if (temp != data)
5056 WREG32(mmRLC_PG_CNTL, data);
5057 } else {
5058 temp = data = RREG32(mmRLC_PG_CNTL);
5059 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
5060
5061 if (temp != data)
5062 WREG32(mmRLC_PG_CNTL, data);
5063 }
5064}
5065
2cc0c0b5 5066static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
62a86fc2
EH		 5067 bool enable)
5068{
5069 uint32_t data, temp;
5070
5071 if (enable) {
5072 /* Enable dynamic MGPG */
5073 temp = data = RREG32(mmRLC_PG_CNTL);
5074 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
5075
5076 if (temp != data)
5077 WREG32(mmRLC_PG_CNTL, data);
5078 } else {
5079 temp = data = RREG32(mmRLC_PG_CNTL);
5080 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
5081
5082 if (temp != data)
5083 WREG32(mmRLC_PG_CNTL, data);
5084 }
5085}
5086
2cc0c0b5 5087static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
62a86fc2
EH		 5088 bool enable)
5089{
5090 uint32_t data, temp;
5091
5092 if (enable) {
5093 /* Enable quick PG */
5094 temp = data = RREG32(mmRLC_PG_CNTL);
5095 data |= 0x100000;
5096
5097 if (temp != data)
5098 WREG32(mmRLC_PG_CNTL, data);
5099 } else {
5100 temp = data = RREG32(mmRLC_PG_CNTL);
5101 data &= ~0x100000;
5102
5103 if (temp != data)
5104 WREG32(mmRLC_PG_CNTL, data);
5105 }
5106}
5107
5fc3aeeb 5108static int gfx_v8_0_set_powergating_state(void *handle,
5109 enum amd_powergating_state state)
aaa36a97 5110{
62a86fc2
EH		 5111 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5112
5113 if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5114 return 0;
5115
5116 switch (adev->asic_type) {
2cc0c0b5
FC		 5117 case CHIP_POLARIS11:
5118 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)
5119 polaris11_enable_gfx_static_mg_power_gating(adev,
62a86fc2 5120 state == AMD_PG_STATE_GATE ? true : false);
2cc0c0b5
FC		 5121 else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)
5122 polaris11_enable_gfx_dynamic_mg_power_gating(adev,
62a86fc2
EH		 5123 state == AMD_PG_STATE_GATE ? true : false);
5124 else
2cc0c0b5 5125 polaris11_enable_gfx_quick_mg_power_gating(adev,
62a86fc2
EH		 5126 state == AMD_PG_STATE_GATE ? true : false);
5127 break;
5128 default:
5129 break;
5130 }
5131
aaa36a97
AD		 5132 return 0;
5133}
5134
79deaaf4 5135static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
14698b6c 5136 uint32_t reg_addr, uint32_t cmd)
6e378858
EH		 5137{
5138 uint32_t data;
5139
5140 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5141
5142 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5143 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5144
5145 data = RREG32(mmRLC_SERDES_WR_CTRL);
146f256f
AD		 5146 if (adev->asic_type == CHIP_STONEY)
5147 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
6e378858
EH		 5148 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5149 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5150 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5151 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5152 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5153 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5154 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
6e378858 5155 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
146f256f
AD		 5156 else
5157 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5158 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5159 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5160 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5161 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5162 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5163 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5164 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5165 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5166 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5167 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
6e378858 5168 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
146f256f
AD		 5169 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5170 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5171 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
6e378858
EH		 5172
5173 WREG32(mmRLC_SERDES_WR_CTRL, data);
5174}
5175
dbff57bc
AD		 5176#define MSG_ENTER_RLC_SAFE_MODE 1
5177#define MSG_EXIT_RLC_SAFE_MODE 0
5178
5179#define RLC_GPR_REG2__REQ_MASK 0x00000001
5180#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5181#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5182
5183static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
5184{
5185 u32 data = 0;
5186 unsigned i;
5187
5188 data = RREG32(mmRLC_CNTL);
5189 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5190 return;
5191
5192 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5193 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5194 AMD_PG_SUPPORT_GFX_DMG))) {
5195 data |= RLC_GPR_REG2__REQ_MASK;
5196 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5197 data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5198 WREG32(mmRLC_GPR_REG2, data);
5199
5200 for (i = 0; i < adev->usec_timeout; i++) {
5201 if ((RREG32(mmRLC_GPM_STAT) &
5202 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5203 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5204 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5205 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5206 break;
5207 udelay(1);
5208 }
5209
5210 for (i = 0; i < adev->usec_timeout; i++) {
5211 if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
5212 break;
5213 udelay(1);
5214 }
5215 adev->gfx.rlc.in_safe_mode = true;
5216 }
5217}
5218
5219static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)
5220{
5221 u32 data;
5222 unsigned i;
5223
5224 data = RREG32(mmRLC_CNTL);
5225 if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
5226 return;
5227
5228 if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
5229 (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
5230 AMD_PG_SUPPORT_GFX_DMG))) {
5231 data |= RLC_GPR_REG2__REQ_MASK;
5232 data &= ~RLC_GPR_REG2__MESSAGE_MASK;
5233 data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
5234 WREG32(mmRLC_GPR_REG2, data);
5235 adev->gfx.rlc.in_safe_mode = false;
5236 }
5237
5238 for (i = 0; i < adev->usec_timeout; i++) {
5239 if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
5240 break;
5241 udelay(1);
5242 }
5243}
5244
5245static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
5246{
5247 u32 data;
5248 unsigned i;
5249
5250 data = RREG32(mmRLC_CNTL);
5251 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5252 return;
5253
5254 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5255 data |= RLC_SAFE_MODE__CMD_MASK;
5256 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5257 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5258 WREG32(mmRLC_SAFE_MODE, data);
5259
5260 for (i = 0; i < adev->usec_timeout; i++) {
5261 if ((RREG32(mmRLC_GPM_STAT) &
5262 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5263 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5264 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5265 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5266 break;
5267 udelay(1);
5268 }
5269
5270 for (i = 0; i < adev->usec_timeout; i++) {
5271 if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
5272 break;
5273 udelay(1);
5274 }
5275 adev->gfx.rlc.in_safe_mode = true;
5276 }
5277}
5278
5279static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
5280{
5281 u32 data = 0;
5282 unsigned i;
5283
5284 data = RREG32(mmRLC_CNTL);
5285 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
5286 return;
5287
5288 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
5289 if (adev->gfx.rlc.in_safe_mode) {
5290 data |= RLC_SAFE_MODE__CMD_MASK;
5291 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5292 WREG32(mmRLC_SAFE_MODE, data);
5293 adev->gfx.rlc.in_safe_mode = false;
5294 }
5295 }
5296
5297 for (i = 0; i < adev->usec_timeout; i++) {
5298 if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
5299 break;
5300 udelay(1);
5301 }
5302}
5303
5304static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev)
5305{
5306 adev->gfx.rlc.in_safe_mode = true;
5307}
5308
5309static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev)
5310{
5311 adev->gfx.rlc.in_safe_mode = false;
5312}
5313
5314static const struct amdgpu_rlc_funcs cz_rlc_funcs = {
5315 .enter_safe_mode = cz_enter_rlc_safe_mode,
5316 .exit_safe_mode = cz_exit_rlc_safe_mode
5317};
5318
5319static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5320 .enter_safe_mode = iceland_enter_rlc_safe_mode,
5321 .exit_safe_mode = iceland_exit_rlc_safe_mode
5322};
5323
5324static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = {
5325 .enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode,
5326 .exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode
5327};
5328
5329static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5330 bool enable)
6e378858
EH		 5331{
5332 uint32_t temp, data;
5333
dbff57bc
AD		 5334 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5335
6e378858 5336 /* It is disabled by HW by default */
14698b6c
AD		 5337 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5338 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5339 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5340 /* 1 - RLC memory Light sleep */
5341 temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
5342 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5343 if (temp != data)
5344 WREG32(mmRLC_MEM_SLP_CNTL, data);
5345 }
6e378858 5346
14698b6c
AD		 5347 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5348 /* 2 - CP memory Light sleep */
5349 temp = data = RREG32(mmCP_MEM_SLP_CNTL);
5350 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5351 if (temp != data)
5352 WREG32(mmCP_MEM_SLP_CNTL, data);
5353 }
5354 }
6e378858
EH		 5355
5356 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5357 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
dbff57bc
AD		 5358 if (adev->flags & AMD_IS_APU)
5359 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5360 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5361 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5362 else
5363 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5364 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5365 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5366 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
6e378858
EH		 5367
5368 if (temp != data)
5369 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5370
5371 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5372 gfx_v8_0_wait_for_rlc_serdes(adev);
5373
5374 /* 5 - clear mgcg override */
79deaaf4 5375 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858 5376
14698b6c
AD		 5377 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5378 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5379 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5380 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5381 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5382 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5383 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5384 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5385 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5386 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5387 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5388 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5389 if (temp != data)
5390 WREG32(mmCGTS_SM_CTRL_REG, data);
5391 }
6e378858
EH		 5392 udelay(50);
5393
5394 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5395 gfx_v8_0_wait_for_rlc_serdes(adev);
5396 } else {
5397 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5398 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5399 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5400 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5401 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5402 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5403 if (temp != data)
5404 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5405
5406 /* 2 - disable MGLS in RLC */
5407 data = RREG32(mmRLC_MEM_SLP_CNTL);
5408 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5409 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5410 WREG32(mmRLC_MEM_SLP_CNTL, data);
5411 }
5412
5413 /* 3 - disable MGLS in CP */
5414 data = RREG32(mmCP_MEM_SLP_CNTL);
5415 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5416 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5417 WREG32(mmCP_MEM_SLP_CNTL, data);
5418 }
5419
5420 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5421 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5422 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5423 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5424 if (temp != data)
5425 WREG32(mmCGTS_SM_CTRL_REG, data);
5426
5427 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5428 gfx_v8_0_wait_for_rlc_serdes(adev);
5429
5430 /* 6 - set mgcg override */
79deaaf4 5431 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5432
5433 udelay(50);
5434
5435 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5436 gfx_v8_0_wait_for_rlc_serdes(adev);
5437 }
dbff57bc
AD		 5438
5439 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858
EH		 5440}
5441
dbff57bc
AD		 5442static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5443 bool enable)
6e378858
EH		 5444{
5445 uint32_t temp, temp1, data, data1;
5446
5447 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5448
dbff57bc
AD		 5449 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5450
14698b6c 5451 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
6e378858
EH		 5452 /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
5453 * Cmp_busy/GFX_Idle interrupts
5454 */
5455 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5456
5457 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5458 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5459 if (temp1 != data1)
5460 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5461
5462 /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5463 gfx_v8_0_wait_for_rlc_serdes(adev);
5464
5465 /* 3 - clear cgcg override */
79deaaf4 5466 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
6e378858
EH		 5467
5468 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5469 gfx_v8_0_wait_for_rlc_serdes(adev);
5470
5471 /* 4 - write cmd to set CGLS */
79deaaf4 5472 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
6e378858
EH		 5473
5474 /* 5 - enable cgcg */
5475 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5476
14698b6c
AD		 5477 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5478 /* enable cgls*/
5479 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
6e378858 5480
14698b6c
AD		 5481 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5482 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
6e378858 5483
14698b6c
AD		 5484 if (temp1 != data1)
5485 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5486 } else {
5487 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5488 }
6e378858
EH		 5489
5490 if (temp != data)
5491 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5492 } else {
5493 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5494 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5495
5496 /* TEST CGCG */
5497 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5498 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5499 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5500 if (temp1 != data1)
5501 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5502
5503 /* read gfx register to wake up cgcg */
5504 RREG32(mmCB_CGTT_SCLK_CTRL);
5505 RREG32(mmCB_CGTT_SCLK_CTRL);
5506 RREG32(mmCB_CGTT_SCLK_CTRL);
5507 RREG32(mmCB_CGTT_SCLK_CTRL);
5508
5509 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5510 gfx_v8_0_wait_for_rlc_serdes(adev);
5511
5512 /* write cmd to Set CGCG Overrride */
79deaaf4 5513 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
6e378858
EH		 5514
5515 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5516 gfx_v8_0_wait_for_rlc_serdes(adev);
5517
5518 /* write cmd to Clear CGLS */
79deaaf4 5519 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
6e378858
EH		 5520
5521 /* disable cgcg, cgls should be disabled too. */
5522 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
14698b6c 5523 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
6e378858
EH		 5524 if (temp != data)
5525 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5526 }
dbff57bc
AD		 5527
5528 adev->gfx.rlc.funcs->exit_safe_mode(adev);
6e378858 5529}
dbff57bc
AD		 5530static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5531 bool enable)
6e378858
EH		 5532{
5533 if (enable) {
5534 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5535 * === MGCG + MGLS + TS(CG/LS) ===
5536 */
dbff57bc
AD		 5537 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5538 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
6e378858
EH		 5539 } else {
5540 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5541 * === CGCG + CGLS ===
5542 */
dbff57bc
AD		 5543 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5544 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
6e378858
EH		 5545 }
5546 return 0;
5547}
5548
5fc3aeeb 5549static int gfx_v8_0_set_clockgating_state(void *handle,
5550 enum amd_clockgating_state state)
aaa36a97 5551{
6e378858
EH		 5552 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5553
5554 switch (adev->asic_type) {
5555 case CHIP_FIJI:
dbff57bc
AD		 5556 case CHIP_CARRIZO:
5557 case CHIP_STONEY:
5558 gfx_v8_0_update_gfx_clock_gating(adev,
5559 state == AMD_CG_STATE_GATE ? true : false);
6e378858
EH		 5560 break;
5561 default:
5562 break;
5563 }
aaa36a97
AD		 5564 return 0;
5565}
5566
5567static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5568{
5569 u32 rptr;
5570
5571 rptr = ring->adev->wb.wb[ring->rptr_offs];
5572
5573 return rptr;
5574}
5575
5576static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5577{
5578 struct amdgpu_device *adev = ring->adev;
5579 u32 wptr;
5580
5581 if (ring->use_doorbell)
5582 /* XXX check if swapping is necessary on BE */
5583 wptr = ring->adev->wb.wb[ring->wptr_offs];
5584 else
5585 wptr = RREG32(mmCP_RB0_WPTR);
5586
5587 return wptr;
5588}
5589
5590static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5591{
5592 struct amdgpu_device *adev = ring->adev;
5593
5594 if (ring->use_doorbell) {
5595 /* XXX check if swapping is necessary on BE */
5596 adev->wb.wb[ring->wptr_offs] = ring->wptr;
5597 WDOORBELL32(ring->doorbell_index, ring->wptr);
5598 } else {
5599 WREG32(mmCP_RB0_WPTR, ring->wptr);
5600 (void)RREG32(mmCP_RB0_WPTR);
5601 }
5602}
5603
d2edb07b 5604static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 5605{
5606 u32 ref_and_mask, reg_mem_engine;
5607
5608 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
5609 switch (ring->me) {
5610 case 1:
5611 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
5612 break;
5613 case 2:
5614 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
5615 break;
5616 default:
5617 return;
5618 }
5619 reg_mem_engine = 0;
5620 } else {
5621 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
5622 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
5623 }
5624
5625 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5626 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
5627 WAIT_REG_MEM_FUNCTION(3) | /* == */
5628 reg_mem_engine));
5629 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
5630 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
5631 amdgpu_ring_write(ring, ref_and_mask);
5632 amdgpu_ring_write(ring, ref_and_mask);
5633 amdgpu_ring_write(ring, 0x20); /* poll interval */
5634}
5635
d35db561
CZ		 5636static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
5637{
5638 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5639 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5640 WRITE_DATA_DST_SEL(0) |
5641 WR_CONFIRM));
5642 amdgpu_ring_write(ring, mmHDP_DEBUG0);
5643 amdgpu_ring_write(ring, 0);
5644 amdgpu_ring_write(ring, 1);
5645
5646}
5647
93323131 5648static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 5649 struct amdgpu_ib *ib,
5650 unsigned vm_id, bool ctx_switch)
aaa36a97
AD		 5651{
5652 u32 header, control = 0;
5653 u32 next_rptr = ring->wptr + 5;
aa2bdb24 5654
f153d286 5655 if (ctx_switch)
aaa36a97
AD		 5656 next_rptr += 2;
5657
5658 next_rptr += 4;
5659 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5660 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5661 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5662 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
5663 amdgpu_ring_write(ring, next_rptr);
5664
aaa36a97 5665 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 5666 if (ctx_switch) {
aaa36a97
AD		 5667 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5668 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 5669 }
5670
de807f81 5671 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 5672 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
5673 else
5674 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5675
d88bf583 5676 control |= ib->length_dw | (vm_id << 24);
aaa36a97
AD		 5677
5678 amdgpu_ring_write(ring, header);
5679 amdgpu_ring_write(ring,
5680#ifdef __BIG_ENDIAN
5681 (2 << 0) |
5682#endif
5683 (ib->gpu_addr & 0xFFFFFFFC));
5684 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5685 amdgpu_ring_write(ring, control);
5686}
5687
93323131 5688static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 5689 struct amdgpu_ib *ib,
5690 unsigned vm_id, bool ctx_switch)
93323131 5691{
5692 u32 header, control = 0;
5693 u32 next_rptr = ring->wptr + 5;
5694
5695 control |= INDIRECT_BUFFER_VALID;
5696
5697 next_rptr += 4;
5698 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5699 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
5700 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
5701 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
5702 amdgpu_ring_write(ring, next_rptr);
5703
5704 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5705
d88bf583 5706 control |= ib->length_dw | (vm_id << 24);
93323131 5707
5708 amdgpu_ring_write(ring, header);
5709 amdgpu_ring_write(ring,
5710#ifdef __BIG_ENDIAN
5711 (2 << 0) |
5712#endif
5713 (ib->gpu_addr & 0xFFFFFFFC));
5714 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
5715 amdgpu_ring_write(ring, control);
5716}
5717
aaa36a97 5718static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 5719 u64 seq, unsigned flags)
aaa36a97 5720{
890ee23f
CZ		 5721 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5722 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5723
aaa36a97
AD		 5724 /* EVENT_WRITE_EOP - flush caches, send int */
5725 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
5726 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
5727 EOP_TC_ACTION_EN |
5728 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5729 EVENT_INDEX(5)));
5730 amdgpu_ring_write(ring, addr & 0xfffffffc);
90bea0ab 5731 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 5732 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 5733 amdgpu_ring_write(ring, lower_32_bits(seq));
5734 amdgpu_ring_write(ring, upper_32_bits(seq));
22c01cc4 5735
aaa36a97
AD		 5736}
5737
b8c7b39e 5738static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97
AD		 5739{
5740 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5907a0d8 5741 uint32_t seq = ring->fence_drv.sync_seq;
22c01cc4
AA		 5742 uint64_t addr = ring->fence_drv.gpu_addr;
5743
5744 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5745 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
9cac5373
CZ		 5746 WAIT_REG_MEM_FUNCTION(3) | /* equal */
5747 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
22c01cc4
AA		 5748 amdgpu_ring_write(ring, addr & 0xfffffffc);
5749 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
5750 amdgpu_ring_write(ring, seq);
5751 amdgpu_ring_write(ring, 0xffffffff);
5752 amdgpu_ring_write(ring, 4); /* poll interval */
aaa36a97 5753
5c3422b0 5754 if (usepfp) {
5755 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5756 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5757 amdgpu_ring_write(ring, 0);
5758 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5759 amdgpu_ring_write(ring, 0);
5760 }
b8c7b39e
CK		 5761}
5762
5763static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5764 unsigned vm_id, uint64_t pd_addr)
5765{
5766 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 5767
aaa36a97
AD		 5768 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5769 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
20a85ff8
CK		 5770 WRITE_DATA_DST_SEL(0)) |
5771 WR_CONFIRM);
aaa36a97
AD		 5772 if (vm_id < 8) {
5773 amdgpu_ring_write(ring,
5774 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
5775 } else {
5776 amdgpu_ring_write(ring,
5777 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
5778 }
5779 amdgpu_ring_write(ring, 0);
5780 amdgpu_ring_write(ring, pd_addr >> 12);
5781
aaa36a97
AD		 5782 /* bits 0-15 are the VM contexts0-15 */
5783 /* invalidate the cache */
5784 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5785 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5786 WRITE_DATA_DST_SEL(0)));
5787 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
5788 amdgpu_ring_write(ring, 0);
5789 amdgpu_ring_write(ring, 1 << vm_id);
5790
5791 /* wait for the invalidate to complete */
5792 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5793 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
5794 WAIT_REG_MEM_FUNCTION(0) | /* always */
5795 WAIT_REG_MEM_ENGINE(0))); /* me */
5796 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
5797 amdgpu_ring_write(ring, 0);
5798 amdgpu_ring_write(ring, 0); /* ref */
5799 amdgpu_ring_write(ring, 0); /* mask */
5800 amdgpu_ring_write(ring, 0x20); /* poll interval */
5801
5802 /* compute doesn't have PFP */
5803 if (usepfp) {
5804 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5805 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5806 amdgpu_ring_write(ring, 0x0);
5c3422b0 5807 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5808 amdgpu_ring_write(ring, 0);
5809 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5810 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 5811 }
5812}
5813
aaa36a97
AD		 5814static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5815{
5816 return ring->adev->wb.wb[ring->rptr_offs];
5817}
5818
5819static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5820{
5821 return ring->adev->wb.wb[ring->wptr_offs];
5822}
5823
5824static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5825{
5826 struct amdgpu_device *adev = ring->adev;
5827
5828 /* XXX check if swapping is necessary on BE */
5829 adev->wb.wb[ring->wptr_offs] = ring->wptr;
5830 WDOORBELL32(ring->doorbell_index, ring->wptr);
5831}
5832
5833static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
5834 u64 addr, u64 seq,
890ee23f 5835 unsigned flags)
aaa36a97 5836{
890ee23f
CZ		 5837 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5838 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5839
aaa36a97
AD		 5840 /* RELEASE_MEM - flush caches, send int */
5841 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
5842 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
5843 EOP_TC_ACTION_EN |
a3d5aaa8 5844 EOP_TC_WB_ACTION_EN |
aaa36a97
AD		 5845 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5846 EVENT_INDEX(5)));
890ee23f 5847 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 5848 amdgpu_ring_write(ring, addr & 0xfffffffc);
5849 amdgpu_ring_write(ring, upper_32_bits(addr));
5850 amdgpu_ring_write(ring, lower_32_bits(seq));
5851 amdgpu_ring_write(ring, upper_32_bits(seq));
5852}
5853
5854static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5855 enum amdgpu_interrupt_state state)
5856{
5857 u32 cp_int_cntl;
5858
5859 switch (state) {
5860 case AMDGPU_IRQ_STATE_DISABLE:
5861 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5862 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5863 TIME_STAMP_INT_ENABLE, 0);
5864 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5865 break;
5866 case AMDGPU_IRQ_STATE_ENABLE:
5867 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5868 cp_int_cntl =
5869 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5870 TIME_STAMP_INT_ENABLE, 1);
5871 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5872 break;
5873 default:
5874 break;
5875 }
5876}
5877
5878static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5879 int me, int pipe,
5880 enum amdgpu_interrupt_state state)
5881{
5882 u32 mec_int_cntl, mec_int_cntl_reg;
5883
5884 /*
5885 * amdgpu controls only pipe 0 of MEC1. That's why this function only
5886 * handles the setting of interrupts for this specific pipe. All other
5887 * pipes' interrupts are set by amdkfd.
5888 */
5889
5890 if (me == 1) {
5891 switch (pipe) {
5892 case 0:
5893 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
5894 break;
5895 default:
5896 DRM_DEBUG("invalid pipe %d\n", pipe);
5897 return;
5898 }
5899 } else {
5900 DRM_DEBUG("invalid me %d\n", me);
5901 return;
5902 }
5903
5904 switch (state) {
5905 case AMDGPU_IRQ_STATE_DISABLE:
5906 mec_int_cntl = RREG32(mec_int_cntl_reg);
5907 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5908 TIME_STAMP_INT_ENABLE, 0);
5909 WREG32(mec_int_cntl_reg, mec_int_cntl);
5910 break;
5911 case AMDGPU_IRQ_STATE_ENABLE:
5912 mec_int_cntl = RREG32(mec_int_cntl_reg);
5913 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5914 TIME_STAMP_INT_ENABLE, 1);
5915 WREG32(mec_int_cntl_reg, mec_int_cntl);
5916 break;
5917 default:
5918 break;
5919 }
5920}
5921
5922static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5923 struct amdgpu_irq_src *source,
5924 unsigned type,
5925 enum amdgpu_interrupt_state state)
5926{
5927 u32 cp_int_cntl;
5928
5929 switch (state) {
5930 case AMDGPU_IRQ_STATE_DISABLE:
5931 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5932 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5933 PRIV_REG_INT_ENABLE, 0);
5934 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5935 break;
5936 case AMDGPU_IRQ_STATE_ENABLE:
5937 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5938 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
04ab3b76 5939 PRIV_REG_INT_ENABLE, 1);
aaa36a97
AD		 5940 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5941 break;
5942 default:
5943 break;
5944 }
5945
5946 return 0;
5947}
5948
5949static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5950 struct amdgpu_irq_src *source,
5951 unsigned type,
5952 enum amdgpu_interrupt_state state)
5953{
5954 u32 cp_int_cntl;
5955
5956 switch (state) {
5957 case AMDGPU_IRQ_STATE_DISABLE:
5958 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5959 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5960 PRIV_INSTR_INT_ENABLE, 0);
5961 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5962 break;
5963 case AMDGPU_IRQ_STATE_ENABLE:
5964 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5965 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5966 PRIV_INSTR_INT_ENABLE, 1);
5967 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5968 break;
5969 default:
5970 break;
5971 }
5972
5973 return 0;
5974}
5975
5976static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5977 struct amdgpu_irq_src *src,
5978 unsigned type,
5979 enum amdgpu_interrupt_state state)
5980{
5981 switch (type) {
5982 case AMDGPU_CP_IRQ_GFX_EOP:
5983 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
5984 break;
5985 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5986 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5987 break;
5988 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5989 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5990 break;
5991 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5992 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5993 break;
5994 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5995 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5996 break;
5997 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5998 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5999 break;
6000 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6001 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6002 break;
6003 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6004 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6005 break;
6006 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6007 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6008 break;
6009 default:
6010 break;
6011 }
6012 return 0;
6013}
6014
6015static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6016 struct amdgpu_irq_src *source,
6017 struct amdgpu_iv_entry *entry)
6018{
6019 int i;
6020 u8 me_id, pipe_id, queue_id;
6021 struct amdgpu_ring *ring;
6022
6023 DRM_DEBUG("IH: CP EOP\n");
6024 me_id = (entry->ring_id & 0x0c) >> 2;
6025 pipe_id = (entry->ring_id & 0x03) >> 0;
6026 queue_id = (entry->ring_id & 0x70) >> 4;
6027
6028 switch (me_id) {
6029 case 0:
6030 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6031 break;
6032 case 1:
6033 case 2:
6034 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6035 ring = &adev->gfx.compute_ring[i];
6036 /* Per-queue interrupt is supported for MEC starting from VI.
6037 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6038 */
6039 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6040 amdgpu_fence_process(ring);
6041 }
6042 break;
6043 }
6044 return 0;
6045}
6046
6047static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6048 struct amdgpu_irq_src *source,
6049 struct amdgpu_iv_entry *entry)
6050{
6051 DRM_ERROR("Illegal register access in command stream\n");
6052 schedule_work(&adev->reset_work);
6053 return 0;
6054}
6055
6056static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6057 struct amdgpu_irq_src *source,
6058 struct amdgpu_iv_entry *entry)
6059{
6060 DRM_ERROR("Illegal instruction in command stream\n");
6061 schedule_work(&adev->reset_work);
6062 return 0;
6063}
6064
5fc3aeeb 6065const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
88a907d6 6066 .name = "gfx_v8_0",
aaa36a97 6067 .early_init = gfx_v8_0_early_init,
ccba7691 6068 .late_init = gfx_v8_0_late_init,
aaa36a97
AD		 6069 .sw_init = gfx_v8_0_sw_init,
6070 .sw_fini = gfx_v8_0_sw_fini,
6071 .hw_init = gfx_v8_0_hw_init,
6072 .hw_fini = gfx_v8_0_hw_fini,
6073 .suspend = gfx_v8_0_suspend,
6074 .resume = gfx_v8_0_resume,
6075 .is_idle = gfx_v8_0_is_idle,
6076 .wait_for_idle = gfx_v8_0_wait_for_idle,
6077 .soft_reset = gfx_v8_0_soft_reset,
aaa36a97
AD		 6078 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6079 .set_powergating_state = gfx_v8_0_set_powergating_state,
6080};
6081
6082static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6083 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
6084 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6085 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6086 .parse_cs = NULL,
93323131 6087 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
aaa36a97 6088 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
b8c7b39e 6089 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6090 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6091 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 6092 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6093 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6094 .test_ring = gfx_v8_0_ring_test_ring,
6095 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6096 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6097 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6098};
6099
6100static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6101 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
6102 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6103 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6104 .parse_cs = NULL,
93323131 6105 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
aaa36a97 6106 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
b8c7b39e 6107 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
aaa36a97
AD		 6108 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6109 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 6110 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
d35db561 6111 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 6112 .test_ring = gfx_v8_0_ring_test_ring,
6113 .test_ib = gfx_v8_0_ring_test_ib,
edff0e28 6114 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 6115 .pad_ib = amdgpu_ring_generic_pad_ib,
aaa36a97
AD		 6116};
6117
6118static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
6119{
6120 int i;
6121
6122 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6123 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
6124
6125 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6126 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
6127}
6128
6129static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
6130 .set = gfx_v8_0_set_eop_interrupt_state,
6131 .process = gfx_v8_0_eop_irq,
6132};
6133
6134static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
6135 .set = gfx_v8_0_set_priv_reg_fault_state,
6136 .process = gfx_v8_0_priv_reg_irq,
6137};
6138
6139static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
6140 .set = gfx_v8_0_set_priv_inst_fault_state,
6141 .process = gfx_v8_0_priv_inst_irq,
6142};
6143
6144static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
6145{
6146 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6147 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
6148
6149 adev->gfx.priv_reg_irq.num_types = 1;
6150 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
6151
6152 adev->gfx.priv_inst_irq.num_types = 1;
6153 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
6154}
6155
dbff57bc
AD		 6156static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
6157{
6158 switch (adev->asic_type) {
6159 case CHIP_TOPAZ:
6160 case CHIP_STONEY:
6161 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
6162 break;
6163 case CHIP_CARRIZO:
6164 adev->gfx.rlc.funcs = &cz_rlc_funcs;
6165 break;
6166 default:
6167 adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs;
6168 break;
6169 }
6170}
6171
aaa36a97
AD		 6172static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
6173{
6174 /* init asci gds info */
6175 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
6176 adev->gds.gws.total_size = 64;
6177 adev->gds.oa.total_size = 16;
6178
6179 if (adev->gds.mem.total_size == 64 * 1024) {
6180 adev->gds.mem.gfx_partition_size = 4096;
6181 adev->gds.mem.cs_partition_size = 4096;
6182
6183 adev->gds.gws.gfx_partition_size = 4;
6184 adev->gds.gws.cs_partition_size = 4;
6185
6186 adev->gds.oa.gfx_partition_size = 4;
6187 adev->gds.oa.cs_partition_size = 1;
6188 } else {
6189 adev->gds.mem.gfx_partition_size = 1024;
6190 adev->gds.mem.cs_partition_size = 1024;
6191
6192 adev->gds.gws.gfx_partition_size = 16;
6193 adev->gds.gws.cs_partition_size = 16;
6194
6195 adev->gds.oa.gfx_partition_size = 4;
6196 adev->gds.oa.cs_partition_size = 4;
6197 }
6198}
6199
8f8e00c1 6200static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
aaa36a97 6201{
8f8e00c1 6202 u32 data, mask;
aaa36a97 6203
8f8e00c1
AD		 6204 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
6205 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
aaa36a97 6206
8f8e00c1
AD		 6207 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6208 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
aaa36a97 6209
6157bd7a 6210 mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
aaa36a97 6211
8f8e00c1 6212 return (~data) & mask;
aaa36a97
AD		 6213}
6214
7dae69a2 6215static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
aaa36a97
AD		 6216{
6217 int i, j, k, counter, active_cu_number = 0;
6218 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 6219 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
aaa36a97 6220
6157bd7a
FC		 6221 memset(cu_info, 0, sizeof(*cu_info));
6222
aaa36a97
AD		 6223 mutex_lock(&adev->grbm_idx_mutex);
6224 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6225 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6226 mask = 1;
6227 ao_bitmap = 0;
6228 counter = 0;
8f8e00c1
AD		 6229 gfx_v8_0_select_se_sh(adev, i, j);
6230 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
aaa36a97
AD		 6231 cu_info->bitmap[i][j] = bitmap;
6232
8f8e00c1 6233 for (k = 0; k < 16; k ++) {
aaa36a97
AD		 6234 if (bitmap & mask) {
6235 if (counter < 2)
6236 ao_bitmap |= mask;
6237 counter ++;
6238 }
6239 mask <<= 1;
6240 }
6241 active_cu_number += counter;
6242 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
6243 }
6244 }
8f8e00c1
AD		 6245 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
6246 mutex_unlock(&adev->grbm_idx_mutex);
aaa36a97
AD		 6247
6248 cu_info->number = active_cu_number;
6249 cu_info->ao_cu_mask = ao_cu_mask;
aaa36a97 6250}
Linux 6.x block layer and io_uring tree(s)