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drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.c
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
486d807c 30#include "cik_structs.h"
a2e73f56
AD		 31#include "atom.h"
32#include "amdgpu_ucode.h"
33#include "clearstate_ci.h"
34
a2e73f56
AD		 35#include "dce/dce_8_0_d.h"
36#include "dce/dce_8_0_sh_mask.h"
37
38#include "bif/bif_4_1_d.h"
39#include "bif/bif_4_1_sh_mask.h"
40
41#include "gca/gfx_7_0_d.h"
42#include "gca/gfx_7_2_enum.h"
43#include "gca/gfx_7_2_sh_mask.h"
44
45#include "gmc/gmc_7_0_d.h"
46#include "gmc/gmc_7_0_sh_mask.h"
47
48#include "oss/oss_2_0_d.h"
49#include "oss/oss_2_0_sh_mask.h"
50
51#define GFX7_NUM_GFX_RINGS 1
268cb4c7 52#define GFX7_MEC_HPD_SIZE 2048
a2e73f56
AD		 53
54static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
56static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
a2e73f56
AD		 57
58MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
59MODULE_FIRMWARE("radeon/bonaire_me.bin");
60MODULE_FIRMWARE("radeon/bonaire_ce.bin");
61MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
62MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63
64MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
65MODULE_FIRMWARE("radeon/hawaii_me.bin");
66MODULE_FIRMWARE("radeon/hawaii_ce.bin");
67MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
68MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69
70MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
71MODULE_FIRMWARE("radeon/kaveri_me.bin");
72MODULE_FIRMWARE("radeon/kaveri_ce.bin");
73MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec.bin");
75MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
76
77MODULE_FIRMWARE("radeon/kabini_pfp.bin");
78MODULE_FIRMWARE("radeon/kabini_me.bin");
79MODULE_FIRMWARE("radeon/kabini_ce.bin");
80MODULE_FIRMWARE("radeon/kabini_rlc.bin");
81MODULE_FIRMWARE("radeon/kabini_mec.bin");
82
83MODULE_FIRMWARE("radeon/mullins_pfp.bin");
84MODULE_FIRMWARE("radeon/mullins_me.bin");
85MODULE_FIRMWARE("radeon/mullins_ce.bin");
86MODULE_FIRMWARE("radeon/mullins_rlc.bin");
87MODULE_FIRMWARE("radeon/mullins_mec.bin");
88
89static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
90{
91 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
92 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
93 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
94 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
95 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
96 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
97 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
98 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
99 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
100 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
101 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
102 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
103 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
104 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
105 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
106 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
107};
108
109static const u32 spectre_rlc_save_restore_register_list[] =
110{
111 (0x0e00 << 16) | (0xc12c >> 2),
112 0x00000000,
113 (0x0e00 << 16) | (0xc140 >> 2),
114 0x00000000,
115 (0x0e00 << 16) | (0xc150 >> 2),
116 0x00000000,
117 (0x0e00 << 16) | (0xc15c >> 2),
118 0x00000000,
119 (0x0e00 << 16) | (0xc168 >> 2),
120 0x00000000,
121 (0x0e00 << 16) | (0xc170 >> 2),
122 0x00000000,
123 (0x0e00 << 16) | (0xc178 >> 2),
124 0x00000000,
125 (0x0e00 << 16) | (0xc204 >> 2),
126 0x00000000,
127 (0x0e00 << 16) | (0xc2b4 >> 2),
128 0x00000000,
129 (0x0e00 << 16) | (0xc2b8 >> 2),
130 0x00000000,
131 (0x0e00 << 16) | (0xc2bc >> 2),
132 0x00000000,
133 (0x0e00 << 16) | (0xc2c0 >> 2),
134 0x00000000,
135 (0x0e00 << 16) | (0x8228 >> 2),
136 0x00000000,
137 (0x0e00 << 16) | (0x829c >> 2),
138 0x00000000,
139 (0x0e00 << 16) | (0x869c >> 2),
140 0x00000000,
141 (0x0600 << 16) | (0x98f4 >> 2),
142 0x00000000,
143 (0x0e00 << 16) | (0x98f8 >> 2),
144 0x00000000,
145 (0x0e00 << 16) | (0x9900 >> 2),
146 0x00000000,
147 (0x0e00 << 16) | (0xc260 >> 2),
148 0x00000000,
149 (0x0e00 << 16) | (0x90e8 >> 2),
150 0x00000000,
151 (0x0e00 << 16) | (0x3c000 >> 2),
152 0x00000000,
153 (0x0e00 << 16) | (0x3c00c >> 2),
154 0x00000000,
155 (0x0e00 << 16) | (0x8c1c >> 2),
156 0x00000000,
157 (0x0e00 << 16) | (0x9700 >> 2),
158 0x00000000,
159 (0x0e00 << 16) | (0xcd20 >> 2),
160 0x00000000,
161 (0x4e00 << 16) | (0xcd20 >> 2),
162 0x00000000,
163 (0x5e00 << 16) | (0xcd20 >> 2),
164 0x00000000,
165 (0x6e00 << 16) | (0xcd20 >> 2),
166 0x00000000,
167 (0x7e00 << 16) | (0xcd20 >> 2),
168 0x00000000,
169 (0x8e00 << 16) | (0xcd20 >> 2),
170 0x00000000,
171 (0x9e00 << 16) | (0xcd20 >> 2),
172 0x00000000,
173 (0xae00 << 16) | (0xcd20 >> 2),
174 0x00000000,
175 (0xbe00 << 16) | (0xcd20 >> 2),
176 0x00000000,
177 (0x0e00 << 16) | (0x89bc >> 2),
178 0x00000000,
179 (0x0e00 << 16) | (0x8900 >> 2),
180 0x00000000,
181 0x3,
182 (0x0e00 << 16) | (0xc130 >> 2),
183 0x00000000,
184 (0x0e00 << 16) | (0xc134 >> 2),
185 0x00000000,
186 (0x0e00 << 16) | (0xc1fc >> 2),
187 0x00000000,
188 (0x0e00 << 16) | (0xc208 >> 2),
189 0x00000000,
190 (0x0e00 << 16) | (0xc264 >> 2),
191 0x00000000,
192 (0x0e00 << 16) | (0xc268 >> 2),
193 0x00000000,
194 (0x0e00 << 16) | (0xc26c >> 2),
195 0x00000000,
196 (0x0e00 << 16) | (0xc270 >> 2),
197 0x00000000,
198 (0x0e00 << 16) | (0xc274 >> 2),
199 0x00000000,
200 (0x0e00 << 16) | (0xc278 >> 2),
201 0x00000000,
202 (0x0e00 << 16) | (0xc27c >> 2),
203 0x00000000,
204 (0x0e00 << 16) | (0xc280 >> 2),
205 0x00000000,
206 (0x0e00 << 16) | (0xc284 >> 2),
207 0x00000000,
208 (0x0e00 << 16) | (0xc288 >> 2),
209 0x00000000,
210 (0x0e00 << 16) | (0xc28c >> 2),
211 0x00000000,
212 (0x0e00 << 16) | (0xc290 >> 2),
213 0x00000000,
214 (0x0e00 << 16) | (0xc294 >> 2),
215 0x00000000,
216 (0x0e00 << 16) | (0xc298 >> 2),
217 0x00000000,
218 (0x0e00 << 16) | (0xc29c >> 2),
219 0x00000000,
220 (0x0e00 << 16) | (0xc2a0 >> 2),
221 0x00000000,
222 (0x0e00 << 16) | (0xc2a4 >> 2),
223 0x00000000,
224 (0x0e00 << 16) | (0xc2a8 >> 2),
225 0x00000000,
226 (0x0e00 << 16) | (0xc2ac >> 2),
227 0x00000000,
228 (0x0e00 << 16) | (0xc2b0 >> 2),
229 0x00000000,
230 (0x0e00 << 16) | (0x301d0 >> 2),
231 0x00000000,
232 (0x0e00 << 16) | (0x30238 >> 2),
233 0x00000000,
234 (0x0e00 << 16) | (0x30250 >> 2),
235 0x00000000,
236 (0x0e00 << 16) | (0x30254 >> 2),
237 0x00000000,
238 (0x0e00 << 16) | (0x30258 >> 2),
239 0x00000000,
240 (0x0e00 << 16) | (0x3025c >> 2),
241 0x00000000,
242 (0x4e00 << 16) | (0xc900 >> 2),
243 0x00000000,
244 (0x5e00 << 16) | (0xc900 >> 2),
245 0x00000000,
246 (0x6e00 << 16) | (0xc900 >> 2),
247 0x00000000,
248 (0x7e00 << 16) | (0xc900 >> 2),
249 0x00000000,
250 (0x8e00 << 16) | (0xc900 >> 2),
251 0x00000000,
252 (0x9e00 << 16) | (0xc900 >> 2),
253 0x00000000,
254 (0xae00 << 16) | (0xc900 >> 2),
255 0x00000000,
256 (0xbe00 << 16) | (0xc900 >> 2),
257 0x00000000,
258 (0x4e00 << 16) | (0xc904 >> 2),
259 0x00000000,
260 (0x5e00 << 16) | (0xc904 >> 2),
261 0x00000000,
262 (0x6e00 << 16) | (0xc904 >> 2),
263 0x00000000,
264 (0x7e00 << 16) | (0xc904 >> 2),
265 0x00000000,
266 (0x8e00 << 16) | (0xc904 >> 2),
267 0x00000000,
268 (0x9e00 << 16) | (0xc904 >> 2),
269 0x00000000,
270 (0xae00 << 16) | (0xc904 >> 2),
271 0x00000000,
272 (0xbe00 << 16) | (0xc904 >> 2),
273 0x00000000,
274 (0x4e00 << 16) | (0xc908 >> 2),
275 0x00000000,
276 (0x5e00 << 16) | (0xc908 >> 2),
277 0x00000000,
278 (0x6e00 << 16) | (0xc908 >> 2),
279 0x00000000,
280 (0x7e00 << 16) | (0xc908 >> 2),
281 0x00000000,
282 (0x8e00 << 16) | (0xc908 >> 2),
283 0x00000000,
284 (0x9e00 << 16) | (0xc908 >> 2),
285 0x00000000,
286 (0xae00 << 16) | (0xc908 >> 2),
287 0x00000000,
288 (0xbe00 << 16) | (0xc908 >> 2),
289 0x00000000,
290 (0x4e00 << 16) | (0xc90c >> 2),
291 0x00000000,
292 (0x5e00 << 16) | (0xc90c >> 2),
293 0x00000000,
294 (0x6e00 << 16) | (0xc90c >> 2),
295 0x00000000,
296 (0x7e00 << 16) | (0xc90c >> 2),
297 0x00000000,
298 (0x8e00 << 16) | (0xc90c >> 2),
299 0x00000000,
300 (0x9e00 << 16) | (0xc90c >> 2),
301 0x00000000,
302 (0xae00 << 16) | (0xc90c >> 2),
303 0x00000000,
304 (0xbe00 << 16) | (0xc90c >> 2),
305 0x00000000,
306 (0x4e00 << 16) | (0xc910 >> 2),
307 0x00000000,
308 (0x5e00 << 16) | (0xc910 >> 2),
309 0x00000000,
310 (0x6e00 << 16) | (0xc910 >> 2),
311 0x00000000,
312 (0x7e00 << 16) | (0xc910 >> 2),
313 0x00000000,
314 (0x8e00 << 16) | (0xc910 >> 2),
315 0x00000000,
316 (0x9e00 << 16) | (0xc910 >> 2),
317 0x00000000,
318 (0xae00 << 16) | (0xc910 >> 2),
319 0x00000000,
320 (0xbe00 << 16) | (0xc910 >> 2),
321 0x00000000,
322 (0x0e00 << 16) | (0xc99c >> 2),
323 0x00000000,
324 (0x0e00 << 16) | (0x9834 >> 2),
325 0x00000000,
326 (0x0000 << 16) | (0x30f00 >> 2),
327 0x00000000,
328 (0x0001 << 16) | (0x30f00 >> 2),
329 0x00000000,
330 (0x0000 << 16) | (0x30f04 >> 2),
331 0x00000000,
332 (0x0001 << 16) | (0x30f04 >> 2),
333 0x00000000,
334 (0x0000 << 16) | (0x30f08 >> 2),
335 0x00000000,
336 (0x0001 << 16) | (0x30f08 >> 2),
337 0x00000000,
338 (0x0000 << 16) | (0x30f0c >> 2),
339 0x00000000,
340 (0x0001 << 16) | (0x30f0c >> 2),
341 0x00000000,
342 (0x0600 << 16) | (0x9b7c >> 2),
343 0x00000000,
344 (0x0e00 << 16) | (0x8a14 >> 2),
345 0x00000000,
346 (0x0e00 << 16) | (0x8a18 >> 2),
347 0x00000000,
348 (0x0600 << 16) | (0x30a00 >> 2),
349 0x00000000,
350 (0x0e00 << 16) | (0x8bf0 >> 2),
351 0x00000000,
352 (0x0e00 << 16) | (0x8bcc >> 2),
353 0x00000000,
354 (0x0e00 << 16) | (0x8b24 >> 2),
355 0x00000000,
356 (0x0e00 << 16) | (0x30a04 >> 2),
357 0x00000000,
358 (0x0600 << 16) | (0x30a10 >> 2),
359 0x00000000,
360 (0x0600 << 16) | (0x30a14 >> 2),
361 0x00000000,
362 (0x0600 << 16) | (0x30a18 >> 2),
363 0x00000000,
364 (0x0600 << 16) | (0x30a2c >> 2),
365 0x00000000,
366 (0x0e00 << 16) | (0xc700 >> 2),
367 0x00000000,
368 (0x0e00 << 16) | (0xc704 >> 2),
369 0x00000000,
370 (0x0e00 << 16) | (0xc708 >> 2),
371 0x00000000,
372 (0x0e00 << 16) | (0xc768 >> 2),
373 0x00000000,
374 (0x0400 << 16) | (0xc770 >> 2),
375 0x00000000,
376 (0x0400 << 16) | (0xc774 >> 2),
377 0x00000000,
378 (0x0400 << 16) | (0xc778 >> 2),
379 0x00000000,
380 (0x0400 << 16) | (0xc77c >> 2),
381 0x00000000,
382 (0x0400 << 16) | (0xc780 >> 2),
383 0x00000000,
384 (0x0400 << 16) | (0xc784 >> 2),
385 0x00000000,
386 (0x0400 << 16) | (0xc788 >> 2),
387 0x00000000,
388 (0x0400 << 16) | (0xc78c >> 2),
389 0x00000000,
390 (0x0400 << 16) | (0xc798 >> 2),
391 0x00000000,
392 (0x0400 << 16) | (0xc79c >> 2),
393 0x00000000,
394 (0x0400 << 16) | (0xc7a0 >> 2),
395 0x00000000,
396 (0x0400 << 16) | (0xc7a4 >> 2),
397 0x00000000,
398 (0x0400 << 16) | (0xc7a8 >> 2),
399 0x00000000,
400 (0x0400 << 16) | (0xc7ac >> 2),
401 0x00000000,
402 (0x0400 << 16) | (0xc7b0 >> 2),
403 0x00000000,
404 (0x0400 << 16) | (0xc7b4 >> 2),
405 0x00000000,
406 (0x0e00 << 16) | (0x9100 >> 2),
407 0x00000000,
408 (0x0e00 << 16) | (0x3c010 >> 2),
409 0x00000000,
410 (0x0e00 << 16) | (0x92a8 >> 2),
411 0x00000000,
412 (0x0e00 << 16) | (0x92ac >> 2),
413 0x00000000,
414 (0x0e00 << 16) | (0x92b4 >> 2),
415 0x00000000,
416 (0x0e00 << 16) | (0x92b8 >> 2),
417 0x00000000,
418 (0x0e00 << 16) | (0x92bc >> 2),
419 0x00000000,
420 (0x0e00 << 16) | (0x92c0 >> 2),
421 0x00000000,
422 (0x0e00 << 16) | (0x92c4 >> 2),
423 0x00000000,
424 (0x0e00 << 16) | (0x92c8 >> 2),
425 0x00000000,
426 (0x0e00 << 16) | (0x92cc >> 2),
427 0x00000000,
428 (0x0e00 << 16) | (0x92d0 >> 2),
429 0x00000000,
430 (0x0e00 << 16) | (0x8c00 >> 2),
431 0x00000000,
432 (0x0e00 << 16) | (0x8c04 >> 2),
433 0x00000000,
434 (0x0e00 << 16) | (0x8c20 >> 2),
435 0x00000000,
436 (0x0e00 << 16) | (0x8c38 >> 2),
437 0x00000000,
438 (0x0e00 << 16) | (0x8c3c >> 2),
439 0x00000000,
440 (0x0e00 << 16) | (0xae00 >> 2),
441 0x00000000,
442 (0x0e00 << 16) | (0x9604 >> 2),
443 0x00000000,
444 (0x0e00 << 16) | (0xac08 >> 2),
445 0x00000000,
446 (0x0e00 << 16) | (0xac0c >> 2),
447 0x00000000,
448 (0x0e00 << 16) | (0xac10 >> 2),
449 0x00000000,
450 (0x0e00 << 16) | (0xac14 >> 2),
451 0x00000000,
452 (0x0e00 << 16) | (0xac58 >> 2),
453 0x00000000,
454 (0x0e00 << 16) | (0xac68 >> 2),
455 0x00000000,
456 (0x0e00 << 16) | (0xac6c >> 2),
457 0x00000000,
458 (0x0e00 << 16) | (0xac70 >> 2),
459 0x00000000,
460 (0x0e00 << 16) | (0xac74 >> 2),
461 0x00000000,
462 (0x0e00 << 16) | (0xac78 >> 2),
463 0x00000000,
464 (0x0e00 << 16) | (0xac7c >> 2),
465 0x00000000,
466 (0x0e00 << 16) | (0xac80 >> 2),
467 0x00000000,
468 (0x0e00 << 16) | (0xac84 >> 2),
469 0x00000000,
470 (0x0e00 << 16) | (0xac88 >> 2),
471 0x00000000,
472 (0x0e00 << 16) | (0xac8c >> 2),
473 0x00000000,
474 (0x0e00 << 16) | (0x970c >> 2),
475 0x00000000,
476 (0x0e00 << 16) | (0x9714 >> 2),
477 0x00000000,
478 (0x0e00 << 16) | (0x9718 >> 2),
479 0x00000000,
480 (0x0e00 << 16) | (0x971c >> 2),
481 0x00000000,
482 (0x0e00 << 16) | (0x31068 >> 2),
483 0x00000000,
484 (0x4e00 << 16) | (0x31068 >> 2),
485 0x00000000,
486 (0x5e00 << 16) | (0x31068 >> 2),
487 0x00000000,
488 (0x6e00 << 16) | (0x31068 >> 2),
489 0x00000000,
490 (0x7e00 << 16) | (0x31068 >> 2),
491 0x00000000,
492 (0x8e00 << 16) | (0x31068 >> 2),
493 0x00000000,
494 (0x9e00 << 16) | (0x31068 >> 2),
495 0x00000000,
496 (0xae00 << 16) | (0x31068 >> 2),
497 0x00000000,
498 (0xbe00 << 16) | (0x31068 >> 2),
499 0x00000000,
500 (0x0e00 << 16) | (0xcd10 >> 2),
501 0x00000000,
502 (0x0e00 << 16) | (0xcd14 >> 2),
503 0x00000000,
504 (0x0e00 << 16) | (0x88b0 >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x88b4 >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x88b8 >> 2),
509 0x00000000,
510 (0x0e00 << 16) | (0x88bc >> 2),
511 0x00000000,
512 (0x0400 << 16) | (0x89c0 >> 2),
513 0x00000000,
514 (0x0e00 << 16) | (0x88c4 >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x88c8 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x88d0 >> 2),
519 0x00000000,
520 (0x0e00 << 16) | (0x88d4 >> 2),
521 0x00000000,
522 (0x0e00 << 16) | (0x88d8 >> 2),
523 0x00000000,
524 (0x0e00 << 16) | (0x8980 >> 2),
525 0x00000000,
526 (0x0e00 << 16) | (0x30938 >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0x3093c >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0x30940 >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0x89a0 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0x30900 >> 2),
535 0x00000000,
536 (0x0e00 << 16) | (0x30904 >> 2),
537 0x00000000,
538 (0x0e00 << 16) | (0x89b4 >> 2),
539 0x00000000,
540 (0x0e00 << 16) | (0x3c210 >> 2),
541 0x00000000,
542 (0x0e00 << 16) | (0x3c214 >> 2),
543 0x00000000,
544 (0x0e00 << 16) | (0x3c218 >> 2),
545 0x00000000,
546 (0x0e00 << 16) | (0x8904 >> 2),
547 0x00000000,
548 0x5,
549 (0x0e00 << 16) | (0x8c28 >> 2),
550 (0x0e00 << 16) | (0x8c2c >> 2),
551 (0x0e00 << 16) | (0x8c30 >> 2),
552 (0x0e00 << 16) | (0x8c34 >> 2),
553 (0x0e00 << 16) | (0x9600 >> 2),
554};
555
556static const u32 kalindi_rlc_save_restore_register_list[] =
557{
558 (0x0e00 << 16) | (0xc12c >> 2),
559 0x00000000,
560 (0x0e00 << 16) | (0xc140 >> 2),
561 0x00000000,
562 (0x0e00 << 16) | (0xc150 >> 2),
563 0x00000000,
564 (0x0e00 << 16) | (0xc15c >> 2),
565 0x00000000,
566 (0x0e00 << 16) | (0xc168 >> 2),
567 0x00000000,
568 (0x0e00 << 16) | (0xc170 >> 2),
569 0x00000000,
570 (0x0e00 << 16) | (0xc204 >> 2),
571 0x00000000,
572 (0x0e00 << 16) | (0xc2b4 >> 2),
573 0x00000000,
574 (0x0e00 << 16) | (0xc2b8 >> 2),
575 0x00000000,
576 (0x0e00 << 16) | (0xc2bc >> 2),
577 0x00000000,
578 (0x0e00 << 16) | (0xc2c0 >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0x8228 >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0x829c >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x869c >> 2),
585 0x00000000,
586 (0x0600 << 16) | (0x98f4 >> 2),
587 0x00000000,
588 (0x0e00 << 16) | (0x98f8 >> 2),
589 0x00000000,
590 (0x0e00 << 16) | (0x9900 >> 2),
591 0x00000000,
592 (0x0e00 << 16) | (0xc260 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0x90e8 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0x3c000 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x3c00c >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x8c1c >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0x9700 >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0xcd20 >> 2),
605 0x00000000,
606 (0x4e00 << 16) | (0xcd20 >> 2),
607 0x00000000,
608 (0x5e00 << 16) | (0xcd20 >> 2),
609 0x00000000,
610 (0x6e00 << 16) | (0xcd20 >> 2),
611 0x00000000,
612 (0x7e00 << 16) | (0xcd20 >> 2),
613 0x00000000,
614 (0x0e00 << 16) | (0x89bc >> 2),
615 0x00000000,
616 (0x0e00 << 16) | (0x8900 >> 2),
617 0x00000000,
618 0x3,
619 (0x0e00 << 16) | (0xc130 >> 2),
620 0x00000000,
621 (0x0e00 << 16) | (0xc134 >> 2),
622 0x00000000,
623 (0x0e00 << 16) | (0xc1fc >> 2),
624 0x00000000,
625 (0x0e00 << 16) | (0xc208 >> 2),
626 0x00000000,
627 (0x0e00 << 16) | (0xc264 >> 2),
628 0x00000000,
629 (0x0e00 << 16) | (0xc268 >> 2),
630 0x00000000,
631 (0x0e00 << 16) | (0xc26c >> 2),
632 0x00000000,
633 (0x0e00 << 16) | (0xc270 >> 2),
634 0x00000000,
635 (0x0e00 << 16) | (0xc274 >> 2),
636 0x00000000,
637 (0x0e00 << 16) | (0xc28c >> 2),
638 0x00000000,
639 (0x0e00 << 16) | (0xc290 >> 2),
640 0x00000000,
641 (0x0e00 << 16) | (0xc294 >> 2),
642 0x00000000,
643 (0x0e00 << 16) | (0xc298 >> 2),
644 0x00000000,
645 (0x0e00 << 16) | (0xc2a0 >> 2),
646 0x00000000,
647 (0x0e00 << 16) | (0xc2a4 >> 2),
648 0x00000000,
649 (0x0e00 << 16) | (0xc2a8 >> 2),
650 0x00000000,
651 (0x0e00 << 16) | (0xc2ac >> 2),
652 0x00000000,
653 (0x0e00 << 16) | (0x301d0 >> 2),
654 0x00000000,
655 (0x0e00 << 16) | (0x30238 >> 2),
656 0x00000000,
657 (0x0e00 << 16) | (0x30250 >> 2),
658 0x00000000,
659 (0x0e00 << 16) | (0x30254 >> 2),
660 0x00000000,
661 (0x0e00 << 16) | (0x30258 >> 2),
662 0x00000000,
663 (0x0e00 << 16) | (0x3025c >> 2),
664 0x00000000,
665 (0x4e00 << 16) | (0xc900 >> 2),
666 0x00000000,
667 (0x5e00 << 16) | (0xc900 >> 2),
668 0x00000000,
669 (0x6e00 << 16) | (0xc900 >> 2),
670 0x00000000,
671 (0x7e00 << 16) | (0xc900 >> 2),
672 0x00000000,
673 (0x4e00 << 16) | (0xc904 >> 2),
674 0x00000000,
675 (0x5e00 << 16) | (0xc904 >> 2),
676 0x00000000,
677 (0x6e00 << 16) | (0xc904 >> 2),
678 0x00000000,
679 (0x7e00 << 16) | (0xc904 >> 2),
680 0x00000000,
681 (0x4e00 << 16) | (0xc908 >> 2),
682 0x00000000,
683 (0x5e00 << 16) | (0xc908 >> 2),
684 0x00000000,
685 (0x6e00 << 16) | (0xc908 >> 2),
686 0x00000000,
687 (0x7e00 << 16) | (0xc908 >> 2),
688 0x00000000,
689 (0x4e00 << 16) | (0xc90c >> 2),
690 0x00000000,
691 (0x5e00 << 16) | (0xc90c >> 2),
692 0x00000000,
693 (0x6e00 << 16) | (0xc90c >> 2),
694 0x00000000,
695 (0x7e00 << 16) | (0xc90c >> 2),
696 0x00000000,
697 (0x4e00 << 16) | (0xc910 >> 2),
698 0x00000000,
699 (0x5e00 << 16) | (0xc910 >> 2),
700 0x00000000,
701 (0x6e00 << 16) | (0xc910 >> 2),
702 0x00000000,
703 (0x7e00 << 16) | (0xc910 >> 2),
704 0x00000000,
705 (0x0e00 << 16) | (0xc99c >> 2),
706 0x00000000,
707 (0x0e00 << 16) | (0x9834 >> 2),
708 0x00000000,
709 (0x0000 << 16) | (0x30f00 >> 2),
710 0x00000000,
711 (0x0000 << 16) | (0x30f04 >> 2),
712 0x00000000,
713 (0x0000 << 16) | (0x30f08 >> 2),
714 0x00000000,
715 (0x0000 << 16) | (0x30f0c >> 2),
716 0x00000000,
717 (0x0600 << 16) | (0x9b7c >> 2),
718 0x00000000,
719 (0x0e00 << 16) | (0x8a14 >> 2),
720 0x00000000,
721 (0x0e00 << 16) | (0x8a18 >> 2),
722 0x00000000,
723 (0x0600 << 16) | (0x30a00 >> 2),
724 0x00000000,
725 (0x0e00 << 16) | (0x8bf0 >> 2),
726 0x00000000,
727 (0x0e00 << 16) | (0x8bcc >> 2),
728 0x00000000,
729 (0x0e00 << 16) | (0x8b24 >> 2),
730 0x00000000,
731 (0x0e00 << 16) | (0x30a04 >> 2),
732 0x00000000,
733 (0x0600 << 16) | (0x30a10 >> 2),
734 0x00000000,
735 (0x0600 << 16) | (0x30a14 >> 2),
736 0x00000000,
737 (0x0600 << 16) | (0x30a18 >> 2),
738 0x00000000,
739 (0x0600 << 16) | (0x30a2c >> 2),
740 0x00000000,
741 (0x0e00 << 16) | (0xc700 >> 2),
742 0x00000000,
743 (0x0e00 << 16) | (0xc704 >> 2),
744 0x00000000,
745 (0x0e00 << 16) | (0xc708 >> 2),
746 0x00000000,
747 (0x0e00 << 16) | (0xc768 >> 2),
748 0x00000000,
749 (0x0400 << 16) | (0xc770 >> 2),
750 0x00000000,
751 (0x0400 << 16) | (0xc774 >> 2),
752 0x00000000,
753 (0x0400 << 16) | (0xc798 >> 2),
754 0x00000000,
755 (0x0400 << 16) | (0xc79c >> 2),
756 0x00000000,
757 (0x0e00 << 16) | (0x9100 >> 2),
758 0x00000000,
759 (0x0e00 << 16) | (0x3c010 >> 2),
760 0x00000000,
761 (0x0e00 << 16) | (0x8c00 >> 2),
762 0x00000000,
763 (0x0e00 << 16) | (0x8c04 >> 2),
764 0x00000000,
765 (0x0e00 << 16) | (0x8c20 >> 2),
766 0x00000000,
767 (0x0e00 << 16) | (0x8c38 >> 2),
768 0x00000000,
769 (0x0e00 << 16) | (0x8c3c >> 2),
770 0x00000000,
771 (0x0e00 << 16) | (0xae00 >> 2),
772 0x00000000,
773 (0x0e00 << 16) | (0x9604 >> 2),
774 0x00000000,
775 (0x0e00 << 16) | (0xac08 >> 2),
776 0x00000000,
777 (0x0e00 << 16) | (0xac0c >> 2),
778 0x00000000,
779 (0x0e00 << 16) | (0xac10 >> 2),
780 0x00000000,
781 (0x0e00 << 16) | (0xac14 >> 2),
782 0x00000000,
783 (0x0e00 << 16) | (0xac58 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xac68 >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0xac6c >> 2),
788 0x00000000,
789 (0x0e00 << 16) | (0xac70 >> 2),
790 0x00000000,
791 (0x0e00 << 16) | (0xac74 >> 2),
792 0x00000000,
793 (0x0e00 << 16) | (0xac78 >> 2),
794 0x00000000,
795 (0x0e00 << 16) | (0xac7c >> 2),
796 0x00000000,
797 (0x0e00 << 16) | (0xac80 >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0xac84 >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0xac88 >> 2),
802 0x00000000,
803 (0x0e00 << 16) | (0xac8c >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0x970c >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0x9714 >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0x9718 >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0x971c >> 2),
812 0x00000000,
813 (0x0e00 << 16) | (0x31068 >> 2),
814 0x00000000,
815 (0x4e00 << 16) | (0x31068 >> 2),
816 0x00000000,
817 (0x5e00 << 16) | (0x31068 >> 2),
818 0x00000000,
819 (0x6e00 << 16) | (0x31068 >> 2),
820 0x00000000,
821 (0x7e00 << 16) | (0x31068 >> 2),
822 0x00000000,
823 (0x0e00 << 16) | (0xcd10 >> 2),
824 0x00000000,
825 (0x0e00 << 16) | (0xcd14 >> 2),
826 0x00000000,
827 (0x0e00 << 16) | (0x88b0 >> 2),
828 0x00000000,
829 (0x0e00 << 16) | (0x88b4 >> 2),
830 0x00000000,
831 (0x0e00 << 16) | (0x88b8 >> 2),
832 0x00000000,
833 (0x0e00 << 16) | (0x88bc >> 2),
834 0x00000000,
835 (0x0400 << 16) | (0x89c0 >> 2),
836 0x00000000,
837 (0x0e00 << 16) | (0x88c4 >> 2),
838 0x00000000,
839 (0x0e00 << 16) | (0x88c8 >> 2),
840 0x00000000,
841 (0x0e00 << 16) | (0x88d0 >> 2),
842 0x00000000,
843 (0x0e00 << 16) | (0x88d4 >> 2),
844 0x00000000,
845 (0x0e00 << 16) | (0x88d8 >> 2),
846 0x00000000,
847 (0x0e00 << 16) | (0x8980 >> 2),
848 0x00000000,
849 (0x0e00 << 16) | (0x30938 >> 2),
850 0x00000000,
851 (0x0e00 << 16) | (0x3093c >> 2),
852 0x00000000,
853 (0x0e00 << 16) | (0x30940 >> 2),
854 0x00000000,
855 (0x0e00 << 16) | (0x89a0 >> 2),
856 0x00000000,
857 (0x0e00 << 16) | (0x30900 >> 2),
858 0x00000000,
859 (0x0e00 << 16) | (0x30904 >> 2),
860 0x00000000,
861 (0x0e00 << 16) | (0x89b4 >> 2),
862 0x00000000,
863 (0x0e00 << 16) | (0x3e1fc >> 2),
864 0x00000000,
865 (0x0e00 << 16) | (0x3c210 >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0x3c214 >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0x3c218 >> 2),
870 0x00000000,
871 (0x0e00 << 16) | (0x8904 >> 2),
872 0x00000000,
873 0x5,
874 (0x0e00 << 16) | (0x8c28 >> 2),
875 (0x0e00 << 16) | (0x8c2c >> 2),
876 (0x0e00 << 16) | (0x8c30 >> 2),
877 (0x0e00 << 16) | (0x8c34 >> 2),
878 (0x0e00 << 16) | (0x9600 >> 2),
879};
880
881static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
882static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
883static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
884static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
7dae69a2 885static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
a2e73f56
AD		 886
887/*
888 * Core functions
889 */
890/**
891 * gfx_v7_0_init_microcode - load ucode images from disk
892 *
893 * @adev: amdgpu_device pointer
894 *
895 * Use the firmware interface to load the ucode images into
896 * the driver (not loaded into hw).
897 * Returns 0 on success, error on failure.
898 */
899static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
900{
901 const char *chip_name;
902 char fw_name[30];
903 int err;
904
905 DRM_DEBUG("\n");
906
907 switch (adev->asic_type) {
908 case CHIP_BONAIRE:
909 chip_name = "bonaire";
910 break;
911 case CHIP_HAWAII:
912 chip_name = "hawaii";
913 break;
914 case CHIP_KAVERI:
915 chip_name = "kaveri";
916 break;
917 case CHIP_KABINI:
918 chip_name = "kabini";
919 break;
920 case CHIP_MULLINS:
921 chip_name = "mullins";
922 break;
923 default: BUG();
924 }
925
926 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
927 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
928 if (err)
929 goto out;
930 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
931 if (err)
932 goto out;
933
934 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
935 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
936 if (err)
937 goto out;
938 err = amdgpu_ucode_validate(adev->gfx.me_fw);
939 if (err)
940 goto out;
941
942 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
943 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
944 if (err)
945 goto out;
946 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
947 if (err)
948 goto out;
949
950 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
951 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
952 if (err)
953 goto out;
954 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
955 if (err)
956 goto out;
957
958 if (adev->asic_type == CHIP_KAVERI) {
959 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
960 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
961 if (err)
962 goto out;
963 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
964 if (err)
965 goto out;
966 }
967
968 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
969 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
970 if (err)
971 goto out;
972 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
973
974out:
975 if (err) {
7ca85295 976 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
a2e73f56
AD		 977 release_firmware(adev->gfx.pfp_fw);
978 adev->gfx.pfp_fw = NULL;
979 release_firmware(adev->gfx.me_fw);
980 adev->gfx.me_fw = NULL;
981 release_firmware(adev->gfx.ce_fw);
982 adev->gfx.ce_fw = NULL;
983 release_firmware(adev->gfx.mec_fw);
984 adev->gfx.mec_fw = NULL;
985 release_firmware(adev->gfx.mec2_fw);
986 adev->gfx.mec2_fw = NULL;
987 release_firmware(adev->gfx.rlc_fw);
988 adev->gfx.rlc_fw = NULL;
989 }
990 return err;
991}
992
e517cd77
ML		 993static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
994{
995 release_firmware(adev->gfx.pfp_fw);
996 adev->gfx.pfp_fw = NULL;
997 release_firmware(adev->gfx.me_fw);
998 adev->gfx.me_fw = NULL;
999 release_firmware(adev->gfx.ce_fw);
1000 adev->gfx.ce_fw = NULL;
1001 release_firmware(adev->gfx.mec_fw);
1002 adev->gfx.mec_fw = NULL;
1003 release_firmware(adev->gfx.mec2_fw);
1004 adev->gfx.mec2_fw = NULL;
1005 release_firmware(adev->gfx.rlc_fw);
1006 adev->gfx.rlc_fw = NULL;
1007}
1008
a2e73f56
AD		 1009/**
1010 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1011 *
1012 * @adev: amdgpu_device pointer
1013 *
1014 * Starting with SI, the tiling setup is done globally in a
1015 * set of 32 tiling modes. Rather than selecting each set of
1016 * parameters per surface as on older asics, we just select
1017 * which index in the tiling table we want to use, and the
1018 * surface uses those parameters (CIK).
1019 */
1020static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1021{
840a20d3
TSD		 1022 const u32 num_tile_mode_states =
1023 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1024 const u32 num_secondary_tile_mode_states =
1025 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1026 u32 reg_offset, split_equal_to_row_size;
1027 uint32_t *tile, *macrotile;
1028
1029 tile = adev->gfx.config.tile_mode_array;
1030 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1031
1032 switch (adev->gfx.config.mem_row_size_in_kb) {
1033 case 1:
1034 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1035 break;
1036 case 2:
1037 default:
1038 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1039 break;
1040 case 4:
1041 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1042 break;
1043 }
1044
840a20d3
TSD		 1045 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1046 tile[reg_offset] = 0;
1047 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1048 macrotile[reg_offset] = 0;
1049
a2e73f56
AD		 1050 switch (adev->asic_type) {
1051 case CHIP_BONAIRE:
840a20d3
TSD		 1052 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1053 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1056 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1057 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1063 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1064 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1065 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1066 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1067 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1068 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1071 TILE_SPLIT(split_equal_to_row_size));
1072 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1073 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1074 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1075 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1076 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1077 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1078 TILE_SPLIT(split_equal_to_row_size));
1079 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1080 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1081 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1082 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1085 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1089 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1090 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1091 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1093 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1094 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1095 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1096 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1097 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1098 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1101 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1102 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1103 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1105 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1106 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1109 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1110 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1115 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1116 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1117 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1118 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1121 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1122 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1123 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1125 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1126 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1127 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1128 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1129 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1130 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1134 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1138 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1139 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1140 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1142 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1143 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1144 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1145 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1147 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1148 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1149 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1150 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1151 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1152 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1153 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1154
1155 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1157 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1158 NUM_BANKS(ADDR_SURF_16_BANK));
1159 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1162 NUM_BANKS(ADDR_SURF_16_BANK));
1163 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1164 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1165 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1166 NUM_BANKS(ADDR_SURF_16_BANK));
1167 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1170 NUM_BANKS(ADDR_SURF_16_BANK));
1171 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1174 NUM_BANKS(ADDR_SURF_16_BANK));
1175 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1178 NUM_BANKS(ADDR_SURF_8_BANK));
1179 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1182 NUM_BANKS(ADDR_SURF_4_BANK));
1183 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1184 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1185 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1186 NUM_BANKS(ADDR_SURF_16_BANK));
1187 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1190 NUM_BANKS(ADDR_SURF_16_BANK));
1191 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1194 NUM_BANKS(ADDR_SURF_16_BANK));
1195 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1198 NUM_BANKS(ADDR_SURF_16_BANK));
1199 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1202 NUM_BANKS(ADDR_SURF_16_BANK));
1203 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1206 NUM_BANKS(ADDR_SURF_8_BANK));
1207 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1210 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1211
840a20d3
TSD		 1212 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1213 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1214 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1215 if (reg_offset != 7)
1216 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1217 break;
1218 case CHIP_HAWAII:
840a20d3
TSD		 1219 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1220 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1223 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1224 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1227 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1231 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1235 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1236 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1237 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1238 TILE_SPLIT(split_equal_to_row_size));
1239 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1240 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1241 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1242 TILE_SPLIT(split_equal_to_row_size));
1243 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1244 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1245 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1246 TILE_SPLIT(split_equal_to_row_size));
1247 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1248 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1249 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1250 TILE_SPLIT(split_equal_to_row_size));
1251 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1252 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1253 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1256 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1264 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1269 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1271 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1275 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1276 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1277 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1279 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1283 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1284 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1287 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1294 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1296 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1298 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1300 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1302 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1304 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1306 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1307 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1308 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1310 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1314 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1318 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1320 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1322 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1324 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1325 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1326 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1327 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1328 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1329 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1330 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1331 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1332 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1333 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1334 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1335 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1337
840a20d3
TSD		 1338 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1341 NUM_BANKS(ADDR_SURF_16_BANK));
1342 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1343 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1344 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1345 NUM_BANKS(ADDR_SURF_16_BANK));
1346 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1349 NUM_BANKS(ADDR_SURF_16_BANK));
1350 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1351 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1352 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1353 NUM_BANKS(ADDR_SURF_16_BANK));
1354 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1355 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1356 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1357 NUM_BANKS(ADDR_SURF_8_BANK));
1358 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1361 NUM_BANKS(ADDR_SURF_4_BANK));
1362 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1363 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1364 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1365 NUM_BANKS(ADDR_SURF_4_BANK));
1366 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1369 NUM_BANKS(ADDR_SURF_16_BANK));
1370 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1371 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1372 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1373 NUM_BANKS(ADDR_SURF_16_BANK));
1374 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1375 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1376 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1377 NUM_BANKS(ADDR_SURF_16_BANK));
1378 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1381 NUM_BANKS(ADDR_SURF_8_BANK));
1382 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1383 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1384 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1385 NUM_BANKS(ADDR_SURF_16_BANK));
1386 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1389 NUM_BANKS(ADDR_SURF_8_BANK));
1390 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1391 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1392 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1393 NUM_BANKS(ADDR_SURF_4_BANK));
1394
1395 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1396 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1397 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1398 if (reg_offset != 7)
1399 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1400 break;
1401 case CHIP_KABINI:
1402 case CHIP_KAVERI:
1403 case CHIP_MULLINS:
1404 default:
840a20d3
TSD		 1405 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1406 PIPE_CONFIG(ADDR_SURF_P2) |
1407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1409 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1410 PIPE_CONFIG(ADDR_SURF_P2) |
1411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1414 PIPE_CONFIG(ADDR_SURF_P2) |
1415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1416 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1417 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1418 PIPE_CONFIG(ADDR_SURF_P2) |
1419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1420 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1421 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1422 PIPE_CONFIG(ADDR_SURF_P2) |
1423 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1424 TILE_SPLIT(split_equal_to_row_size));
1425 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1426 PIPE_CONFIG(ADDR_SURF_P2) |
1427 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1428 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1429 PIPE_CONFIG(ADDR_SURF_P2) |
1430 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1431 TILE_SPLIT(split_equal_to_row_size));
1432 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1433 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1434 PIPE_CONFIG(ADDR_SURF_P2));
1435 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1436 PIPE_CONFIG(ADDR_SURF_P2) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1438 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1439 PIPE_CONFIG(ADDR_SURF_P2) |
1440 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1441 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1442 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1443 PIPE_CONFIG(ADDR_SURF_P2) |
1444 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1446 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1447 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1448 PIPE_CONFIG(ADDR_SURF_P2) |
1449 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1450 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1451 PIPE_CONFIG(ADDR_SURF_P2) |
1452 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1453 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1454 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1455 PIPE_CONFIG(ADDR_SURF_P2) |
1456 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1457 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1458 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1459 PIPE_CONFIG(ADDR_SURF_P2) |
1460 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1461 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1462 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1463 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1464 PIPE_CONFIG(ADDR_SURF_P2) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1468 PIPE_CONFIG(ADDR_SURF_P2) |
1469 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1470 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1471 PIPE_CONFIG(ADDR_SURF_P2) |
1472 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1473 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1474 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1475 PIPE_CONFIG(ADDR_SURF_P2) |
1476 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1477 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1478 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1479 PIPE_CONFIG(ADDR_SURF_P2) |
1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1481 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1482 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1483 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1484 PIPE_CONFIG(ADDR_SURF_P2) |
1485 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1487 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1488 PIPE_CONFIG(ADDR_SURF_P2) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1491 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1492 PIPE_CONFIG(ADDR_SURF_P2) |
1493 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1494 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1495 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1496 PIPE_CONFIG(ADDR_SURF_P2) |
1497 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1498 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1499 PIPE_CONFIG(ADDR_SURF_P2) |
1500 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1501 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1502 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1503 PIPE_CONFIG(ADDR_SURF_P2) |
1504 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1505 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1506 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1507
1508 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1511 NUM_BANKS(ADDR_SURF_8_BANK));
1512 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1513 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1514 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1515 NUM_BANKS(ADDR_SURF_8_BANK));
1516 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1517 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1518 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1519 NUM_BANKS(ADDR_SURF_8_BANK));
1520 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1523 NUM_BANKS(ADDR_SURF_8_BANK));
1524 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1525 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1526 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1527 NUM_BANKS(ADDR_SURF_8_BANK));
1528 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1529 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1530 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1531 NUM_BANKS(ADDR_SURF_8_BANK));
1532 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535 NUM_BANKS(ADDR_SURF_8_BANK));
1536 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1539 NUM_BANKS(ADDR_SURF_16_BANK));
1540 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1543 NUM_BANKS(ADDR_SURF_16_BANK));
1544 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1547 NUM_BANKS(ADDR_SURF_16_BANK));
1548 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1551 NUM_BANKS(ADDR_SURF_16_BANK));
1552 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1555 NUM_BANKS(ADDR_SURF_16_BANK));
1556 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1559 NUM_BANKS(ADDR_SURF_16_BANK));
1560 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1563 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1564
840a20d3
TSD		 1565 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1566 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1567 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1568 if (reg_offset != 7)
1569 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1570 break;
1571 }
1572}
1573
1574/**
1575 * gfx_v7_0_select_se_sh - select which SE, SH to address
1576 *
1577 * @adev: amdgpu_device pointer
1578 * @se_num: shader engine to address
1579 * @sh_num: sh block to address
1580 *
1581 * Select which SE, SH combinations to address. Certain
1582 * registers are instanced per SE or SH. 0xffffffff means
1583 * broadcast to all SEs or SHs (CIK).
1584 */
05fb7291 1585static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
9559ef5b 1586 u32 se_num, u32 sh_num, u32 instance)
a2e73f56 1587{
9559ef5b
TSD		 1588 u32 data;
1589
1590 if (instance == 0xffffffff)
1591 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1592 else
1593 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
a2e73f56
AD		 1594
1595 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1596 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1597 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1598 else if (se_num == 0xffffffff)
1599 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1600 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1601 else if (sh_num == 0xffffffff)
1602 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1603 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1604 else
1605 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1606 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1607 WREG32(mmGRBM_GFX_INDEX, data);
1608}
1609
a2e73f56 1610/**
8f8e00c1 1611 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1612 *
1613 * @adev: amdgpu_device pointer
a2e73f56 1614 *
8f8e00c1
AD		 1615 * Calculates the bitmask of enabled RBs (CIK).
1616 * Returns the enabled RB bitmask.
a2e73f56 1617 */
8f8e00c1 1618static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1619{
1620 u32 data, mask;
1621
1622 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1623 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1624
8f8e00c1 1625 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1626 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1627
378506a7
AD		 1628 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1629 adev->gfx.config.max_sh_per_se);
a2e73f56 1630
8f8e00c1 1631 return (~data) & mask;
a2e73f56
AD		 1632}
1633
0b2138a4
HR		 1634static void
1635gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1636{
1637 switch (adev->asic_type) {
1638 case CHIP_BONAIRE:
1639 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1640 SE_XSEL(1) | SE_YSEL(1);
1641 *rconf1 |= 0x0;
1642 break;
1643 case CHIP_HAWAII:
1644 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1645 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1646 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1647 SE_YSEL(3);
1648 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1649 SE_PAIR_YSEL(2);
1650 break;
1651 case CHIP_KAVERI:
1652 *rconf |= RB_MAP_PKR0(2);
1653 *rconf1 |= 0x0;
1654 break;
1655 case CHIP_KABINI:
1656 case CHIP_MULLINS:
1657 *rconf |= 0x0;
1658 *rconf1 |= 0x0;
1659 break;
1660 default:
1661 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1662 break;
1663 }
1664}
1665
1666static void
1667gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1668 u32 raster_config, u32 raster_config_1,
1669 unsigned rb_mask, unsigned num_rb)
1670{
1671 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1672 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1673 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1674 unsigned rb_per_se = num_rb / num_se;
1675 unsigned se_mask[4];
1676 unsigned se;
1677
1678 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1679 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1680 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1681 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1682
1683 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1684 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1685 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1686
1687 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1688 (!se_mask[2] && !se_mask[3]))) {
1689 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1690
1691 if (!se_mask[0] && !se_mask[1]) {
1692 raster_config_1 |=
1693 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1694 } else {
1695 raster_config_1 |=
1696 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1697 }
1698 }
1699
1700 for (se = 0; se < num_se; se++) {
1701 unsigned raster_config_se = raster_config;
1702 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1703 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1704 int idx = (se / 2) * 2;
1705
1706 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1707 raster_config_se &= ~SE_MAP_MASK;
1708
1709 if (!se_mask[idx]) {
1710 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1711 } else {
1712 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1713 }
1714 }
1715
1716 pkr0_mask &= rb_mask;
1717 pkr1_mask &= rb_mask;
1718 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1719 raster_config_se &= ~PKR_MAP_MASK;
1720
1721 if (!pkr0_mask) {
1722 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1723 } else {
1724 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1725 }
1726 }
1727
1728 if (rb_per_se >= 2) {
1729 unsigned rb0_mask = 1 << (se * rb_per_se);
1730 unsigned rb1_mask = rb0_mask << 1;
1731
1732 rb0_mask &= rb_mask;
1733 rb1_mask &= rb_mask;
1734 if (!rb0_mask || !rb1_mask) {
1735 raster_config_se &= ~RB_MAP_PKR0_MASK;
1736
1737 if (!rb0_mask) {
1738 raster_config_se |=
1739 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1740 } else {
1741 raster_config_se |=
1742 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1743 }
1744 }
1745
1746 if (rb_per_se > 2) {
1747 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1748 rb1_mask = rb0_mask << 1;
1749 rb0_mask &= rb_mask;
1750 rb1_mask &= rb_mask;
1751 if (!rb0_mask || !rb1_mask) {
1752 raster_config_se &= ~RB_MAP_PKR1_MASK;
1753
1754 if (!rb0_mask) {
1755 raster_config_se |=
1756 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1757 } else {
1758 raster_config_se |=
1759 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1760 }
1761 }
1762 }
1763 }
1764
1765 /* GRBM_GFX_INDEX has a different offset on CI+ */
1766 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1767 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1768 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1769 }
1770
1771 /* GRBM_GFX_INDEX has a different offset on CI+ */
1772 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1773}
1774
a2e73f56
AD		 1775/**
1776 * gfx_v7_0_setup_rb - setup the RBs on the asic
1777 *
1778 * @adev: amdgpu_device pointer
1779 * @se_num: number of SEs (shader engines) for the asic
1780 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1781 *
1782 * Configures per-SE/SH RB registers (CIK).
1783 */
8f8e00c1 1784static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1785{
1786 int i, j;
aac1e3ca 1787 u32 data;
0b2138a4 1788 u32 raster_config = 0, raster_config_1 = 0;
8f8e00c1 1789 u32 active_rbs = 0;
6157bd7a
FC		 1790 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1791 adev->gfx.config.max_sh_per_se;
0b2138a4 1792 unsigned num_rb_pipes;
a2e73f56
AD		 1793
1794 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1795 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1796 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 1797 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
8f8e00c1 1798 data = gfx_v7_0_get_rb_active_bitmap(adev);
6157bd7a
FC		 1799 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1800 rb_bitmap_width_per_sh);
a2e73f56
AD		 1801 }
1802 }
9559ef5b 1803 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56 1804
8f8e00c1 1805 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 1806 adev->gfx.config.num_rbs = hweight32(active_rbs);
0b2138a4
HR		 1807
1808 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1809 adev->gfx.config.max_shader_engines, 16);
1810
1811 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1812
1813 if (!adev->gfx.config.backend_enable_mask ||
1814 adev->gfx.config.num_rbs >= num_rb_pipes) {
1815 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1816 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1817 } else {
1818 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1819 adev->gfx.config.backend_enable_mask,
1820 num_rb_pipes);
1821 }
1822 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 1823}
1824
cd06bf68
BG		 1825/**
1826 * gmc_v7_0_init_compute_vmid - gart enable
1827 *
dc102c43 1828 * @adev: amdgpu_device pointer
cd06bf68
BG		 1829 *
1830 * Initialize compute vmid sh_mem registers
1831 *
1832 */
1833#define DEFAULT_SH_MEM_BASES (0x6000)
1834#define FIRST_COMPUTE_VMID (8)
1835#define LAST_COMPUTE_VMID (16)
1836static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1837{
1838 int i;
1839 uint32_t sh_mem_config;
1840 uint32_t sh_mem_bases;
1841
1842 /*
1843 * Configure apertures:
1844 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1845 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1846 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1847 */
1848 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1849 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1850 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1851 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1852 mutex_lock(&adev->srbm_mutex);
1853 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1854 cik_srbm_select(adev, 0, 0, 0, i);
1855 /* CP and shaders */
1856 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1857 WREG32(mmSH_MEM_APE1_BASE, 1);
1858 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1859 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1860 }
1861 cik_srbm_select(adev, 0, 0, 0, 0);
1862 mutex_unlock(&adev->srbm_mutex);
1863}
1864
df6e2c4a
JZ		 1865static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1866{
1867 adev->gfx.config.double_offchip_lds_buf = 1;
1868}
1869
a2e73f56
AD		 1870/**
1871 * gfx_v7_0_gpu_init - setup the 3D engine
1872 *
1873 * @adev: amdgpu_device pointer
1874 *
1875 * Configures the 3D engine and tiling configuration
1876 * registers so that the 3D engine is usable.
1877 */
1878static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1879{
8fe73328
JZ		 1880 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1881 u32 tmp;
a2e73f56
AD		 1882 int i;
1883
a2e73f56
AD		 1884 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1885
d93f3ca7
AD		 1886 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1887 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1888 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1889
1890 gfx_v7_0_tiling_mode_table_init(adev);
1891
8f8e00c1 1892 gfx_v7_0_setup_rb(adev);
7dae69a2 1893 gfx_v7_0_get_cu_info(adev);
df6e2c4a 1894 gfx_v7_0_config_init(adev);
a2e73f56
AD		 1895
1896 /* set HW defaults for 3D engine */
1897 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1898 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1899 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1900
1901 mutex_lock(&adev->grbm_idx_mutex);
1902 /*
1903 * making sure that the following register writes will be broadcasted
1904 * to all the shaders
1905 */
9559ef5b 1906 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 1907
1908 /* XXX SH_MEM regs */
1909 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1910 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165 1911 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
8fe73328
JZ		 1912 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1913 MTYPE_NC);
1914 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1915 MTYPE_UC);
1916 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1917
1918 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1919 SWIZZLE_ENABLE, 1);
1920 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1921 ELEMENT_SIZE, 1);
1922 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1923 INDEX_STRIDE, 3);
74a5d165 1924
a2e73f56 1925 mutex_lock(&adev->srbm_mutex);
7645670d 1926 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
8fe73328
JZ		 1927 if (i == 0)
1928 sh_mem_base = 0;
1929 else
1930 sh_mem_base = adev->mc.shared_aperture_start >> 48;
a2e73f56
AD		 1931 cik_srbm_select(adev, 0, 0, 0, i);
1932 /* CP and shaders */
74a5d165 1933 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1934 WREG32(mmSH_MEM_APE1_BASE, 1);
1935 WREG32(mmSH_MEM_APE1_LIMIT, 0);
8fe73328
JZ		 1936 WREG32(mmSH_MEM_BASES, sh_mem_base);
1937 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
a2e73f56
AD		 1938 }
1939 cik_srbm_select(adev, 0, 0, 0, 0);
1940 mutex_unlock(&adev->srbm_mutex);
1941
cd06bf68
BG		 1942 gmc_v7_0_init_compute_vmid(adev);
1943
a2e73f56
AD		 1944 WREG32(mmSX_DEBUG_1, 0x20);
1945
1946 WREG32(mmTA_CNTL_AUX, 0x00010000);
1947
1948 tmp = RREG32(mmSPI_CONFIG_CNTL);
1949 tmp |= 0x03000000;
1950 WREG32(mmSPI_CONFIG_CNTL, tmp);
1951
1952 WREG32(mmSQ_CONFIG, 1);
1953
1954 WREG32(mmDB_DEBUG, 0);
1955
1956 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1957 tmp |= 0x00000400;
1958 WREG32(mmDB_DEBUG2, tmp);
1959
1960 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1961 tmp |= 0x00020200;
1962 WREG32(mmDB_DEBUG3, tmp);
1963
1964 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1965 tmp |= 0x00018208;
1966 WREG32(mmCB_HW_CONTROL, tmp);
1967
1968 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1969
1970 WREG32(mmPA_SC_FIFO_SIZE,
1971 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1972 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1973 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1974 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1975
1976 WREG32(mmVGT_NUM_INSTANCES, 1);
1977
1978 WREG32(mmCP_PERFMON_CNTL, 0);
1979
1980 WREG32(mmSQ_CONFIG, 0);
1981
1982 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1983 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1984 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1985
1986 WREG32(mmVGT_CACHE_INVALIDATION,
1987 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1988 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1989
1990 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1991 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1992
1993 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1994 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1995 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
d2383267 1996
1997 tmp = RREG32(mmSPI_ARB_PRIORITY);
1998 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
1999 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2000 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2001 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2002 WREG32(mmSPI_ARB_PRIORITY, tmp);
2003
a2e73f56
AD		 2004 mutex_unlock(&adev->grbm_idx_mutex);
2005
2006 udelay(50);
2007}
2008
2009/*
2010 * GPU scratch registers helpers function.
2011 */
2012/**
2013 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2014 *
2015 * @adev: amdgpu_device pointer
2016 *
2017 * Set up the number and offset of the CP scratch registers.
2018 * NOTE: use of CP scratch registers is a legacy inferface and
2019 * is not used by default on newer asics (r6xx+). On newer asics,
2020 * memory buffers are used for fences rather than scratch regs.
2021 */
2022static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2023{
a2e73f56
AD		 2024 adev->gfx.scratch.num_reg = 7;
2025 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
50261151 2026 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
a2e73f56
AD		 2027}
2028
2029/**
2030 * gfx_v7_0_ring_test_ring - basic gfx ring test
2031 *
2032 * @adev: amdgpu_device pointer
2033 * @ring: amdgpu_ring structure holding ring information
2034 *
2035 * Allocate a scratch register and write to it using the gfx ring (CIK).
2036 * Provides a basic gfx ring test to verify that the ring is working.
2037 * Used by gfx_v7_0_cp_gfx_resume();
2038 * Returns 0 on success, error on failure.
2039 */
2040static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2041{
2042 struct amdgpu_device *adev = ring->adev;
2043 uint32_t scratch;
2044 uint32_t tmp = 0;
2045 unsigned i;
2046 int r;
2047
2048 r = amdgpu_gfx_scratch_get(adev, &scratch);
2049 if (r) {
2050 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2051 return r;
2052 }
2053 WREG32(scratch, 0xCAFEDEAD);
a27de35c 2054 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 2055 if (r) {
2056 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2057 amdgpu_gfx_scratch_free(adev, scratch);
2058 return r;
2059 }
2060 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2061 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2062 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 2063 amdgpu_ring_commit(ring);
a2e73f56
AD		 2064
2065 for (i = 0; i < adev->usec_timeout; i++) {
2066 tmp = RREG32(scratch);
2067 if (tmp == 0xDEADBEEF)
2068 break;
2069 DRM_UDELAY(1);
2070 }
2071 if (i < adev->usec_timeout) {
2072 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2073 } else {
2074 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2075 ring->idx, scratch, tmp);
2076 r = -EINVAL;
2077 }
2078 amdgpu_gfx_scratch_free(adev, scratch);
2079 return r;
2080}
2081
2082/**
d2edb07b 2083 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 2084 *
2085 * @adev: amdgpu_device pointer
2086 * @ridx: amdgpu ring index
2087 *
2088 * Emits an hdp flush on the cp.
2089 */
d2edb07b 2090static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 2091{
2092 u32 ref_and_mask;
21cd942e 2093 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56 2094
21cd942e 2095 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
a2e73f56
AD		 2096 switch (ring->me) {
2097 case 1:
2098 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2099 break;
2100 case 2:
2101 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2102 break;
2103 default:
2104 return;
2105 }
2106 } else {
2107 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2108 }
2109
2110 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2111 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2112 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 2113 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 2114 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2115 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2116 amdgpu_ring_write(ring, ref_and_mask);
2117 amdgpu_ring_write(ring, ref_and_mask);
2118 amdgpu_ring_write(ring, 0x20); /* poll interval */
2119}
2120
45682886
ML		 2121static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2122{
2123 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2124 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2125 EVENT_INDEX(4));
2126
2127 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2128 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2129 EVENT_INDEX(0));
2130}
2131
2132
0955860b
CZ		 2133/**
2134 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2135 *
2136 * @adev: amdgpu_device pointer
2137 * @ridx: amdgpu ring index
2138 *
2139 * Emits an hdp invalidate on the cp.
2140 */
2141static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2142{
2143 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2144 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2145 WRITE_DATA_DST_SEL(0) |
2146 WR_CONFIRM));
2147 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2148 amdgpu_ring_write(ring, 0);
2149 amdgpu_ring_write(ring, 1);
2150}
2151
a2e73f56
AD		 2152/**
2153 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2154 *
2155 * @adev: amdgpu_device pointer
2156 * @fence: amdgpu fence object
2157 *
2158 * Emits a fence sequnce number on the gfx ring and flushes
2159 * GPU caches.
2160 */
2161static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 2162 u64 seq, unsigned flags)
a2e73f56 2163{
890ee23f
CZ		 2164 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2165 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 2166 /* Workaround for cache flush problems. First send a dummy EOP
2167 * event down the pipe with seq one below.
2168 */
2169 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2170 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2171 EOP_TC_ACTION_EN |
2172 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2173 EVENT_INDEX(5)));
2174 amdgpu_ring_write(ring, addr & 0xfffffffc);
2175 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2176 DATA_SEL(1) | INT_SEL(0));
2177 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2178 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2179
2180 /* Then send the real EOP event down the pipe. */
2181 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2182 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2183 EOP_TC_ACTION_EN |
2184 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2185 EVENT_INDEX(5)));
2186 amdgpu_ring_write(ring, addr & 0xfffffffc);
2187 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 2188 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2189 amdgpu_ring_write(ring, lower_32_bits(seq));
2190 amdgpu_ring_write(ring, upper_32_bits(seq));
2191}
2192
2193/**
2194 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2195 *
2196 * @adev: amdgpu_device pointer
2197 * @fence: amdgpu fence object
2198 *
2199 * Emits a fence sequnce number on the compute ring and flushes
2200 * GPU caches.
2201 */
2202static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2203 u64 addr, u64 seq,
890ee23f 2204 unsigned flags)
a2e73f56 2205{
890ee23f
CZ		 2206 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2207 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2208
a2e73f56
AD		 2209 /* RELEASE_MEM - flush caches, send int */
2210 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2211 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2212 EOP_TC_ACTION_EN |
2213 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2214 EVENT_INDEX(5)));
890ee23f 2215 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2216 amdgpu_ring_write(ring, addr & 0xfffffffc);
2217 amdgpu_ring_write(ring, upper_32_bits(addr));
2218 amdgpu_ring_write(ring, lower_32_bits(seq));
2219 amdgpu_ring_write(ring, upper_32_bits(seq));
2220}
2221
a2e73f56
AD		 2222/*
2223 * IB stuff
2224 */
2225/**
2226 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2227 *
2228 * @ring: amdgpu_ring structure holding ring information
2229 * @ib: amdgpu indirect buffer object
2230 *
2231 * Emits an DE (drawing engine) or CE (constant engine) IB
2232 * on the gfx ring. IBs are usually generated by userspace
2233 * acceleration drivers and submitted to the kernel for
2234 * sheduling on the ring. This function schedules the IB
2235 * on the gfx ring for execution by the GPU.
2236 */
93323131 2237static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 2238 struct amdgpu_ib *ib,
2239 unsigned vm_id, bool ctx_switch)
a2e73f56
AD		 2240{
2241 u32 header, control = 0;
a2e73f56 2242
a2e73f56 2243 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 2244 if (ctx_switch) {
a2e73f56
AD		 2245 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2246 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2247 }
2248
de807f81 2249 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2250 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2251 else
2252 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2253
d88bf583 2254 control |= ib->length_dw | (vm_id << 24);
a2e73f56
AD		 2255
2256 amdgpu_ring_write(ring, header);
2257 amdgpu_ring_write(ring,
2258#ifdef __BIG_ENDIAN
2259 (2 << 0) |
2260#endif
2261 (ib->gpu_addr & 0xFFFFFFFC));
2262 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2263 amdgpu_ring_write(ring, control);
2264}
2265
93323131 2266static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 2267 struct amdgpu_ib *ib,
2268 unsigned vm_id, bool ctx_switch)
93323131 2269{
33b7ed01 2270 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
93323131 2271
33b7ed01 2272 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
93323131 2273 amdgpu_ring_write(ring,
2274#ifdef __BIG_ENDIAN
2275 (2 << 0) |
2276#endif
2277 (ib->gpu_addr & 0xFFFFFFFC));
2278 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2279 amdgpu_ring_write(ring, control);
2280}
2281
753ad49c
ML		 2282static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2283{
2284 uint32_t dw2 = 0;
2285
2286 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2287 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
45682886 2288 gfx_v7_0_ring_emit_vgt_flush(ring);
753ad49c
ML		 2289 /* set load_global_config & load_global_uconfig */
2290 dw2 |= 0x8001;
2291 /* set load_cs_sh_regs */
2292 dw2 |= 0x01000000;
2293 /* set load_per_context_state & load_gfx_sh_regs */
2294 dw2 |= 0x10002;
2295 }
2296
2297 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2298 amdgpu_ring_write(ring, dw2);
2299 amdgpu_ring_write(ring, 0);
2300}
2301
a2e73f56
AD		 2302/**
2303 * gfx_v7_0_ring_test_ib - basic ring IB test
2304 *
2305 * @ring: amdgpu_ring structure holding ring information
2306 *
2307 * Allocate an IB and execute it on the gfx ring (CIK).
2308 * Provides a basic gfx ring test to verify that IBs are working.
2309 * Returns 0 on success, error on failure.
2310 */
bbec97aa 2311static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
a2e73f56
AD		 2312{
2313 struct amdgpu_device *adev = ring->adev;
2314 struct amdgpu_ib ib;
f54d1867 2315 struct dma_fence *f = NULL;
a2e73f56
AD		 2316 uint32_t scratch;
2317 uint32_t tmp = 0;
bbec97aa 2318 long r;
a2e73f56
AD		 2319
2320 r = amdgpu_gfx_scratch_get(adev, &scratch);
2321 if (r) {
bbec97aa 2322 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
a2e73f56
AD		 2323 return r;
2324 }
2325 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2326 memset(&ib, 0, sizeof(ib));
b07c60c0 2327 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56 2328 if (r) {
bbec97aa 2329 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
42d13693 2330 goto err1;
a2e73f56
AD		 2331 }
2332 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2333 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2334 ib.ptr[2] = 0xDEADBEEF;
2335 ib.length_dw = 3;
42d13693 2336
50ddc75e 2337 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
42d13693
CZ		 2338 if (r)
2339 goto err2;
2340
f54d1867 2341 r = dma_fence_wait_timeout(f, false, timeout);
bbec97aa
CK		 2342 if (r == 0) {
2343 DRM_ERROR("amdgpu: IB test timed out\n");
2344 r = -ETIMEDOUT;
2345 goto err2;
2346 } else if (r < 0) {
2347 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
42d13693 2348 goto err2;
a2e73f56 2349 }
6d44565d
CK		 2350 tmp = RREG32(scratch);
2351 if (tmp == 0xDEADBEEF) {
2352 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
bbec97aa 2353 r = 0;
a2e73f56
AD		 2354 } else {
2355 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2356 scratch, tmp);
2357 r = -EINVAL;
2358 }
42d13693
CZ		 2359
2360err2:
cc55c45d 2361 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 2362 dma_fence_put(f);
42d13693
CZ		 2363err1:
2364 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2365 return r;
2366}
2367
2368/*
2369 * CP.
2370 * On CIK, gfx and compute now have independant command processors.
2371 *
2372 * GFX
2373 * Gfx consists of a single ring and can process both gfx jobs and
2374 * compute jobs. The gfx CP consists of three microengines (ME):
2375 * PFP - Pre-Fetch Parser
2376 * ME - Micro Engine
2377 * CE - Constant Engine
2378 * The PFP and ME make up what is considered the Drawing Engine (DE).
2379 * The CE is an asynchronous engine used for updating buffer desciptors
2380 * used by the DE so that they can be loaded into cache in parallel
2381 * while the DE is processing state update packets.
2382 *
2383 * Compute
2384 * The compute CP consists of two microengines (ME):
2385 * MEC1 - Compute MicroEngine 1
2386 * MEC2 - Compute MicroEngine 2
2387 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2388 * The queues are exposed to userspace and are programmed directly
2389 * by the compute runtime.
2390 */
2391/**
2392 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2393 *
2394 * @adev: amdgpu_device pointer
2395 * @enable: enable or disable the MEs
2396 *
2397 * Halts or unhalts the gfx MEs.
2398 */
2399static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2400{
2401 int i;
2402
2403 if (enable) {
2404 WREG32(mmCP_ME_CNTL, 0);
2405 } else {
2406 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2407 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2408 adev->gfx.gfx_ring[i].ready = false;
2409 }
2410 udelay(50);
2411}
2412
2413/**
2414 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2415 *
2416 * @adev: amdgpu_device pointer
2417 *
2418 * Loads the gfx PFP, ME, and CE ucode.
2419 * Returns 0 for success, -EINVAL if the ucode is not available.
2420 */
2421static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2422{
2423 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2424 const struct gfx_firmware_header_v1_0 *ce_hdr;
2425 const struct gfx_firmware_header_v1_0 *me_hdr;
2426 const __le32 *fw_data;
2427 unsigned i, fw_size;
2428
2429 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2430 return -EINVAL;
2431
2432 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2433 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2434 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2435
2436 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2437 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2438 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2439 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2440 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2441 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2442 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2443 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2444 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2445
2446 gfx_v7_0_cp_gfx_enable(adev, false);
2447
2448 /* PFP */
2449 fw_data = (const __le32 *)
2450 (adev->gfx.pfp_fw->data +
2451 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2452 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2453 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2454 for (i = 0; i < fw_size; i++)
2455 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2456 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2457
2458 /* CE */
2459 fw_data = (const __le32 *)
2460 (adev->gfx.ce_fw->data +
2461 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2462 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2463 WREG32(mmCP_CE_UCODE_ADDR, 0);
2464 for (i = 0; i < fw_size; i++)
2465 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2466 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2467
2468 /* ME */
2469 fw_data = (const __le32 *)
2470 (adev->gfx.me_fw->data +
2471 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2472 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2473 WREG32(mmCP_ME_RAM_WADDR, 0);
2474 for (i = 0; i < fw_size; i++)
2475 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2476 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2477
2478 return 0;
2479}
2480
2481/**
2482 * gfx_v7_0_cp_gfx_start - start the gfx ring
2483 *
2484 * @adev: amdgpu_device pointer
2485 *
2486 * Enables the ring and loads the clear state context and other
2487 * packets required to init the ring.
2488 * Returns 0 for success, error for failure.
2489 */
2490static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2491{
2492 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2493 const struct cs_section_def *sect = NULL;
2494 const struct cs_extent_def *ext = NULL;
2495 int r, i;
2496
2497 /* init the CP */
2498 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2499 WREG32(mmCP_ENDIAN_SWAP, 0);
2500 WREG32(mmCP_DEVICE_ID, 1);
2501
2502 gfx_v7_0_cp_gfx_enable(adev, true);
2503
a27de35c 2504 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2505 if (r) {
2506 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2507 return r;
2508 }
2509
2510 /* init the CE partitions. CE only used for gfx on CIK */
2511 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2512 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2513 amdgpu_ring_write(ring, 0x8000);
2514 amdgpu_ring_write(ring, 0x8000);
2515
2516 /* clear state buffer */
2517 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2518 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2519
2520 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2521 amdgpu_ring_write(ring, 0x80000000);
2522 amdgpu_ring_write(ring, 0x80000000);
2523
2524 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2525 for (ext = sect->section; ext->extent != NULL; ++ext) {
2526 if (sect->id == SECT_CONTEXT) {
2527 amdgpu_ring_write(ring,
2528 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2529 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2530 for (i = 0; i < ext->reg_count; i++)
2531 amdgpu_ring_write(ring, ext->extent[i]);
2532 }
2533 }
2534 }
2535
2536 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2537 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2538 switch (adev->asic_type) {
2539 case CHIP_BONAIRE:
2540 amdgpu_ring_write(ring, 0x16000012);
2541 amdgpu_ring_write(ring, 0x00000000);
2542 break;
2543 case CHIP_KAVERI:
2544 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2545 amdgpu_ring_write(ring, 0x00000000);
2546 break;
2547 case CHIP_KABINI:
2548 case CHIP_MULLINS:
2549 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2550 amdgpu_ring_write(ring, 0x00000000);
2551 break;
2552 case CHIP_HAWAII:
2553 amdgpu_ring_write(ring, 0x3a00161a);
2554 amdgpu_ring_write(ring, 0x0000002e);
2555 break;
2556 default:
2557 amdgpu_ring_write(ring, 0x00000000);
2558 amdgpu_ring_write(ring, 0x00000000);
2559 break;
2560 }
2561
2562 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2563 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2564
2565 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2566 amdgpu_ring_write(ring, 0);
2567
2568 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2569 amdgpu_ring_write(ring, 0x00000316);
2570 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2571 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2572
a27de35c 2573 amdgpu_ring_commit(ring);
a2e73f56
AD		 2574
2575 return 0;
2576}
2577
2578/**
2579 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2580 *
2581 * @adev: amdgpu_device pointer
2582 *
2583 * Program the location and size of the gfx ring buffer
2584 * and test it to make sure it's working.
2585 * Returns 0 for success, error for failure.
2586 */
2587static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2588{
2589 struct amdgpu_ring *ring;
2590 u32 tmp;
2591 u32 rb_bufsz;
2592 u64 rb_addr, rptr_addr;
2593 int r;
2594
2595 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2596 if (adev->asic_type != CHIP_HAWAII)
2597 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2598
2599 /* Set the write pointer delay */
2600 WREG32(mmCP_RB_WPTR_DELAY, 0);
2601
2602 /* set the RB to use vmid 0 */
2603 WREG32(mmCP_RB_VMID, 0);
2604
2605 WREG32(mmSCRATCH_ADDR, 0);
2606
2607 /* ring 0 - compute and gfx */
2608 /* Set ring buffer size */
2609 ring = &adev->gfx.gfx_ring[0];
2610 rb_bufsz = order_base_2(ring->ring_size / 8);
2611 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2612#ifdef __BIG_ENDIAN
454fc95e 2613 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2614#endif
2615 WREG32(mmCP_RB0_CNTL, tmp);
2616
2617 /* Initialize the ring buffer's read and write pointers */
2618 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2619 ring->wptr = 0;
536fbf94 2620 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
a2e73f56
AD		 2621
2622 /* set the wb address wether it's enabled or not */
2623 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2624 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2625 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2626
2627 /* scratch register shadowing is no longer supported */
2628 WREG32(mmSCRATCH_UMSK, 0);
2629
2630 mdelay(1);
2631 WREG32(mmCP_RB0_CNTL, tmp);
2632
2633 rb_addr = ring->gpu_addr >> 8;
2634 WREG32(mmCP_RB0_BASE, rb_addr);
2635 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2636
2637 /* start the ring */
2638 gfx_v7_0_cp_gfx_start(adev);
2639 ring->ready = true;
2640 r = amdgpu_ring_test_ring(ring);
2641 if (r) {
2642 ring->ready = false;
2643 return r;
2644 }
2645
2646 return 0;
2647}
2648
536fbf94 2649static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
a2e73f56 2650{
7edd6b2f 2651 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2652}
2653
536fbf94 2654static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
a2e73f56
AD		 2655{
2656 struct amdgpu_device *adev = ring->adev;
a2e73f56 2657
7edd6b2f 2658 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2659}
2660
2661static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2662{
2663 struct amdgpu_device *adev = ring->adev;
2664
536fbf94 2665 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
a2e73f56
AD		 2666 (void)RREG32(mmCP_RB0_WPTR);
2667}
2668
536fbf94 2669static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
a2e73f56 2670{
a2e73f56 2671 /* XXX check if swapping is necessary on BE */
7edd6b2f 2672 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2673}
2674
2675static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2676{
2677 struct amdgpu_device *adev = ring->adev;
2678
2679 /* XXX check if swapping is necessary on BE */
536fbf94
KW		 2680 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2681 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
a2e73f56
AD		 2682}
2683
2684/**
2685 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2686 *
2687 * @adev: amdgpu_device pointer
2688 * @enable: enable or disable the MEs
2689 *
2690 * Halts or unhalts the compute MEs.
2691 */
2692static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2693{
2694 int i;
2695
2696 if (enable) {
2697 WREG32(mmCP_MEC_CNTL, 0);
2698 } else {
2699 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2700 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2701 adev->gfx.compute_ring[i].ready = false;
2702 }
2703 udelay(50);
2704}
2705
2706/**
2707 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2708 *
2709 * @adev: amdgpu_device pointer
2710 *
2711 * Loads the compute MEC1&2 ucode.
2712 * Returns 0 for success, -EINVAL if the ucode is not available.
2713 */
2714static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2715{
2716 const struct gfx_firmware_header_v1_0 *mec_hdr;
2717 const __le32 *fw_data;
2718 unsigned i, fw_size;
2719
2720 if (!adev->gfx.mec_fw)
2721 return -EINVAL;
2722
2723 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2724 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2725 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2726 adev->gfx.mec_feature_version = le32_to_cpu(
2727 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2728
2729 gfx_v7_0_cp_compute_enable(adev, false);
2730
2731 /* MEC1 */
2732 fw_data = (const __le32 *)
2733 (adev->gfx.mec_fw->data +
2734 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2735 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2736 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2737 for (i = 0; i < fw_size; i++)
2738 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2739 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2740
2741 if (adev->asic_type == CHIP_KAVERI) {
2742 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2743
2744 if (!adev->gfx.mec2_fw)
2745 return -EINVAL;
2746
2747 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2748 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2749 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2750 adev->gfx.mec2_feature_version = le32_to_cpu(
2751 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2752
2753 /* MEC2 */
2754 fw_data = (const __le32 *)
2755 (adev->gfx.mec2_fw->data +
2756 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2757 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2758 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2759 for (i = 0; i < fw_size; i++)
2760 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2761 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2762 }
2763
2764 return 0;
2765}
2766
a2e73f56
AD		 2767/**
2768 * gfx_v7_0_cp_compute_fini - stop the compute queues
2769 *
2770 * @adev: amdgpu_device pointer
2771 *
2772 * Stop the compute queues and tear down the driver queue
2773 * info.
2774 */
2775static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2776{
2777 int i, r;
2778
2779 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2780 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2781
2782 if (ring->mqd_obj) {
c81a1a74 2783 r = amdgpu_bo_reserve(ring->mqd_obj, true);
a2e73f56
AD		 2784 if (unlikely(r != 0))
2785 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2786
2787 amdgpu_bo_unpin(ring->mqd_obj);
2788 amdgpu_bo_unreserve(ring->mqd_obj);
2789
2790 amdgpu_bo_unref(&ring->mqd_obj);
2791 ring->mqd_obj = NULL;
2792 }
2793 }
2794}
2795
2796static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2797{
2798 int r;
2799
2800 if (adev->gfx.mec.hpd_eop_obj) {
c81a1a74 2801 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
a2e73f56
AD		 2802 if (unlikely(r != 0))
2803 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2804 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2805 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2806
2807 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2808 adev->gfx.mec.hpd_eop_obj = NULL;
2809 }
2810}
2811
a2e73f56
AD		 2812static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2813{
2814 int r;
2815 u32 *hpd;
42794b27 2816 size_t mec_hpd_size;
a2e73f56 2817
78c16834
AR		 2818 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2819
42794b27
AR		 2820 switch (adev->asic_type) {
2821 case CHIP_KAVERI:
2822 adev->gfx.mec.num_mec = 2;
2823 break;
2824 case CHIP_BONAIRE:
2825 case CHIP_HAWAII:
2826 case CHIP_KABINI:
2827 case CHIP_MULLINS:
2828 default:
2829 adev->gfx.mec.num_mec = 1;
2830 break;
2831 }
2832 adev->gfx.mec.num_pipe_per_mec = 4;
2833 adev->gfx.mec.num_queue_per_pipe = 8;
a2e73f56 2834
78c16834 2835 /* take ownership of the relevant compute queues */
41f6a99a 2836 amdgpu_gfx_compute_queue_acquire(adev);
78c16834
AR		 2837
2838 /* allocate space for ALL pipes (even the ones we don't own) */
42794b27
AR		 2839 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2840 * GFX7_MEC_HPD_SIZE * 2;
a2e73f56
AD		 2841 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2842 r = amdgpu_bo_create(adev,
42794b27 2843 mec_hpd_size,
a2e73f56 2844 PAGE_SIZE, true,
72d7668b 2845 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2846 &adev->gfx.mec.hpd_eop_obj);
2847 if (r) {
2848 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2849 return r;
2850 }
2851 }
2852
2853 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2854 if (unlikely(r != 0)) {
2855 gfx_v7_0_mec_fini(adev);
2856 return r;
2857 }
2858 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2859 &adev->gfx.mec.hpd_eop_gpu_addr);
2860 if (r) {
2861 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2862 gfx_v7_0_mec_fini(adev);
2863 return r;
2864 }
2865 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2866 if (r) {
2867 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2868 gfx_v7_0_mec_fini(adev);
2869 return r;
2870 }
2871
2872 /* clear memory. Not sure if this is required or not */
42794b27 2873 memset(hpd, 0, mec_hpd_size);
a2e73f56
AD		 2874
2875 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2876 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2877
2878 return 0;
2879}
2880
2881struct hqd_registers
2882{
2883 u32 cp_mqd_base_addr;
2884 u32 cp_mqd_base_addr_hi;
2885 u32 cp_hqd_active;
2886 u32 cp_hqd_vmid;
2887 u32 cp_hqd_persistent_state;
2888 u32 cp_hqd_pipe_priority;
2889 u32 cp_hqd_queue_priority;
2890 u32 cp_hqd_quantum;
2891 u32 cp_hqd_pq_base;
2892 u32 cp_hqd_pq_base_hi;
2893 u32 cp_hqd_pq_rptr;
2894 u32 cp_hqd_pq_rptr_report_addr;
2895 u32 cp_hqd_pq_rptr_report_addr_hi;
2896 u32 cp_hqd_pq_wptr_poll_addr;
2897 u32 cp_hqd_pq_wptr_poll_addr_hi;
2898 u32 cp_hqd_pq_doorbell_control;
2899 u32 cp_hqd_pq_wptr;
2900 u32 cp_hqd_pq_control;
2901 u32 cp_hqd_ib_base_addr;
2902 u32 cp_hqd_ib_base_addr_hi;
2903 u32 cp_hqd_ib_rptr;
2904 u32 cp_hqd_ib_control;
2905 u32 cp_hqd_iq_timer;
2906 u32 cp_hqd_iq_rptr;
2907 u32 cp_hqd_dequeue_request;
2908 u32 cp_hqd_dma_offload;
2909 u32 cp_hqd_sema_cmd;
2910 u32 cp_hqd_msg_type;
2911 u32 cp_hqd_atomic0_preop_lo;
2912 u32 cp_hqd_atomic0_preop_hi;
2913 u32 cp_hqd_atomic1_preop_lo;
2914 u32 cp_hqd_atomic1_preop_hi;
2915 u32 cp_hqd_hq_scheduler0;
2916 u32 cp_hqd_hq_scheduler1;
2917 u32 cp_mqd_control;
2918};
2919
42794b27
AR		 2920static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2921 int mec, int pipe)
a2e73f56 2922{
a2e73f56 2923 u64 eop_gpu_addr;
34130fb1 2924 u32 tmp;
42794b27
AR		 2925 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2926 * GFX7_MEC_HPD_SIZE * 2;
a2e73f56 2927
a2e73f56 2928 mutex_lock(&adev->srbm_mutex);
34130fb1 2929 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
a2e73f56 2930
42794b27 2931 cik_srbm_select(adev, mec + 1, pipe, 0, 0);
a2e73f56 2932
34130fb1
AR		 2933 /* write the EOP addr */
2934 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2935 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
a2e73f56 2936
34130fb1
AR		 2937 /* set the VMID assigned */
2938 WREG32(mmCP_HPD_EOP_VMID, 0);
a2e73f56 2939
34130fb1
AR		 2940 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2941 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2942 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2943 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2944 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
a2e73f56 2945
a2e73f56
AD		 2946 cik_srbm_select(adev, 0, 0, 0, 0);
2947 mutex_unlock(&adev->srbm_mutex);
34130fb1 2948}
a2e73f56 2949
34130fb1
AR		 2950static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2951{
2952 int i;
a2e73f56 2953
34130fb1
AR		 2954 /* disable the queue if it's active */
2955 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2956 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2957 for (i = 0; i < adev->usec_timeout; i++) {
2958 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2959 break;
2960 udelay(1);
a2e73f56
AD		 2961 }
2962
34130fb1
AR		 2963 if (i == adev->usec_timeout)
2964 return -ETIMEDOUT;
a2e73f56 2965
34130fb1
AR		 2966 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2967 WREG32(mmCP_HQD_PQ_RPTR, 0);
2968 WREG32(mmCP_HQD_PQ_WPTR, 0);
2969 }
a2e73f56 2970
34130fb1
AR		 2971 return 0;
2972}
a2e73f56 2973
34130fb1 2974static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
486d807c 2975 struct cik_mqd *mqd,
34130fb1
AR		 2976 uint64_t mqd_gpu_addr,
2977 struct amdgpu_ring *ring)
2978{
2979 u64 hqd_gpu_addr;
2980 u64 wb_gpu_addr;
a2e73f56 2981
34130fb1 2982 /* init the mqd struct */
486d807c 2983 memset(mqd, 0, sizeof(struct cik_mqd));
a2e73f56 2984
34130fb1 2985 mqd->header = 0xC0310800;
486d807c
AR		 2986 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2987 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2988 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2989 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
a2e73f56 2990
34130fb1 2991 /* enable doorbell? */
486d807c 2992 mqd->cp_hqd_pq_doorbell_control =
34130fb1
AR		 2993 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2994 if (ring->use_doorbell)
486d807c 2995 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
34130fb1 2996 else
486d807c 2997 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
34130fb1
AR		 2998
2999 /* set the pointer to the MQD */
486d807c
AR		 3000 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3001 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
34130fb1
AR		 3002
3003 /* set MQD vmid to 0 */
486d807c
AR		 3004 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3005 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
34130fb1
AR		 3006
3007 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3008 hqd_gpu_addr = ring->gpu_addr >> 8;
486d807c
AR		 3009 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3010 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
34130fb1
AR		 3011
3012 /* set up the HQD, this is similar to CP_RB0_CNTL */
486d807c
AR		 3013 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3014 mqd->cp_hqd_pq_control &=
34130fb1
AR		 3015 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3016 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3017
486d807c 3018 mqd->cp_hqd_pq_control |=
34130fb1 3019 order_base_2(ring->ring_size / 8);
486d807c 3020 mqd->cp_hqd_pq_control |=
34130fb1 3021 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
a2e73f56 3022#ifdef __BIG_ENDIAN
486d807c 3023 mqd->cp_hqd_pq_control |=
34130fb1 3024 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56 3025#endif
486d807c 3026 mqd->cp_hqd_pq_control &=
34130fb1 3027 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
a2e73f56
AD		 3028 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3029 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
486d807c 3030 mqd->cp_hqd_pq_control |=
34130fb1
AR		 3031 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3032 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
a2e73f56 3033
34130fb1
AR		 3034 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3035 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
486d807c
AR		 3036 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3037 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
34130fb1
AR		 3038
3039 /* set the wb address wether it's enabled or not */
3040 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
486d807c
AR		 3041 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3042 mqd->cp_hqd_pq_rptr_report_addr_hi =
34130fb1
AR		 3043 upper_32_bits(wb_gpu_addr) & 0xffff;
3044
3045 /* enable the doorbell if requested */
3046 if (ring->use_doorbell) {
486d807c 3047 mqd->cp_hqd_pq_doorbell_control =
34130fb1 3048 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
486d807c 3049 mqd->cp_hqd_pq_doorbell_control &=
34130fb1 3050 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
486d807c 3051 mqd->cp_hqd_pq_doorbell_control |=
34130fb1
AR		 3052 (ring->doorbell_index <<
3053 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
486d807c 3054 mqd->cp_hqd_pq_doorbell_control |=
34130fb1 3055 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
486d807c 3056 mqd->cp_hqd_pq_doorbell_control &=
34130fb1
AR		 3057 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3058 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3059
3060 } else {
486d807c 3061 mqd->cp_hqd_pq_doorbell_control = 0;
34130fb1
AR		 3062 }
3063
3064 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3065 ring->wptr = 0;
486d807c
AR		 3066 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
3067 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
34130fb1
AR		 3068
3069 /* set the vmid for the queue */
486d807c 3070 mqd->cp_hqd_vmid = 0;
34130fb1 3071
97bf47b2
AR		 3072 /* defaults */
3073 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
3074 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
3075 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
3076 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
3077 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
3078 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
3079 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
3080 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
3081 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
3082 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
3083 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
3084 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3085 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
3086 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
3087 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
3088 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
3089
34130fb1 3090 /* activate the queue */
486d807c 3091 mqd->cp_hqd_active = 1;
34130fb1
AR		 3092}
3093
97bf47b2 3094int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
34130fb1 3095{
894700f3
AR		 3096 uint32_t tmp;
3097 uint32_t mqd_reg;
3098 uint32_t *mqd_data;
3099
3100 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3101 mqd_data = &mqd->cp_mqd_base_addr_lo;
34130fb1
AR		 3102
3103 /* disable wptr polling */
3104 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3105 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3106 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3107
894700f3
AR		 3108 /* program all HQD registers */
3109 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3110 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
97bf47b2 3111
34130fb1 3112 /* activate the HQD */
894700f3
AR		 3113 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3114 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
34130fb1
AR		 3115
3116 return 0;
3117}
3118
3119static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3120{
3121 int r;
3122 u64 mqd_gpu_addr;
486d807c 3123 struct cik_mqd *mqd;
34130fb1
AR		 3124 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3125
3126 if (ring->mqd_obj == NULL) {
3127 r = amdgpu_bo_create(adev,
486d807c 3128 sizeof(struct cik_mqd),
34130fb1
AR		 3129 PAGE_SIZE, true,
3130 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
3131 &ring->mqd_obj);
3132 if (r) {
3133 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3134 return r;
a2e73f56 3135 }
34130fb1 3136 }
a2e73f56 3137
34130fb1
AR		 3138 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3139 if (unlikely(r != 0))
3140 goto out;
a2e73f56 3141
34130fb1
AR		 3142 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3143 &mqd_gpu_addr);
3144 if (r) {
3145 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3146 goto out_unreserve;
3147 }
3148 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd);
3149 if (r) {
3150 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3151 goto out_unreserve;
3152 }
a2e73f56 3153
34130fb1
AR		 3154 mutex_lock(&adev->srbm_mutex);
3155 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
a2e73f56 3156
34130fb1
AR		 3157 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3158 gfx_v7_0_mqd_deactivate(adev);
3159 gfx_v7_0_mqd_commit(adev, mqd);
a2e73f56 3160
34130fb1
AR		 3161 cik_srbm_select(adev, 0, 0, 0, 0);
3162 mutex_unlock(&adev->srbm_mutex);
a2e73f56 3163
34130fb1
AR		 3164 amdgpu_bo_kunmap(ring->mqd_obj);
3165out_unreserve:
3166 amdgpu_bo_unreserve(ring->mqd_obj);
3167out:
3168 return 0;
3169}
3170
3171/**
3172 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3173 *
3174 * @adev: amdgpu_device pointer
3175 *
3176 * Program the compute queues and test them to make sure they
3177 * are working.
3178 * Returns 0 for success, error for failure.
3179 */
3180static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3181{
3182 int r, i, j;
3183 u32 tmp;
3184 struct amdgpu_ring *ring;
3185
3186 /* fix up chicken bits */
3187 tmp = RREG32(mmCP_CPF_DEBUG);
3188 tmp |= (1 << 23);
3189 WREG32(mmCP_CPF_DEBUG, tmp);
3190
42794b27 3191 /* init all pipes (even the ones we don't own) */
34130fb1 3192 for (i = 0; i < adev->gfx.mec.num_mec; i++)
42794b27 3193 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
34130fb1
AR		 3194 gfx_v7_0_compute_pipe_init(adev, i, j);
3195
3196 /* init the queues */
3197 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3198 r = gfx_v7_0_compute_queue_init(adev, i);
3199 if (r) {
3200 gfx_v7_0_cp_compute_fini(adev);
3201 return r;
3202 }
53960b4f 3203 }
3204
3205 gfx_v7_0_cp_compute_enable(adev, true);
3206
3207 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3208 ring = &adev->gfx.compute_ring[i];
34130fb1 3209 ring->ready = true;
a2e73f56
AD		 3210 r = amdgpu_ring_test_ring(ring);
3211 if (r)
3212 ring->ready = false;
3213 }
3214
3215 return 0;
3216}
3217
3218static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3219{
3220 gfx_v7_0_cp_gfx_enable(adev, enable);
3221 gfx_v7_0_cp_compute_enable(adev, enable);
3222}
3223
3224static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3225{
3226 int r;
3227
3228 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3229 if (r)
3230 return r;
3231 r = gfx_v7_0_cp_compute_load_microcode(adev);
3232 if (r)
3233 return r;
3234
3235 return 0;
3236}
3237
3238static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3239 bool enable)
3240{
3241 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3242
3243 if (enable)
3244 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3245 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3246 else
3247 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3248 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3249 WREG32(mmCP_INT_CNTL_RING0, tmp);
3250}
3251
3252static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3253{
3254 int r;
3255
3256 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3257
3258 r = gfx_v7_0_cp_load_microcode(adev);
3259 if (r)
3260 return r;
3261
3262 r = gfx_v7_0_cp_gfx_resume(adev);
3263 if (r)
3264 return r;
3265 r = gfx_v7_0_cp_compute_resume(adev);
3266 if (r)
3267 return r;
3268
3269 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3270
3271 return 0;
3272}
3273
b8c7b39e
CK		 3274/**
3275 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3276 *
3277 * @ring: the ring to emmit the commands to
3278 *
3279 * Sync the command pipeline with the PFP. E.g. wait for everything
3280 * to be completed.
3281 */
3282static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3283{
21cd942e 3284 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
914f9e18
CZ		 3285 uint32_t seq = ring->fence_drv.sync_seq;
3286 uint64_t addr = ring->fence_drv.gpu_addr;
3287
3288 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3289 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3290 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3291 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3292 amdgpu_ring_write(ring, addr & 0xfffffffc);
3293 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3294 amdgpu_ring_write(ring, seq);
3295 amdgpu_ring_write(ring, 0xffffffff);
3296 amdgpu_ring_write(ring, 4); /* poll interval */
3297
b8c7b39e
CK		 3298 if (usepfp) {
3299 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3300 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3301 amdgpu_ring_write(ring, 0);
3302 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3303 amdgpu_ring_write(ring, 0);
3304 }
3305}
3306
a2e73f56
AD		 3307/*
3308 * vm
3309 * VMID 0 is the physical GPU addresses as used by the kernel.
3310 * VMIDs 1-15 are used for userspace clients and are handled
3311 * by the amdgpu vm/hsa code.
3312 */
3313/**
3314 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3315 *
3316 * @adev: amdgpu_device pointer
3317 *
3318 * Update the page table base and flush the VM TLB
3319 * using the CP (CIK).
3320 */
3321static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3322 unsigned vm_id, uint64_t pd_addr)
3323{
21cd942e 3324 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
feebe91a 3325
a2e73f56
AD		 3326 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3327 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3328 WRITE_DATA_DST_SEL(0)));
3329 if (vm_id < 8) {
3330 amdgpu_ring_write(ring,
3331 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3332 } else {
3333 amdgpu_ring_write(ring,
3334 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3335 }
3336 amdgpu_ring_write(ring, 0);
3337 amdgpu_ring_write(ring, pd_addr >> 12);
3338
a2e73f56
AD		 3339 /* bits 0-15 are the VM contexts0-15 */
3340 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3341 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3342 WRITE_DATA_DST_SEL(0)));
3343 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3344 amdgpu_ring_write(ring, 0);
3345 amdgpu_ring_write(ring, 1 << vm_id);
3346
3347 /* wait for the invalidate to complete */
3348 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3349 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3350 WAIT_REG_MEM_FUNCTION(0) | /* always */
3351 WAIT_REG_MEM_ENGINE(0))); /* me */
3352 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3353 amdgpu_ring_write(ring, 0);
3354 amdgpu_ring_write(ring, 0); /* ref */
3355 amdgpu_ring_write(ring, 0); /* mask */
3356 amdgpu_ring_write(ring, 0x20); /* poll interval */
3357
3358 /* compute doesn't have PFP */
3359 if (usepfp) {
3360 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3361 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3362 amdgpu_ring_write(ring, 0x0);
3363
3364 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3365 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3366 amdgpu_ring_write(ring, 0);
3367 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3368 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3369 }
3370}
3371
3372/*
3373 * RLC
3374 * The RLC is a multi-purpose microengine that handles a
3375 * variety of functions.
3376 */
3377static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3378{
3379 int r;
3380
3381 /* save restore block */
3382 if (adev->gfx.rlc.save_restore_obj) {
c81a1a74 3383 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, true);
a2e73f56
AD		 3384 if (unlikely(r != 0))
3385 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3386 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3387 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3388
3389 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3390 adev->gfx.rlc.save_restore_obj = NULL;
3391 }
3392
3393 /* clear state block */
3394 if (adev->gfx.rlc.clear_state_obj) {
c81a1a74 3395 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
a2e73f56
AD		 3396 if (unlikely(r != 0))
3397 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3398 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3399 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3400
3401 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3402 adev->gfx.rlc.clear_state_obj = NULL;
3403 }
3404
3405 /* clear state block */
3406 if (adev->gfx.rlc.cp_table_obj) {
c81a1a74 3407 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true);
a2e73f56
AD		 3408 if (unlikely(r != 0))
3409 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3410 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3411 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3412
3413 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3414 adev->gfx.rlc.cp_table_obj = NULL;
3415 }
3416}
3417
3418static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3419{
3420 const u32 *src_ptr;
3421 volatile u32 *dst_ptr;
3422 u32 dws, i;
3423 const struct cs_section_def *cs_data;
3424 int r;
3425
3426 /* allocate rlc buffers */
2f7d10b3 3427 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3428 if (adev->asic_type == CHIP_KAVERI) {
3429 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3430 adev->gfx.rlc.reg_list_size =
3431 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3432 } else {
3433 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3434 adev->gfx.rlc.reg_list_size =
3435 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3436 }
3437 }
3438 adev->gfx.rlc.cs_data = ci_cs_data;
b58bc559 3439 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
e36091ed 3440 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
a2e73f56
AD		 3441
3442 src_ptr = adev->gfx.rlc.reg_list;
3443 dws = adev->gfx.rlc.reg_list_size;
3444 dws += (5 * 16) + 48 + 48 + 64;
3445
3446 cs_data = adev->gfx.rlc.cs_data;
3447
3448 if (src_ptr) {
3449 /* save restore block */
3450 if (adev->gfx.rlc.save_restore_obj == NULL) {
3451 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d 3452 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 3453 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3454 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b
CK		 3455 NULL, NULL,
3456 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3457 if (r) {
3458 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3459 return r;
3460 }
3461 }
3462
3463 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3464 if (unlikely(r != 0)) {
3465 gfx_v7_0_rlc_fini(adev);
3466 return r;
3467 }
3468 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3469 &adev->gfx.rlc.save_restore_gpu_addr);
3470 if (r) {
3471 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3472 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3473 gfx_v7_0_rlc_fini(adev);
3474 return r;
3475 }
3476
3477 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3478 if (r) {
3479 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3480 gfx_v7_0_rlc_fini(adev);
3481 return r;
3482 }
3483 /* write the sr buffer */
3484 dst_ptr = adev->gfx.rlc.sr_ptr;
3485 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3486 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3487 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3488 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3489 }
3490
3491 if (cs_data) {
3492 /* clear state block */
3493 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3494
3495 if (adev->gfx.rlc.clear_state_obj == NULL) {
3496 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d 3497 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 3498 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3499 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b
CK		 3500 NULL, NULL,
3501 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3502 if (r) {
3503 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3504 gfx_v7_0_rlc_fini(adev);
3505 return r;
3506 }
3507 }
3508 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3509 if (unlikely(r != 0)) {
3510 gfx_v7_0_rlc_fini(adev);
3511 return r;
3512 }
3513 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3514 &adev->gfx.rlc.clear_state_gpu_addr);
3515 if (r) {
3516 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3517 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3518 gfx_v7_0_rlc_fini(adev);
3519 return r;
3520 }
3521
3522 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3523 if (r) {
3524 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3525 gfx_v7_0_rlc_fini(adev);
3526 return r;
3527 }
3528 /* set up the cs buffer */
3529 dst_ptr = adev->gfx.rlc.cs_ptr;
3530 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3531 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3532 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3533 }
3534
3535 if (adev->gfx.rlc.cp_table_size) {
3536 if (adev->gfx.rlc.cp_table_obj == NULL) {
3537 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d 3538 AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5
CK		 3539 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3540 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b
CK		 3541 NULL, NULL,
3542 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3543 if (r) {
3544 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3545 gfx_v7_0_rlc_fini(adev);
3546 return r;
3547 }
3548 }
3549
3550 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3551 if (unlikely(r != 0)) {
3552 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3553 gfx_v7_0_rlc_fini(adev);
3554 return r;
3555 }
3556 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3557 &adev->gfx.rlc.cp_table_gpu_addr);
3558 if (r) {
3559 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3560 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3561 gfx_v7_0_rlc_fini(adev);
3562 return r;
3563 }
3564 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3565 if (r) {
3566 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3567 gfx_v7_0_rlc_fini(adev);
3568 return r;
3569 }
3570
3571 gfx_v7_0_init_cp_pg_table(adev);
3572
3573 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3574 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3575
3576 }
3577
3578 return 0;
3579}
3580
3581static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3582{
3583 u32 tmp;
3584
3585 tmp = RREG32(mmRLC_LB_CNTL);
3586 if (enable)
3587 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3588 else
3589 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3590 WREG32(mmRLC_LB_CNTL, tmp);
3591}
3592
3593static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3594{
3595 u32 i, j, k;
3596 u32 mask;
3597
3598 mutex_lock(&adev->grbm_idx_mutex);
3599 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3600 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 3601 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
a2e73f56
AD		 3602 for (k = 0; k < adev->usec_timeout; k++) {
3603 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3604 break;
3605 udelay(1);
3606 }
3607 }
3608 }
9559ef5b 3609 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3610 mutex_unlock(&adev->grbm_idx_mutex);
3611
3612 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3613 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3614 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3615 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3616 for (k = 0; k < adev->usec_timeout; k++) {
3617 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3618 break;
3619 udelay(1);
3620 }
3621}
3622
3623static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3624{
3625 u32 tmp;
3626
3627 tmp = RREG32(mmRLC_CNTL);
3628 if (tmp != rlc)
3629 WREG32(mmRLC_CNTL, rlc);
3630}
3631
3632static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3633{
3634 u32 data, orig;
3635
3636 orig = data = RREG32(mmRLC_CNTL);
3637
3638 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3639 u32 i;
3640
3641 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3642 WREG32(mmRLC_CNTL, data);
3643
3644 for (i = 0; i < adev->usec_timeout; i++) {
3645 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3646 break;
3647 udelay(1);
3648 }
3649
3650 gfx_v7_0_wait_for_rlc_serdes(adev);
3651 }
3652
3653 return orig;
3654}
3655
06120a1e 3656static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3657{
3658 u32 tmp, i, mask;
3659
3660 tmp = 0x1 | (1 << 1);
3661 WREG32(mmRLC_GPR_REG2, tmp);
3662
3663 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3664 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3665 for (i = 0; i < adev->usec_timeout; i++) {
3666 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3667 break;
3668 udelay(1);
3669 }
3670
3671 for (i = 0; i < adev->usec_timeout; i++) {
3672 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3673 break;
3674 udelay(1);
3675 }
3676}
3677
06120a1e 3678static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3679{
3680 u32 tmp;
3681
3682 tmp = 0x1 | (0 << 1);
3683 WREG32(mmRLC_GPR_REG2, tmp);
3684}
3685
3686/**
3687 * gfx_v7_0_rlc_stop - stop the RLC ME
3688 *
3689 * @adev: amdgpu_device pointer
3690 *
3691 * Halt the RLC ME (MicroEngine) (CIK).
3692 */
4d54588e 3693static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
a2e73f56
AD		 3694{
3695 WREG32(mmRLC_CNTL, 0);
3696
3697 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3698
3699 gfx_v7_0_wait_for_rlc_serdes(adev);
3700}
3701
3702/**
3703 * gfx_v7_0_rlc_start - start the RLC ME
3704 *
3705 * @adev: amdgpu_device pointer
3706 *
3707 * Unhalt the RLC ME (MicroEngine) (CIK).
3708 */
3709static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3710{
3711 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3712
3713 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3714
3715 udelay(50);
3716}
3717
3718static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3719{
3720 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3721
3722 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3723 WREG32(mmGRBM_SOFT_RESET, tmp);
3724 udelay(50);
3725 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3726 WREG32(mmGRBM_SOFT_RESET, tmp);
3727 udelay(50);
3728}
3729
3730/**
3731 * gfx_v7_0_rlc_resume - setup the RLC hw
3732 *
3733 * @adev: amdgpu_device pointer
3734 *
3735 * Initialize the RLC registers, load the ucode,
3736 * and start the RLC (CIK).
3737 * Returns 0 for success, -EINVAL if the ucode is not available.
3738 */
3739static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3740{
3741 const struct rlc_firmware_header_v1_0 *hdr;
3742 const __le32 *fw_data;
3743 unsigned i, fw_size;
3744 u32 tmp;
3745
3746 if (!adev->gfx.rlc_fw)
3747 return -EINVAL;
3748
3749 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3750 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3751 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3752 adev->gfx.rlc_feature_version = le32_to_cpu(
3753 hdr->ucode_feature_version);
a2e73f56
AD		 3754
3755 gfx_v7_0_rlc_stop(adev);
3756
3757 /* disable CG */
3758 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3759 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3760
3761 gfx_v7_0_rlc_reset(adev);
3762
3763 gfx_v7_0_init_pg(adev);
3764
3765 WREG32(mmRLC_LB_CNTR_INIT, 0);
3766 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3767
3768 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3769 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3770 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3771 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3772 WREG32(mmRLC_LB_CNTL, 0x80000004);
3773 mutex_unlock(&adev->grbm_idx_mutex);
3774
3775 WREG32(mmRLC_MC_CNTL, 0);
3776 WREG32(mmRLC_UCODE_CNTL, 0);
3777
3778 fw_data = (const __le32 *)
3779 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3780 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3781 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3782 for (i = 0; i < fw_size; i++)
3783 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3784 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3785
3786 /* XXX - find out what chips support lbpw */
3787 gfx_v7_0_enable_lbpw(adev, false);
3788
3789 if (adev->asic_type == CHIP_BONAIRE)
3790 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3791
3792 gfx_v7_0_rlc_start(adev);
3793
3794 return 0;
3795}
3796
3797static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3798{
3799 u32 data, orig, tmp, tmp2;
3800
3801 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3802
e3b04bc7 3803 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
a2e73f56
AD		 3804 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3805
3806 tmp = gfx_v7_0_halt_rlc(adev);
3807
3808 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3809 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3810 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3811 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3812 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3813 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3814 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3815 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3816 mutex_unlock(&adev->grbm_idx_mutex);
3817
3818 gfx_v7_0_update_rlc(adev, tmp);
3819
3820 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
dfa6c82e
AD		 3821 if (orig != data)
3822 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3823
a2e73f56
AD		 3824 } else {
3825 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3826
3827 RREG32(mmCB_CGTT_SCLK_CTRL);
3828 RREG32(mmCB_CGTT_SCLK_CTRL);
3829 RREG32(mmCB_CGTT_SCLK_CTRL);
3830 RREG32(mmCB_CGTT_SCLK_CTRL);
3831
3832 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
dfa6c82e
AD		 3833 if (orig != data)
3834 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
a2e73f56 3835
dfa6c82e
AD		 3836 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3837 }
a2e73f56
AD		 3838}
3839
3840static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3841{
3842 u32 data, orig, tmp = 0;
3843
e3b04bc7
AD		 3844 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3845 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3846 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
a2e73f56
AD		 3847 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3848 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3849 if (orig != data)
3850 WREG32(mmCP_MEM_SLP_CNTL, data);
3851 }
3852 }
3853
3854 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3855 data |= 0x00000001;
3856 data &= 0xfffffffd;
3857 if (orig != data)
3858 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3859
3860 tmp = gfx_v7_0_halt_rlc(adev);
3861
3862 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3863 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3864 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3865 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3866 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3867 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3868 WREG32(mmRLC_SERDES_WR_CTRL, data);
3869 mutex_unlock(&adev->grbm_idx_mutex);
3870
3871 gfx_v7_0_update_rlc(adev, tmp);
3872
e3b04bc7 3873 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
a2e73f56
AD		 3874 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3875 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3876 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3877 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3878 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
e3b04bc7
AD		 3879 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3880 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
a2e73f56
AD		 3881 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3882 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3883 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3884 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3885 if (orig != data)
3886 WREG32(mmCGTS_SM_CTRL_REG, data);
3887 }
3888 } else {
3889 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3890 data |= 0x00000003;
3891 if (orig != data)
3892 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3893
3894 data = RREG32(mmRLC_MEM_SLP_CNTL);
3895 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3896 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3897 WREG32(mmRLC_MEM_SLP_CNTL, data);
3898 }
3899
3900 data = RREG32(mmCP_MEM_SLP_CNTL);
3901 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3902 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3903 WREG32(mmCP_MEM_SLP_CNTL, data);
3904 }
3905
3906 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3907 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3908 if (orig != data)
3909 WREG32(mmCGTS_SM_CTRL_REG, data);
3910
3911 tmp = gfx_v7_0_halt_rlc(adev);
3912
3913 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3914 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3915 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3916 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3917 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3918 WREG32(mmRLC_SERDES_WR_CTRL, data);
3919 mutex_unlock(&adev->grbm_idx_mutex);
3920
3921 gfx_v7_0_update_rlc(adev, tmp);
3922 }
3923}
3924
3925static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3926 bool enable)
3927{
3928 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3929 /* order matters! */
3930 if (enable) {
3931 gfx_v7_0_enable_mgcg(adev, true);
3932 gfx_v7_0_enable_cgcg(adev, true);
3933 } else {
3934 gfx_v7_0_enable_cgcg(adev, false);
3935 gfx_v7_0_enable_mgcg(adev, false);
3936 }
3937 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3938}
3939
3940static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3941 bool enable)
3942{
3943 u32 data, orig;
3944
3945 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3946 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3947 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3948 else
3949 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3950 if (orig != data)
3951 WREG32(mmRLC_PG_CNTL, data);
3952}
3953
3954static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3955 bool enable)
3956{
3957 u32 data, orig;
3958
3959 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3960 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3961 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3962 else
3963 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3964 if (orig != data)
3965 WREG32(mmRLC_PG_CNTL, data);
3966}
3967
3968static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3969{
3970 u32 data, orig;
3971
3972 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3973 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
a2e73f56
AD		 3974 data &= ~0x8000;
3975 else
3976 data |= 0x8000;
3977 if (orig != data)
3978 WREG32(mmRLC_PG_CNTL, data);
3979}
3980
3981static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3982{
3983 u32 data, orig;
3984
3985 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3986 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
a2e73f56
AD		 3987 data &= ~0x2000;
3988 else
3989 data |= 0x2000;
3990 if (orig != data)
3991 WREG32(mmRLC_PG_CNTL, data);
3992}
3993
3994static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3995{
3996 const __le32 *fw_data;
3997 volatile u32 *dst_ptr;
3998 int me, i, max_me = 4;
3999 u32 bo_offset = 0;
4000 u32 table_offset, table_size;
4001
4002 if (adev->asic_type == CHIP_KAVERI)
4003 max_me = 5;
4004
4005 if (adev->gfx.rlc.cp_table_ptr == NULL)
4006 return;
4007
4008 /* write the cp table buffer */
4009 dst_ptr = adev->gfx.rlc.cp_table_ptr;
4010 for (me = 0; me < max_me; me++) {
4011 if (me == 0) {
4012 const struct gfx_firmware_header_v1_0 *hdr =
4013 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4014 fw_data = (const __le32 *)
4015 (adev->gfx.ce_fw->data +
4016 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4017 table_offset = le32_to_cpu(hdr->jt_offset);
4018 table_size = le32_to_cpu(hdr->jt_size);
4019 } else if (me == 1) {
4020 const struct gfx_firmware_header_v1_0 *hdr =
4021 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4022 fw_data = (const __le32 *)
4023 (adev->gfx.pfp_fw->data +
4024 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4025 table_offset = le32_to_cpu(hdr->jt_offset);
4026 table_size = le32_to_cpu(hdr->jt_size);
4027 } else if (me == 2) {
4028 const struct gfx_firmware_header_v1_0 *hdr =
4029 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4030 fw_data = (const __le32 *)
4031 (adev->gfx.me_fw->data +
4032 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4033 table_offset = le32_to_cpu(hdr->jt_offset);
4034 table_size = le32_to_cpu(hdr->jt_size);
4035 } else if (me == 3) {
4036 const struct gfx_firmware_header_v1_0 *hdr =
4037 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4038 fw_data = (const __le32 *)
4039 (adev->gfx.mec_fw->data +
4040 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4041 table_offset = le32_to_cpu(hdr->jt_offset);
4042 table_size = le32_to_cpu(hdr->jt_size);
4043 } else {
4044 const struct gfx_firmware_header_v1_0 *hdr =
4045 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4046 fw_data = (const __le32 *)
4047 (adev->gfx.mec2_fw->data +
4048 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4049 table_offset = le32_to_cpu(hdr->jt_offset);
4050 table_size = le32_to_cpu(hdr->jt_size);
4051 }
4052
4053 for (i = 0; i < table_size; i ++) {
4054 dst_ptr[bo_offset + i] =
4055 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4056 }
4057
4058 bo_offset += table_size;
4059 }
4060}
4061
4062static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4063 bool enable)
4064{
4065 u32 data, orig;
4066
e3b04bc7 4067 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
a2e73f56
AD		 4068 orig = data = RREG32(mmRLC_PG_CNTL);
4069 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4070 if (orig != data)
4071 WREG32(mmRLC_PG_CNTL, data);
4072
4073 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4074 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4075 if (orig != data)
4076 WREG32(mmRLC_AUTO_PG_CTRL, data);
4077 } else {
4078 orig = data = RREG32(mmRLC_PG_CNTL);
4079 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4080 if (orig != data)
4081 WREG32(mmRLC_PG_CNTL, data);
4082
4083 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4084 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4085 if (orig != data)
4086 WREG32(mmRLC_AUTO_PG_CTRL, data);
4087
4088 data = RREG32(mmDB_RENDER_CONTROL);
4089 }
4090}
4091
324c614a
NH		 4092static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4093 u32 bitmap)
4094{
4095 u32 data;
4096
4097 if (!bitmap)
4098 return;
4099
4100 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4101 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4102
4103 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
4104}
4105
8f8e00c1 4106static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 4107{
8f8e00c1 4108 u32 data, mask;
a2e73f56 4109
8f8e00c1
AD		 4110 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4111 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 4112
8f8e00c1
AD		 4113 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4114 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 4115
378506a7 4116 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
a2e73f56 4117
8f8e00c1 4118 return (~data) & mask;
a2e73f56
AD		 4119}
4120
4121static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4122{
7dae69a2 4123 u32 tmp;
a2e73f56 4124
7dae69a2 4125 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
a2e73f56
AD		 4126
4127 tmp = RREG32(mmRLC_MAX_PG_CU);
4128 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
7dae69a2 4129 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
a2e73f56
AD		 4130 WREG32(mmRLC_MAX_PG_CU, tmp);
4131}
4132
4133static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4134 bool enable)
4135{
4136 u32 data, orig;
4137
4138 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 4139 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
a2e73f56
AD		 4140 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4141 else
4142 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4143 if (orig != data)
4144 WREG32(mmRLC_PG_CNTL, data);
4145}
4146
4147static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4148 bool enable)
4149{
4150 u32 data, orig;
4151
4152 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 4153 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
a2e73f56
AD		 4154 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4155 else
4156 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4157 if (orig != data)
4158 WREG32(mmRLC_PG_CNTL, data);
4159}
4160
4161#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4162#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4163
4164static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4165{
4166 u32 data, orig;
4167 u32 i;
4168
4169 if (adev->gfx.rlc.cs_data) {
4170 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4171 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4172 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4173 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4174 } else {
4175 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4176 for (i = 0; i < 3; i++)
4177 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4178 }
4179 if (adev->gfx.rlc.reg_list) {
4180 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4181 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4182 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4183 }
4184
4185 orig = data = RREG32(mmRLC_PG_CNTL);
4186 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4187 if (orig != data)
4188 WREG32(mmRLC_PG_CNTL, data);
4189
4190 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4191 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4192
4193 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4194 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4195 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4196 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4197
4198 data = 0x10101010;
4199 WREG32(mmRLC_PG_DELAY, data);
4200
4201 data = RREG32(mmRLC_PG_DELAY_2);
4202 data &= ~0xff;
4203 data |= 0x3;
4204 WREG32(mmRLC_PG_DELAY_2, data);
4205
4206 data = RREG32(mmRLC_AUTO_PG_CTRL);
4207 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4208 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4209 WREG32(mmRLC_AUTO_PG_CTRL, data);
4210
4211}
4212
4213static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4214{
4215 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4216 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4217 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4218}
4219
4220static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4221{
4222 u32 count = 0;
4223 const struct cs_section_def *sect = NULL;
4224 const struct cs_extent_def *ext = NULL;
4225
4226 if (adev->gfx.rlc.cs_data == NULL)
4227 return 0;
4228
4229 /* begin clear state */
4230 count += 2;
4231 /* context control state */
4232 count += 3;
4233
4234 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4235 for (ext = sect->section; ext->extent != NULL; ++ext) {
4236 if (sect->id == SECT_CONTEXT)
4237 count += 2 + ext->reg_count;
4238 else
4239 return 0;
4240 }
4241 }
4242 /* pa_sc_raster_config/pa_sc_raster_config1 */
4243 count += 4;
4244 /* end clear state */
4245 count += 2;
4246 /* clear state */
4247 count += 2;
4248
4249 return count;
4250}
4251
4252static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4253 volatile u32 *buffer)
4254{
4255 u32 count = 0, i;
4256 const struct cs_section_def *sect = NULL;
4257 const struct cs_extent_def *ext = NULL;
4258
4259 if (adev->gfx.rlc.cs_data == NULL)
4260 return;
4261 if (buffer == NULL)
4262 return;
4263
4264 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4265 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4266
4267 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4268 buffer[count++] = cpu_to_le32(0x80000000);
4269 buffer[count++] = cpu_to_le32(0x80000000);
4270
4271 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4272 for (ext = sect->section; ext->extent != NULL; ++ext) {
4273 if (sect->id == SECT_CONTEXT) {
4274 buffer[count++] =
4275 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4276 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4277 for (i = 0; i < ext->reg_count; i++)
4278 buffer[count++] = cpu_to_le32(ext->extent[i]);
4279 } else {
4280 return;
4281 }
4282 }
4283 }
4284
4285 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4286 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4287 switch (adev->asic_type) {
4288 case CHIP_BONAIRE:
4289 buffer[count++] = cpu_to_le32(0x16000012);
4290 buffer[count++] = cpu_to_le32(0x00000000);
4291 break;
4292 case CHIP_KAVERI:
4293 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4294 buffer[count++] = cpu_to_le32(0x00000000);
4295 break;
4296 case CHIP_KABINI:
4297 case CHIP_MULLINS:
4298 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4299 buffer[count++] = cpu_to_le32(0x00000000);
4300 break;
4301 case CHIP_HAWAII:
4302 buffer[count++] = cpu_to_le32(0x3a00161a);
4303 buffer[count++] = cpu_to_le32(0x0000002e);
4304 break;
4305 default:
4306 buffer[count++] = cpu_to_le32(0x00000000);
4307 buffer[count++] = cpu_to_le32(0x00000000);
4308 break;
4309 }
4310
4311 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4312 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4313
4314 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4315 buffer[count++] = cpu_to_le32(0);
4316}
4317
4318static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4319{
e3b04bc7
AD		 4320 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4321 AMD_PG_SUPPORT_GFX_SMG |
4322 AMD_PG_SUPPORT_GFX_DMG |
4323 AMD_PG_SUPPORT_CP |
4324 AMD_PG_SUPPORT_GDS |
4325 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56
AD		 4326 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4327 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
e3b04bc7 4328 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4329 gfx_v7_0_init_gfx_cgpg(adev);
4330 gfx_v7_0_enable_cp_pg(adev, true);
4331 gfx_v7_0_enable_gds_pg(adev, true);
4332 }
4333 gfx_v7_0_init_ao_cu_mask(adev);
4334 gfx_v7_0_update_gfx_pg(adev, true);
4335 }
4336}
4337
4338static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4339{
e3b04bc7
AD		 4340 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4341 AMD_PG_SUPPORT_GFX_SMG |
4342 AMD_PG_SUPPORT_GFX_DMG |
4343 AMD_PG_SUPPORT_CP |
4344 AMD_PG_SUPPORT_GDS |
4345 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4346 gfx_v7_0_update_gfx_pg(adev, false);
e3b04bc7 4347 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4348 gfx_v7_0_enable_cp_pg(adev, false);
4349 gfx_v7_0_enable_gds_pg(adev, false);
4350 }
4351 }
4352}
4353
4354/**
4355 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4356 *
4357 * @adev: amdgpu_device pointer
4358 *
4359 * Fetches a GPU clock counter snapshot (SI).
4360 * Returns the 64 bit clock counter snapshot.
4361 */
b95e31fd 4362static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
a2e73f56
AD		 4363{
4364 uint64_t clock;
4365
4366 mutex_lock(&adev->gfx.gpu_clock_mutex);
4367 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4368 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4369 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4370 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4371 return clock;
4372}
4373
4374static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4375 uint32_t vmid,
4376 uint32_t gds_base, uint32_t gds_size,
4377 uint32_t gws_base, uint32_t gws_size,
4378 uint32_t oa_base, uint32_t oa_size)
4379{
4380 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4381 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4382
4383 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4384 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4385
4386 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4387 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4388
4389 /* GDS Base */
4390 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4391 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4392 WRITE_DATA_DST_SEL(0)));
4393 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4394 amdgpu_ring_write(ring, 0);
4395 amdgpu_ring_write(ring, gds_base);
4396
4397 /* GDS Size */
4398 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4399 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4400 WRITE_DATA_DST_SEL(0)));
4401 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4402 amdgpu_ring_write(ring, 0);
4403 amdgpu_ring_write(ring, gds_size);
4404
4405 /* GWS */
4406 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4407 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4408 WRITE_DATA_DST_SEL(0)));
4409 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4410 amdgpu_ring_write(ring, 0);
4411 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4412
4413 /* OA */
4414 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4415 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4416 WRITE_DATA_DST_SEL(0)));
4417 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4418 amdgpu_ring_write(ring, 0);
4419 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4420}
4421
472259f0
TSD		 4422static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4423{
4098e6cd
TSD		 4424 WREG32(mmSQ_IND_INDEX,
4425 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4426 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4427 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4428 (SQ_IND_INDEX__FORCE_READ_MASK));
472259f0
TSD		 4429 return RREG32(mmSQ_IND_DATA);
4430}
4431
cc3f5b8d
TSD		 4432static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4433 uint32_t wave, uint32_t thread,
4434 uint32_t regno, uint32_t num, uint32_t *out)
4435{
4436 WREG32(mmSQ_IND_INDEX,
4437 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4438 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4439 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4440 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4441 (SQ_IND_INDEX__FORCE_READ_MASK) |
4442 (SQ_IND_INDEX__AUTO_INCR_MASK));
4443 while (num--)
4444 *(out++) = RREG32(mmSQ_IND_DATA);
4445}
4446
472259f0
TSD		 4447static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4448{
4449 /* type 0 wave data */
4450 dst[(*no_fields)++] = 0;
4451 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4452 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4453 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4454 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4455 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4456 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4457 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4458 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4459 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4460 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4461 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4462 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
74f3ce31
TSD		 4463 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4464 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4465 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4466 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4467 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4468 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
472259f0
TSD		 4469}
4470
cc3f5b8d
TSD		 4471static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4472 uint32_t wave, uint32_t start,
4473 uint32_t size, uint32_t *dst)
4474{
4475 wave_read_regs(
4476 adev, simd, wave, 0,
4477 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4478}
4479
b95e31fd
AD		 4480static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4481 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
05fb7291 4482 .select_se_sh = &gfx_v7_0_select_se_sh,
472259f0 4483 .read_wave_data = &gfx_v7_0_read_wave_data,
cc3f5b8d 4484 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
b95e31fd
AD		 4485};
4486
06120a1e
AD		 4487static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4488 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4489 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4490};
4491
5fc3aeeb 4492static int gfx_v7_0_early_init(void *handle)
a2e73f56 4493{
5fc3aeeb 4494 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4495
4496 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
78c16834 4497 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
b95e31fd 4498 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
06120a1e 4499 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
a2e73f56
AD		 4500 gfx_v7_0_set_ring_funcs(adev);
4501 gfx_v7_0_set_irq_funcs(adev);
4502 gfx_v7_0_set_gds_init(adev);
4503
4504 return 0;
4505}
4506
ef720532
AD		 4507static int gfx_v7_0_late_init(void *handle)
4508{
4509 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4510 int r;
4511
4512 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4513 if (r)
4514 return r;
4515
4516 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4517 if (r)
4518 return r;
4519
4520 return 0;
4521}
4522
d93f3ca7
AD		 4523static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4524{
4525 u32 gb_addr_config;
4526 u32 mc_shared_chmap, mc_arb_ramcfg;
4527 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4528 u32 tmp;
4529
4530 switch (adev->asic_type) {
4531 case CHIP_BONAIRE:
4532 adev->gfx.config.max_shader_engines = 2;
4533 adev->gfx.config.max_tile_pipes = 4;
4534 adev->gfx.config.max_cu_per_sh = 7;
4535 adev->gfx.config.max_sh_per_se = 1;
4536 adev->gfx.config.max_backends_per_se = 2;
4537 adev->gfx.config.max_texture_channel_caches = 4;
4538 adev->gfx.config.max_gprs = 256;
4539 adev->gfx.config.max_gs_threads = 32;
4540 adev->gfx.config.max_hw_contexts = 8;
4541
4542 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4543 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4544 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4545 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4546 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4547 break;
4548 case CHIP_HAWAII:
4549 adev->gfx.config.max_shader_engines = 4;
4550 adev->gfx.config.max_tile_pipes = 16;
4551 adev->gfx.config.max_cu_per_sh = 11;
4552 adev->gfx.config.max_sh_per_se = 1;
4553 adev->gfx.config.max_backends_per_se = 4;
4554 adev->gfx.config.max_texture_channel_caches = 16;
4555 adev->gfx.config.max_gprs = 256;
4556 adev->gfx.config.max_gs_threads = 32;
4557 adev->gfx.config.max_hw_contexts = 8;
4558
4559 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4560 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4561 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4562 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4563 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4564 break;
4565 case CHIP_KAVERI:
4566 adev->gfx.config.max_shader_engines = 1;
4567 adev->gfx.config.max_tile_pipes = 4;
4568 if ((adev->pdev->device == 0x1304) ||
4569 (adev->pdev->device == 0x1305) ||
4570 (adev->pdev->device == 0x130C) ||
4571 (adev->pdev->device == 0x130F) ||
4572 (adev->pdev->device == 0x1310) ||
4573 (adev->pdev->device == 0x1311) ||
4574 (adev->pdev->device == 0x131C)) {
4575 adev->gfx.config.max_cu_per_sh = 8;
4576 adev->gfx.config.max_backends_per_se = 2;
4577 } else if ((adev->pdev->device == 0x1309) ||
4578 (adev->pdev->device == 0x130A) ||
4579 (adev->pdev->device == 0x130D) ||
4580 (adev->pdev->device == 0x1313) ||
4581 (adev->pdev->device == 0x131D)) {
4582 adev->gfx.config.max_cu_per_sh = 6;
4583 adev->gfx.config.max_backends_per_se = 2;
4584 } else if ((adev->pdev->device == 0x1306) ||
4585 (adev->pdev->device == 0x1307) ||
4586 (adev->pdev->device == 0x130B) ||
4587 (adev->pdev->device == 0x130E) ||
4588 (adev->pdev->device == 0x1315) ||
4589 (adev->pdev->device == 0x131B)) {
4590 adev->gfx.config.max_cu_per_sh = 4;
4591 adev->gfx.config.max_backends_per_se = 1;
4592 } else {
4593 adev->gfx.config.max_cu_per_sh = 3;
4594 adev->gfx.config.max_backends_per_se = 1;
4595 }
4596 adev->gfx.config.max_sh_per_se = 1;
4597 adev->gfx.config.max_texture_channel_caches = 4;
4598 adev->gfx.config.max_gprs = 256;
4599 adev->gfx.config.max_gs_threads = 16;
4600 adev->gfx.config.max_hw_contexts = 8;
4601
4602 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4603 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4604 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4605 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4606 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4607 break;
4608 case CHIP_KABINI:
4609 case CHIP_MULLINS:
4610 default:
4611 adev->gfx.config.max_shader_engines = 1;
4612 adev->gfx.config.max_tile_pipes = 2;
4613 adev->gfx.config.max_cu_per_sh = 2;
4614 adev->gfx.config.max_sh_per_se = 1;
4615 adev->gfx.config.max_backends_per_se = 1;
4616 adev->gfx.config.max_texture_channel_caches = 2;
4617 adev->gfx.config.max_gprs = 256;
4618 adev->gfx.config.max_gs_threads = 16;
4619 adev->gfx.config.max_hw_contexts = 8;
4620
4621 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4622 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4623 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4624 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4625 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4626 break;
4627 }
4628
4629 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4630 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4631 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4632
4633 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4634 adev->gfx.config.mem_max_burst_length_bytes = 256;
4635 if (adev->flags & AMD_IS_APU) {
4636 /* Get memory bank mapping mode. */
4637 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4638 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4639 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4640
4641 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4642 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4643 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4644
4645 /* Validate settings in case only one DIMM installed. */
4646 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4647 dimm00_addr_map = 0;
4648 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4649 dimm01_addr_map = 0;
4650 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4651 dimm10_addr_map = 0;
4652 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4653 dimm11_addr_map = 0;
4654
4655 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4656 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4657 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4658 adev->gfx.config.mem_row_size_in_kb = 2;
4659 else
4660 adev->gfx.config.mem_row_size_in_kb = 1;
4661 } else {
4662 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4663 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4664 if (adev->gfx.config.mem_row_size_in_kb > 4)
4665 adev->gfx.config.mem_row_size_in_kb = 4;
4666 }
4667 /* XXX use MC settings? */
4668 adev->gfx.config.shader_engine_tile_size = 32;
4669 adev->gfx.config.num_gpus = 1;
4670 adev->gfx.config.multi_gpu_tile_size = 64;
4671
4672 /* fix up row size */
4673 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4674 switch (adev->gfx.config.mem_row_size_in_kb) {
4675 case 1:
4676 default:
4677 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4678 break;
4679 case 2:
4680 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4681 break;
4682 case 4:
4683 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4684 break;
4685 }
4686 adev->gfx.config.gb_addr_config = gb_addr_config;
4687}
4688
e33fec48
AR		 4689static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4690 int mec, int pipe, int queue)
4691{
4692 int r;
4693 unsigned irq_type;
4694 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4695
4696 /* mec0 is me1 */
4697 ring->me = mec + 1;
4698 ring->pipe = pipe;
4699 ring->queue = queue;
4700
4701 ring->ring_obj = NULL;
4702 ring->use_doorbell = true;
4703 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
4704 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4705
4706 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4707 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4708 + ring->pipe;
4709
4710 /* type-2 packets are deprecated on MEC, use type-3 instead */
4711 r = amdgpu_ring_init(adev, ring, 1024,
4712 &adev->gfx.eop_irq, irq_type);
4713 if (r)
4714 return r;
4715
4716
4717 return 0;
4718}
4719
5fc3aeeb 4720static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4721{
4722 struct amdgpu_ring *ring;
5fc3aeeb 4723 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
e33fec48 4724 int i, j, k, r, ring_id;
a2e73f56
AD		 4725
4726 /* EOP Event */
d766e6a3 4727 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
a2e73f56
AD		 4728 if (r)
4729 return r;
4730
4731 /* Privileged reg */
d766e6a3
AD		 4732 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
4733 &adev->gfx.priv_reg_irq);
a2e73f56
AD		 4734 if (r)
4735 return r;
4736
4737 /* Privileged inst */
d766e6a3
AD		 4738 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
4739 &adev->gfx.priv_inst_irq);
a2e73f56
AD		 4740 if (r)
4741 return r;
4742
4743 gfx_v7_0_scratch_init(adev);
4744
4745 r = gfx_v7_0_init_microcode(adev);
4746 if (r) {
4747 DRM_ERROR("Failed to load gfx firmware!\n");
4748 return r;
4749 }
4750
4751 r = gfx_v7_0_rlc_init(adev);
4752 if (r) {
4753 DRM_ERROR("Failed to init rlc BOs!\n");
4754 return r;
4755 }
4756
4757 /* allocate mec buffers */
4758 r = gfx_v7_0_mec_init(adev);
4759 if (r) {
4760 DRM_ERROR("Failed to init MEC BOs!\n");
4761 return r;
4762 }
4763
a2e73f56
AD		 4764 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4765 ring = &adev->gfx.gfx_ring[i];
4766 ring->ring_obj = NULL;
4767 sprintf(ring->name, "gfx");
2800de2e 4768 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 4769 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
a2e73f56
AD		 4770 if (r)
4771 return r;
4772 }
4773
e33fec48
AR		 4774 /* set up the compute queues - allocate horizontally across pipes */
4775 ring_id = 0;
4776 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4777 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4778 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2db0cdbe 4779 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
e33fec48
AR		 4780 continue;
4781
4782 r = gfx_v7_0_compute_ring_init(adev,
4783 ring_id,
4784 i, k, j);
4785 if (r)
4786 return r;
4787
4788 ring_id++;
4789 }
4790 }
a2e73f56
AD		 4791 }
4792
4793 /* reserve GDS, GWS and OA resource for gfx */
78bbbd9c
CK		 4794 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4795 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4796 &adev->gds.gds_gfx_bo, NULL, NULL);
a2e73f56
AD		 4797 if (r)
4798 return r;
4799
78bbbd9c
CK		 4800 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4801 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4802 &adev->gds.gws_gfx_bo, NULL, NULL);
a2e73f56
AD		 4803 if (r)
4804 return r;
4805
78bbbd9c
CK		 4806 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4807 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4808 &adev->gds.oa_gfx_bo, NULL, NULL);
a2e73f56
AD		 4809 if (r)
4810 return r;
4811
d93f3ca7
AD		 4812 adev->gfx.ce_ram_size = 0x8000;
4813
4814 gfx_v7_0_gpu_early_init(adev);
4815
a2e73f56
AD		 4816 return r;
4817}
4818
5fc3aeeb 4819static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4820{
4821 int i;
5fc3aeeb 4822 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4823
8640faed
JZ		 4824 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4825 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4826 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
a2e73f56
AD		 4827
4828 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4829 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4830 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4831 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4832
a2e73f56
AD		 4833 gfx_v7_0_cp_compute_fini(adev);
4834 gfx_v7_0_rlc_fini(adev);
4835 gfx_v7_0_mec_fini(adev);
e517cd77 4836 gfx_v7_0_free_microcode(adev);
a2e73f56
AD		 4837
4838 return 0;
4839}
4840
5fc3aeeb 4841static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4842{
4843 int r;
5fc3aeeb 4844 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4845
4846 gfx_v7_0_gpu_init(adev);
4847
4848 /* init rlc */
4849 r = gfx_v7_0_rlc_resume(adev);
4850 if (r)
4851 return r;
4852
4853 r = gfx_v7_0_cp_resume(adev);
4854 if (r)
4855 return r;
4856
4857 return r;
4858}
4859
5fc3aeeb 4860static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4861{
5fc3aeeb 4862 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4863
ef720532
AD		 4864 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4865 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4866 gfx_v7_0_cp_enable(adev, false);
4867 gfx_v7_0_rlc_stop(adev);
4868 gfx_v7_0_fini_pg(adev);
4869
4870 return 0;
4871}
4872
5fc3aeeb 4873static int gfx_v7_0_suspend(void *handle)
a2e73f56 4874{
5fc3aeeb 4875 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4876
a2e73f56
AD		 4877 return gfx_v7_0_hw_fini(adev);
4878}
4879
5fc3aeeb 4880static int gfx_v7_0_resume(void *handle)
a2e73f56 4881{
5fc3aeeb 4882 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4883
a2e73f56
AD		 4884 return gfx_v7_0_hw_init(adev);
4885}
4886
5fc3aeeb 4887static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4888{
5fc3aeeb 4889 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4890
a2e73f56
AD		 4891 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4892 return false;
4893 else
4894 return true;
4895}
4896
5fc3aeeb 4897static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4898{
4899 unsigned i;
4900 u32 tmp;
5fc3aeeb 4901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4902
4903 for (i = 0; i < adev->usec_timeout; i++) {
4904 /* read MC_STATUS */
4905 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4906
4907 if (!tmp)
4908 return 0;
4909 udelay(1);
4910 }
4911 return -ETIMEDOUT;
4912}
4913
5fc3aeeb 4914static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4915{
4916 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4917 u32 tmp;
5fc3aeeb 4918 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4919
4920 /* GRBM_STATUS */
4921 tmp = RREG32(mmGRBM_STATUS);
4922 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4923 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4924 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4925 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4926 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4927 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4928 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4929 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4930
4931 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4932 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4933 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4934 }
4935
4936 /* GRBM_STATUS2 */
4937 tmp = RREG32(mmGRBM_STATUS2);
4938 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4939 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4940
4941 /* SRBM_STATUS */
4942 tmp = RREG32(mmSRBM_STATUS);
4943 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4944 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4945
4946 if (grbm_soft_reset || srbm_soft_reset) {
a2e73f56
AD		 4947 /* disable CG/PG */
4948 gfx_v7_0_fini_pg(adev);
4949 gfx_v7_0_update_cg(adev, false);
4950
4951 /* stop the rlc */
4952 gfx_v7_0_rlc_stop(adev);
4953
4954 /* Disable GFX parsing/prefetching */
4955 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4956
4957 /* Disable MEC parsing/prefetching */
4958 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4959
4960 if (grbm_soft_reset) {
4961 tmp = RREG32(mmGRBM_SOFT_RESET);
4962 tmp |= grbm_soft_reset;
4963 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4964 WREG32(mmGRBM_SOFT_RESET, tmp);
4965 tmp = RREG32(mmGRBM_SOFT_RESET);
4966
4967 udelay(50);
4968
4969 tmp &= ~grbm_soft_reset;
4970 WREG32(mmGRBM_SOFT_RESET, tmp);
4971 tmp = RREG32(mmGRBM_SOFT_RESET);
4972 }
4973
4974 if (srbm_soft_reset) {
4975 tmp = RREG32(mmSRBM_SOFT_RESET);
4976 tmp |= srbm_soft_reset;
4977 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4978 WREG32(mmSRBM_SOFT_RESET, tmp);
4979 tmp = RREG32(mmSRBM_SOFT_RESET);
4980
4981 udelay(50);
4982
4983 tmp &= ~srbm_soft_reset;
4984 WREG32(mmSRBM_SOFT_RESET, tmp);
4985 tmp = RREG32(mmSRBM_SOFT_RESET);
4986 }
4987 /* Wait a little for things to settle down */
4988 udelay(50);
a2e73f56
AD		 4989 }
4990 return 0;
4991}
4992
4993static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4994 enum amdgpu_interrupt_state state)
4995{
4996 u32 cp_int_cntl;
4997
4998 switch (state) {
4999 case AMDGPU_IRQ_STATE_DISABLE:
5000 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5001 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5002 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5003 break;
5004 case AMDGPU_IRQ_STATE_ENABLE:
5005 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5006 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5007 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5008 break;
5009 default:
5010 break;
5011 }
5012}
5013
5014static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5015 int me, int pipe,
5016 enum amdgpu_interrupt_state state)
5017{
763a47b8
AR		 5018 /* Me 0 is for graphics and Me 2 is reserved for HW scheduling
5019 * So we should only really be configuring ME 1 i.e. MEC0
a2e73f56 5020 */
763a47b8
AR		 5021 if (me != 1) {
5022 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
a2e73f56
AD		 5023 return;
5024 }
5025
763a47b8
AR		 5026 if (pipe >= adev->gfx.mec.num_pipe_per_mec) {
5027 DRM_ERROR("Ignoring request to enable interrupts for invalid "
5028 "me:%d pipe:%d\n", pipe, me);
5029 return;
a2e73f56 5030 }
763a47b8
AR		 5031
5032 mutex_lock(&adev->srbm_mutex);
5033 cik_srbm_select(adev, me, pipe, 0, 0);
5034
5035 WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE,
5036 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
5037
5038 cik_srbm_select(adev, 0, 0, 0, 0);
5039 mutex_unlock(&adev->srbm_mutex);
a2e73f56
AD		 5040}
5041
5042static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5043 struct amdgpu_irq_src *src,
5044 unsigned type,
5045 enum amdgpu_interrupt_state state)
5046{
5047 u32 cp_int_cntl;
5048
5049 switch (state) {
5050 case AMDGPU_IRQ_STATE_DISABLE:
5051 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5052 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5053 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5054 break;
5055 case AMDGPU_IRQ_STATE_ENABLE:
5056 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5057 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5058 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5059 break;
5060 default:
5061 break;
5062 }
5063
5064 return 0;
5065}
5066
5067static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5068 struct amdgpu_irq_src *src,
5069 unsigned type,
5070 enum amdgpu_interrupt_state state)
5071{
5072 u32 cp_int_cntl;
5073
5074 switch (state) {
5075 case AMDGPU_IRQ_STATE_DISABLE:
5076 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5077 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5078 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5079 break;
5080 case AMDGPU_IRQ_STATE_ENABLE:
5081 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5082 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5083 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5084 break;
5085 default:
5086 break;
5087 }
5088
5089 return 0;
5090}
5091
5092static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5093 struct amdgpu_irq_src *src,
5094 unsigned type,
5095 enum amdgpu_interrupt_state state)
5096{
5097 switch (type) {
5098 case AMDGPU_CP_IRQ_GFX_EOP:
5099 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5100 break;
5101 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5102 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5103 break;
5104 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5105 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5106 break;
5107 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5108 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5109 break;
5110 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5111 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5112 break;
5113 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5114 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5115 break;
5116 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5117 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5118 break;
5119 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5120 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5121 break;
5122 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5123 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5124 break;
5125 default:
5126 break;
5127 }
5128 return 0;
5129}
5130
5131static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5132 struct amdgpu_irq_src *source,
5133 struct amdgpu_iv_entry *entry)
5134{
5135 u8 me_id, pipe_id;
5136 struct amdgpu_ring *ring;
5137 int i;
5138
5139 DRM_DEBUG("IH: CP EOP\n");
5140 me_id = (entry->ring_id & 0x0c) >> 2;
5141 pipe_id = (entry->ring_id & 0x03) >> 0;
5142 switch (me_id) {
5143 case 0:
5144 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5145 break;
5146 case 1:
5147 case 2:
5148 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5149 ring = &adev->gfx.compute_ring[i];
8b18300c 5150 if ((ring->me == me_id) && (ring->pipe == pipe_id))
a2e73f56
AD		 5151 amdgpu_fence_process(ring);
5152 }
5153 break;
5154 }
5155 return 0;
5156}
5157
5158static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5159 struct amdgpu_irq_src *source,
5160 struct amdgpu_iv_entry *entry)
5161{
5162 DRM_ERROR("Illegal register access in command stream\n");
5163 schedule_work(&adev->reset_work);
5164 return 0;
5165}
5166
5167static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5168 struct amdgpu_irq_src *source,
5169 struct amdgpu_iv_entry *entry)
5170{
5171 DRM_ERROR("Illegal instruction in command stream\n");
5172 // XXX soft reset the gfx block only
5173 schedule_work(&adev->reset_work);
5174 return 0;
5175}
5176
5fc3aeeb 5177static int gfx_v7_0_set_clockgating_state(void *handle,
5178 enum amd_clockgating_state state)
a2e73f56
AD		 5179{
5180 bool gate = false;
5fc3aeeb 5181 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5182
5fc3aeeb 5183 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 5184 gate = true;
5185
5186 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5187 /* order matters! */
5188 if (gate) {
5189 gfx_v7_0_enable_mgcg(adev, true);
5190 gfx_v7_0_enable_cgcg(adev, true);
5191 } else {
5192 gfx_v7_0_enable_cgcg(adev, false);
5193 gfx_v7_0_enable_mgcg(adev, false);
5194 }
5195 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5196
5197 return 0;
5198}
5199
5fc3aeeb 5200static int gfx_v7_0_set_powergating_state(void *handle,
5201 enum amd_powergating_state state)
a2e73f56
AD		 5202{
5203 bool gate = false;
5fc3aeeb 5204 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5205
5fc3aeeb 5206 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 5207 gate = true;
5208
e3b04bc7
AD		 5209 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5210 AMD_PG_SUPPORT_GFX_SMG |
5211 AMD_PG_SUPPORT_GFX_DMG |
5212 AMD_PG_SUPPORT_CP |
5213 AMD_PG_SUPPORT_GDS |
5214 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 5215 gfx_v7_0_update_gfx_pg(adev, gate);
e3b04bc7 5216 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 5217 gfx_v7_0_enable_cp_pg(adev, gate);
5218 gfx_v7_0_enable_gds_pg(adev, gate);
5219 }
5220 }
5221
5222 return 0;
5223}
5224
a1255107 5225static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
88a907d6 5226 .name = "gfx_v7_0",
a2e73f56 5227 .early_init = gfx_v7_0_early_init,
ef720532 5228 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 5229 .sw_init = gfx_v7_0_sw_init,
5230 .sw_fini = gfx_v7_0_sw_fini,
5231 .hw_init = gfx_v7_0_hw_init,
5232 .hw_fini = gfx_v7_0_hw_fini,
5233 .suspend = gfx_v7_0_suspend,
5234 .resume = gfx_v7_0_resume,
5235 .is_idle = gfx_v7_0_is_idle,
5236 .wait_for_idle = gfx_v7_0_wait_for_idle,
5237 .soft_reset = gfx_v7_0_soft_reset,
a2e73f56
AD		 5238 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5239 .set_powergating_state = gfx_v7_0_set_powergating_state,
5240};
5241
a2e73f56 5242static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
21cd942e 5243 .type = AMDGPU_RING_TYPE_GFX,
79887142
CK		 5244 .align_mask = 0xff,
5245 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
536fbf94 5246 .support_64bit_ptrs = false,
f1c0efc5 5247 .get_rptr = gfx_v7_0_ring_get_rptr,
a2e73f56
AD		 5248 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5249 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
e12f3d7a
CK		 5250 .emit_frame_size =
5251 20 + /* gfx_v7_0_ring_emit_gds_switch */
5252 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5253 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5254 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5255 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5256 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
45682886 5257 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
e12f3d7a 5258 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
93323131 5259 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 5260 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
b8c7b39e 5261 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 5262 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5263 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 5264 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 5265 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 5266 .test_ring = gfx_v7_0_ring_test_ring,
5267 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5268 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5269 .pad_ib = amdgpu_ring_generic_pad_ib,
753ad49c 5270 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
a2e73f56
AD		 5271};
5272
5273static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
21cd942e 5274 .type = AMDGPU_RING_TYPE_COMPUTE,
79887142
CK		 5275 .align_mask = 0xff,
5276 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
536fbf94 5277 .support_64bit_ptrs = false,
f1c0efc5 5278 .get_rptr = gfx_v7_0_ring_get_rptr,
a2e73f56
AD		 5279 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5280 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
e12f3d7a
CK		 5281 .emit_frame_size =
5282 20 + /* gfx_v7_0_ring_emit_gds_switch */
5283 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5284 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5285 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5286 17 + /* gfx_v7_0_ring_emit_vm_flush */
5287 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5288 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
93323131 5289 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 5290 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
b8c7b39e 5291 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 5292 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5293 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 5294 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 5295 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 5296 .test_ring = gfx_v7_0_ring_test_ring,
5297 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5298 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5299 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5300};
5301
5302static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5303{
5304 int i;
5305
5306 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5307 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5308 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5309 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5310}
5311
5312static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5313 .set = gfx_v7_0_set_eop_interrupt_state,
5314 .process = gfx_v7_0_eop_irq,
5315};
5316
5317static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5318 .set = gfx_v7_0_set_priv_reg_fault_state,
5319 .process = gfx_v7_0_priv_reg_irq,
5320};
5321
5322static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5323 .set = gfx_v7_0_set_priv_inst_fault_state,
5324 .process = gfx_v7_0_priv_inst_irq,
5325};
5326
5327static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5328{
5329 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5330 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5331
5332 adev->gfx.priv_reg_irq.num_types = 1;
5333 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5334
5335 adev->gfx.priv_inst_irq.num_types = 1;
5336 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5337}
5338
5339static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5340{
5341 /* init asci gds info */
5342 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5343 adev->gds.gws.total_size = 64;
5344 adev->gds.oa.total_size = 16;
5345
5346 if (adev->gds.mem.total_size == 64 * 1024) {
5347 adev->gds.mem.gfx_partition_size = 4096;
5348 adev->gds.mem.cs_partition_size = 4096;
5349
5350 adev->gds.gws.gfx_partition_size = 4;
5351 adev->gds.gws.cs_partition_size = 4;
5352
5353 adev->gds.oa.gfx_partition_size = 4;
5354 adev->gds.oa.cs_partition_size = 1;
5355 } else {
5356 adev->gds.mem.gfx_partition_size = 1024;
5357 adev->gds.mem.cs_partition_size = 1024;
5358
5359 adev->gds.gws.gfx_partition_size = 16;
5360 adev->gds.gws.cs_partition_size = 16;
5361
5362 adev->gds.oa.gfx_partition_size = 4;
5363 adev->gds.oa.cs_partition_size = 4;
5364 }
5365}
5366
5367
7dae69a2 5368static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
a2e73f56
AD		 5369{
5370 int i, j, k, counter, active_cu_number = 0;
5371 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 5372 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
324c614a 5373 unsigned disable_masks[4 * 2];
fe723cd3
RZ		 5374 u32 ao_cu_num;
5375
5376 if (adev->flags & AMD_IS_APU)
5377 ao_cu_num = 2;
5378 else
5379 ao_cu_num = adev->gfx.config.max_cu_per_sh;
a2e73f56 5380
6157bd7a
FC		 5381 memset(cu_info, 0, sizeof(*cu_info));
5382
324c614a
NH		 5383 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5384
a2e73f56
AD		 5385 mutex_lock(&adev->grbm_idx_mutex);
5386 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5387 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5388 mask = 1;
5389 ao_bitmap = 0;
5390 counter = 0;
9559ef5b 5391 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
324c614a
NH		 5392 if (i < 4 && j < 2)
5393 gfx_v7_0_set_user_cu_inactive_bitmap(
5394 adev, disable_masks[i * 2 + j]);
8f8e00c1 5395 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5396 cu_info->bitmap[i][j] = bitmap;
5397
fe723cd3 5398 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
a2e73f56 5399 if (bitmap & mask) {
fe723cd3 5400 if (counter < ao_cu_num)
a2e73f56
AD		 5401 ao_bitmap |= mask;
5402 counter ++;
5403 }
5404 mask <<= 1;
5405 }
5406 active_cu_number += counter;
5407 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5408 }
5409 }
9559ef5b 5410 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8f8e00c1 5411 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5412
5413 cu_info->number = active_cu_number;
5414 cu_info->ao_cu_mask = ao_cu_mask;
a2e73f56 5415}
a1255107
AD		 5416
5417const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5418{
5419 .type = AMD_IP_BLOCK_TYPE_GFX,
5420 .major = 7,
5421 .minor = 0,
5422 .rev = 0,
5423 .funcs = &gfx_v7_0_ip_funcs,
5424};
5425
5426const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5427{
5428 .type = AMD_IP_BLOCK_TYPE_GFX,
5429 .major = 7,
5430 .minor = 1,
5431 .rev = 0,
5432 .funcs = &gfx_v7_0_ip_funcs,
5433};
5434
5435const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5436{
5437 .type = AMD_IP_BLOCK_TYPE_GFX,
5438 .major = 7,
5439 .minor = 2,
5440 .rev = 0,
5441 .funcs = &gfx_v7_0_ip_funcs,
5442};
5443
5444const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5445{
5446 .type = AMD_IP_BLOCK_TYPE_GFX,
5447 .major = 7,
5448 .minor = 3,
5449 .rev = 0,
5450 .funcs = &gfx_v7_0_ip_funcs,
5451};
Linux 6.x block layer and io_uring tree(s)