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drm/amdgpu: fix VM faults caused by vm_grab_id() v4
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
a2e73f56
AD		 34#include "dce/dce_8_0_d.h"
35#include "dce/dce_8_0_sh_mask.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gca/gfx_7_0_d.h"
41#include "gca/gfx_7_2_enum.h"
42#include "gca/gfx_7_2_sh_mask.h"
43
44#include "gmc/gmc_7_0_d.h"
45#include "gmc/gmc_7_0_sh_mask.h"
46
47#include "oss/oss_2_0_d.h"
48#include "oss/oss_2_0_sh_mask.h"
49
50#define GFX7_NUM_GFX_RINGS 1
51#define GFX7_NUM_COMPUTE_RINGS 8
52
53static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
56int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
57
58MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
59MODULE_FIRMWARE("radeon/bonaire_me.bin");
60MODULE_FIRMWARE("radeon/bonaire_ce.bin");
61MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
62MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63
64MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
65MODULE_FIRMWARE("radeon/hawaii_me.bin");
66MODULE_FIRMWARE("radeon/hawaii_ce.bin");
67MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
68MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69
70MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
71MODULE_FIRMWARE("radeon/kaveri_me.bin");
72MODULE_FIRMWARE("radeon/kaveri_ce.bin");
73MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec.bin");
75MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
76
77MODULE_FIRMWARE("radeon/kabini_pfp.bin");
78MODULE_FIRMWARE("radeon/kabini_me.bin");
79MODULE_FIRMWARE("radeon/kabini_ce.bin");
80MODULE_FIRMWARE("radeon/kabini_rlc.bin");
81MODULE_FIRMWARE("radeon/kabini_mec.bin");
82
83MODULE_FIRMWARE("radeon/mullins_pfp.bin");
84MODULE_FIRMWARE("radeon/mullins_me.bin");
85MODULE_FIRMWARE("radeon/mullins_ce.bin");
86MODULE_FIRMWARE("radeon/mullins_rlc.bin");
87MODULE_FIRMWARE("radeon/mullins_mec.bin");
88
89static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
90{
91 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
92 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
93 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
94 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
95 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
96 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
97 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
98 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
99 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
100 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
101 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
102 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
103 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
104 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
105 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
106 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
107};
108
109static const u32 spectre_rlc_save_restore_register_list[] =
110{
111 (0x0e00 << 16) | (0xc12c >> 2),
112 0x00000000,
113 (0x0e00 << 16) | (0xc140 >> 2),
114 0x00000000,
115 (0x0e00 << 16) | (0xc150 >> 2),
116 0x00000000,
117 (0x0e00 << 16) | (0xc15c >> 2),
118 0x00000000,
119 (0x0e00 << 16) | (0xc168 >> 2),
120 0x00000000,
121 (0x0e00 << 16) | (0xc170 >> 2),
122 0x00000000,
123 (0x0e00 << 16) | (0xc178 >> 2),
124 0x00000000,
125 (0x0e00 << 16) | (0xc204 >> 2),
126 0x00000000,
127 (0x0e00 << 16) | (0xc2b4 >> 2),
128 0x00000000,
129 (0x0e00 << 16) | (0xc2b8 >> 2),
130 0x00000000,
131 (0x0e00 << 16) | (0xc2bc >> 2),
132 0x00000000,
133 (0x0e00 << 16) | (0xc2c0 >> 2),
134 0x00000000,
135 (0x0e00 << 16) | (0x8228 >> 2),
136 0x00000000,
137 (0x0e00 << 16) | (0x829c >> 2),
138 0x00000000,
139 (0x0e00 << 16) | (0x869c >> 2),
140 0x00000000,
141 (0x0600 << 16) | (0x98f4 >> 2),
142 0x00000000,
143 (0x0e00 << 16) | (0x98f8 >> 2),
144 0x00000000,
145 (0x0e00 << 16) | (0x9900 >> 2),
146 0x00000000,
147 (0x0e00 << 16) | (0xc260 >> 2),
148 0x00000000,
149 (0x0e00 << 16) | (0x90e8 >> 2),
150 0x00000000,
151 (0x0e00 << 16) | (0x3c000 >> 2),
152 0x00000000,
153 (0x0e00 << 16) | (0x3c00c >> 2),
154 0x00000000,
155 (0x0e00 << 16) | (0x8c1c >> 2),
156 0x00000000,
157 (0x0e00 << 16) | (0x9700 >> 2),
158 0x00000000,
159 (0x0e00 << 16) | (0xcd20 >> 2),
160 0x00000000,
161 (0x4e00 << 16) | (0xcd20 >> 2),
162 0x00000000,
163 (0x5e00 << 16) | (0xcd20 >> 2),
164 0x00000000,
165 (0x6e00 << 16) | (0xcd20 >> 2),
166 0x00000000,
167 (0x7e00 << 16) | (0xcd20 >> 2),
168 0x00000000,
169 (0x8e00 << 16) | (0xcd20 >> 2),
170 0x00000000,
171 (0x9e00 << 16) | (0xcd20 >> 2),
172 0x00000000,
173 (0xae00 << 16) | (0xcd20 >> 2),
174 0x00000000,
175 (0xbe00 << 16) | (0xcd20 >> 2),
176 0x00000000,
177 (0x0e00 << 16) | (0x89bc >> 2),
178 0x00000000,
179 (0x0e00 << 16) | (0x8900 >> 2),
180 0x00000000,
181 0x3,
182 (0x0e00 << 16) | (0xc130 >> 2),
183 0x00000000,
184 (0x0e00 << 16) | (0xc134 >> 2),
185 0x00000000,
186 (0x0e00 << 16) | (0xc1fc >> 2),
187 0x00000000,
188 (0x0e00 << 16) | (0xc208 >> 2),
189 0x00000000,
190 (0x0e00 << 16) | (0xc264 >> 2),
191 0x00000000,
192 (0x0e00 << 16) | (0xc268 >> 2),
193 0x00000000,
194 (0x0e00 << 16) | (0xc26c >> 2),
195 0x00000000,
196 (0x0e00 << 16) | (0xc270 >> 2),
197 0x00000000,
198 (0x0e00 << 16) | (0xc274 >> 2),
199 0x00000000,
200 (0x0e00 << 16) | (0xc278 >> 2),
201 0x00000000,
202 (0x0e00 << 16) | (0xc27c >> 2),
203 0x00000000,
204 (0x0e00 << 16) | (0xc280 >> 2),
205 0x00000000,
206 (0x0e00 << 16) | (0xc284 >> 2),
207 0x00000000,
208 (0x0e00 << 16) | (0xc288 >> 2),
209 0x00000000,
210 (0x0e00 << 16) | (0xc28c >> 2),
211 0x00000000,
212 (0x0e00 << 16) | (0xc290 >> 2),
213 0x00000000,
214 (0x0e00 << 16) | (0xc294 >> 2),
215 0x00000000,
216 (0x0e00 << 16) | (0xc298 >> 2),
217 0x00000000,
218 (0x0e00 << 16) | (0xc29c >> 2),
219 0x00000000,
220 (0x0e00 << 16) | (0xc2a0 >> 2),
221 0x00000000,
222 (0x0e00 << 16) | (0xc2a4 >> 2),
223 0x00000000,
224 (0x0e00 << 16) | (0xc2a8 >> 2),
225 0x00000000,
226 (0x0e00 << 16) | (0xc2ac >> 2),
227 0x00000000,
228 (0x0e00 << 16) | (0xc2b0 >> 2),
229 0x00000000,
230 (0x0e00 << 16) | (0x301d0 >> 2),
231 0x00000000,
232 (0x0e00 << 16) | (0x30238 >> 2),
233 0x00000000,
234 (0x0e00 << 16) | (0x30250 >> 2),
235 0x00000000,
236 (0x0e00 << 16) | (0x30254 >> 2),
237 0x00000000,
238 (0x0e00 << 16) | (0x30258 >> 2),
239 0x00000000,
240 (0x0e00 << 16) | (0x3025c >> 2),
241 0x00000000,
242 (0x4e00 << 16) | (0xc900 >> 2),
243 0x00000000,
244 (0x5e00 << 16) | (0xc900 >> 2),
245 0x00000000,
246 (0x6e00 << 16) | (0xc900 >> 2),
247 0x00000000,
248 (0x7e00 << 16) | (0xc900 >> 2),
249 0x00000000,
250 (0x8e00 << 16) | (0xc900 >> 2),
251 0x00000000,
252 (0x9e00 << 16) | (0xc900 >> 2),
253 0x00000000,
254 (0xae00 << 16) | (0xc900 >> 2),
255 0x00000000,
256 (0xbe00 << 16) | (0xc900 >> 2),
257 0x00000000,
258 (0x4e00 << 16) | (0xc904 >> 2),
259 0x00000000,
260 (0x5e00 << 16) | (0xc904 >> 2),
261 0x00000000,
262 (0x6e00 << 16) | (0xc904 >> 2),
263 0x00000000,
264 (0x7e00 << 16) | (0xc904 >> 2),
265 0x00000000,
266 (0x8e00 << 16) | (0xc904 >> 2),
267 0x00000000,
268 (0x9e00 << 16) | (0xc904 >> 2),
269 0x00000000,
270 (0xae00 << 16) | (0xc904 >> 2),
271 0x00000000,
272 (0xbe00 << 16) | (0xc904 >> 2),
273 0x00000000,
274 (0x4e00 << 16) | (0xc908 >> 2),
275 0x00000000,
276 (0x5e00 << 16) | (0xc908 >> 2),
277 0x00000000,
278 (0x6e00 << 16) | (0xc908 >> 2),
279 0x00000000,
280 (0x7e00 << 16) | (0xc908 >> 2),
281 0x00000000,
282 (0x8e00 << 16) | (0xc908 >> 2),
283 0x00000000,
284 (0x9e00 << 16) | (0xc908 >> 2),
285 0x00000000,
286 (0xae00 << 16) | (0xc908 >> 2),
287 0x00000000,
288 (0xbe00 << 16) | (0xc908 >> 2),
289 0x00000000,
290 (0x4e00 << 16) | (0xc90c >> 2),
291 0x00000000,
292 (0x5e00 << 16) | (0xc90c >> 2),
293 0x00000000,
294 (0x6e00 << 16) | (0xc90c >> 2),
295 0x00000000,
296 (0x7e00 << 16) | (0xc90c >> 2),
297 0x00000000,
298 (0x8e00 << 16) | (0xc90c >> 2),
299 0x00000000,
300 (0x9e00 << 16) | (0xc90c >> 2),
301 0x00000000,
302 (0xae00 << 16) | (0xc90c >> 2),
303 0x00000000,
304 (0xbe00 << 16) | (0xc90c >> 2),
305 0x00000000,
306 (0x4e00 << 16) | (0xc910 >> 2),
307 0x00000000,
308 (0x5e00 << 16) | (0xc910 >> 2),
309 0x00000000,
310 (0x6e00 << 16) | (0xc910 >> 2),
311 0x00000000,
312 (0x7e00 << 16) | (0xc910 >> 2),
313 0x00000000,
314 (0x8e00 << 16) | (0xc910 >> 2),
315 0x00000000,
316 (0x9e00 << 16) | (0xc910 >> 2),
317 0x00000000,
318 (0xae00 << 16) | (0xc910 >> 2),
319 0x00000000,
320 (0xbe00 << 16) | (0xc910 >> 2),
321 0x00000000,
322 (0x0e00 << 16) | (0xc99c >> 2),
323 0x00000000,
324 (0x0e00 << 16) | (0x9834 >> 2),
325 0x00000000,
326 (0x0000 << 16) | (0x30f00 >> 2),
327 0x00000000,
328 (0x0001 << 16) | (0x30f00 >> 2),
329 0x00000000,
330 (0x0000 << 16) | (0x30f04 >> 2),
331 0x00000000,
332 (0x0001 << 16) | (0x30f04 >> 2),
333 0x00000000,
334 (0x0000 << 16) | (0x30f08 >> 2),
335 0x00000000,
336 (0x0001 << 16) | (0x30f08 >> 2),
337 0x00000000,
338 (0x0000 << 16) | (0x30f0c >> 2),
339 0x00000000,
340 (0x0001 << 16) | (0x30f0c >> 2),
341 0x00000000,
342 (0x0600 << 16) | (0x9b7c >> 2),
343 0x00000000,
344 (0x0e00 << 16) | (0x8a14 >> 2),
345 0x00000000,
346 (0x0e00 << 16) | (0x8a18 >> 2),
347 0x00000000,
348 (0x0600 << 16) | (0x30a00 >> 2),
349 0x00000000,
350 (0x0e00 << 16) | (0x8bf0 >> 2),
351 0x00000000,
352 (0x0e00 << 16) | (0x8bcc >> 2),
353 0x00000000,
354 (0x0e00 << 16) | (0x8b24 >> 2),
355 0x00000000,
356 (0x0e00 << 16) | (0x30a04 >> 2),
357 0x00000000,
358 (0x0600 << 16) | (0x30a10 >> 2),
359 0x00000000,
360 (0x0600 << 16) | (0x30a14 >> 2),
361 0x00000000,
362 (0x0600 << 16) | (0x30a18 >> 2),
363 0x00000000,
364 (0x0600 << 16) | (0x30a2c >> 2),
365 0x00000000,
366 (0x0e00 << 16) | (0xc700 >> 2),
367 0x00000000,
368 (0x0e00 << 16) | (0xc704 >> 2),
369 0x00000000,
370 (0x0e00 << 16) | (0xc708 >> 2),
371 0x00000000,
372 (0x0e00 << 16) | (0xc768 >> 2),
373 0x00000000,
374 (0x0400 << 16) | (0xc770 >> 2),
375 0x00000000,
376 (0x0400 << 16) | (0xc774 >> 2),
377 0x00000000,
378 (0x0400 << 16) | (0xc778 >> 2),
379 0x00000000,
380 (0x0400 << 16) | (0xc77c >> 2),
381 0x00000000,
382 (0x0400 << 16) | (0xc780 >> 2),
383 0x00000000,
384 (0x0400 << 16) | (0xc784 >> 2),
385 0x00000000,
386 (0x0400 << 16) | (0xc788 >> 2),
387 0x00000000,
388 (0x0400 << 16) | (0xc78c >> 2),
389 0x00000000,
390 (0x0400 << 16) | (0xc798 >> 2),
391 0x00000000,
392 (0x0400 << 16) | (0xc79c >> 2),
393 0x00000000,
394 (0x0400 << 16) | (0xc7a0 >> 2),
395 0x00000000,
396 (0x0400 << 16) | (0xc7a4 >> 2),
397 0x00000000,
398 (0x0400 << 16) | (0xc7a8 >> 2),
399 0x00000000,
400 (0x0400 << 16) | (0xc7ac >> 2),
401 0x00000000,
402 (0x0400 << 16) | (0xc7b0 >> 2),
403 0x00000000,
404 (0x0400 << 16) | (0xc7b4 >> 2),
405 0x00000000,
406 (0x0e00 << 16) | (0x9100 >> 2),
407 0x00000000,
408 (0x0e00 << 16) | (0x3c010 >> 2),
409 0x00000000,
410 (0x0e00 << 16) | (0x92a8 >> 2),
411 0x00000000,
412 (0x0e00 << 16) | (0x92ac >> 2),
413 0x00000000,
414 (0x0e00 << 16) | (0x92b4 >> 2),
415 0x00000000,
416 (0x0e00 << 16) | (0x92b8 >> 2),
417 0x00000000,
418 (0x0e00 << 16) | (0x92bc >> 2),
419 0x00000000,
420 (0x0e00 << 16) | (0x92c0 >> 2),
421 0x00000000,
422 (0x0e00 << 16) | (0x92c4 >> 2),
423 0x00000000,
424 (0x0e00 << 16) | (0x92c8 >> 2),
425 0x00000000,
426 (0x0e00 << 16) | (0x92cc >> 2),
427 0x00000000,
428 (0x0e00 << 16) | (0x92d0 >> 2),
429 0x00000000,
430 (0x0e00 << 16) | (0x8c00 >> 2),
431 0x00000000,
432 (0x0e00 << 16) | (0x8c04 >> 2),
433 0x00000000,
434 (0x0e00 << 16) | (0x8c20 >> 2),
435 0x00000000,
436 (0x0e00 << 16) | (0x8c38 >> 2),
437 0x00000000,
438 (0x0e00 << 16) | (0x8c3c >> 2),
439 0x00000000,
440 (0x0e00 << 16) | (0xae00 >> 2),
441 0x00000000,
442 (0x0e00 << 16) | (0x9604 >> 2),
443 0x00000000,
444 (0x0e00 << 16) | (0xac08 >> 2),
445 0x00000000,
446 (0x0e00 << 16) | (0xac0c >> 2),
447 0x00000000,
448 (0x0e00 << 16) | (0xac10 >> 2),
449 0x00000000,
450 (0x0e00 << 16) | (0xac14 >> 2),
451 0x00000000,
452 (0x0e00 << 16) | (0xac58 >> 2),
453 0x00000000,
454 (0x0e00 << 16) | (0xac68 >> 2),
455 0x00000000,
456 (0x0e00 << 16) | (0xac6c >> 2),
457 0x00000000,
458 (0x0e00 << 16) | (0xac70 >> 2),
459 0x00000000,
460 (0x0e00 << 16) | (0xac74 >> 2),
461 0x00000000,
462 (0x0e00 << 16) | (0xac78 >> 2),
463 0x00000000,
464 (0x0e00 << 16) | (0xac7c >> 2),
465 0x00000000,
466 (0x0e00 << 16) | (0xac80 >> 2),
467 0x00000000,
468 (0x0e00 << 16) | (0xac84 >> 2),
469 0x00000000,
470 (0x0e00 << 16) | (0xac88 >> 2),
471 0x00000000,
472 (0x0e00 << 16) | (0xac8c >> 2),
473 0x00000000,
474 (0x0e00 << 16) | (0x970c >> 2),
475 0x00000000,
476 (0x0e00 << 16) | (0x9714 >> 2),
477 0x00000000,
478 (0x0e00 << 16) | (0x9718 >> 2),
479 0x00000000,
480 (0x0e00 << 16) | (0x971c >> 2),
481 0x00000000,
482 (0x0e00 << 16) | (0x31068 >> 2),
483 0x00000000,
484 (0x4e00 << 16) | (0x31068 >> 2),
485 0x00000000,
486 (0x5e00 << 16) | (0x31068 >> 2),
487 0x00000000,
488 (0x6e00 << 16) | (0x31068 >> 2),
489 0x00000000,
490 (0x7e00 << 16) | (0x31068 >> 2),
491 0x00000000,
492 (0x8e00 << 16) | (0x31068 >> 2),
493 0x00000000,
494 (0x9e00 << 16) | (0x31068 >> 2),
495 0x00000000,
496 (0xae00 << 16) | (0x31068 >> 2),
497 0x00000000,
498 (0xbe00 << 16) | (0x31068 >> 2),
499 0x00000000,
500 (0x0e00 << 16) | (0xcd10 >> 2),
501 0x00000000,
502 (0x0e00 << 16) | (0xcd14 >> 2),
503 0x00000000,
504 (0x0e00 << 16) | (0x88b0 >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x88b4 >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x88b8 >> 2),
509 0x00000000,
510 (0x0e00 << 16) | (0x88bc >> 2),
511 0x00000000,
512 (0x0400 << 16) | (0x89c0 >> 2),
513 0x00000000,
514 (0x0e00 << 16) | (0x88c4 >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x88c8 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x88d0 >> 2),
519 0x00000000,
520 (0x0e00 << 16) | (0x88d4 >> 2),
521 0x00000000,
522 (0x0e00 << 16) | (0x88d8 >> 2),
523 0x00000000,
524 (0x0e00 << 16) | (0x8980 >> 2),
525 0x00000000,
526 (0x0e00 << 16) | (0x30938 >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0x3093c >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0x30940 >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0x89a0 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0x30900 >> 2),
535 0x00000000,
536 (0x0e00 << 16) | (0x30904 >> 2),
537 0x00000000,
538 (0x0e00 << 16) | (0x89b4 >> 2),
539 0x00000000,
540 (0x0e00 << 16) | (0x3c210 >> 2),
541 0x00000000,
542 (0x0e00 << 16) | (0x3c214 >> 2),
543 0x00000000,
544 (0x0e00 << 16) | (0x3c218 >> 2),
545 0x00000000,
546 (0x0e00 << 16) | (0x8904 >> 2),
547 0x00000000,
548 0x5,
549 (0x0e00 << 16) | (0x8c28 >> 2),
550 (0x0e00 << 16) | (0x8c2c >> 2),
551 (0x0e00 << 16) | (0x8c30 >> 2),
552 (0x0e00 << 16) | (0x8c34 >> 2),
553 (0x0e00 << 16) | (0x9600 >> 2),
554};
555
556static const u32 kalindi_rlc_save_restore_register_list[] =
557{
558 (0x0e00 << 16) | (0xc12c >> 2),
559 0x00000000,
560 (0x0e00 << 16) | (0xc140 >> 2),
561 0x00000000,
562 (0x0e00 << 16) | (0xc150 >> 2),
563 0x00000000,
564 (0x0e00 << 16) | (0xc15c >> 2),
565 0x00000000,
566 (0x0e00 << 16) | (0xc168 >> 2),
567 0x00000000,
568 (0x0e00 << 16) | (0xc170 >> 2),
569 0x00000000,
570 (0x0e00 << 16) | (0xc204 >> 2),
571 0x00000000,
572 (0x0e00 << 16) | (0xc2b4 >> 2),
573 0x00000000,
574 (0x0e00 << 16) | (0xc2b8 >> 2),
575 0x00000000,
576 (0x0e00 << 16) | (0xc2bc >> 2),
577 0x00000000,
578 (0x0e00 << 16) | (0xc2c0 >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0x8228 >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0x829c >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x869c >> 2),
585 0x00000000,
586 (0x0600 << 16) | (0x98f4 >> 2),
587 0x00000000,
588 (0x0e00 << 16) | (0x98f8 >> 2),
589 0x00000000,
590 (0x0e00 << 16) | (0x9900 >> 2),
591 0x00000000,
592 (0x0e00 << 16) | (0xc260 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0x90e8 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0x3c000 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x3c00c >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x8c1c >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0x9700 >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0xcd20 >> 2),
605 0x00000000,
606 (0x4e00 << 16) | (0xcd20 >> 2),
607 0x00000000,
608 (0x5e00 << 16) | (0xcd20 >> 2),
609 0x00000000,
610 (0x6e00 << 16) | (0xcd20 >> 2),
611 0x00000000,
612 (0x7e00 << 16) | (0xcd20 >> 2),
613 0x00000000,
614 (0x0e00 << 16) | (0x89bc >> 2),
615 0x00000000,
616 (0x0e00 << 16) | (0x8900 >> 2),
617 0x00000000,
618 0x3,
619 (0x0e00 << 16) | (0xc130 >> 2),
620 0x00000000,
621 (0x0e00 << 16) | (0xc134 >> 2),
622 0x00000000,
623 (0x0e00 << 16) | (0xc1fc >> 2),
624 0x00000000,
625 (0x0e00 << 16) | (0xc208 >> 2),
626 0x00000000,
627 (0x0e00 << 16) | (0xc264 >> 2),
628 0x00000000,
629 (0x0e00 << 16) | (0xc268 >> 2),
630 0x00000000,
631 (0x0e00 << 16) | (0xc26c >> 2),
632 0x00000000,
633 (0x0e00 << 16) | (0xc270 >> 2),
634 0x00000000,
635 (0x0e00 << 16) | (0xc274 >> 2),
636 0x00000000,
637 (0x0e00 << 16) | (0xc28c >> 2),
638 0x00000000,
639 (0x0e00 << 16) | (0xc290 >> 2),
640 0x00000000,
641 (0x0e00 << 16) | (0xc294 >> 2),
642 0x00000000,
643 (0x0e00 << 16) | (0xc298 >> 2),
644 0x00000000,
645 (0x0e00 << 16) | (0xc2a0 >> 2),
646 0x00000000,
647 (0x0e00 << 16) | (0xc2a4 >> 2),
648 0x00000000,
649 (0x0e00 << 16) | (0xc2a8 >> 2),
650 0x00000000,
651 (0x0e00 << 16) | (0xc2ac >> 2),
652 0x00000000,
653 (0x0e00 << 16) | (0x301d0 >> 2),
654 0x00000000,
655 (0x0e00 << 16) | (0x30238 >> 2),
656 0x00000000,
657 (0x0e00 << 16) | (0x30250 >> 2),
658 0x00000000,
659 (0x0e00 << 16) | (0x30254 >> 2),
660 0x00000000,
661 (0x0e00 << 16) | (0x30258 >> 2),
662 0x00000000,
663 (0x0e00 << 16) | (0x3025c >> 2),
664 0x00000000,
665 (0x4e00 << 16) | (0xc900 >> 2),
666 0x00000000,
667 (0x5e00 << 16) | (0xc900 >> 2),
668 0x00000000,
669 (0x6e00 << 16) | (0xc900 >> 2),
670 0x00000000,
671 (0x7e00 << 16) | (0xc900 >> 2),
672 0x00000000,
673 (0x4e00 << 16) | (0xc904 >> 2),
674 0x00000000,
675 (0x5e00 << 16) | (0xc904 >> 2),
676 0x00000000,
677 (0x6e00 << 16) | (0xc904 >> 2),
678 0x00000000,
679 (0x7e00 << 16) | (0xc904 >> 2),
680 0x00000000,
681 (0x4e00 << 16) | (0xc908 >> 2),
682 0x00000000,
683 (0x5e00 << 16) | (0xc908 >> 2),
684 0x00000000,
685 (0x6e00 << 16) | (0xc908 >> 2),
686 0x00000000,
687 (0x7e00 << 16) | (0xc908 >> 2),
688 0x00000000,
689 (0x4e00 << 16) | (0xc90c >> 2),
690 0x00000000,
691 (0x5e00 << 16) | (0xc90c >> 2),
692 0x00000000,
693 (0x6e00 << 16) | (0xc90c >> 2),
694 0x00000000,
695 (0x7e00 << 16) | (0xc90c >> 2),
696 0x00000000,
697 (0x4e00 << 16) | (0xc910 >> 2),
698 0x00000000,
699 (0x5e00 << 16) | (0xc910 >> 2),
700 0x00000000,
701 (0x6e00 << 16) | (0xc910 >> 2),
702 0x00000000,
703 (0x7e00 << 16) | (0xc910 >> 2),
704 0x00000000,
705 (0x0e00 << 16) | (0xc99c >> 2),
706 0x00000000,
707 (0x0e00 << 16) | (0x9834 >> 2),
708 0x00000000,
709 (0x0000 << 16) | (0x30f00 >> 2),
710 0x00000000,
711 (0x0000 << 16) | (0x30f04 >> 2),
712 0x00000000,
713 (0x0000 << 16) | (0x30f08 >> 2),
714 0x00000000,
715 (0x0000 << 16) | (0x30f0c >> 2),
716 0x00000000,
717 (0x0600 << 16) | (0x9b7c >> 2),
718 0x00000000,
719 (0x0e00 << 16) | (0x8a14 >> 2),
720 0x00000000,
721 (0x0e00 << 16) | (0x8a18 >> 2),
722 0x00000000,
723 (0x0600 << 16) | (0x30a00 >> 2),
724 0x00000000,
725 (0x0e00 << 16) | (0x8bf0 >> 2),
726 0x00000000,
727 (0x0e00 << 16) | (0x8bcc >> 2),
728 0x00000000,
729 (0x0e00 << 16) | (0x8b24 >> 2),
730 0x00000000,
731 (0x0e00 << 16) | (0x30a04 >> 2),
732 0x00000000,
733 (0x0600 << 16) | (0x30a10 >> 2),
734 0x00000000,
735 (0x0600 << 16) | (0x30a14 >> 2),
736 0x00000000,
737 (0x0600 << 16) | (0x30a18 >> 2),
738 0x00000000,
739 (0x0600 << 16) | (0x30a2c >> 2),
740 0x00000000,
741 (0x0e00 << 16) | (0xc700 >> 2),
742 0x00000000,
743 (0x0e00 << 16) | (0xc704 >> 2),
744 0x00000000,
745 (0x0e00 << 16) | (0xc708 >> 2),
746 0x00000000,
747 (0x0e00 << 16) | (0xc768 >> 2),
748 0x00000000,
749 (0x0400 << 16) | (0xc770 >> 2),
750 0x00000000,
751 (0x0400 << 16) | (0xc774 >> 2),
752 0x00000000,
753 (0x0400 << 16) | (0xc798 >> 2),
754 0x00000000,
755 (0x0400 << 16) | (0xc79c >> 2),
756 0x00000000,
757 (0x0e00 << 16) | (0x9100 >> 2),
758 0x00000000,
759 (0x0e00 << 16) | (0x3c010 >> 2),
760 0x00000000,
761 (0x0e00 << 16) | (0x8c00 >> 2),
762 0x00000000,
763 (0x0e00 << 16) | (0x8c04 >> 2),
764 0x00000000,
765 (0x0e00 << 16) | (0x8c20 >> 2),
766 0x00000000,
767 (0x0e00 << 16) | (0x8c38 >> 2),
768 0x00000000,
769 (0x0e00 << 16) | (0x8c3c >> 2),
770 0x00000000,
771 (0x0e00 << 16) | (0xae00 >> 2),
772 0x00000000,
773 (0x0e00 << 16) | (0x9604 >> 2),
774 0x00000000,
775 (0x0e00 << 16) | (0xac08 >> 2),
776 0x00000000,
777 (0x0e00 << 16) | (0xac0c >> 2),
778 0x00000000,
779 (0x0e00 << 16) | (0xac10 >> 2),
780 0x00000000,
781 (0x0e00 << 16) | (0xac14 >> 2),
782 0x00000000,
783 (0x0e00 << 16) | (0xac58 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xac68 >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0xac6c >> 2),
788 0x00000000,
789 (0x0e00 << 16) | (0xac70 >> 2),
790 0x00000000,
791 (0x0e00 << 16) | (0xac74 >> 2),
792 0x00000000,
793 (0x0e00 << 16) | (0xac78 >> 2),
794 0x00000000,
795 (0x0e00 << 16) | (0xac7c >> 2),
796 0x00000000,
797 (0x0e00 << 16) | (0xac80 >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0xac84 >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0xac88 >> 2),
802 0x00000000,
803 (0x0e00 << 16) | (0xac8c >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0x970c >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0x9714 >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0x9718 >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0x971c >> 2),
812 0x00000000,
813 (0x0e00 << 16) | (0x31068 >> 2),
814 0x00000000,
815 (0x4e00 << 16) | (0x31068 >> 2),
816 0x00000000,
817 (0x5e00 << 16) | (0x31068 >> 2),
818 0x00000000,
819 (0x6e00 << 16) | (0x31068 >> 2),
820 0x00000000,
821 (0x7e00 << 16) | (0x31068 >> 2),
822 0x00000000,
823 (0x0e00 << 16) | (0xcd10 >> 2),
824 0x00000000,
825 (0x0e00 << 16) | (0xcd14 >> 2),
826 0x00000000,
827 (0x0e00 << 16) | (0x88b0 >> 2),
828 0x00000000,
829 (0x0e00 << 16) | (0x88b4 >> 2),
830 0x00000000,
831 (0x0e00 << 16) | (0x88b8 >> 2),
832 0x00000000,
833 (0x0e00 << 16) | (0x88bc >> 2),
834 0x00000000,
835 (0x0400 << 16) | (0x89c0 >> 2),
836 0x00000000,
837 (0x0e00 << 16) | (0x88c4 >> 2),
838 0x00000000,
839 (0x0e00 << 16) | (0x88c8 >> 2),
840 0x00000000,
841 (0x0e00 << 16) | (0x88d0 >> 2),
842 0x00000000,
843 (0x0e00 << 16) | (0x88d4 >> 2),
844 0x00000000,
845 (0x0e00 << 16) | (0x88d8 >> 2),
846 0x00000000,
847 (0x0e00 << 16) | (0x8980 >> 2),
848 0x00000000,
849 (0x0e00 << 16) | (0x30938 >> 2),
850 0x00000000,
851 (0x0e00 << 16) | (0x3093c >> 2),
852 0x00000000,
853 (0x0e00 << 16) | (0x30940 >> 2),
854 0x00000000,
855 (0x0e00 << 16) | (0x89a0 >> 2),
856 0x00000000,
857 (0x0e00 << 16) | (0x30900 >> 2),
858 0x00000000,
859 (0x0e00 << 16) | (0x30904 >> 2),
860 0x00000000,
861 (0x0e00 << 16) | (0x89b4 >> 2),
862 0x00000000,
863 (0x0e00 << 16) | (0x3e1fc >> 2),
864 0x00000000,
865 (0x0e00 << 16) | (0x3c210 >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0x3c214 >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0x3c218 >> 2),
870 0x00000000,
871 (0x0e00 << 16) | (0x8904 >> 2),
872 0x00000000,
873 0x5,
874 (0x0e00 << 16) | (0x8c28 >> 2),
875 (0x0e00 << 16) | (0x8c2c >> 2),
876 (0x0e00 << 16) | (0x8c30 >> 2),
877 (0x0e00 << 16) | (0x8c34 >> 2),
878 (0x0e00 << 16) | (0x9600 >> 2),
879};
880
881static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
882static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
883static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
884static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
885
886/*
887 * Core functions
888 */
889/**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899{
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992}
993
994/**
995 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
996 *
997 * @adev: amdgpu_device pointer
998 *
999 * Starting with SI, the tiling setup is done globally in a
1000 * set of 32 tiling modes. Rather than selecting each set of
1001 * parameters per surface as on older asics, we just select
1002 * which index in the tiling table we want to use, and the
1003 * surface uses those parameters (CIK).
1004 */
1005static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1006{
840a20d3
TSD		 1007 const u32 num_tile_mode_states =
1008 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1009 const u32 num_secondary_tile_mode_states =
1010 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1011 u32 reg_offset, split_equal_to_row_size;
1012 uint32_t *tile, *macrotile;
1013
1014 tile = adev->gfx.config.tile_mode_array;
1015 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1016
1017 switch (adev->gfx.config.mem_row_size_in_kb) {
1018 case 1:
1019 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1020 break;
1021 case 2:
1022 default:
1023 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1024 break;
1025 case 4:
1026 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1027 break;
1028 }
1029
840a20d3
TSD		 1030 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1031 tile[reg_offset] = 0;
1032 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1033 macrotile[reg_offset] = 0;
1034
a2e73f56
AD		 1035 switch (adev->asic_type) {
1036 case CHIP_BONAIRE:
840a20d3
TSD		 1037 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1044 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1045 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1049 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1056 TILE_SPLIT(split_equal_to_row_size));
1057 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1063 TILE_SPLIT(split_equal_to_row_size));
1064 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1065 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1067 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1070 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1078 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1079 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1082 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1086 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1102 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1106 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1110 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1115 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1119 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1130 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1134 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1138 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1139
1140 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1143 NUM_BANKS(ADDR_SURF_16_BANK));
1144 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1147 NUM_BANKS(ADDR_SURF_16_BANK));
1148 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_16_BANK));
1152 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1155 NUM_BANKS(ADDR_SURF_16_BANK));
1156 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163 NUM_BANKS(ADDR_SURF_8_BANK));
1164 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1167 NUM_BANKS(ADDR_SURF_4_BANK));
1168 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1179 NUM_BANKS(ADDR_SURF_16_BANK));
1180 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1183 NUM_BANKS(ADDR_SURF_16_BANK));
1184 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1191 NUM_BANKS(ADDR_SURF_8_BANK));
1192 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1195 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1196
840a20d3
TSD		 1197 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1198 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1199 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1200 if (reg_offset != 7)
1201 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1202 break;
1203 case CHIP_HAWAII:
840a20d3
TSD		 1204 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1212 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1215 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1216 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1220 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223 TILE_SPLIT(split_equal_to_row_size));
1224 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1227 TILE_SPLIT(split_equal_to_row_size));
1228 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1231 TILE_SPLIT(split_equal_to_row_size));
1232 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1235 TILE_SPLIT(split_equal_to_row_size));
1236 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1238 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1241 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1245 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1249 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1253 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1256 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1264 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1269 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1272 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1276 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1279 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1308 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1310 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1314 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1318 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1319 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1322
840a20d3
TSD		 1323 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1326 NUM_BANKS(ADDR_SURF_16_BANK));
1327 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1330 NUM_BANKS(ADDR_SURF_16_BANK));
1331 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334 NUM_BANKS(ADDR_SURF_16_BANK));
1335 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338 NUM_BANKS(ADDR_SURF_16_BANK));
1339 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1342 NUM_BANKS(ADDR_SURF_8_BANK));
1343 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1346 NUM_BANKS(ADDR_SURF_4_BANK));
1347 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_4_BANK));
1351 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358 NUM_BANKS(ADDR_SURF_16_BANK));
1359 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_16_BANK));
1363 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_8_BANK));
1367 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_8_BANK));
1375 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_4_BANK));
1379
1380 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1381 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1382 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1383 if (reg_offset != 7)
1384 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1385 break;
1386 case CHIP_KABINI:
1387 case CHIP_KAVERI:
1388 case CHIP_MULLINS:
1389 default:
840a20d3
TSD		 1390 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391 PIPE_CONFIG(ADDR_SURF_P2) |
1392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P2) |
1396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1398 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1399 PIPE_CONFIG(ADDR_SURF_P2) |
1400 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1402 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1403 PIPE_CONFIG(ADDR_SURF_P2) |
1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1405 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1406 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1409 TILE_SPLIT(split_equal_to_row_size));
1410 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1414 PIPE_CONFIG(ADDR_SURF_P2) |
1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1416 TILE_SPLIT(split_equal_to_row_size));
1417 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1418 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1419 PIPE_CONFIG(ADDR_SURF_P2));
1420 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421 PIPE_CONFIG(ADDR_SURF_P2) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1423 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424 PIPE_CONFIG(ADDR_SURF_P2) |
1425 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1431 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1432 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1433 PIPE_CONFIG(ADDR_SURF_P2) |
1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1435 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1436 PIPE_CONFIG(ADDR_SURF_P2) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1439 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1453 PIPE_CONFIG(ADDR_SURF_P2) |
1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1455 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1459 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1464 PIPE_CONFIG(ADDR_SURF_P2) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1468 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1471 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1473 PIPE_CONFIG(ADDR_SURF_P2) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1477 PIPE_CONFIG(ADDR_SURF_P2) |
1478 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1481 PIPE_CONFIG(ADDR_SURF_P2) |
1482 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1483 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1484 PIPE_CONFIG(ADDR_SURF_P2) |
1485 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1487 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1488 PIPE_CONFIG(ADDR_SURF_P2) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1491 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1492
1493 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1496 NUM_BANKS(ADDR_SURF_8_BANK));
1497 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1500 NUM_BANKS(ADDR_SURF_8_BANK));
1501 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504 NUM_BANKS(ADDR_SURF_8_BANK));
1505 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508 NUM_BANKS(ADDR_SURF_8_BANK));
1509 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524 NUM_BANKS(ADDR_SURF_16_BANK));
1525 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528 NUM_BANKS(ADDR_SURF_16_BANK));
1529 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532 NUM_BANKS(ADDR_SURF_16_BANK));
1533 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1536 NUM_BANKS(ADDR_SURF_16_BANK));
1537 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1548 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1549
840a20d3
TSD		 1550 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1551 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1552 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1553 if (reg_offset != 7)
1554 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1555 break;
1556 }
1557}
1558
1559/**
1560 * gfx_v7_0_select_se_sh - select which SE, SH to address
1561 *
1562 * @adev: amdgpu_device pointer
1563 * @se_num: shader engine to address
1564 * @sh_num: sh block to address
1565 *
1566 * Select which SE, SH combinations to address. Certain
1567 * registers are instanced per SE or SH. 0xffffffff means
1568 * broadcast to all SEs or SHs (CIK).
1569 */
1570void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1571{
1572 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1573
1574 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1575 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1576 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1577 else if (se_num == 0xffffffff)
1578 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1579 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1580 else if (sh_num == 0xffffffff)
1581 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1582 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1583 else
1584 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1585 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1586 WREG32(mmGRBM_GFX_INDEX, data);
1587}
1588
1589/**
1590 * gfx_v7_0_create_bitmask - create a bitmask
1591 *
1592 * @bit_width: length of the mask
1593 *
1594 * create a variable length bit mask (CIK).
1595 * Returns the bitmask.
1596 */
1597static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1598{
8f8e00c1 1599 return (u32)((1ULL << bit_width) - 1);
a2e73f56
AD		 1600}
1601
1602/**
8f8e00c1 1603 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1604 *
1605 * @adev: amdgpu_device pointer
a2e73f56 1606 *
8f8e00c1
AD		 1607 * Calculates the bitmask of enabled RBs (CIK).
1608 * Returns the enabled RB bitmask.
a2e73f56 1609 */
8f8e00c1 1610static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1611{
1612 u32 data, mask;
1613
1614 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1615 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1616
8f8e00c1 1617 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1618 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1619
8f8e00c1
AD		 1620 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1621 adev->gfx.config.max_sh_per_se);
a2e73f56 1622
8f8e00c1 1623 return (~data) & mask;
a2e73f56
AD		 1624}
1625
1626/**
1627 * gfx_v7_0_setup_rb - setup the RBs on the asic
1628 *
1629 * @adev: amdgpu_device pointer
1630 * @se_num: number of SEs (shader engines) for the asic
1631 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1632 *
1633 * Configures per-SE/SH RB registers (CIK).
1634 */
8f8e00c1 1635static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1636{
1637 int i, j;
aac1e3ca 1638 u32 data;
8f8e00c1 1639 u32 active_rbs = 0;
a2e73f56
AD		 1640
1641 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1642 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1643 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
a2e73f56 1644 gfx_v7_0_select_se_sh(adev, i, j);
8f8e00c1 1645 data = gfx_v7_0_get_rb_active_bitmap(adev);
a2e73f56 1646 if (adev->asic_type == CHIP_HAWAII)
8f8e00c1
AD		 1647 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1648 HAWAII_RB_BITMAP_WIDTH_PER_SH);
a2e73f56 1649 else
8f8e00c1
AD		 1650 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1651 CIK_RB_BITMAP_WIDTH_PER_SH);
a2e73f56
AD		 1652 }
1653 }
1654 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1655 mutex_unlock(&adev->grbm_idx_mutex);
1656
8f8e00c1 1657 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 1658 adev->gfx.config.num_rbs = hweight32(active_rbs);
a2e73f56
AD		 1659}
1660
cd06bf68
BG		 1661/**
1662 * gmc_v7_0_init_compute_vmid - gart enable
1663 *
1664 * @rdev: amdgpu_device pointer
1665 *
1666 * Initialize compute vmid sh_mem registers
1667 *
1668 */
1669#define DEFAULT_SH_MEM_BASES (0x6000)
1670#define FIRST_COMPUTE_VMID (8)
1671#define LAST_COMPUTE_VMID (16)
1672static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1673{
1674 int i;
1675 uint32_t sh_mem_config;
1676 uint32_t sh_mem_bases;
1677
1678 /*
1679 * Configure apertures:
1680 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1681 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1682 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1683 */
1684 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1685 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1686 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1687 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1688 mutex_lock(&adev->srbm_mutex);
1689 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1690 cik_srbm_select(adev, 0, 0, 0, i);
1691 /* CP and shaders */
1692 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1693 WREG32(mmSH_MEM_APE1_BASE, 1);
1694 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1695 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1696 }
1697 cik_srbm_select(adev, 0, 0, 0, 0);
1698 mutex_unlock(&adev->srbm_mutex);
1699}
1700
a2e73f56
AD		 1701/**
1702 * gfx_v7_0_gpu_init - setup the 3D engine
1703 *
1704 * @adev: amdgpu_device pointer
1705 *
1706 * Configures the 3D engine and tiling configuration
1707 * registers so that the 3D engine is usable.
1708 */
1709static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1710{
d93f3ca7 1711 u32 tmp, sh_mem_cfg;
a2e73f56
AD		 1712 int i;
1713
a2e73f56
AD		 1714 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1715
d93f3ca7
AD		 1716 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1717 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1718 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1719
1720 gfx_v7_0_tiling_mode_table_init(adev);
1721
8f8e00c1 1722 gfx_v7_0_setup_rb(adev);
a2e73f56
AD		 1723
1724 /* set HW defaults for 3D engine */
1725 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1726 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1727 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1728
1729 mutex_lock(&adev->grbm_idx_mutex);
1730 /*
1731 * making sure that the following register writes will be broadcasted
1732 * to all the shaders
1733 */
1734 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1735
1736 /* XXX SH_MEM regs */
1737 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1738 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165
JX		 1739 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1740
a2e73f56
AD		 1741 mutex_lock(&adev->srbm_mutex);
1742 for (i = 0; i < 16; i++) {
1743 cik_srbm_select(adev, 0, 0, 0, i);
1744 /* CP and shaders */
74a5d165 1745 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1746 WREG32(mmSH_MEM_APE1_BASE, 1);
1747 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1748 WREG32(mmSH_MEM_BASES, 0);
1749 }
1750 cik_srbm_select(adev, 0, 0, 0, 0);
1751 mutex_unlock(&adev->srbm_mutex);
1752
cd06bf68
BG		 1753 gmc_v7_0_init_compute_vmid(adev);
1754
a2e73f56
AD		 1755 WREG32(mmSX_DEBUG_1, 0x20);
1756
1757 WREG32(mmTA_CNTL_AUX, 0x00010000);
1758
1759 tmp = RREG32(mmSPI_CONFIG_CNTL);
1760 tmp |= 0x03000000;
1761 WREG32(mmSPI_CONFIG_CNTL, tmp);
1762
1763 WREG32(mmSQ_CONFIG, 1);
1764
1765 WREG32(mmDB_DEBUG, 0);
1766
1767 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1768 tmp |= 0x00000400;
1769 WREG32(mmDB_DEBUG2, tmp);
1770
1771 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1772 tmp |= 0x00020200;
1773 WREG32(mmDB_DEBUG3, tmp);
1774
1775 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1776 tmp |= 0x00018208;
1777 WREG32(mmCB_HW_CONTROL, tmp);
1778
1779 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1780
1781 WREG32(mmPA_SC_FIFO_SIZE,
1782 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1783 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1784 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1785 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1786
1787 WREG32(mmVGT_NUM_INSTANCES, 1);
1788
1789 WREG32(mmCP_PERFMON_CNTL, 0);
1790
1791 WREG32(mmSQ_CONFIG, 0);
1792
1793 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1794 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1795 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1796
1797 WREG32(mmVGT_CACHE_INVALIDATION,
1798 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1799 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1800
1801 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1802 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1803
1804 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1805 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1806 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1807 mutex_unlock(&adev->grbm_idx_mutex);
1808
1809 udelay(50);
1810}
1811
1812/*
1813 * GPU scratch registers helpers function.
1814 */
1815/**
1816 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1817 *
1818 * @adev: amdgpu_device pointer
1819 *
1820 * Set up the number and offset of the CP scratch registers.
1821 * NOTE: use of CP scratch registers is a legacy inferface and
1822 * is not used by default on newer asics (r6xx+). On newer asics,
1823 * memory buffers are used for fences rather than scratch regs.
1824 */
1825static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1826{
1827 int i;
1828
1829 adev->gfx.scratch.num_reg = 7;
1830 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1831 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1832 adev->gfx.scratch.free[i] = true;
1833 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1834 }
1835}
1836
1837/**
1838 * gfx_v7_0_ring_test_ring - basic gfx ring test
1839 *
1840 * @adev: amdgpu_device pointer
1841 * @ring: amdgpu_ring structure holding ring information
1842 *
1843 * Allocate a scratch register and write to it using the gfx ring (CIK).
1844 * Provides a basic gfx ring test to verify that the ring is working.
1845 * Used by gfx_v7_0_cp_gfx_resume();
1846 * Returns 0 on success, error on failure.
1847 */
1848static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1849{
1850 struct amdgpu_device *adev = ring->adev;
1851 uint32_t scratch;
1852 uint32_t tmp = 0;
1853 unsigned i;
1854 int r;
1855
1856 r = amdgpu_gfx_scratch_get(adev, &scratch);
1857 if (r) {
1858 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1859 return r;
1860 }
1861 WREG32(scratch, 0xCAFEDEAD);
a27de35c 1862 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 1863 if (r) {
1864 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1865 amdgpu_gfx_scratch_free(adev, scratch);
1866 return r;
1867 }
1868 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1869 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1870 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 1871 amdgpu_ring_commit(ring);
a2e73f56
AD		 1872
1873 for (i = 0; i < adev->usec_timeout; i++) {
1874 tmp = RREG32(scratch);
1875 if (tmp == 0xDEADBEEF)
1876 break;
1877 DRM_UDELAY(1);
1878 }
1879 if (i < adev->usec_timeout) {
1880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1881 } else {
1882 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1883 ring->idx, scratch, tmp);
1884 r = -EINVAL;
1885 }
1886 amdgpu_gfx_scratch_free(adev, scratch);
1887 return r;
1888}
1889
1890/**
d2edb07b 1891 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 1892 *
1893 * @adev: amdgpu_device pointer
1894 * @ridx: amdgpu ring index
1895 *
1896 * Emits an hdp flush on the cp.
1897 */
d2edb07b 1898static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 1899{
1900 u32 ref_and_mask;
d9b5327a 1901 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56
AD		 1902
1903 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1904 switch (ring->me) {
1905 case 1:
1906 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1907 break;
1908 case 2:
1909 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1910 break;
1911 default:
1912 return;
1913 }
1914 } else {
1915 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1916 }
1917
1918 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1919 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1920 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 1921 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 1922 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1923 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1924 amdgpu_ring_write(ring, ref_and_mask);
1925 amdgpu_ring_write(ring, ref_and_mask);
1926 amdgpu_ring_write(ring, 0x20); /* poll interval */
1927}
1928
1929/**
1930 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1931 *
1932 * @adev: amdgpu_device pointer
1933 * @fence: amdgpu fence object
1934 *
1935 * Emits a fence sequnce number on the gfx ring and flushes
1936 * GPU caches.
1937 */
1938static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 1939 u64 seq, unsigned flags)
a2e73f56 1940{
890ee23f
CZ		 1941 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1942 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 1943 /* Workaround for cache flush problems. First send a dummy EOP
1944 * event down the pipe with seq one below.
1945 */
1946 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1947 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1948 EOP_TC_ACTION_EN |
1949 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1950 EVENT_INDEX(5)));
1951 amdgpu_ring_write(ring, addr & 0xfffffffc);
1952 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1953 DATA_SEL(1) | INT_SEL(0));
1954 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1955 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1956
1957 /* Then send the real EOP event down the pipe. */
1958 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1959 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1960 EOP_TC_ACTION_EN |
1961 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1962 EVENT_INDEX(5)));
1963 amdgpu_ring_write(ring, addr & 0xfffffffc);
1964 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 1965 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 1966 amdgpu_ring_write(ring, lower_32_bits(seq));
1967 amdgpu_ring_write(ring, upper_32_bits(seq));
1968}
1969
1970/**
1971 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
1972 *
1973 * @adev: amdgpu_device pointer
1974 * @fence: amdgpu fence object
1975 *
1976 * Emits a fence sequnce number on the compute ring and flushes
1977 * GPU caches.
1978 */
1979static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
1980 u64 addr, u64 seq,
890ee23f 1981 unsigned flags)
a2e73f56 1982{
890ee23f
CZ		 1983 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1984 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1985
a2e73f56
AD		 1986 /* RELEASE_MEM - flush caches, send int */
1987 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
1988 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1989 EOP_TC_ACTION_EN |
1990 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1991 EVENT_INDEX(5)));
890ee23f 1992 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 1993 amdgpu_ring_write(ring, addr & 0xfffffffc);
1994 amdgpu_ring_write(ring, upper_32_bits(addr));
1995 amdgpu_ring_write(ring, lower_32_bits(seq));
1996 amdgpu_ring_write(ring, upper_32_bits(seq));
1997}
1998
a2e73f56
AD		 1999/*
2000 * IB stuff
2001 */
2002/**
2003 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2004 *
2005 * @ring: amdgpu_ring structure holding ring information
2006 * @ib: amdgpu indirect buffer object
2007 *
2008 * Emits an DE (drawing engine) or CE (constant engine) IB
2009 * on the gfx ring. IBs are usually generated by userspace
2010 * acceleration drivers and submitted to the kernel for
2011 * sheduling on the ring. This function schedules the IB
2012 * on the gfx ring for execution by the GPU.
2013 */
93323131 2014static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
a2e73f56
AD		 2015 struct amdgpu_ib *ib)
2016{
3cb485f3 2017 bool need_ctx_switch = ring->current_ctx != ib->ctx;
a2e73f56
AD		 2018 u32 header, control = 0;
2019 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 2020
2021 /* drop the CE preamble IB for the same context */
93323131 2022 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
aa2bdb24
JZ		 2023 return;
2024
93323131 2025 if (need_ctx_switch)
a2e73f56
AD		 2026 next_rptr += 2;
2027
2028 next_rptr += 4;
2029 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2030 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2031 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2032 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2033 amdgpu_ring_write(ring, next_rptr);
2034
a2e73f56 2035 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
93323131 2036 if (need_ctx_switch) {
a2e73f56
AD		 2037 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2038 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2039 }
2040
de807f81 2041 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2042 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2043 else
2044 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2045
4ff37a83 2046 control |= ib->length_dw | (ib->vm_id << 24);
a2e73f56
AD		 2047
2048 amdgpu_ring_write(ring, header);
2049 amdgpu_ring_write(ring,
2050#ifdef __BIG_ENDIAN
2051 (2 << 0) |
2052#endif
2053 (ib->gpu_addr & 0xFFFFFFFC));
2054 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2055 amdgpu_ring_write(ring, control);
2056}
2057
93323131 2058static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2059 struct amdgpu_ib *ib)
2060{
2061 u32 header, control = 0;
2062 u32 next_rptr = ring->wptr + 5;
2063
2064 control |= INDIRECT_BUFFER_VALID;
2065 next_rptr += 4;
2066 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2067 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2068 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2069 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2070 amdgpu_ring_write(ring, next_rptr);
2071
2072 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2073
4ff37a83 2074 control |= ib->length_dw | (ib->vm_id << 24);
93323131 2075
2076 amdgpu_ring_write(ring, header);
2077 amdgpu_ring_write(ring,
2078#ifdef __BIG_ENDIAN
2079 (2 << 0) |
2080#endif
2081 (ib->gpu_addr & 0xFFFFFFFC));
2082 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2083 amdgpu_ring_write(ring, control);
2084}
2085
a2e73f56
AD		 2086/**
2087 * gfx_v7_0_ring_test_ib - basic ring IB test
2088 *
2089 * @ring: amdgpu_ring structure holding ring information
2090 *
2091 * Allocate an IB and execute it on the gfx ring (CIK).
2092 * Provides a basic gfx ring test to verify that IBs are working.
2093 * Returns 0 on success, error on failure.
2094 */
2095static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2096{
2097 struct amdgpu_device *adev = ring->adev;
2098 struct amdgpu_ib ib;
1763552e 2099 struct fence *f = NULL;
a2e73f56
AD		 2100 uint32_t scratch;
2101 uint32_t tmp = 0;
2102 unsigned i;
2103 int r;
2104
2105 r = amdgpu_gfx_scratch_get(adev, &scratch);
2106 if (r) {
2107 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2108 return r;
2109 }
2110 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2111 memset(&ib, 0, sizeof(ib));
b07c60c0 2112 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56
AD		 2113 if (r) {
2114 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 2115 goto err1;
a2e73f56
AD		 2116 }
2117 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2118 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2119 ib.ptr[2] = 0xDEADBEEF;
2120 ib.length_dw = 3;
42d13693 2121
e86f9cee
CK		 2122 r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
2123 NULL, &f);
42d13693
CZ		 2124 if (r)
2125 goto err2;
2126
1763552e 2127 r = fence_wait(f, false);
a2e73f56
AD		 2128 if (r) {
2129 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 2130 goto err2;
a2e73f56
AD		 2131 }
2132 for (i = 0; i < adev->usec_timeout; i++) {
2133 tmp = RREG32(scratch);
2134 if (tmp == 0xDEADBEEF)
2135 break;
2136 DRM_UDELAY(1);
2137 }
2138 if (i < adev->usec_timeout) {
2139 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 2140 ring->idx, i);
2141 goto err2;
a2e73f56
AD		 2142 } else {
2143 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2144 scratch, tmp);
2145 r = -EINVAL;
2146 }
42d13693
CZ		 2147
2148err2:
281b4223 2149 fence_put(f);
a2e73f56 2150 amdgpu_ib_free(adev, &ib);
42d13693
CZ		 2151err1:
2152 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2153 return r;
2154}
2155
2156/*
2157 * CP.
2158 * On CIK, gfx and compute now have independant command processors.
2159 *
2160 * GFX
2161 * Gfx consists of a single ring and can process both gfx jobs and
2162 * compute jobs. The gfx CP consists of three microengines (ME):
2163 * PFP - Pre-Fetch Parser
2164 * ME - Micro Engine
2165 * CE - Constant Engine
2166 * The PFP and ME make up what is considered the Drawing Engine (DE).
2167 * The CE is an asynchronous engine used for updating buffer desciptors
2168 * used by the DE so that they can be loaded into cache in parallel
2169 * while the DE is processing state update packets.
2170 *
2171 * Compute
2172 * The compute CP consists of two microengines (ME):
2173 * MEC1 - Compute MicroEngine 1
2174 * MEC2 - Compute MicroEngine 2
2175 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2176 * The queues are exposed to userspace and are programmed directly
2177 * by the compute runtime.
2178 */
2179/**
2180 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2181 *
2182 * @adev: amdgpu_device pointer
2183 * @enable: enable or disable the MEs
2184 *
2185 * Halts or unhalts the gfx MEs.
2186 */
2187static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2188{
2189 int i;
2190
2191 if (enable) {
2192 WREG32(mmCP_ME_CNTL, 0);
2193 } else {
2194 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2195 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2196 adev->gfx.gfx_ring[i].ready = false;
2197 }
2198 udelay(50);
2199}
2200
2201/**
2202 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2203 *
2204 * @adev: amdgpu_device pointer
2205 *
2206 * Loads the gfx PFP, ME, and CE ucode.
2207 * Returns 0 for success, -EINVAL if the ucode is not available.
2208 */
2209static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2210{
2211 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2212 const struct gfx_firmware_header_v1_0 *ce_hdr;
2213 const struct gfx_firmware_header_v1_0 *me_hdr;
2214 const __le32 *fw_data;
2215 unsigned i, fw_size;
2216
2217 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2218 return -EINVAL;
2219
2220 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2221 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2222 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2223
2224 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2225 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2226 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2227 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2228 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2229 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2230 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2231 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2232 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2233
2234 gfx_v7_0_cp_gfx_enable(adev, false);
2235
2236 /* PFP */
2237 fw_data = (const __le32 *)
2238 (adev->gfx.pfp_fw->data +
2239 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2240 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2241 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2242 for (i = 0; i < fw_size; i++)
2243 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2244 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2245
2246 /* CE */
2247 fw_data = (const __le32 *)
2248 (adev->gfx.ce_fw->data +
2249 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2250 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2251 WREG32(mmCP_CE_UCODE_ADDR, 0);
2252 for (i = 0; i < fw_size; i++)
2253 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2254 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2255
2256 /* ME */
2257 fw_data = (const __le32 *)
2258 (adev->gfx.me_fw->data +
2259 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2260 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2261 WREG32(mmCP_ME_RAM_WADDR, 0);
2262 for (i = 0; i < fw_size; i++)
2263 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2264 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2265
2266 return 0;
2267}
2268
2269/**
2270 * gfx_v7_0_cp_gfx_start - start the gfx ring
2271 *
2272 * @adev: amdgpu_device pointer
2273 *
2274 * Enables the ring and loads the clear state context and other
2275 * packets required to init the ring.
2276 * Returns 0 for success, error for failure.
2277 */
2278static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2279{
2280 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2281 const struct cs_section_def *sect = NULL;
2282 const struct cs_extent_def *ext = NULL;
2283 int r, i;
2284
2285 /* init the CP */
2286 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2287 WREG32(mmCP_ENDIAN_SWAP, 0);
2288 WREG32(mmCP_DEVICE_ID, 1);
2289
2290 gfx_v7_0_cp_gfx_enable(adev, true);
2291
a27de35c 2292 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2293 if (r) {
2294 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2295 return r;
2296 }
2297
2298 /* init the CE partitions. CE only used for gfx on CIK */
2299 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2300 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2301 amdgpu_ring_write(ring, 0x8000);
2302 amdgpu_ring_write(ring, 0x8000);
2303
2304 /* clear state buffer */
2305 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2306 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2307
2308 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2309 amdgpu_ring_write(ring, 0x80000000);
2310 amdgpu_ring_write(ring, 0x80000000);
2311
2312 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2313 for (ext = sect->section; ext->extent != NULL; ++ext) {
2314 if (sect->id == SECT_CONTEXT) {
2315 amdgpu_ring_write(ring,
2316 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2317 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2318 for (i = 0; i < ext->reg_count; i++)
2319 amdgpu_ring_write(ring, ext->extent[i]);
2320 }
2321 }
2322 }
2323
2324 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2325 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2326 switch (adev->asic_type) {
2327 case CHIP_BONAIRE:
2328 amdgpu_ring_write(ring, 0x16000012);
2329 amdgpu_ring_write(ring, 0x00000000);
2330 break;
2331 case CHIP_KAVERI:
2332 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2333 amdgpu_ring_write(ring, 0x00000000);
2334 break;
2335 case CHIP_KABINI:
2336 case CHIP_MULLINS:
2337 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2338 amdgpu_ring_write(ring, 0x00000000);
2339 break;
2340 case CHIP_HAWAII:
2341 amdgpu_ring_write(ring, 0x3a00161a);
2342 amdgpu_ring_write(ring, 0x0000002e);
2343 break;
2344 default:
2345 amdgpu_ring_write(ring, 0x00000000);
2346 amdgpu_ring_write(ring, 0x00000000);
2347 break;
2348 }
2349
2350 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2351 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2352
2353 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2354 amdgpu_ring_write(ring, 0);
2355
2356 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2357 amdgpu_ring_write(ring, 0x00000316);
2358 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2359 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2360
a27de35c 2361 amdgpu_ring_commit(ring);
a2e73f56
AD		 2362
2363 return 0;
2364}
2365
2366/**
2367 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2368 *
2369 * @adev: amdgpu_device pointer
2370 *
2371 * Program the location and size of the gfx ring buffer
2372 * and test it to make sure it's working.
2373 * Returns 0 for success, error for failure.
2374 */
2375static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2376{
2377 struct amdgpu_ring *ring;
2378 u32 tmp;
2379 u32 rb_bufsz;
2380 u64 rb_addr, rptr_addr;
2381 int r;
2382
2383 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2384 if (adev->asic_type != CHIP_HAWAII)
2385 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2386
2387 /* Set the write pointer delay */
2388 WREG32(mmCP_RB_WPTR_DELAY, 0);
2389
2390 /* set the RB to use vmid 0 */
2391 WREG32(mmCP_RB_VMID, 0);
2392
2393 WREG32(mmSCRATCH_ADDR, 0);
2394
2395 /* ring 0 - compute and gfx */
2396 /* Set ring buffer size */
2397 ring = &adev->gfx.gfx_ring[0];
2398 rb_bufsz = order_base_2(ring->ring_size / 8);
2399 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2400#ifdef __BIG_ENDIAN
454fc95e 2401 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2402#endif
2403 WREG32(mmCP_RB0_CNTL, tmp);
2404
2405 /* Initialize the ring buffer's read and write pointers */
2406 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2407 ring->wptr = 0;
2408 WREG32(mmCP_RB0_WPTR, ring->wptr);
2409
2410 /* set the wb address wether it's enabled or not */
2411 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2412 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2413 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2414
2415 /* scratch register shadowing is no longer supported */
2416 WREG32(mmSCRATCH_UMSK, 0);
2417
2418 mdelay(1);
2419 WREG32(mmCP_RB0_CNTL, tmp);
2420
2421 rb_addr = ring->gpu_addr >> 8;
2422 WREG32(mmCP_RB0_BASE, rb_addr);
2423 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2424
2425 /* start the ring */
2426 gfx_v7_0_cp_gfx_start(adev);
2427 ring->ready = true;
2428 r = amdgpu_ring_test_ring(ring);
2429 if (r) {
2430 ring->ready = false;
2431 return r;
2432 }
2433
2434 return 0;
2435}
2436
2437static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2438{
7edd6b2f 2439 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2440}
2441
2442static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2443{
2444 struct amdgpu_device *adev = ring->adev;
a2e73f56 2445
7edd6b2f 2446 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2447}
2448
2449static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2450{
2451 struct amdgpu_device *adev = ring->adev;
2452
2453 WREG32(mmCP_RB0_WPTR, ring->wptr);
2454 (void)RREG32(mmCP_RB0_WPTR);
2455}
2456
2457static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2458{
7edd6b2f 2459 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2460}
2461
2462static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2463{
a2e73f56 2464 /* XXX check if swapping is necessary on BE */
7edd6b2f 2465 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2466}
2467
2468static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2469{
2470 struct amdgpu_device *adev = ring->adev;
2471
2472 /* XXX check if swapping is necessary on BE */
2473 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2474 WDOORBELL32(ring->doorbell_index, ring->wptr);
2475}
2476
2477/**
2478 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2479 *
2480 * @adev: amdgpu_device pointer
2481 * @enable: enable or disable the MEs
2482 *
2483 * Halts or unhalts the compute MEs.
2484 */
2485static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2486{
2487 int i;
2488
2489 if (enable) {
2490 WREG32(mmCP_MEC_CNTL, 0);
2491 } else {
2492 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2493 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2494 adev->gfx.compute_ring[i].ready = false;
2495 }
2496 udelay(50);
2497}
2498
2499/**
2500 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2501 *
2502 * @adev: amdgpu_device pointer
2503 *
2504 * Loads the compute MEC1&2 ucode.
2505 * Returns 0 for success, -EINVAL if the ucode is not available.
2506 */
2507static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2508{
2509 const struct gfx_firmware_header_v1_0 *mec_hdr;
2510 const __le32 *fw_data;
2511 unsigned i, fw_size;
2512
2513 if (!adev->gfx.mec_fw)
2514 return -EINVAL;
2515
2516 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2517 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2518 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2519 adev->gfx.mec_feature_version = le32_to_cpu(
2520 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2521
2522 gfx_v7_0_cp_compute_enable(adev, false);
2523
2524 /* MEC1 */
2525 fw_data = (const __le32 *)
2526 (adev->gfx.mec_fw->data +
2527 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2528 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2529 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2530 for (i = 0; i < fw_size; i++)
2531 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2532 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2533
2534 if (adev->asic_type == CHIP_KAVERI) {
2535 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2536
2537 if (!adev->gfx.mec2_fw)
2538 return -EINVAL;
2539
2540 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2541 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2542 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2543 adev->gfx.mec2_feature_version = le32_to_cpu(
2544 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2545
2546 /* MEC2 */
2547 fw_data = (const __le32 *)
2548 (adev->gfx.mec2_fw->data +
2549 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2550 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2551 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2552 for (i = 0; i < fw_size; i++)
2553 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2554 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2555 }
2556
2557 return 0;
2558}
2559
a2e73f56
AD		 2560/**
2561 * gfx_v7_0_cp_compute_fini - stop the compute queues
2562 *
2563 * @adev: amdgpu_device pointer
2564 *
2565 * Stop the compute queues and tear down the driver queue
2566 * info.
2567 */
2568static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2569{
2570 int i, r;
2571
2572 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2573 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2574
2575 if (ring->mqd_obj) {
2576 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2577 if (unlikely(r != 0))
2578 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2579
2580 amdgpu_bo_unpin(ring->mqd_obj);
2581 amdgpu_bo_unreserve(ring->mqd_obj);
2582
2583 amdgpu_bo_unref(&ring->mqd_obj);
2584 ring->mqd_obj = NULL;
2585 }
2586 }
2587}
2588
2589static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2590{
2591 int r;
2592
2593 if (adev->gfx.mec.hpd_eop_obj) {
2594 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2595 if (unlikely(r != 0))
2596 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2597 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2598 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2599
2600 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2601 adev->gfx.mec.hpd_eop_obj = NULL;
2602 }
2603}
2604
2605#define MEC_HPD_SIZE 2048
2606
2607static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2608{
2609 int r;
2610 u32 *hpd;
2611
2612 /*
2613 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2614 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2615 * Nonetheless, we assign only 1 pipe because all other pipes will
2616 * be handled by KFD
2617 */
2618 adev->gfx.mec.num_mec = 1;
2619 adev->gfx.mec.num_pipe = 1;
2620 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2621
2622 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2623 r = amdgpu_bo_create(adev,
2624 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2625 PAGE_SIZE, true,
72d7668b 2626 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2627 &adev->gfx.mec.hpd_eop_obj);
2628 if (r) {
2629 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2630 return r;
2631 }
2632 }
2633
2634 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2635 if (unlikely(r != 0)) {
2636 gfx_v7_0_mec_fini(adev);
2637 return r;
2638 }
2639 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2640 &adev->gfx.mec.hpd_eop_gpu_addr);
2641 if (r) {
2642 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2643 gfx_v7_0_mec_fini(adev);
2644 return r;
2645 }
2646 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2647 if (r) {
2648 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2649 gfx_v7_0_mec_fini(adev);
2650 return r;
2651 }
2652
2653 /* clear memory. Not sure if this is required or not */
2654 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2655
2656 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2657 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2658
2659 return 0;
2660}
2661
2662struct hqd_registers
2663{
2664 u32 cp_mqd_base_addr;
2665 u32 cp_mqd_base_addr_hi;
2666 u32 cp_hqd_active;
2667 u32 cp_hqd_vmid;
2668 u32 cp_hqd_persistent_state;
2669 u32 cp_hqd_pipe_priority;
2670 u32 cp_hqd_queue_priority;
2671 u32 cp_hqd_quantum;
2672 u32 cp_hqd_pq_base;
2673 u32 cp_hqd_pq_base_hi;
2674 u32 cp_hqd_pq_rptr;
2675 u32 cp_hqd_pq_rptr_report_addr;
2676 u32 cp_hqd_pq_rptr_report_addr_hi;
2677 u32 cp_hqd_pq_wptr_poll_addr;
2678 u32 cp_hqd_pq_wptr_poll_addr_hi;
2679 u32 cp_hqd_pq_doorbell_control;
2680 u32 cp_hqd_pq_wptr;
2681 u32 cp_hqd_pq_control;
2682 u32 cp_hqd_ib_base_addr;
2683 u32 cp_hqd_ib_base_addr_hi;
2684 u32 cp_hqd_ib_rptr;
2685 u32 cp_hqd_ib_control;
2686 u32 cp_hqd_iq_timer;
2687 u32 cp_hqd_iq_rptr;
2688 u32 cp_hqd_dequeue_request;
2689 u32 cp_hqd_dma_offload;
2690 u32 cp_hqd_sema_cmd;
2691 u32 cp_hqd_msg_type;
2692 u32 cp_hqd_atomic0_preop_lo;
2693 u32 cp_hqd_atomic0_preop_hi;
2694 u32 cp_hqd_atomic1_preop_lo;
2695 u32 cp_hqd_atomic1_preop_hi;
2696 u32 cp_hqd_hq_scheduler0;
2697 u32 cp_hqd_hq_scheduler1;
2698 u32 cp_mqd_control;
2699};
2700
2701struct bonaire_mqd
2702{
2703 u32 header;
2704 u32 dispatch_initiator;
2705 u32 dimensions[3];
2706 u32 start_idx[3];
2707 u32 num_threads[3];
2708 u32 pipeline_stat_enable;
2709 u32 perf_counter_enable;
2710 u32 pgm[2];
2711 u32 tba[2];
2712 u32 tma[2];
2713 u32 pgm_rsrc[2];
2714 u32 vmid;
2715 u32 resource_limits;
2716 u32 static_thread_mgmt01[2];
2717 u32 tmp_ring_size;
2718 u32 static_thread_mgmt23[2];
2719 u32 restart[3];
2720 u32 thread_trace_enable;
2721 u32 reserved1;
2722 u32 user_data[16];
2723 u32 vgtcs_invoke_count[2];
2724 struct hqd_registers queue_state;
2725 u32 dequeue_cntr;
2726 u32 interrupt_queue[64];
2727};
2728
2729/**
2730 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2731 *
2732 * @adev: amdgpu_device pointer
2733 *
2734 * Program the compute queues and test them to make sure they
2735 * are working.
2736 * Returns 0 for success, error for failure.
2737 */
2738static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2739{
2740 int r, i, j;
2741 u32 tmp;
2742 bool use_doorbell = true;
2743 u64 hqd_gpu_addr;
2744 u64 mqd_gpu_addr;
2745 u64 eop_gpu_addr;
2746 u64 wb_gpu_addr;
2747 u32 *buf;
2748 struct bonaire_mqd *mqd;
2749
6e9821b2 2750 gfx_v7_0_cp_compute_enable(adev, true);
a2e73f56
AD		 2751
2752 /* fix up chicken bits */
2753 tmp = RREG32(mmCP_CPF_DEBUG);
2754 tmp |= (1 << 23);
2755 WREG32(mmCP_CPF_DEBUG, tmp);
2756
2757 /* init the pipes */
2758 mutex_lock(&adev->srbm_mutex);
2759 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2760 int me = (i < 4) ? 1 : 2;
2761 int pipe = (i < 4) ? i : (i - 4);
2762
2763 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2764
2765 cik_srbm_select(adev, me, pipe, 0, 0);
2766
2767 /* write the EOP addr */
2768 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2769 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2770
2771 /* set the VMID assigned */
2772 WREG32(mmCP_HPD_EOP_VMID, 0);
2773
2774 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2775 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2776 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2777 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2778 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2779 }
2780 cik_srbm_select(adev, 0, 0, 0, 0);
2781 mutex_unlock(&adev->srbm_mutex);
2782
2783 /* init the queues. Just two for now. */
2784 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2785 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2786
2787 if (ring->mqd_obj == NULL) {
2788 r = amdgpu_bo_create(adev,
2789 sizeof(struct bonaire_mqd),
2790 PAGE_SIZE, true,
72d7668b 2791 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2792 &ring->mqd_obj);
2793 if (r) {
2794 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2795 return r;
2796 }
2797 }
2798
2799 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2800 if (unlikely(r != 0)) {
2801 gfx_v7_0_cp_compute_fini(adev);
2802 return r;
2803 }
2804 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2805 &mqd_gpu_addr);
2806 if (r) {
2807 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2808 gfx_v7_0_cp_compute_fini(adev);
2809 return r;
2810 }
2811 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2812 if (r) {
2813 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2814 gfx_v7_0_cp_compute_fini(adev);
2815 return r;
2816 }
2817
2818 /* init the mqd struct */
2819 memset(buf, 0, sizeof(struct bonaire_mqd));
2820
2821 mqd = (struct bonaire_mqd *)buf;
2822 mqd->header = 0xC0310800;
2823 mqd->static_thread_mgmt01[0] = 0xffffffff;
2824 mqd->static_thread_mgmt01[1] = 0xffffffff;
2825 mqd->static_thread_mgmt23[0] = 0xffffffff;
2826 mqd->static_thread_mgmt23[1] = 0xffffffff;
2827
2828 mutex_lock(&adev->srbm_mutex);
2829 cik_srbm_select(adev, ring->me,
2830 ring->pipe,
2831 ring->queue, 0);
2832
2833 /* disable wptr polling */
2834 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2835 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2836 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2837
2838 /* enable doorbell? */
2839 mqd->queue_state.cp_hqd_pq_doorbell_control =
2840 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2841 if (use_doorbell)
2842 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2843 else
2844 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2845 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2846 mqd->queue_state.cp_hqd_pq_doorbell_control);
2847
2848 /* disable the queue if it's active */
2849 mqd->queue_state.cp_hqd_dequeue_request = 0;
2850 mqd->queue_state.cp_hqd_pq_rptr = 0;
2851 mqd->queue_state.cp_hqd_pq_wptr= 0;
2852 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2853 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2854 for (j = 0; j < adev->usec_timeout; j++) {
2855 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2856 break;
2857 udelay(1);
2858 }
2859 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2860 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2861 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2862 }
2863
2864 /* set the pointer to the MQD */
2865 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2866 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2867 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2868 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2869 /* set MQD vmid to 0 */
2870 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2871 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2872 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2873
2874 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2875 hqd_gpu_addr = ring->gpu_addr >> 8;
2876 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2877 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2878 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2879 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2880
2881 /* set up the HQD, this is similar to CP_RB0_CNTL */
2882 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2883 mqd->queue_state.cp_hqd_pq_control &=
2884 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2885 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2886
2887 mqd->queue_state.cp_hqd_pq_control |=
2888 order_base_2(ring->ring_size / 8);
2889 mqd->queue_state.cp_hqd_pq_control |=
2890 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2891#ifdef __BIG_ENDIAN
454fc95e
AD		 2892 mqd->queue_state.cp_hqd_pq_control |=
2893 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 2894#endif
2895 mqd->queue_state.cp_hqd_pq_control &=
2896 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2897 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2898 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2899 mqd->queue_state.cp_hqd_pq_control |=
2900 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2901 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2902 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2903
2904 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2905 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2906 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2907 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2908 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2909 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2910 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2911
2912 /* set the wb address wether it's enabled or not */
2913 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2914 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2915 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2916 upper_32_bits(wb_gpu_addr) & 0xffff;
2917 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2918 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2919 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2920 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2921
2922 /* enable the doorbell if requested */
2923 if (use_doorbell) {
2924 mqd->queue_state.cp_hqd_pq_doorbell_control =
2925 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2926 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2927 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2928 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2929 (ring->doorbell_index <<
2930 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2931 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2932 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2933 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2934 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2935 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2936
2937 } else {
2938 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2939 }
2940 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2941 mqd->queue_state.cp_hqd_pq_doorbell_control);
2942
2943 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2944 ring->wptr = 0;
2945 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2946 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2947 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2948
2949 /* set the vmid for the queue */
2950 mqd->queue_state.cp_hqd_vmid = 0;
2951 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2952
2953 /* activate the queue */
2954 mqd->queue_state.cp_hqd_active = 1;
2955 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2956
2957 cik_srbm_select(adev, 0, 0, 0, 0);
2958 mutex_unlock(&adev->srbm_mutex);
2959
2960 amdgpu_bo_kunmap(ring->mqd_obj);
2961 amdgpu_bo_unreserve(ring->mqd_obj);
2962
2963 ring->ready = true;
2964 r = amdgpu_ring_test_ring(ring);
2965 if (r)
2966 ring->ready = false;
2967 }
2968
2969 return 0;
2970}
2971
2972static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
2973{
2974 gfx_v7_0_cp_gfx_enable(adev, enable);
2975 gfx_v7_0_cp_compute_enable(adev, enable);
2976}
2977
2978static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
2979{
2980 int r;
2981
2982 r = gfx_v7_0_cp_gfx_load_microcode(adev);
2983 if (r)
2984 return r;
2985 r = gfx_v7_0_cp_compute_load_microcode(adev);
2986 if (r)
2987 return r;
2988
2989 return 0;
2990}
2991
2992static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2993 bool enable)
2994{
2995 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2996
2997 if (enable)
2998 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
2999 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3000 else
3001 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3002 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3003 WREG32(mmCP_INT_CNTL_RING0, tmp);
3004}
3005
3006static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3007{
3008 int r;
3009
3010 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3011
3012 r = gfx_v7_0_cp_load_microcode(adev);
3013 if (r)
3014 return r;
3015
3016 r = gfx_v7_0_cp_gfx_resume(adev);
3017 if (r)
3018 return r;
3019 r = gfx_v7_0_cp_compute_resume(adev);
3020 if (r)
3021 return r;
3022
3023 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3024
3025 return 0;
3026}
3027
a2e73f56
AD		 3028/*
3029 * vm
3030 * VMID 0 is the physical GPU addresses as used by the kernel.
3031 * VMIDs 1-15 are used for userspace clients and are handled
3032 * by the amdgpu vm/hsa code.
3033 */
3034/**
3035 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3036 *
3037 * @adev: amdgpu_device pointer
3038 *
3039 * Update the page table base and flush the VM TLB
3040 * using the CP (CIK).
3041 */
3042static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3043 unsigned vm_id, uint64_t pd_addr)
3044{
3045 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 3046 if (usepfp) {
3047 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3048 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3049 amdgpu_ring_write(ring, 0);
3050 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3051 amdgpu_ring_write(ring, 0);
3052 }
a2e73f56
AD		 3053
3054 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3055 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3056 WRITE_DATA_DST_SEL(0)));
3057 if (vm_id < 8) {
3058 amdgpu_ring_write(ring,
3059 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3060 } else {
3061 amdgpu_ring_write(ring,
3062 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3063 }
3064 amdgpu_ring_write(ring, 0);
3065 amdgpu_ring_write(ring, pd_addr >> 12);
3066
a2e73f56
AD		 3067 /* bits 0-15 are the VM contexts0-15 */
3068 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3069 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3070 WRITE_DATA_DST_SEL(0)));
3071 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3072 amdgpu_ring_write(ring, 0);
3073 amdgpu_ring_write(ring, 1 << vm_id);
3074
3075 /* wait for the invalidate to complete */
3076 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3077 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3078 WAIT_REG_MEM_FUNCTION(0) | /* always */
3079 WAIT_REG_MEM_ENGINE(0))); /* me */
3080 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3081 amdgpu_ring_write(ring, 0);
3082 amdgpu_ring_write(ring, 0); /* ref */
3083 amdgpu_ring_write(ring, 0); /* mask */
3084 amdgpu_ring_write(ring, 0x20); /* poll interval */
3085
3086 /* compute doesn't have PFP */
3087 if (usepfp) {
3088 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3089 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3090 amdgpu_ring_write(ring, 0x0);
3091
3092 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3093 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3094 amdgpu_ring_write(ring, 0);
3095 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3096 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3097 }
3098}
3099
3100/*
3101 * RLC
3102 * The RLC is a multi-purpose microengine that handles a
3103 * variety of functions.
3104 */
3105static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3106{
3107 int r;
3108
3109 /* save restore block */
3110 if (adev->gfx.rlc.save_restore_obj) {
3111 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3112 if (unlikely(r != 0))
3113 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3114 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3115 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3116
3117 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3118 adev->gfx.rlc.save_restore_obj = NULL;
3119 }
3120
3121 /* clear state block */
3122 if (adev->gfx.rlc.clear_state_obj) {
3123 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3124 if (unlikely(r != 0))
3125 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3126 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3127 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3128
3129 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3130 adev->gfx.rlc.clear_state_obj = NULL;
3131 }
3132
3133 /* clear state block */
3134 if (adev->gfx.rlc.cp_table_obj) {
3135 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3136 if (unlikely(r != 0))
3137 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3138 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3139 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3140
3141 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3142 adev->gfx.rlc.cp_table_obj = NULL;
3143 }
3144}
3145
3146static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3147{
3148 const u32 *src_ptr;
3149 volatile u32 *dst_ptr;
3150 u32 dws, i;
3151 const struct cs_section_def *cs_data;
3152 int r;
3153
3154 /* allocate rlc buffers */
2f7d10b3 3155 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3156 if (adev->asic_type == CHIP_KAVERI) {
3157 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3158 adev->gfx.rlc.reg_list_size =
3159 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3160 } else {
3161 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3162 adev->gfx.rlc.reg_list_size =
3163 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3164 }
3165 }
3166 adev->gfx.rlc.cs_data = ci_cs_data;
3167 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3168
3169 src_ptr = adev->gfx.rlc.reg_list;
3170 dws = adev->gfx.rlc.reg_list_size;
3171 dws += (5 * 16) + 48 + 48 + 64;
3172
3173 cs_data = adev->gfx.rlc.cs_data;
3174
3175 if (src_ptr) {
3176 /* save restore block */
3177 if (adev->gfx.rlc.save_restore_obj == NULL) {
3178 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3179 AMDGPU_GEM_DOMAIN_VRAM,
3180 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3181 NULL, NULL,
3182 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3183 if (r) {
3184 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3185 return r;
3186 }
3187 }
3188
3189 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3190 if (unlikely(r != 0)) {
3191 gfx_v7_0_rlc_fini(adev);
3192 return r;
3193 }
3194 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3195 &adev->gfx.rlc.save_restore_gpu_addr);
3196 if (r) {
3197 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3198 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3199 gfx_v7_0_rlc_fini(adev);
3200 return r;
3201 }
3202
3203 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3204 if (r) {
3205 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3206 gfx_v7_0_rlc_fini(adev);
3207 return r;
3208 }
3209 /* write the sr buffer */
3210 dst_ptr = adev->gfx.rlc.sr_ptr;
3211 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3212 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3213 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3214 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3215 }
3216
3217 if (cs_data) {
3218 /* clear state block */
3219 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3220
3221 if (adev->gfx.rlc.clear_state_obj == NULL) {
3222 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3223 AMDGPU_GEM_DOMAIN_VRAM,
3224 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3225 NULL, NULL,
3226 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3227 if (r) {
3228 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3229 gfx_v7_0_rlc_fini(adev);
3230 return r;
3231 }
3232 }
3233 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3234 if (unlikely(r != 0)) {
3235 gfx_v7_0_rlc_fini(adev);
3236 return r;
3237 }
3238 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3239 &adev->gfx.rlc.clear_state_gpu_addr);
3240 if (r) {
3241 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3242 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3243 gfx_v7_0_rlc_fini(adev);
3244 return r;
3245 }
3246
3247 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3248 if (r) {
3249 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3250 gfx_v7_0_rlc_fini(adev);
3251 return r;
3252 }
3253 /* set up the cs buffer */
3254 dst_ptr = adev->gfx.rlc.cs_ptr;
3255 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3256 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3257 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3258 }
3259
3260 if (adev->gfx.rlc.cp_table_size) {
3261 if (adev->gfx.rlc.cp_table_obj == NULL) {
3262 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d
AD		 3263 AMDGPU_GEM_DOMAIN_VRAM,
3264 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3265 NULL, NULL,
3266 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3267 if (r) {
3268 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3269 gfx_v7_0_rlc_fini(adev);
3270 return r;
3271 }
3272 }
3273
3274 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3275 if (unlikely(r != 0)) {
3276 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3277 gfx_v7_0_rlc_fini(adev);
3278 return r;
3279 }
3280 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3281 &adev->gfx.rlc.cp_table_gpu_addr);
3282 if (r) {
3283 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3284 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3285 gfx_v7_0_rlc_fini(adev);
3286 return r;
3287 }
3288 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3289 if (r) {
3290 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3291 gfx_v7_0_rlc_fini(adev);
3292 return r;
3293 }
3294
3295 gfx_v7_0_init_cp_pg_table(adev);
3296
3297 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3298 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3299
3300 }
3301
3302 return 0;
3303}
3304
3305static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3306{
3307 u32 tmp;
3308
3309 tmp = RREG32(mmRLC_LB_CNTL);
3310 if (enable)
3311 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3312 else
3313 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3314 WREG32(mmRLC_LB_CNTL, tmp);
3315}
3316
3317static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3318{
3319 u32 i, j, k;
3320 u32 mask;
3321
3322 mutex_lock(&adev->grbm_idx_mutex);
3323 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3324 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3325 gfx_v7_0_select_se_sh(adev, i, j);
3326 for (k = 0; k < adev->usec_timeout; k++) {
3327 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3328 break;
3329 udelay(1);
3330 }
3331 }
3332 }
3333 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3334 mutex_unlock(&adev->grbm_idx_mutex);
3335
3336 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3337 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3338 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3339 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3340 for (k = 0; k < adev->usec_timeout; k++) {
3341 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3342 break;
3343 udelay(1);
3344 }
3345}
3346
3347static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3348{
3349 u32 tmp;
3350
3351 tmp = RREG32(mmRLC_CNTL);
3352 if (tmp != rlc)
3353 WREG32(mmRLC_CNTL, rlc);
3354}
3355
3356static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3357{
3358 u32 data, orig;
3359
3360 orig = data = RREG32(mmRLC_CNTL);
3361
3362 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3363 u32 i;
3364
3365 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3366 WREG32(mmRLC_CNTL, data);
3367
3368 for (i = 0; i < adev->usec_timeout; i++) {
3369 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3370 break;
3371 udelay(1);
3372 }
3373
3374 gfx_v7_0_wait_for_rlc_serdes(adev);
3375 }
3376
3377 return orig;
3378}
3379
3380void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3381{
3382 u32 tmp, i, mask;
3383
3384 tmp = 0x1 | (1 << 1);
3385 WREG32(mmRLC_GPR_REG2, tmp);
3386
3387 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3388 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3389 for (i = 0; i < adev->usec_timeout; i++) {
3390 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3391 break;
3392 udelay(1);
3393 }
3394
3395 for (i = 0; i < adev->usec_timeout; i++) {
3396 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3397 break;
3398 udelay(1);
3399 }
3400}
3401
3402void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3403{
3404 u32 tmp;
3405
3406 tmp = 0x1 | (0 << 1);
3407 WREG32(mmRLC_GPR_REG2, tmp);
3408}
3409
3410/**
3411 * gfx_v7_0_rlc_stop - stop the RLC ME
3412 *
3413 * @adev: amdgpu_device pointer
3414 *
3415 * Halt the RLC ME (MicroEngine) (CIK).
3416 */
3417void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3418{
3419 WREG32(mmRLC_CNTL, 0);
3420
3421 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3422
3423 gfx_v7_0_wait_for_rlc_serdes(adev);
3424}
3425
3426/**
3427 * gfx_v7_0_rlc_start - start the RLC ME
3428 *
3429 * @adev: amdgpu_device pointer
3430 *
3431 * Unhalt the RLC ME (MicroEngine) (CIK).
3432 */
3433static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3434{
3435 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3436
3437 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3438
3439 udelay(50);
3440}
3441
3442static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3443{
3444 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3445
3446 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3447 WREG32(mmGRBM_SOFT_RESET, tmp);
3448 udelay(50);
3449 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3450 WREG32(mmGRBM_SOFT_RESET, tmp);
3451 udelay(50);
3452}
3453
3454/**
3455 * gfx_v7_0_rlc_resume - setup the RLC hw
3456 *
3457 * @adev: amdgpu_device pointer
3458 *
3459 * Initialize the RLC registers, load the ucode,
3460 * and start the RLC (CIK).
3461 * Returns 0 for success, -EINVAL if the ucode is not available.
3462 */
3463static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3464{
3465 const struct rlc_firmware_header_v1_0 *hdr;
3466 const __le32 *fw_data;
3467 unsigned i, fw_size;
3468 u32 tmp;
3469
3470 if (!adev->gfx.rlc_fw)
3471 return -EINVAL;
3472
3473 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3474 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3475 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3476 adev->gfx.rlc_feature_version = le32_to_cpu(
3477 hdr->ucode_feature_version);
a2e73f56
AD		 3478
3479 gfx_v7_0_rlc_stop(adev);
3480
3481 /* disable CG */
3482 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3483 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3484
3485 gfx_v7_0_rlc_reset(adev);
3486
3487 gfx_v7_0_init_pg(adev);
3488
3489 WREG32(mmRLC_LB_CNTR_INIT, 0);
3490 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3491
3492 mutex_lock(&adev->grbm_idx_mutex);
3493 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3494 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3495 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3496 WREG32(mmRLC_LB_CNTL, 0x80000004);
3497 mutex_unlock(&adev->grbm_idx_mutex);
3498
3499 WREG32(mmRLC_MC_CNTL, 0);
3500 WREG32(mmRLC_UCODE_CNTL, 0);
3501
3502 fw_data = (const __le32 *)
3503 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3504 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3505 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3506 for (i = 0; i < fw_size; i++)
3507 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3508 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3509
3510 /* XXX - find out what chips support lbpw */
3511 gfx_v7_0_enable_lbpw(adev, false);
3512
3513 if (adev->asic_type == CHIP_BONAIRE)
3514 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3515
3516 gfx_v7_0_rlc_start(adev);
3517
3518 return 0;
3519}
3520
3521static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3522{
3523 u32 data, orig, tmp, tmp2;
3524
3525 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3526
3527 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
3528 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3529
3530 tmp = gfx_v7_0_halt_rlc(adev);
3531
3532 mutex_lock(&adev->grbm_idx_mutex);
3533 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3534 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3535 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3536 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3537 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3538 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3539 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3540 mutex_unlock(&adev->grbm_idx_mutex);
3541
3542 gfx_v7_0_update_rlc(adev, tmp);
3543
3544 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3545 } else {
3546 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3547
3548 RREG32(mmCB_CGTT_SCLK_CTRL);
3549 RREG32(mmCB_CGTT_SCLK_CTRL);
3550 RREG32(mmCB_CGTT_SCLK_CTRL);
3551 RREG32(mmCB_CGTT_SCLK_CTRL);
3552
3553 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3554 }
3555
3556 if (orig != data)
3557 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3558
3559}
3560
3561static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3562{
3563 u32 data, orig, tmp = 0;
3564
3565 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
3566 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
3567 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
3568 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3569 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3570 if (orig != data)
3571 WREG32(mmCP_MEM_SLP_CNTL, data);
3572 }
3573 }
3574
3575 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3576 data |= 0x00000001;
3577 data &= 0xfffffffd;
3578 if (orig != data)
3579 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3580
3581 tmp = gfx_v7_0_halt_rlc(adev);
3582
3583 mutex_lock(&adev->grbm_idx_mutex);
3584 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3585 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3586 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3587 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3588 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3589 WREG32(mmRLC_SERDES_WR_CTRL, data);
3590 mutex_unlock(&adev->grbm_idx_mutex);
3591
3592 gfx_v7_0_update_rlc(adev, tmp);
3593
3594 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
3595 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3596 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3597 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3598 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3599 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3600 if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
3601 (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
3602 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3603 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3604 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3605 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3606 if (orig != data)
3607 WREG32(mmCGTS_SM_CTRL_REG, data);
3608 }
3609 } else {
3610 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3611 data |= 0x00000003;
3612 if (orig != data)
3613 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3614
3615 data = RREG32(mmRLC_MEM_SLP_CNTL);
3616 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3617 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3618 WREG32(mmRLC_MEM_SLP_CNTL, data);
3619 }
3620
3621 data = RREG32(mmCP_MEM_SLP_CNTL);
3622 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3623 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3624 WREG32(mmCP_MEM_SLP_CNTL, data);
3625 }
3626
3627 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3628 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3629 if (orig != data)
3630 WREG32(mmCGTS_SM_CTRL_REG, data);
3631
3632 tmp = gfx_v7_0_halt_rlc(adev);
3633
3634 mutex_lock(&adev->grbm_idx_mutex);
3635 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3636 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3637 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3638 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3639 WREG32(mmRLC_SERDES_WR_CTRL, data);
3640 mutex_unlock(&adev->grbm_idx_mutex);
3641
3642 gfx_v7_0_update_rlc(adev, tmp);
3643 }
3644}
3645
3646static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3647 bool enable)
3648{
3649 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3650 /* order matters! */
3651 if (enable) {
3652 gfx_v7_0_enable_mgcg(adev, true);
3653 gfx_v7_0_enable_cgcg(adev, true);
3654 } else {
3655 gfx_v7_0_enable_cgcg(adev, false);
3656 gfx_v7_0_enable_mgcg(adev, false);
3657 }
3658 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3659}
3660
3661static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3662 bool enable)
3663{
3664 u32 data, orig;
3665
3666 orig = data = RREG32(mmRLC_PG_CNTL);
3667 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
3668 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3669 else
3670 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3671 if (orig != data)
3672 WREG32(mmRLC_PG_CNTL, data);
3673}
3674
3675static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3676 bool enable)
3677{
3678 u32 data, orig;
3679
3680 orig = data = RREG32(mmRLC_PG_CNTL);
3681 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
3682 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3683 else
3684 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3685 if (orig != data)
3686 WREG32(mmRLC_PG_CNTL, data);
3687}
3688
3689static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3690{
3691 u32 data, orig;
3692
3693 orig = data = RREG32(mmRLC_PG_CNTL);
3694 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
3695 data &= ~0x8000;
3696 else
3697 data |= 0x8000;
3698 if (orig != data)
3699 WREG32(mmRLC_PG_CNTL, data);
3700}
3701
3702static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3703{
3704 u32 data, orig;
3705
3706 orig = data = RREG32(mmRLC_PG_CNTL);
3707 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
3708 data &= ~0x2000;
3709 else
3710 data |= 0x2000;
3711 if (orig != data)
3712 WREG32(mmRLC_PG_CNTL, data);
3713}
3714
3715static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3716{
3717 const __le32 *fw_data;
3718 volatile u32 *dst_ptr;
3719 int me, i, max_me = 4;
3720 u32 bo_offset = 0;
3721 u32 table_offset, table_size;
3722
3723 if (adev->asic_type == CHIP_KAVERI)
3724 max_me = 5;
3725
3726 if (adev->gfx.rlc.cp_table_ptr == NULL)
3727 return;
3728
3729 /* write the cp table buffer */
3730 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3731 for (me = 0; me < max_me; me++) {
3732 if (me == 0) {
3733 const struct gfx_firmware_header_v1_0 *hdr =
3734 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3735 fw_data = (const __le32 *)
3736 (adev->gfx.ce_fw->data +
3737 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3738 table_offset = le32_to_cpu(hdr->jt_offset);
3739 table_size = le32_to_cpu(hdr->jt_size);
3740 } else if (me == 1) {
3741 const struct gfx_firmware_header_v1_0 *hdr =
3742 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3743 fw_data = (const __le32 *)
3744 (adev->gfx.pfp_fw->data +
3745 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3746 table_offset = le32_to_cpu(hdr->jt_offset);
3747 table_size = le32_to_cpu(hdr->jt_size);
3748 } else if (me == 2) {
3749 const struct gfx_firmware_header_v1_0 *hdr =
3750 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3751 fw_data = (const __le32 *)
3752 (adev->gfx.me_fw->data +
3753 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3754 table_offset = le32_to_cpu(hdr->jt_offset);
3755 table_size = le32_to_cpu(hdr->jt_size);
3756 } else if (me == 3) {
3757 const struct gfx_firmware_header_v1_0 *hdr =
3758 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3759 fw_data = (const __le32 *)
3760 (adev->gfx.mec_fw->data +
3761 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3762 table_offset = le32_to_cpu(hdr->jt_offset);
3763 table_size = le32_to_cpu(hdr->jt_size);
3764 } else {
3765 const struct gfx_firmware_header_v1_0 *hdr =
3766 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3767 fw_data = (const __le32 *)
3768 (adev->gfx.mec2_fw->data +
3769 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3770 table_offset = le32_to_cpu(hdr->jt_offset);
3771 table_size = le32_to_cpu(hdr->jt_size);
3772 }
3773
3774 for (i = 0; i < table_size; i ++) {
3775 dst_ptr[bo_offset + i] =
3776 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3777 }
3778
3779 bo_offset += table_size;
3780 }
3781}
3782
3783static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3784 bool enable)
3785{
3786 u32 data, orig;
3787
3788 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
3789 orig = data = RREG32(mmRLC_PG_CNTL);
3790 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3791 if (orig != data)
3792 WREG32(mmRLC_PG_CNTL, data);
3793
3794 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3795 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3796 if (orig != data)
3797 WREG32(mmRLC_AUTO_PG_CTRL, data);
3798 } else {
3799 orig = data = RREG32(mmRLC_PG_CNTL);
3800 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3801 if (orig != data)
3802 WREG32(mmRLC_PG_CNTL, data);
3803
3804 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3805 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3806 if (orig != data)
3807 WREG32(mmRLC_AUTO_PG_CTRL, data);
3808
3809 data = RREG32(mmDB_RENDER_CONTROL);
3810 }
3811}
3812
8f8e00c1 3813static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 3814{
8f8e00c1 3815 u32 data, mask;
a2e73f56 3816
8f8e00c1
AD		 3817 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3818 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 3819
8f8e00c1
AD		 3820 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3821 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 3822
8f8e00c1
AD		 3823 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
3824 adev->gfx.config.max_sh_per_se);
a2e73f56 3825
8f8e00c1 3826 return (~data) & mask;
a2e73f56
AD		 3827}
3828
3829static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3830{
3831 uint32_t tmp, active_cu_number;
3832 struct amdgpu_cu_info cu_info;
3833
3834 gfx_v7_0_get_cu_info(adev, &cu_info);
3835 tmp = cu_info.ao_cu_mask;
3836 active_cu_number = cu_info.number;
3837
3838 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
3839
3840 tmp = RREG32(mmRLC_MAX_PG_CU);
3841 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3842 tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3843 WREG32(mmRLC_MAX_PG_CU, tmp);
3844}
3845
3846static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3847 bool enable)
3848{
3849 u32 data, orig;
3850
3851 orig = data = RREG32(mmRLC_PG_CNTL);
3852 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
3853 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3854 else
3855 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3856 if (orig != data)
3857 WREG32(mmRLC_PG_CNTL, data);
3858}
3859
3860static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3861 bool enable)
3862{
3863 u32 data, orig;
3864
3865 orig = data = RREG32(mmRLC_PG_CNTL);
3866 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
3867 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3868 else
3869 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3870 if (orig != data)
3871 WREG32(mmRLC_PG_CNTL, data);
3872}
3873
3874#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3875#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3876
3877static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3878{
3879 u32 data, orig;
3880 u32 i;
3881
3882 if (adev->gfx.rlc.cs_data) {
3883 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3884 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3885 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3886 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3887 } else {
3888 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3889 for (i = 0; i < 3; i++)
3890 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3891 }
3892 if (adev->gfx.rlc.reg_list) {
3893 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3894 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3895 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3896 }
3897
3898 orig = data = RREG32(mmRLC_PG_CNTL);
3899 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3900 if (orig != data)
3901 WREG32(mmRLC_PG_CNTL, data);
3902
3903 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3904 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3905
3906 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3907 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3908 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3909 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3910
3911 data = 0x10101010;
3912 WREG32(mmRLC_PG_DELAY, data);
3913
3914 data = RREG32(mmRLC_PG_DELAY_2);
3915 data &= ~0xff;
3916 data |= 0x3;
3917 WREG32(mmRLC_PG_DELAY_2, data);
3918
3919 data = RREG32(mmRLC_AUTO_PG_CTRL);
3920 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3921 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3922 WREG32(mmRLC_AUTO_PG_CTRL, data);
3923
3924}
3925
3926static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3927{
3928 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3929 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3930 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3931}
3932
3933static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3934{
3935 u32 count = 0;
3936 const struct cs_section_def *sect = NULL;
3937 const struct cs_extent_def *ext = NULL;
3938
3939 if (adev->gfx.rlc.cs_data == NULL)
3940 return 0;
3941
3942 /* begin clear state */
3943 count += 2;
3944 /* context control state */
3945 count += 3;
3946
3947 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3948 for (ext = sect->section; ext->extent != NULL; ++ext) {
3949 if (sect->id == SECT_CONTEXT)
3950 count += 2 + ext->reg_count;
3951 else
3952 return 0;
3953 }
3954 }
3955 /* pa_sc_raster_config/pa_sc_raster_config1 */
3956 count += 4;
3957 /* end clear state */
3958 count += 2;
3959 /* clear state */
3960 count += 2;
3961
3962 return count;
3963}
3964
3965static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
3966 volatile u32 *buffer)
3967{
3968 u32 count = 0, i;
3969 const struct cs_section_def *sect = NULL;
3970 const struct cs_extent_def *ext = NULL;
3971
3972 if (adev->gfx.rlc.cs_data == NULL)
3973 return;
3974 if (buffer == NULL)
3975 return;
3976
3977 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3978 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3979
3980 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3981 buffer[count++] = cpu_to_le32(0x80000000);
3982 buffer[count++] = cpu_to_le32(0x80000000);
3983
3984 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3985 for (ext = sect->section; ext->extent != NULL; ++ext) {
3986 if (sect->id == SECT_CONTEXT) {
3987 buffer[count++] =
3988 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3989 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3990 for (i = 0; i < ext->reg_count; i++)
3991 buffer[count++] = cpu_to_le32(ext->extent[i]);
3992 } else {
3993 return;
3994 }
3995 }
3996 }
3997
3998 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3999 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4000 switch (adev->asic_type) {
4001 case CHIP_BONAIRE:
4002 buffer[count++] = cpu_to_le32(0x16000012);
4003 buffer[count++] = cpu_to_le32(0x00000000);
4004 break;
4005 case CHIP_KAVERI:
4006 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4007 buffer[count++] = cpu_to_le32(0x00000000);
4008 break;
4009 case CHIP_KABINI:
4010 case CHIP_MULLINS:
4011 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4012 buffer[count++] = cpu_to_le32(0x00000000);
4013 break;
4014 case CHIP_HAWAII:
4015 buffer[count++] = cpu_to_le32(0x3a00161a);
4016 buffer[count++] = cpu_to_le32(0x0000002e);
4017 break;
4018 default:
4019 buffer[count++] = cpu_to_le32(0x00000000);
4020 buffer[count++] = cpu_to_le32(0x00000000);
4021 break;
4022 }
4023
4024 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4025 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4026
4027 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4028 buffer[count++] = cpu_to_le32(0);
4029}
4030
4031static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4032{
4033 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4034 AMDGPU_PG_SUPPORT_GFX_SMG |
4035 AMDGPU_PG_SUPPORT_GFX_DMG |
4036 AMDGPU_PG_SUPPORT_CP |
4037 AMDGPU_PG_SUPPORT_GDS |
4038 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4039 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4040 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4041 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4042 gfx_v7_0_init_gfx_cgpg(adev);
4043 gfx_v7_0_enable_cp_pg(adev, true);
4044 gfx_v7_0_enable_gds_pg(adev, true);
4045 }
4046 gfx_v7_0_init_ao_cu_mask(adev);
4047 gfx_v7_0_update_gfx_pg(adev, true);
4048 }
4049}
4050
4051static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4052{
4053 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4054 AMDGPU_PG_SUPPORT_GFX_SMG |
4055 AMDGPU_PG_SUPPORT_GFX_DMG |
4056 AMDGPU_PG_SUPPORT_CP |
4057 AMDGPU_PG_SUPPORT_GDS |
4058 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4059 gfx_v7_0_update_gfx_pg(adev, false);
4060 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4061 gfx_v7_0_enable_cp_pg(adev, false);
4062 gfx_v7_0_enable_gds_pg(adev, false);
4063 }
4064 }
4065}
4066
4067/**
4068 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4069 *
4070 * @adev: amdgpu_device pointer
4071 *
4072 * Fetches a GPU clock counter snapshot (SI).
4073 * Returns the 64 bit clock counter snapshot.
4074 */
4075uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4076{
4077 uint64_t clock;
4078
4079 mutex_lock(&adev->gfx.gpu_clock_mutex);
4080 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4081 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4082 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4083 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4084 return clock;
4085}
4086
4087static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4088 uint32_t vmid,
4089 uint32_t gds_base, uint32_t gds_size,
4090 uint32_t gws_base, uint32_t gws_size,
4091 uint32_t oa_base, uint32_t oa_size)
4092{
4093 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4094 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4095
4096 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4097 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4098
4099 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4100 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4101
4102 /* GDS Base */
4103 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4104 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4105 WRITE_DATA_DST_SEL(0)));
4106 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4107 amdgpu_ring_write(ring, 0);
4108 amdgpu_ring_write(ring, gds_base);
4109
4110 /* GDS Size */
4111 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4112 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4113 WRITE_DATA_DST_SEL(0)));
4114 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4115 amdgpu_ring_write(ring, 0);
4116 amdgpu_ring_write(ring, gds_size);
4117
4118 /* GWS */
4119 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4120 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4121 WRITE_DATA_DST_SEL(0)));
4122 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4123 amdgpu_ring_write(ring, 0);
4124 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4125
4126 /* OA */
4127 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4128 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4129 WRITE_DATA_DST_SEL(0)));
4130 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4131 amdgpu_ring_write(ring, 0);
4132 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4133}
4134
5fc3aeeb 4135static int gfx_v7_0_early_init(void *handle)
a2e73f56 4136{
5fc3aeeb 4137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4138
4139 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4140 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4141 gfx_v7_0_set_ring_funcs(adev);
4142 gfx_v7_0_set_irq_funcs(adev);
4143 gfx_v7_0_set_gds_init(adev);
4144
4145 return 0;
4146}
4147
ef720532
AD		 4148static int gfx_v7_0_late_init(void *handle)
4149{
4150 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4151 int r;
4152
4153 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4154 if (r)
4155 return r;
4156
4157 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4158 if (r)
4159 return r;
4160
4161 return 0;
4162}
4163
d93f3ca7
AD		 4164static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4165{
4166 u32 gb_addr_config;
4167 u32 mc_shared_chmap, mc_arb_ramcfg;
4168 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4169 u32 tmp;
4170
4171 switch (adev->asic_type) {
4172 case CHIP_BONAIRE:
4173 adev->gfx.config.max_shader_engines = 2;
4174 adev->gfx.config.max_tile_pipes = 4;
4175 adev->gfx.config.max_cu_per_sh = 7;
4176 adev->gfx.config.max_sh_per_se = 1;
4177 adev->gfx.config.max_backends_per_se = 2;
4178 adev->gfx.config.max_texture_channel_caches = 4;
4179 adev->gfx.config.max_gprs = 256;
4180 adev->gfx.config.max_gs_threads = 32;
4181 adev->gfx.config.max_hw_contexts = 8;
4182
4183 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4184 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4185 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4186 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4187 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4188 break;
4189 case CHIP_HAWAII:
4190 adev->gfx.config.max_shader_engines = 4;
4191 adev->gfx.config.max_tile_pipes = 16;
4192 adev->gfx.config.max_cu_per_sh = 11;
4193 adev->gfx.config.max_sh_per_se = 1;
4194 adev->gfx.config.max_backends_per_se = 4;
4195 adev->gfx.config.max_texture_channel_caches = 16;
4196 adev->gfx.config.max_gprs = 256;
4197 adev->gfx.config.max_gs_threads = 32;
4198 adev->gfx.config.max_hw_contexts = 8;
4199
4200 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4201 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4202 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4203 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4204 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4205 break;
4206 case CHIP_KAVERI:
4207 adev->gfx.config.max_shader_engines = 1;
4208 adev->gfx.config.max_tile_pipes = 4;
4209 if ((adev->pdev->device == 0x1304) ||
4210 (adev->pdev->device == 0x1305) ||
4211 (adev->pdev->device == 0x130C) ||
4212 (adev->pdev->device == 0x130F) ||
4213 (adev->pdev->device == 0x1310) ||
4214 (adev->pdev->device == 0x1311) ||
4215 (adev->pdev->device == 0x131C)) {
4216 adev->gfx.config.max_cu_per_sh = 8;
4217 adev->gfx.config.max_backends_per_se = 2;
4218 } else if ((adev->pdev->device == 0x1309) ||
4219 (adev->pdev->device == 0x130A) ||
4220 (adev->pdev->device == 0x130D) ||
4221 (adev->pdev->device == 0x1313) ||
4222 (adev->pdev->device == 0x131D)) {
4223 adev->gfx.config.max_cu_per_sh = 6;
4224 adev->gfx.config.max_backends_per_se = 2;
4225 } else if ((adev->pdev->device == 0x1306) ||
4226 (adev->pdev->device == 0x1307) ||
4227 (adev->pdev->device == 0x130B) ||
4228 (adev->pdev->device == 0x130E) ||
4229 (adev->pdev->device == 0x1315) ||
4230 (adev->pdev->device == 0x131B)) {
4231 adev->gfx.config.max_cu_per_sh = 4;
4232 adev->gfx.config.max_backends_per_se = 1;
4233 } else {
4234 adev->gfx.config.max_cu_per_sh = 3;
4235 adev->gfx.config.max_backends_per_se = 1;
4236 }
4237 adev->gfx.config.max_sh_per_se = 1;
4238 adev->gfx.config.max_texture_channel_caches = 4;
4239 adev->gfx.config.max_gprs = 256;
4240 adev->gfx.config.max_gs_threads = 16;
4241 adev->gfx.config.max_hw_contexts = 8;
4242
4243 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4244 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4245 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4246 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4247 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4248 break;
4249 case CHIP_KABINI:
4250 case CHIP_MULLINS:
4251 default:
4252 adev->gfx.config.max_shader_engines = 1;
4253 adev->gfx.config.max_tile_pipes = 2;
4254 adev->gfx.config.max_cu_per_sh = 2;
4255 adev->gfx.config.max_sh_per_se = 1;
4256 adev->gfx.config.max_backends_per_se = 1;
4257 adev->gfx.config.max_texture_channel_caches = 2;
4258 adev->gfx.config.max_gprs = 256;
4259 adev->gfx.config.max_gs_threads = 16;
4260 adev->gfx.config.max_hw_contexts = 8;
4261
4262 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4263 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4264 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4265 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4266 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4267 break;
4268 }
4269
4270 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4271 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4272 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4273
4274 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4275 adev->gfx.config.mem_max_burst_length_bytes = 256;
4276 if (adev->flags & AMD_IS_APU) {
4277 /* Get memory bank mapping mode. */
4278 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4279 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4280 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4281
4282 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4283 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4284 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4285
4286 /* Validate settings in case only one DIMM installed. */
4287 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4288 dimm00_addr_map = 0;
4289 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4290 dimm01_addr_map = 0;
4291 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4292 dimm10_addr_map = 0;
4293 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4294 dimm11_addr_map = 0;
4295
4296 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4297 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4298 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4299 adev->gfx.config.mem_row_size_in_kb = 2;
4300 else
4301 adev->gfx.config.mem_row_size_in_kb = 1;
4302 } else {
4303 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4304 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4305 if (adev->gfx.config.mem_row_size_in_kb > 4)
4306 adev->gfx.config.mem_row_size_in_kb = 4;
4307 }
4308 /* XXX use MC settings? */
4309 adev->gfx.config.shader_engine_tile_size = 32;
4310 adev->gfx.config.num_gpus = 1;
4311 adev->gfx.config.multi_gpu_tile_size = 64;
4312
4313 /* fix up row size */
4314 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4315 switch (adev->gfx.config.mem_row_size_in_kb) {
4316 case 1:
4317 default:
4318 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4319 break;
4320 case 2:
4321 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4322 break;
4323 case 4:
4324 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4325 break;
4326 }
4327 adev->gfx.config.gb_addr_config = gb_addr_config;
4328}
4329
5fc3aeeb 4330static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4331{
4332 struct amdgpu_ring *ring;
5fc3aeeb 4333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4334 int i, r;
4335
4336 /* EOP Event */
4337 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4338 if (r)
4339 return r;
4340
4341 /* Privileged reg */
4342 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4343 if (r)
4344 return r;
4345
4346 /* Privileged inst */
4347 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4348 if (r)
4349 return r;
4350
4351 gfx_v7_0_scratch_init(adev);
4352
4353 r = gfx_v7_0_init_microcode(adev);
4354 if (r) {
4355 DRM_ERROR("Failed to load gfx firmware!\n");
4356 return r;
4357 }
4358
4359 r = gfx_v7_0_rlc_init(adev);
4360 if (r) {
4361 DRM_ERROR("Failed to init rlc BOs!\n");
4362 return r;
4363 }
4364
4365 /* allocate mec buffers */
4366 r = gfx_v7_0_mec_init(adev);
4367 if (r) {
4368 DRM_ERROR("Failed to init MEC BOs!\n");
4369 return r;
4370 }
4371
a2e73f56
AD		 4372 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4373 ring = &adev->gfx.gfx_ring[i];
4374 ring->ring_obj = NULL;
4375 sprintf(ring->name, "gfx");
4376 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4377 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4378 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4379 AMDGPU_RING_TYPE_GFX);
4380 if (r)
4381 return r;
4382 }
4383
4384 /* set up the compute queues */
4385 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4386 unsigned irq_type;
4387
4388 /* max 32 queues per MEC */
4389 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4390 DRM_ERROR("Too many (%d) compute rings!\n", i);
4391 break;
4392 }
4393 ring = &adev->gfx.compute_ring[i];
4394 ring->ring_obj = NULL;
4395 ring->use_doorbell = true;
4396 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4397 ring->me = 1; /* first MEC */
4398 ring->pipe = i / 8;
4399 ring->queue = i % 8;
4400 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
4401 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4402 /* type-2 packets are deprecated on MEC, use type-3 instead */
4403 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4404 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4405 &adev->gfx.eop_irq, irq_type,
4406 AMDGPU_RING_TYPE_COMPUTE);
4407 if (r)
4408 return r;
4409 }
4410
4411 /* reserve GDS, GWS and OA resource for gfx */
4412 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4413 PAGE_SIZE, true,
4414 AMDGPU_GEM_DOMAIN_GDS, 0,
72d7668b 4415 NULL, NULL, &adev->gds.gds_gfx_bo);
a2e73f56
AD		 4416 if (r)
4417 return r;
4418
4419 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4420 PAGE_SIZE, true,
4421 AMDGPU_GEM_DOMAIN_GWS, 0,
72d7668b 4422 NULL, NULL, &adev->gds.gws_gfx_bo);
a2e73f56
AD		 4423 if (r)
4424 return r;
4425
4426 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4427 PAGE_SIZE, true,
4428 AMDGPU_GEM_DOMAIN_OA, 0,
72d7668b 4429 NULL, NULL, &adev->gds.oa_gfx_bo);
a2e73f56
AD		 4430 if (r)
4431 return r;
4432
d93f3ca7
AD		 4433 adev->gfx.ce_ram_size = 0x8000;
4434
4435 gfx_v7_0_gpu_early_init(adev);
4436
a2e73f56
AD		 4437 return r;
4438}
4439
5fc3aeeb 4440static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4441{
4442 int i;
5fc3aeeb 4443 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4444
4445 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4446 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4447 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4448
4449 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4450 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4451 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4452 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4453
a2e73f56
AD		 4454 gfx_v7_0_cp_compute_fini(adev);
4455 gfx_v7_0_rlc_fini(adev);
4456 gfx_v7_0_mec_fini(adev);
4457
4458 return 0;
4459}
4460
5fc3aeeb 4461static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4462{
4463 int r;
5fc3aeeb 4464 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4465
4466 gfx_v7_0_gpu_init(adev);
4467
4468 /* init rlc */
4469 r = gfx_v7_0_rlc_resume(adev);
4470 if (r)
4471 return r;
4472
4473 r = gfx_v7_0_cp_resume(adev);
4474 if (r)
4475 return r;
4476
4477 return r;
4478}
4479
5fc3aeeb 4480static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4481{
5fc3aeeb 4482 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4483
ef720532
AD		 4484 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4485 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4486 gfx_v7_0_cp_enable(adev, false);
4487 gfx_v7_0_rlc_stop(adev);
4488 gfx_v7_0_fini_pg(adev);
4489
4490 return 0;
4491}
4492
5fc3aeeb 4493static int gfx_v7_0_suspend(void *handle)
a2e73f56 4494{
5fc3aeeb 4495 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4496
a2e73f56
AD		 4497 return gfx_v7_0_hw_fini(adev);
4498}
4499
5fc3aeeb 4500static int gfx_v7_0_resume(void *handle)
a2e73f56 4501{
5fc3aeeb 4502 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4503
a2e73f56
AD		 4504 return gfx_v7_0_hw_init(adev);
4505}
4506
5fc3aeeb 4507static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4508{
5fc3aeeb 4509 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4510
a2e73f56
AD		 4511 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4512 return false;
4513 else
4514 return true;
4515}
4516
5fc3aeeb 4517static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4518{
4519 unsigned i;
4520 u32 tmp;
5fc3aeeb 4521 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4522
4523 for (i = 0; i < adev->usec_timeout; i++) {
4524 /* read MC_STATUS */
4525 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4526
4527 if (!tmp)
4528 return 0;
4529 udelay(1);
4530 }
4531 return -ETIMEDOUT;
4532}
4533
5fc3aeeb 4534static void gfx_v7_0_print_status(void *handle)
a2e73f56
AD		 4535{
4536 int i;
5fc3aeeb 4537 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4538
4539 dev_info(adev->dev, "GFX 7.x registers\n");
4540 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
4541 RREG32(mmGRBM_STATUS));
4542 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
4543 RREG32(mmGRBM_STATUS2));
4544 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4545 RREG32(mmGRBM_STATUS_SE0));
4546 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4547 RREG32(mmGRBM_STATUS_SE1));
4548 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4549 RREG32(mmGRBM_STATUS_SE2));
4550 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4551 RREG32(mmGRBM_STATUS_SE3));
4552 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4553 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4554 RREG32(mmCP_STALLED_STAT1));
4555 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4556 RREG32(mmCP_STALLED_STAT2));
4557 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4558 RREG32(mmCP_STALLED_STAT3));
4559 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4560 RREG32(mmCP_CPF_BUSY_STAT));
4561 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4562 RREG32(mmCP_CPF_STALLED_STAT1));
4563 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4564 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4565 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4566 RREG32(mmCP_CPC_STALLED_STAT1));
4567 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4568
4569 for (i = 0; i < 32; i++) {
4570 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
4571 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4572 }
4573 for (i = 0; i < 16; i++) {
4574 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
4575 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4576 }
4577 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4578 dev_info(adev->dev, " se: %d\n", i);
4579 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
4580 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
4581 RREG32(mmPA_SC_RASTER_CONFIG));
4582 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
4583 RREG32(mmPA_SC_RASTER_CONFIG_1));
4584 }
4585 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4586
4587 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
4588 RREG32(mmGB_ADDR_CONFIG));
4589 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
4590 RREG32(mmHDP_ADDR_CONFIG));
4591 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
4592 RREG32(mmDMIF_ADDR_CALC));
a2e73f56
AD		 4593
4594 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
4595 RREG32(mmCP_MEQ_THRESHOLDS));
4596 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
4597 RREG32(mmSX_DEBUG_1));
4598 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
4599 RREG32(mmTA_CNTL_AUX));
4600 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
4601 RREG32(mmSPI_CONFIG_CNTL));
4602 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
4603 RREG32(mmSQ_CONFIG));
4604 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
4605 RREG32(mmDB_DEBUG));
4606 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
4607 RREG32(mmDB_DEBUG2));
4608 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
4609 RREG32(mmDB_DEBUG3));
4610 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
4611 RREG32(mmCB_HW_CONTROL));
4612 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
4613 RREG32(mmSPI_CONFIG_CNTL_1));
4614 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
4615 RREG32(mmPA_SC_FIFO_SIZE));
4616 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
4617 RREG32(mmVGT_NUM_INSTANCES));
4618 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
4619 RREG32(mmCP_PERFMON_CNTL));
4620 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4621 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4622 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
4623 RREG32(mmVGT_CACHE_INVALIDATION));
4624 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
4625 RREG32(mmVGT_GS_VERTEX_REUSE));
4626 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4627 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4628 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
4629 RREG32(mmPA_CL_ENHANCE));
4630 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
4631 RREG32(mmPA_SC_ENHANCE));
4632
4633 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
4634 RREG32(mmCP_ME_CNTL));
4635 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
4636 RREG32(mmCP_MAX_CONTEXT));
4637 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
4638 RREG32(mmCP_ENDIAN_SWAP));
4639 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
4640 RREG32(mmCP_DEVICE_ID));
4641
4642 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4643 RREG32(mmCP_SEM_WAIT_TIMER));
4644 if (adev->asic_type != CHIP_HAWAII)
4645 dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
4646 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
4647
4648 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4649 RREG32(mmCP_RB_WPTR_DELAY));
4650 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4651 RREG32(mmCP_RB_VMID));
4652 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4653 RREG32(mmCP_RB0_CNTL));
4654 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4655 RREG32(mmCP_RB0_WPTR));
4656 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4657 RREG32(mmCP_RB0_RPTR_ADDR));
4658 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4659 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4660 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4661 RREG32(mmCP_RB0_CNTL));
4662 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4663 RREG32(mmCP_RB0_BASE));
4664 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4665 RREG32(mmCP_RB0_BASE_HI));
4666 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4667 RREG32(mmCP_MEC_CNTL));
4668 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4669 RREG32(mmCP_CPF_DEBUG));
4670
4671 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4672 RREG32(mmSCRATCH_ADDR));
4673 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4674 RREG32(mmSCRATCH_UMSK));
4675
4676 /* init the pipes */
4677 mutex_lock(&adev->srbm_mutex);
4678 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4679 int me = (i < 4) ? 1 : 2;
4680 int pipe = (i < 4) ? i : (i - 4);
4681 int queue;
4682
4683 dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe);
4684 cik_srbm_select(adev, me, pipe, 0, 0);
4685 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n",
4686 RREG32(mmCP_HPD_EOP_BASE_ADDR));
4687 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
4688 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
4689 dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n",
4690 RREG32(mmCP_HPD_EOP_VMID));
4691 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n",
4692 RREG32(mmCP_HPD_EOP_CONTROL));
4693
0fd64291 4694 for (queue = 0; queue < 8; queue++) {
a2e73f56
AD		 4695 cik_srbm_select(adev, me, pipe, queue, 0);
4696 dev_info(adev->dev, " queue: %d\n", queue);
4697 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
4698 RREG32(mmCP_PQ_WPTR_POLL_CNTL));
4699 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
4700 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
4701 dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n",
4702 RREG32(mmCP_HQD_ACTIVE));
4703 dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
4704 RREG32(mmCP_HQD_DEQUEUE_REQUEST));
4705 dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n",
4706 RREG32(mmCP_HQD_PQ_RPTR));
4707 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
4708 RREG32(mmCP_HQD_PQ_WPTR));
4709 dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n",
4710 RREG32(mmCP_HQD_PQ_BASE));
4711 dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n",
4712 RREG32(mmCP_HQD_PQ_BASE_HI));
4713 dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n",
4714 RREG32(mmCP_HQD_PQ_CONTROL));
4715 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
4716 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
4717 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
4718 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
4719 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
4720 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
4721 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
4722 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
4723 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
4724 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
4725 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
4726 RREG32(mmCP_HQD_PQ_WPTR));
4727 dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n",
4728 RREG32(mmCP_HQD_VMID));
4729 dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n",
4730 RREG32(mmCP_MQD_BASE_ADDR));
4731 dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n",
4732 RREG32(mmCP_MQD_BASE_ADDR_HI));
4733 dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n",
4734 RREG32(mmCP_MQD_CONTROL));
4735 }
4736 }
4737 cik_srbm_select(adev, 0, 0, 0, 0);
4738 mutex_unlock(&adev->srbm_mutex);
4739
4740 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4741 RREG32(mmCP_INT_CNTL_RING0));
4742 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4743 RREG32(mmRLC_LB_CNTL));
4744 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4745 RREG32(mmRLC_CNTL));
4746 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4747 RREG32(mmRLC_CGCG_CGLS_CTRL));
4748 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4749 RREG32(mmRLC_LB_CNTR_INIT));
4750 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4751 RREG32(mmRLC_LB_CNTR_MAX));
4752 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4753 RREG32(mmRLC_LB_INIT_CU_MASK));
4754 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4755 RREG32(mmRLC_LB_PARAMS));
4756 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4757 RREG32(mmRLC_LB_CNTL));
4758 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4759 RREG32(mmRLC_MC_CNTL));
4760 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4761 RREG32(mmRLC_UCODE_CNTL));
4762
4763 if (adev->asic_type == CHIP_BONAIRE)
4764 dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
4765 RREG32(mmRLC_DRIVER_CPDMA_STATUS));
4766
4767 mutex_lock(&adev->srbm_mutex);
4768 for (i = 0; i < 16; i++) {
4769 cik_srbm_select(adev, 0, 0, 0, i);
4770 dev_info(adev->dev, " VM %d:\n", i);
4771 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4772 RREG32(mmSH_MEM_CONFIG));
4773 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4774 RREG32(mmSH_MEM_APE1_BASE));
4775 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
4776 RREG32(mmSH_MEM_APE1_LIMIT));
4777 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
4778 RREG32(mmSH_MEM_BASES));
4779 }
4780 cik_srbm_select(adev, 0, 0, 0, 0);
4781 mutex_unlock(&adev->srbm_mutex);
4782}
4783
5fc3aeeb 4784static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4785{
4786 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4787 u32 tmp;
5fc3aeeb 4788 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4789
4790 /* GRBM_STATUS */
4791 tmp = RREG32(mmGRBM_STATUS);
4792 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4793 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4794 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4795 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4796 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4797 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4798 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4799 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4800
4801 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4802 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4803 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4804 }
4805
4806 /* GRBM_STATUS2 */
4807 tmp = RREG32(mmGRBM_STATUS2);
4808 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4809 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4810
4811 /* SRBM_STATUS */
4812 tmp = RREG32(mmSRBM_STATUS);
4813 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4814 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4815
4816 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 4817 gfx_v7_0_print_status((void *)adev);
a2e73f56
AD		 4818 /* disable CG/PG */
4819 gfx_v7_0_fini_pg(adev);
4820 gfx_v7_0_update_cg(adev, false);
4821
4822 /* stop the rlc */
4823 gfx_v7_0_rlc_stop(adev);
4824
4825 /* Disable GFX parsing/prefetching */
4826 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4827
4828 /* Disable MEC parsing/prefetching */
4829 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4830
4831 if (grbm_soft_reset) {
4832 tmp = RREG32(mmGRBM_SOFT_RESET);
4833 tmp |= grbm_soft_reset;
4834 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4835 WREG32(mmGRBM_SOFT_RESET, tmp);
4836 tmp = RREG32(mmGRBM_SOFT_RESET);
4837
4838 udelay(50);
4839
4840 tmp &= ~grbm_soft_reset;
4841 WREG32(mmGRBM_SOFT_RESET, tmp);
4842 tmp = RREG32(mmGRBM_SOFT_RESET);
4843 }
4844
4845 if (srbm_soft_reset) {
4846 tmp = RREG32(mmSRBM_SOFT_RESET);
4847 tmp |= srbm_soft_reset;
4848 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4849 WREG32(mmSRBM_SOFT_RESET, tmp);
4850 tmp = RREG32(mmSRBM_SOFT_RESET);
4851
4852 udelay(50);
4853
4854 tmp &= ~srbm_soft_reset;
4855 WREG32(mmSRBM_SOFT_RESET, tmp);
4856 tmp = RREG32(mmSRBM_SOFT_RESET);
4857 }
4858 /* Wait a little for things to settle down */
4859 udelay(50);
5fc3aeeb 4860 gfx_v7_0_print_status((void *)adev);
a2e73f56
AD		 4861 }
4862 return 0;
4863}
4864
4865static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4866 enum amdgpu_interrupt_state state)
4867{
4868 u32 cp_int_cntl;
4869
4870 switch (state) {
4871 case AMDGPU_IRQ_STATE_DISABLE:
4872 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4873 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4874 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4875 break;
4876 case AMDGPU_IRQ_STATE_ENABLE:
4877 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4878 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4879 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4880 break;
4881 default:
4882 break;
4883 }
4884}
4885
4886static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4887 int me, int pipe,
4888 enum amdgpu_interrupt_state state)
4889{
4890 u32 mec_int_cntl, mec_int_cntl_reg;
4891
4892 /*
4893 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4894 * handles the setting of interrupts for this specific pipe. All other
4895 * pipes' interrupts are set by amdkfd.
4896 */
4897
4898 if (me == 1) {
4899 switch (pipe) {
4900 case 0:
4901 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4902 break;
4903 default:
4904 DRM_DEBUG("invalid pipe %d\n", pipe);
4905 return;
4906 }
4907 } else {
4908 DRM_DEBUG("invalid me %d\n", me);
4909 return;
4910 }
4911
4912 switch (state) {
4913 case AMDGPU_IRQ_STATE_DISABLE:
4914 mec_int_cntl = RREG32(mec_int_cntl_reg);
4915 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4916 WREG32(mec_int_cntl_reg, mec_int_cntl);
4917 break;
4918 case AMDGPU_IRQ_STATE_ENABLE:
4919 mec_int_cntl = RREG32(mec_int_cntl_reg);
4920 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4921 WREG32(mec_int_cntl_reg, mec_int_cntl);
4922 break;
4923 default:
4924 break;
4925 }
4926}
4927
4928static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4929 struct amdgpu_irq_src *src,
4930 unsigned type,
4931 enum amdgpu_interrupt_state state)
4932{
4933 u32 cp_int_cntl;
4934
4935 switch (state) {
4936 case AMDGPU_IRQ_STATE_DISABLE:
4937 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4938 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4939 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4940 break;
4941 case AMDGPU_IRQ_STATE_ENABLE:
4942 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4943 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4944 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4945 break;
4946 default:
4947 break;
4948 }
4949
4950 return 0;
4951}
4952
4953static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4954 struct amdgpu_irq_src *src,
4955 unsigned type,
4956 enum amdgpu_interrupt_state state)
4957{
4958 u32 cp_int_cntl;
4959
4960 switch (state) {
4961 case AMDGPU_IRQ_STATE_DISABLE:
4962 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4963 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4964 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4965 break;
4966 case AMDGPU_IRQ_STATE_ENABLE:
4967 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4968 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4969 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4970 break;
4971 default:
4972 break;
4973 }
4974
4975 return 0;
4976}
4977
4978static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4979 struct amdgpu_irq_src *src,
4980 unsigned type,
4981 enum amdgpu_interrupt_state state)
4982{
4983 switch (type) {
4984 case AMDGPU_CP_IRQ_GFX_EOP:
4985 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4986 break;
4987 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4988 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4989 break;
4990 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4991 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4992 break;
4993 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4994 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4995 break;
4996 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4997 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4998 break;
4999 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5000 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5001 break;
5002 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5003 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5004 break;
5005 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5006 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5007 break;
5008 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5009 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5010 break;
5011 default:
5012 break;
5013 }
5014 return 0;
5015}
5016
5017static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5018 struct amdgpu_irq_src *source,
5019 struct amdgpu_iv_entry *entry)
5020{
5021 u8 me_id, pipe_id;
5022 struct amdgpu_ring *ring;
5023 int i;
5024
5025 DRM_DEBUG("IH: CP EOP\n");
5026 me_id = (entry->ring_id & 0x0c) >> 2;
5027 pipe_id = (entry->ring_id & 0x03) >> 0;
5028 switch (me_id) {
5029 case 0:
5030 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5031 break;
5032 case 1:
5033 case 2:
5034 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5035 ring = &adev->gfx.compute_ring[i];
5036 if ((ring->me == me_id) & (ring->pipe == pipe_id))
5037 amdgpu_fence_process(ring);
5038 }
5039 break;
5040 }
5041 return 0;
5042}
5043
5044static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5045 struct amdgpu_irq_src *source,
5046 struct amdgpu_iv_entry *entry)
5047{
5048 DRM_ERROR("Illegal register access in command stream\n");
5049 schedule_work(&adev->reset_work);
5050 return 0;
5051}
5052
5053static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5054 struct amdgpu_irq_src *source,
5055 struct amdgpu_iv_entry *entry)
5056{
5057 DRM_ERROR("Illegal instruction in command stream\n");
5058 // XXX soft reset the gfx block only
5059 schedule_work(&adev->reset_work);
5060 return 0;
5061}
5062
5fc3aeeb 5063static int gfx_v7_0_set_clockgating_state(void *handle,
5064 enum amd_clockgating_state state)
a2e73f56
AD		 5065{
5066 bool gate = false;
5fc3aeeb 5067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5068
5fc3aeeb 5069 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 5070 gate = true;
5071
5072 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5073 /* order matters! */
5074 if (gate) {
5075 gfx_v7_0_enable_mgcg(adev, true);
5076 gfx_v7_0_enable_cgcg(adev, true);
5077 } else {
5078 gfx_v7_0_enable_cgcg(adev, false);
5079 gfx_v7_0_enable_mgcg(adev, false);
5080 }
5081 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5082
5083 return 0;
5084}
5085
5fc3aeeb 5086static int gfx_v7_0_set_powergating_state(void *handle,
5087 enum amd_powergating_state state)
a2e73f56
AD		 5088{
5089 bool gate = false;
5fc3aeeb 5090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5091
5fc3aeeb 5092 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 5093 gate = true;
5094
5095 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
5096 AMDGPU_PG_SUPPORT_GFX_SMG |
5097 AMDGPU_PG_SUPPORT_GFX_DMG |
5098 AMDGPU_PG_SUPPORT_CP |
5099 AMDGPU_PG_SUPPORT_GDS |
5100 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
5101 gfx_v7_0_update_gfx_pg(adev, gate);
5102 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
5103 gfx_v7_0_enable_cp_pg(adev, gate);
5104 gfx_v7_0_enable_gds_pg(adev, gate);
5105 }
5106 }
5107
5108 return 0;
5109}
5110
5fc3aeeb 5111const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
a2e73f56 5112 .early_init = gfx_v7_0_early_init,
ef720532 5113 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 5114 .sw_init = gfx_v7_0_sw_init,
5115 .sw_fini = gfx_v7_0_sw_fini,
5116 .hw_init = gfx_v7_0_hw_init,
5117 .hw_fini = gfx_v7_0_hw_fini,
5118 .suspend = gfx_v7_0_suspend,
5119 .resume = gfx_v7_0_resume,
5120 .is_idle = gfx_v7_0_is_idle,
5121 .wait_for_idle = gfx_v7_0_wait_for_idle,
5122 .soft_reset = gfx_v7_0_soft_reset,
5123 .print_status = gfx_v7_0_print_status,
5124 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5125 .set_powergating_state = gfx_v7_0_set_powergating_state,
5126};
5127
a2e73f56
AD		 5128static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5129 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
5130 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5131 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5132 .parse_cs = NULL,
93323131 5133 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 5134 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
a2e73f56
AD		 5135 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5136 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 5137 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
a2e73f56
AD		 5138 .test_ring = gfx_v7_0_ring_test_ring,
5139 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5140 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5141 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5142};
5143
5144static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5145 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
5146 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5147 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5148 .parse_cs = NULL,
93323131 5149 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 5150 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
a2e73f56
AD		 5151 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5152 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 5153 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
a2e73f56
AD		 5154 .test_ring = gfx_v7_0_ring_test_ring,
5155 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5156 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5157 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5158};
5159
5160static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5161{
5162 int i;
5163
5164 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5165 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5166 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5167 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5168}
5169
5170static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5171 .set = gfx_v7_0_set_eop_interrupt_state,
5172 .process = gfx_v7_0_eop_irq,
5173};
5174
5175static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5176 .set = gfx_v7_0_set_priv_reg_fault_state,
5177 .process = gfx_v7_0_priv_reg_irq,
5178};
5179
5180static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5181 .set = gfx_v7_0_set_priv_inst_fault_state,
5182 .process = gfx_v7_0_priv_inst_irq,
5183};
5184
5185static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5186{
5187 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5188 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5189
5190 adev->gfx.priv_reg_irq.num_types = 1;
5191 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5192
5193 adev->gfx.priv_inst_irq.num_types = 1;
5194 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5195}
5196
5197static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5198{
5199 /* init asci gds info */
5200 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5201 adev->gds.gws.total_size = 64;
5202 adev->gds.oa.total_size = 16;
5203
5204 if (adev->gds.mem.total_size == 64 * 1024) {
5205 adev->gds.mem.gfx_partition_size = 4096;
5206 adev->gds.mem.cs_partition_size = 4096;
5207
5208 adev->gds.gws.gfx_partition_size = 4;
5209 adev->gds.gws.cs_partition_size = 4;
5210
5211 adev->gds.oa.gfx_partition_size = 4;
5212 adev->gds.oa.cs_partition_size = 1;
5213 } else {
5214 adev->gds.mem.gfx_partition_size = 1024;
5215 adev->gds.mem.cs_partition_size = 1024;
5216
5217 adev->gds.gws.gfx_partition_size = 16;
5218 adev->gds.gws.cs_partition_size = 16;
5219
5220 adev->gds.oa.gfx_partition_size = 4;
5221 adev->gds.oa.cs_partition_size = 4;
5222 }
5223}
5224
5225
5226int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
5cb60bf6 5227 struct amdgpu_cu_info *cu_info)
a2e73f56
AD		 5228{
5229 int i, j, k, counter, active_cu_number = 0;
5230 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5231
5232 if (!adev || !cu_info)
5233 return -EINVAL;
5234
5235 mutex_lock(&adev->grbm_idx_mutex);
5236 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5237 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5238 mask = 1;
5239 ao_bitmap = 0;
5240 counter = 0;
8f8e00c1
AD		 5241 gfx_v7_0_select_se_sh(adev, i, j);
5242 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5243 cu_info->bitmap[i][j] = bitmap;
5244
8f8e00c1 5245 for (k = 0; k < 16; k ++) {
a2e73f56
AD		 5246 if (bitmap & mask) {
5247 if (counter < 2)
5248 ao_bitmap |= mask;
5249 counter ++;
5250 }
5251 mask <<= 1;
5252 }
5253 active_cu_number += counter;
5254 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5255 }
5256 }
8f8e00c1
AD		 5257 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5258 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5259
5260 cu_info->number = active_cu_number;
5261 cu_info->ao_cu_mask = ao_cu_mask;
8f8e00c1 5262
a2e73f56
AD		 5263 return 0;
5264}
Linux 6.x block layer and io_uring tree(s)