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drm/amdgpu/gfx7: switch to using the existing rlc callbacks
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
a2e73f56
AD		 34#include "dce/dce_8_0_d.h"
35#include "dce/dce_8_0_sh_mask.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gca/gfx_7_0_d.h"
41#include "gca/gfx_7_2_enum.h"
42#include "gca/gfx_7_2_sh_mask.h"
43
44#include "gmc/gmc_7_0_d.h"
45#include "gmc/gmc_7_0_sh_mask.h"
46
47#include "oss/oss_2_0_d.h"
48#include "oss/oss_2_0_sh_mask.h"
49
50#define GFX7_NUM_GFX_RINGS 1
51#define GFX7_NUM_COMPUTE_RINGS 8
52
53static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
a2e73f56
AD		 56
57MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58MODULE_FIRMWARE("radeon/bonaire_me.bin");
59MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61MODULE_FIRMWARE("radeon/bonaire_mec.bin");
62
63MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64MODULE_FIRMWARE("radeon/hawaii_me.bin");
65MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68
69MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70MODULE_FIRMWARE("radeon/kaveri_me.bin");
71MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
75
76MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77MODULE_FIRMWARE("radeon/kabini_me.bin");
78MODULE_FIRMWARE("radeon/kabini_ce.bin");
79MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80MODULE_FIRMWARE("radeon/kabini_mec.bin");
81
82MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83MODULE_FIRMWARE("radeon/mullins_me.bin");
84MODULE_FIRMWARE("radeon/mullins_ce.bin");
85MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86MODULE_FIRMWARE("radeon/mullins_mec.bin");
87
88static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
89{
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
106};
107
108static const u32 spectre_rlc_save_restore_register_list[] =
109{
110 (0x0e00 << 16) | (0xc12c >> 2),
111 0x00000000,
112 (0x0e00 << 16) | (0xc140 >> 2),
113 0x00000000,
114 (0x0e00 << 16) | (0xc150 >> 2),
115 0x00000000,
116 (0x0e00 << 16) | (0xc15c >> 2),
117 0x00000000,
118 (0x0e00 << 16) | (0xc168 >> 2),
119 0x00000000,
120 (0x0e00 << 16) | (0xc170 >> 2),
121 0x00000000,
122 (0x0e00 << 16) | (0xc178 >> 2),
123 0x00000000,
124 (0x0e00 << 16) | (0xc204 >> 2),
125 0x00000000,
126 (0x0e00 << 16) | (0xc2b4 >> 2),
127 0x00000000,
128 (0x0e00 << 16) | (0xc2b8 >> 2),
129 0x00000000,
130 (0x0e00 << 16) | (0xc2bc >> 2),
131 0x00000000,
132 (0x0e00 << 16) | (0xc2c0 >> 2),
133 0x00000000,
134 (0x0e00 << 16) | (0x8228 >> 2),
135 0x00000000,
136 (0x0e00 << 16) | (0x829c >> 2),
137 0x00000000,
138 (0x0e00 << 16) | (0x869c >> 2),
139 0x00000000,
140 (0x0600 << 16) | (0x98f4 >> 2),
141 0x00000000,
142 (0x0e00 << 16) | (0x98f8 >> 2),
143 0x00000000,
144 (0x0e00 << 16) | (0x9900 >> 2),
145 0x00000000,
146 (0x0e00 << 16) | (0xc260 >> 2),
147 0x00000000,
148 (0x0e00 << 16) | (0x90e8 >> 2),
149 0x00000000,
150 (0x0e00 << 16) | (0x3c000 >> 2),
151 0x00000000,
152 (0x0e00 << 16) | (0x3c00c >> 2),
153 0x00000000,
154 (0x0e00 << 16) | (0x8c1c >> 2),
155 0x00000000,
156 (0x0e00 << 16) | (0x9700 >> 2),
157 0x00000000,
158 (0x0e00 << 16) | (0xcd20 >> 2),
159 0x00000000,
160 (0x4e00 << 16) | (0xcd20 >> 2),
161 0x00000000,
162 (0x5e00 << 16) | (0xcd20 >> 2),
163 0x00000000,
164 (0x6e00 << 16) | (0xcd20 >> 2),
165 0x00000000,
166 (0x7e00 << 16) | (0xcd20 >> 2),
167 0x00000000,
168 (0x8e00 << 16) | (0xcd20 >> 2),
169 0x00000000,
170 (0x9e00 << 16) | (0xcd20 >> 2),
171 0x00000000,
172 (0xae00 << 16) | (0xcd20 >> 2),
173 0x00000000,
174 (0xbe00 << 16) | (0xcd20 >> 2),
175 0x00000000,
176 (0x0e00 << 16) | (0x89bc >> 2),
177 0x00000000,
178 (0x0e00 << 16) | (0x8900 >> 2),
179 0x00000000,
180 0x3,
181 (0x0e00 << 16) | (0xc130 >> 2),
182 0x00000000,
183 (0x0e00 << 16) | (0xc134 >> 2),
184 0x00000000,
185 (0x0e00 << 16) | (0xc1fc >> 2),
186 0x00000000,
187 (0x0e00 << 16) | (0xc208 >> 2),
188 0x00000000,
189 (0x0e00 << 16) | (0xc264 >> 2),
190 0x00000000,
191 (0x0e00 << 16) | (0xc268 >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc26c >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc270 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc274 >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc278 >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc27c >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc280 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc284 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc288 >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc28c >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc290 >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc294 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0xc298 >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0xc29c >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0xc2a0 >> 2),
220 0x00000000,
221 (0x0e00 << 16) | (0xc2a4 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0xc2a8 >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0xc2ac >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc2b0 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0x301d0 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0x30238 >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0x30250 >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x30254 >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x30258 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0x3025c >> 2),
240 0x00000000,
241 (0x4e00 << 16) | (0xc900 >> 2),
242 0x00000000,
243 (0x5e00 << 16) | (0xc900 >> 2),
244 0x00000000,
245 (0x6e00 << 16) | (0xc900 >> 2),
246 0x00000000,
247 (0x7e00 << 16) | (0xc900 >> 2),
248 0x00000000,
249 (0x8e00 << 16) | (0xc900 >> 2),
250 0x00000000,
251 (0x9e00 << 16) | (0xc900 >> 2),
252 0x00000000,
253 (0xae00 << 16) | (0xc900 >> 2),
254 0x00000000,
255 (0xbe00 << 16) | (0xc900 >> 2),
256 0x00000000,
257 (0x4e00 << 16) | (0xc904 >> 2),
258 0x00000000,
259 (0x5e00 << 16) | (0xc904 >> 2),
260 0x00000000,
261 (0x6e00 << 16) | (0xc904 >> 2),
262 0x00000000,
263 (0x7e00 << 16) | (0xc904 >> 2),
264 0x00000000,
265 (0x8e00 << 16) | (0xc904 >> 2),
266 0x00000000,
267 (0x9e00 << 16) | (0xc904 >> 2),
268 0x00000000,
269 (0xae00 << 16) | (0xc904 >> 2),
270 0x00000000,
271 (0xbe00 << 16) | (0xc904 >> 2),
272 0x00000000,
273 (0x4e00 << 16) | (0xc908 >> 2),
274 0x00000000,
275 (0x5e00 << 16) | (0xc908 >> 2),
276 0x00000000,
277 (0x6e00 << 16) | (0xc908 >> 2),
278 0x00000000,
279 (0x7e00 << 16) | (0xc908 >> 2),
280 0x00000000,
281 (0x8e00 << 16) | (0xc908 >> 2),
282 0x00000000,
283 (0x9e00 << 16) | (0xc908 >> 2),
284 0x00000000,
285 (0xae00 << 16) | (0xc908 >> 2),
286 0x00000000,
287 (0xbe00 << 16) | (0xc908 >> 2),
288 0x00000000,
289 (0x4e00 << 16) | (0xc90c >> 2),
290 0x00000000,
291 (0x5e00 << 16) | (0xc90c >> 2),
292 0x00000000,
293 (0x6e00 << 16) | (0xc90c >> 2),
294 0x00000000,
295 (0x7e00 << 16) | (0xc90c >> 2),
296 0x00000000,
297 (0x8e00 << 16) | (0xc90c >> 2),
298 0x00000000,
299 (0x9e00 << 16) | (0xc90c >> 2),
300 0x00000000,
301 (0xae00 << 16) | (0xc90c >> 2),
302 0x00000000,
303 (0xbe00 << 16) | (0xc90c >> 2),
304 0x00000000,
305 (0x4e00 << 16) | (0xc910 >> 2),
306 0x00000000,
307 (0x5e00 << 16) | (0xc910 >> 2),
308 0x00000000,
309 (0x6e00 << 16) | (0xc910 >> 2),
310 0x00000000,
311 (0x7e00 << 16) | (0xc910 >> 2),
312 0x00000000,
313 (0x8e00 << 16) | (0xc910 >> 2),
314 0x00000000,
315 (0x9e00 << 16) | (0xc910 >> 2),
316 0x00000000,
317 (0xae00 << 16) | (0xc910 >> 2),
318 0x00000000,
319 (0xbe00 << 16) | (0xc910 >> 2),
320 0x00000000,
321 (0x0e00 << 16) | (0xc99c >> 2),
322 0x00000000,
323 (0x0e00 << 16) | (0x9834 >> 2),
324 0x00000000,
325 (0x0000 << 16) | (0x30f00 >> 2),
326 0x00000000,
327 (0x0001 << 16) | (0x30f00 >> 2),
328 0x00000000,
329 (0x0000 << 16) | (0x30f04 >> 2),
330 0x00000000,
331 (0x0001 << 16) | (0x30f04 >> 2),
332 0x00000000,
333 (0x0000 << 16) | (0x30f08 >> 2),
334 0x00000000,
335 (0x0001 << 16) | (0x30f08 >> 2),
336 0x00000000,
337 (0x0000 << 16) | (0x30f0c >> 2),
338 0x00000000,
339 (0x0001 << 16) | (0x30f0c >> 2),
340 0x00000000,
341 (0x0600 << 16) | (0x9b7c >> 2),
342 0x00000000,
343 (0x0e00 << 16) | (0x8a14 >> 2),
344 0x00000000,
345 (0x0e00 << 16) | (0x8a18 >> 2),
346 0x00000000,
347 (0x0600 << 16) | (0x30a00 >> 2),
348 0x00000000,
349 (0x0e00 << 16) | (0x8bf0 >> 2),
350 0x00000000,
351 (0x0e00 << 16) | (0x8bcc >> 2),
352 0x00000000,
353 (0x0e00 << 16) | (0x8b24 >> 2),
354 0x00000000,
355 (0x0e00 << 16) | (0x30a04 >> 2),
356 0x00000000,
357 (0x0600 << 16) | (0x30a10 >> 2),
358 0x00000000,
359 (0x0600 << 16) | (0x30a14 >> 2),
360 0x00000000,
361 (0x0600 << 16) | (0x30a18 >> 2),
362 0x00000000,
363 (0x0600 << 16) | (0x30a2c >> 2),
364 0x00000000,
365 (0x0e00 << 16) | (0xc700 >> 2),
366 0x00000000,
367 (0x0e00 << 16) | (0xc704 >> 2),
368 0x00000000,
369 (0x0e00 << 16) | (0xc708 >> 2),
370 0x00000000,
371 (0x0e00 << 16) | (0xc768 >> 2),
372 0x00000000,
373 (0x0400 << 16) | (0xc770 >> 2),
374 0x00000000,
375 (0x0400 << 16) | (0xc774 >> 2),
376 0x00000000,
377 (0x0400 << 16) | (0xc778 >> 2),
378 0x00000000,
379 (0x0400 << 16) | (0xc77c >> 2),
380 0x00000000,
381 (0x0400 << 16) | (0xc780 >> 2),
382 0x00000000,
383 (0x0400 << 16) | (0xc784 >> 2),
384 0x00000000,
385 (0x0400 << 16) | (0xc788 >> 2),
386 0x00000000,
387 (0x0400 << 16) | (0xc78c >> 2),
388 0x00000000,
389 (0x0400 << 16) | (0xc798 >> 2),
390 0x00000000,
391 (0x0400 << 16) | (0xc79c >> 2),
392 0x00000000,
393 (0x0400 << 16) | (0xc7a0 >> 2),
394 0x00000000,
395 (0x0400 << 16) | (0xc7a4 >> 2),
396 0x00000000,
397 (0x0400 << 16) | (0xc7a8 >> 2),
398 0x00000000,
399 (0x0400 << 16) | (0xc7ac >> 2),
400 0x00000000,
401 (0x0400 << 16) | (0xc7b0 >> 2),
402 0x00000000,
403 (0x0400 << 16) | (0xc7b4 >> 2),
404 0x00000000,
405 (0x0e00 << 16) | (0x9100 >> 2),
406 0x00000000,
407 (0x0e00 << 16) | (0x3c010 >> 2),
408 0x00000000,
409 (0x0e00 << 16) | (0x92a8 >> 2),
410 0x00000000,
411 (0x0e00 << 16) | (0x92ac >> 2),
412 0x00000000,
413 (0x0e00 << 16) | (0x92b4 >> 2),
414 0x00000000,
415 (0x0e00 << 16) | (0x92b8 >> 2),
416 0x00000000,
417 (0x0e00 << 16) | (0x92bc >> 2),
418 0x00000000,
419 (0x0e00 << 16) | (0x92c0 >> 2),
420 0x00000000,
421 (0x0e00 << 16) | (0x92c4 >> 2),
422 0x00000000,
423 (0x0e00 << 16) | (0x92c8 >> 2),
424 0x00000000,
425 (0x0e00 << 16) | (0x92cc >> 2),
426 0x00000000,
427 (0x0e00 << 16) | (0x92d0 >> 2),
428 0x00000000,
429 (0x0e00 << 16) | (0x8c00 >> 2),
430 0x00000000,
431 (0x0e00 << 16) | (0x8c04 >> 2),
432 0x00000000,
433 (0x0e00 << 16) | (0x8c20 >> 2),
434 0x00000000,
435 (0x0e00 << 16) | (0x8c38 >> 2),
436 0x00000000,
437 (0x0e00 << 16) | (0x8c3c >> 2),
438 0x00000000,
439 (0x0e00 << 16) | (0xae00 >> 2),
440 0x00000000,
441 (0x0e00 << 16) | (0x9604 >> 2),
442 0x00000000,
443 (0x0e00 << 16) | (0xac08 >> 2),
444 0x00000000,
445 (0x0e00 << 16) | (0xac0c >> 2),
446 0x00000000,
447 (0x0e00 << 16) | (0xac10 >> 2),
448 0x00000000,
449 (0x0e00 << 16) | (0xac14 >> 2),
450 0x00000000,
451 (0x0e00 << 16) | (0xac58 >> 2),
452 0x00000000,
453 (0x0e00 << 16) | (0xac68 >> 2),
454 0x00000000,
455 (0x0e00 << 16) | (0xac6c >> 2),
456 0x00000000,
457 (0x0e00 << 16) | (0xac70 >> 2),
458 0x00000000,
459 (0x0e00 << 16) | (0xac74 >> 2),
460 0x00000000,
461 (0x0e00 << 16) | (0xac78 >> 2),
462 0x00000000,
463 (0x0e00 << 16) | (0xac7c >> 2),
464 0x00000000,
465 (0x0e00 << 16) | (0xac80 >> 2),
466 0x00000000,
467 (0x0e00 << 16) | (0xac84 >> 2),
468 0x00000000,
469 (0x0e00 << 16) | (0xac88 >> 2),
470 0x00000000,
471 (0x0e00 << 16) | (0xac8c >> 2),
472 0x00000000,
473 (0x0e00 << 16) | (0x970c >> 2),
474 0x00000000,
475 (0x0e00 << 16) | (0x9714 >> 2),
476 0x00000000,
477 (0x0e00 << 16) | (0x9718 >> 2),
478 0x00000000,
479 (0x0e00 << 16) | (0x971c >> 2),
480 0x00000000,
481 (0x0e00 << 16) | (0x31068 >> 2),
482 0x00000000,
483 (0x4e00 << 16) | (0x31068 >> 2),
484 0x00000000,
485 (0x5e00 << 16) | (0x31068 >> 2),
486 0x00000000,
487 (0x6e00 << 16) | (0x31068 >> 2),
488 0x00000000,
489 (0x7e00 << 16) | (0x31068 >> 2),
490 0x00000000,
491 (0x8e00 << 16) | (0x31068 >> 2),
492 0x00000000,
493 (0x9e00 << 16) | (0x31068 >> 2),
494 0x00000000,
495 (0xae00 << 16) | (0x31068 >> 2),
496 0x00000000,
497 (0xbe00 << 16) | (0x31068 >> 2),
498 0x00000000,
499 (0x0e00 << 16) | (0xcd10 >> 2),
500 0x00000000,
501 (0x0e00 << 16) | (0xcd14 >> 2),
502 0x00000000,
503 (0x0e00 << 16) | (0x88b0 >> 2),
504 0x00000000,
505 (0x0e00 << 16) | (0x88b4 >> 2),
506 0x00000000,
507 (0x0e00 << 16) | (0x88b8 >> 2),
508 0x00000000,
509 (0x0e00 << 16) | (0x88bc >> 2),
510 0x00000000,
511 (0x0400 << 16) | (0x89c0 >> 2),
512 0x00000000,
513 (0x0e00 << 16) | (0x88c4 >> 2),
514 0x00000000,
515 (0x0e00 << 16) | (0x88c8 >> 2),
516 0x00000000,
517 (0x0e00 << 16) | (0x88d0 >> 2),
518 0x00000000,
519 (0x0e00 << 16) | (0x88d4 >> 2),
520 0x00000000,
521 (0x0e00 << 16) | (0x88d8 >> 2),
522 0x00000000,
523 (0x0e00 << 16) | (0x8980 >> 2),
524 0x00000000,
525 (0x0e00 << 16) | (0x30938 >> 2),
526 0x00000000,
527 (0x0e00 << 16) | (0x3093c >> 2),
528 0x00000000,
529 (0x0e00 << 16) | (0x30940 >> 2),
530 0x00000000,
531 (0x0e00 << 16) | (0x89a0 >> 2),
532 0x00000000,
533 (0x0e00 << 16) | (0x30900 >> 2),
534 0x00000000,
535 (0x0e00 << 16) | (0x30904 >> 2),
536 0x00000000,
537 (0x0e00 << 16) | (0x89b4 >> 2),
538 0x00000000,
539 (0x0e00 << 16) | (0x3c210 >> 2),
540 0x00000000,
541 (0x0e00 << 16) | (0x3c214 >> 2),
542 0x00000000,
543 (0x0e00 << 16) | (0x3c218 >> 2),
544 0x00000000,
545 (0x0e00 << 16) | (0x8904 >> 2),
546 0x00000000,
547 0x5,
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
553};
554
555static const u32 kalindi_rlc_save_restore_register_list[] =
556{
557 (0x0e00 << 16) | (0xc12c >> 2),
558 0x00000000,
559 (0x0e00 << 16) | (0xc140 >> 2),
560 0x00000000,
561 (0x0e00 << 16) | (0xc150 >> 2),
562 0x00000000,
563 (0x0e00 << 16) | (0xc15c >> 2),
564 0x00000000,
565 (0x0e00 << 16) | (0xc168 >> 2),
566 0x00000000,
567 (0x0e00 << 16) | (0xc170 >> 2),
568 0x00000000,
569 (0x0e00 << 16) | (0xc204 >> 2),
570 0x00000000,
571 (0x0e00 << 16) | (0xc2b4 >> 2),
572 0x00000000,
573 (0x0e00 << 16) | (0xc2b8 >> 2),
574 0x00000000,
575 (0x0e00 << 16) | (0xc2bc >> 2),
576 0x00000000,
577 (0x0e00 << 16) | (0xc2c0 >> 2),
578 0x00000000,
579 (0x0e00 << 16) | (0x8228 >> 2),
580 0x00000000,
581 (0x0e00 << 16) | (0x829c >> 2),
582 0x00000000,
583 (0x0e00 << 16) | (0x869c >> 2),
584 0x00000000,
585 (0x0600 << 16) | (0x98f4 >> 2),
586 0x00000000,
587 (0x0e00 << 16) | (0x98f8 >> 2),
588 0x00000000,
589 (0x0e00 << 16) | (0x9900 >> 2),
590 0x00000000,
591 (0x0e00 << 16) | (0xc260 >> 2),
592 0x00000000,
593 (0x0e00 << 16) | (0x90e8 >> 2),
594 0x00000000,
595 (0x0e00 << 16) | (0x3c000 >> 2),
596 0x00000000,
597 (0x0e00 << 16) | (0x3c00c >> 2),
598 0x00000000,
599 (0x0e00 << 16) | (0x8c1c >> 2),
600 0x00000000,
601 (0x0e00 << 16) | (0x9700 >> 2),
602 0x00000000,
603 (0x0e00 << 16) | (0xcd20 >> 2),
604 0x00000000,
605 (0x4e00 << 16) | (0xcd20 >> 2),
606 0x00000000,
607 (0x5e00 << 16) | (0xcd20 >> 2),
608 0x00000000,
609 (0x6e00 << 16) | (0xcd20 >> 2),
610 0x00000000,
611 (0x7e00 << 16) | (0xcd20 >> 2),
612 0x00000000,
613 (0x0e00 << 16) | (0x89bc >> 2),
614 0x00000000,
615 (0x0e00 << 16) | (0x8900 >> 2),
616 0x00000000,
617 0x3,
618 (0x0e00 << 16) | (0xc130 >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0xc134 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xc1fc >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xc208 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xc264 >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xc268 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xc26c >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xc270 >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xc274 >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0xc28c >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0xc290 >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc294 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc298 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc2a0 >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc2a4 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc2a8 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc2ac >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0x301d0 >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0x30238 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0x30250 >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0x30254 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x30258 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x3025c >> 2),
663 0x00000000,
664 (0x4e00 << 16) | (0xc900 >> 2),
665 0x00000000,
666 (0x5e00 << 16) | (0xc900 >> 2),
667 0x00000000,
668 (0x6e00 << 16) | (0xc900 >> 2),
669 0x00000000,
670 (0x7e00 << 16) | (0xc900 >> 2),
671 0x00000000,
672 (0x4e00 << 16) | (0xc904 >> 2),
673 0x00000000,
674 (0x5e00 << 16) | (0xc904 >> 2),
675 0x00000000,
676 (0x6e00 << 16) | (0xc904 >> 2),
677 0x00000000,
678 (0x7e00 << 16) | (0xc904 >> 2),
679 0x00000000,
680 (0x4e00 << 16) | (0xc908 >> 2),
681 0x00000000,
682 (0x5e00 << 16) | (0xc908 >> 2),
683 0x00000000,
684 (0x6e00 << 16) | (0xc908 >> 2),
685 0x00000000,
686 (0x7e00 << 16) | (0xc908 >> 2),
687 0x00000000,
688 (0x4e00 << 16) | (0xc90c >> 2),
689 0x00000000,
690 (0x5e00 << 16) | (0xc90c >> 2),
691 0x00000000,
692 (0x6e00 << 16) | (0xc90c >> 2),
693 0x00000000,
694 (0x7e00 << 16) | (0xc90c >> 2),
695 0x00000000,
696 (0x4e00 << 16) | (0xc910 >> 2),
697 0x00000000,
698 (0x5e00 << 16) | (0xc910 >> 2),
699 0x00000000,
700 (0x6e00 << 16) | (0xc910 >> 2),
701 0x00000000,
702 (0x7e00 << 16) | (0xc910 >> 2),
703 0x00000000,
704 (0x0e00 << 16) | (0xc99c >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0x9834 >> 2),
707 0x00000000,
708 (0x0000 << 16) | (0x30f00 >> 2),
709 0x00000000,
710 (0x0000 << 16) | (0x30f04 >> 2),
711 0x00000000,
712 (0x0000 << 16) | (0x30f08 >> 2),
713 0x00000000,
714 (0x0000 << 16) | (0x30f0c >> 2),
715 0x00000000,
716 (0x0600 << 16) | (0x9b7c >> 2),
717 0x00000000,
718 (0x0e00 << 16) | (0x8a14 >> 2),
719 0x00000000,
720 (0x0e00 << 16) | (0x8a18 >> 2),
721 0x00000000,
722 (0x0600 << 16) | (0x30a00 >> 2),
723 0x00000000,
724 (0x0e00 << 16) | (0x8bf0 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0x8bcc >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0x8b24 >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0x30a04 >> 2),
731 0x00000000,
732 (0x0600 << 16) | (0x30a10 >> 2),
733 0x00000000,
734 (0x0600 << 16) | (0x30a14 >> 2),
735 0x00000000,
736 (0x0600 << 16) | (0x30a18 >> 2),
737 0x00000000,
738 (0x0600 << 16) | (0x30a2c >> 2),
739 0x00000000,
740 (0x0e00 << 16) | (0xc700 >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0xc704 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0xc708 >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0xc768 >> 2),
747 0x00000000,
748 (0x0400 << 16) | (0xc770 >> 2),
749 0x00000000,
750 (0x0400 << 16) | (0xc774 >> 2),
751 0x00000000,
752 (0x0400 << 16) | (0xc798 >> 2),
753 0x00000000,
754 (0x0400 << 16) | (0xc79c >> 2),
755 0x00000000,
756 (0x0e00 << 16) | (0x9100 >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x3c010 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x8c00 >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c04 >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x8c20 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0x8c38 >> 2),
767 0x00000000,
768 (0x0e00 << 16) | (0x8c3c >> 2),
769 0x00000000,
770 (0x0e00 << 16) | (0xae00 >> 2),
771 0x00000000,
772 (0x0e00 << 16) | (0x9604 >> 2),
773 0x00000000,
774 (0x0e00 << 16) | (0xac08 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0xac0c >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0xac10 >> 2),
779 0x00000000,
780 (0x0e00 << 16) | (0xac14 >> 2),
781 0x00000000,
782 (0x0e00 << 16) | (0xac58 >> 2),
783 0x00000000,
784 (0x0e00 << 16) | (0xac68 >> 2),
785 0x00000000,
786 (0x0e00 << 16) | (0xac6c >> 2),
787 0x00000000,
788 (0x0e00 << 16) | (0xac70 >> 2),
789 0x00000000,
790 (0x0e00 << 16) | (0xac74 >> 2),
791 0x00000000,
792 (0x0e00 << 16) | (0xac78 >> 2),
793 0x00000000,
794 (0x0e00 << 16) | (0xac7c >> 2),
795 0x00000000,
796 (0x0e00 << 16) | (0xac80 >> 2),
797 0x00000000,
798 (0x0e00 << 16) | (0xac84 >> 2),
799 0x00000000,
800 (0x0e00 << 16) | (0xac88 >> 2),
801 0x00000000,
802 (0x0e00 << 16) | (0xac8c >> 2),
803 0x00000000,
804 (0x0e00 << 16) | (0x970c >> 2),
805 0x00000000,
806 (0x0e00 << 16) | (0x9714 >> 2),
807 0x00000000,
808 (0x0e00 << 16) | (0x9718 >> 2),
809 0x00000000,
810 (0x0e00 << 16) | (0x971c >> 2),
811 0x00000000,
812 (0x0e00 << 16) | (0x31068 >> 2),
813 0x00000000,
814 (0x4e00 << 16) | (0x31068 >> 2),
815 0x00000000,
816 (0x5e00 << 16) | (0x31068 >> 2),
817 0x00000000,
818 (0x6e00 << 16) | (0x31068 >> 2),
819 0x00000000,
820 (0x7e00 << 16) | (0x31068 >> 2),
821 0x00000000,
822 (0x0e00 << 16) | (0xcd10 >> 2),
823 0x00000000,
824 (0x0e00 << 16) | (0xcd14 >> 2),
825 0x00000000,
826 (0x0e00 << 16) | (0x88b0 >> 2),
827 0x00000000,
828 (0x0e00 << 16) | (0x88b4 >> 2),
829 0x00000000,
830 (0x0e00 << 16) | (0x88b8 >> 2),
831 0x00000000,
832 (0x0e00 << 16) | (0x88bc >> 2),
833 0x00000000,
834 (0x0400 << 16) | (0x89c0 >> 2),
835 0x00000000,
836 (0x0e00 << 16) | (0x88c4 >> 2),
837 0x00000000,
838 (0x0e00 << 16) | (0x88c8 >> 2),
839 0x00000000,
840 (0x0e00 << 16) | (0x88d0 >> 2),
841 0x00000000,
842 (0x0e00 << 16) | (0x88d4 >> 2),
843 0x00000000,
844 (0x0e00 << 16) | (0x88d8 >> 2),
845 0x00000000,
846 (0x0e00 << 16) | (0x8980 >> 2),
847 0x00000000,
848 (0x0e00 << 16) | (0x30938 >> 2),
849 0x00000000,
850 (0x0e00 << 16) | (0x3093c >> 2),
851 0x00000000,
852 (0x0e00 << 16) | (0x30940 >> 2),
853 0x00000000,
854 (0x0e00 << 16) | (0x89a0 >> 2),
855 0x00000000,
856 (0x0e00 << 16) | (0x30900 >> 2),
857 0x00000000,
858 (0x0e00 << 16) | (0x30904 >> 2),
859 0x00000000,
860 (0x0e00 << 16) | (0x89b4 >> 2),
861 0x00000000,
862 (0x0e00 << 16) | (0x3e1fc >> 2),
863 0x00000000,
864 (0x0e00 << 16) | (0x3c210 >> 2),
865 0x00000000,
866 (0x0e00 << 16) | (0x3c214 >> 2),
867 0x00000000,
868 (0x0e00 << 16) | (0x3c218 >> 2),
869 0x00000000,
870 (0x0e00 << 16) | (0x8904 >> 2),
871 0x00000000,
872 0x5,
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
878};
879
880static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
7dae69a2 884static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
a2e73f56
AD		 885
886/*
887 * Core functions
888 */
889/**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899{
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992}
993
e517cd77
ML		 994static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
995{
996 release_firmware(adev->gfx.pfp_fw);
997 adev->gfx.pfp_fw = NULL;
998 release_firmware(adev->gfx.me_fw);
999 adev->gfx.me_fw = NULL;
1000 release_firmware(adev->gfx.ce_fw);
1001 adev->gfx.ce_fw = NULL;
1002 release_firmware(adev->gfx.mec_fw);
1003 adev->gfx.mec_fw = NULL;
1004 release_firmware(adev->gfx.mec2_fw);
1005 adev->gfx.mec2_fw = NULL;
1006 release_firmware(adev->gfx.rlc_fw);
1007 adev->gfx.rlc_fw = NULL;
1008}
1009
a2e73f56
AD		 1010/**
1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1012 *
1013 * @adev: amdgpu_device pointer
1014 *
1015 * Starting with SI, the tiling setup is done globally in a
1016 * set of 32 tiling modes. Rather than selecting each set of
1017 * parameters per surface as on older asics, we just select
1018 * which index in the tiling table we want to use, and the
1019 * surface uses those parameters (CIK).
1020 */
1021static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1022{
840a20d3
TSD		 1023 const u32 num_tile_mode_states =
1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1025 const u32 num_secondary_tile_mode_states =
1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1027 u32 reg_offset, split_equal_to_row_size;
1028 uint32_t *tile, *macrotile;
1029
1030 tile = adev->gfx.config.tile_mode_array;
1031 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1032
1033 switch (adev->gfx.config.mem_row_size_in_kb) {
1034 case 1:
1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1036 break;
1037 case 2:
1038 default:
1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1040 break;
1041 case 4:
1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1043 break;
1044 }
1045
840a20d3
TSD		 1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1047 tile[reg_offset] = 0;
1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1049 macrotile[reg_offset] = 0;
1050
a2e73f56
AD		 1051 switch (adev->asic_type) {
1052 case CHIP_BONAIRE:
840a20d3
TSD		 1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1072 TILE_SPLIT(split_equal_to_row_size));
1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1079 TILE_SPLIT(split_equal_to_row_size));
1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1155
1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163 NUM_BANKS(ADDR_SURF_16_BANK));
1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167 NUM_BANKS(ADDR_SURF_16_BANK));
1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_4_BANK));
1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191 NUM_BANKS(ADDR_SURF_16_BANK));
1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1195 NUM_BANKS(ADDR_SURF_16_BANK));
1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1203 NUM_BANKS(ADDR_SURF_16_BANK));
1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1207 NUM_BANKS(ADDR_SURF_8_BANK));
1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1212
840a20d3
TSD		 1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1216 if (reg_offset != 7)
1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1218 break;
1219 case CHIP_HAWAII:
840a20d3
TSD		 1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1239 TILE_SPLIT(split_equal_to_row_size));
1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1243 TILE_SPLIT(split_equal_to_row_size));
1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1247 TILE_SPLIT(split_equal_to_row_size));
1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1251 TILE_SPLIT(split_equal_to_row_size));
1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1338
840a20d3
TSD		 1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342 NUM_BANKS(ADDR_SURF_16_BANK));
1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346 NUM_BANKS(ADDR_SURF_16_BANK));
1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_16_BANK));
1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1358 NUM_BANKS(ADDR_SURF_8_BANK));
1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_4_BANK));
1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_4_BANK));
1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_16_BANK));
1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_16_BANK));
1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1382 NUM_BANKS(ADDR_SURF_8_BANK));
1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1386 NUM_BANKS(ADDR_SURF_16_BANK));
1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1390 NUM_BANKS(ADDR_SURF_8_BANK));
1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1394 NUM_BANKS(ADDR_SURF_4_BANK));
1395
1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1399 if (reg_offset != 7)
1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1401 break;
1402 case CHIP_KABINI:
1403 case CHIP_KAVERI:
1404 case CHIP_MULLINS:
1405 default:
840a20d3
TSD		 1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415 PIPE_CONFIG(ADDR_SURF_P2) |
1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P2) |
1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 PIPE_CONFIG(ADDR_SURF_P2) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1425 TILE_SPLIT(split_equal_to_row_size));
1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1427 PIPE_CONFIG(ADDR_SURF_P2) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430 PIPE_CONFIG(ADDR_SURF_P2) |
1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1432 TILE_SPLIT(split_equal_to_row_size));
1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1435 PIPE_CONFIG(ADDR_SURF_P2));
1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452 PIPE_CONFIG(ADDR_SURF_P2) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1465 PIPE_CONFIG(ADDR_SURF_P2) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472 PIPE_CONFIG(ADDR_SURF_P2) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1476 PIPE_CONFIG(ADDR_SURF_P2) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1480 PIPE_CONFIG(ADDR_SURF_P2) |
1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1485 PIPE_CONFIG(ADDR_SURF_P2) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1489 PIPE_CONFIG(ADDR_SURF_P2) |
1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1493 PIPE_CONFIG(ADDR_SURF_P2) |
1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P2) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500 PIPE_CONFIG(ADDR_SURF_P2) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1504 PIPE_CONFIG(ADDR_SURF_P2) |
1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1508
1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1524 NUM_BANKS(ADDR_SURF_8_BANK));
1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1528 NUM_BANKS(ADDR_SURF_8_BANK));
1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532 NUM_BANKS(ADDR_SURF_8_BANK));
1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536 NUM_BANKS(ADDR_SURF_8_BANK));
1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548 NUM_BANKS(ADDR_SURF_16_BANK));
1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1552 NUM_BANKS(ADDR_SURF_16_BANK));
1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1556 NUM_BANKS(ADDR_SURF_16_BANK));
1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1560 NUM_BANKS(ADDR_SURF_16_BANK));
1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1564 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1565
840a20d3
TSD		 1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1569 if (reg_offset != 7)
1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1571 break;
1572 }
1573}
1574
1575/**
1576 * gfx_v7_0_select_se_sh - select which SE, SH to address
1577 *
1578 * @adev: amdgpu_device pointer
1579 * @se_num: shader engine to address
1580 * @sh_num: sh block to address
1581 *
1582 * Select which SE, SH combinations to address. Certain
1583 * registers are instanced per SE or SH. 0xffffffff means
1584 * broadcast to all SEs or SHs (CIK).
1585 */
05fb7291
AD		 1586static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1587 u32 se_num, u32 sh_num)
a2e73f56
AD		 1588{
1589 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1590
1591 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1592 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1593 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1594 else if (se_num == 0xffffffff)
1595 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1596 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1597 else if (sh_num == 0xffffffff)
1598 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1599 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1600 else
1601 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1602 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1603 WREG32(mmGRBM_GFX_INDEX, data);
1604}
1605
1606/**
1607 * gfx_v7_0_create_bitmask - create a bitmask
1608 *
1609 * @bit_width: length of the mask
1610 *
1611 * create a variable length bit mask (CIK).
1612 * Returns the bitmask.
1613 */
1614static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1615{
8f8e00c1 1616 return (u32)((1ULL << bit_width) - 1);
a2e73f56
AD		 1617}
1618
1619/**
8f8e00c1 1620 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1621 *
1622 * @adev: amdgpu_device pointer
a2e73f56 1623 *
8f8e00c1
AD		 1624 * Calculates the bitmask of enabled RBs (CIK).
1625 * Returns the enabled RB bitmask.
a2e73f56 1626 */
8f8e00c1 1627static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1628{
1629 u32 data, mask;
1630
1631 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1632 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1633
8f8e00c1 1634 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1635 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1636
8f8e00c1
AD		 1637 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1638 adev->gfx.config.max_sh_per_se);
a2e73f56 1639
8f8e00c1 1640 return (~data) & mask;
a2e73f56
AD		 1641}
1642
1643/**
1644 * gfx_v7_0_setup_rb - setup the RBs on the asic
1645 *
1646 * @adev: amdgpu_device pointer
1647 * @se_num: number of SEs (shader engines) for the asic
1648 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1649 *
1650 * Configures per-SE/SH RB registers (CIK).
1651 */
8f8e00c1 1652static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1653{
1654 int i, j;
aac1e3ca 1655 u32 data;
8f8e00c1 1656 u32 active_rbs = 0;
6157bd7a
FC		 1657 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1658 adev->gfx.config.max_sh_per_se;
a2e73f56
AD		 1659
1660 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1661 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1662 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
a2e73f56 1663 gfx_v7_0_select_se_sh(adev, i, j);
8f8e00c1 1664 data = gfx_v7_0_get_rb_active_bitmap(adev);
6157bd7a
FC		 1665 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1666 rb_bitmap_width_per_sh);
a2e73f56
AD		 1667 }
1668 }
1669 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1670 mutex_unlock(&adev->grbm_idx_mutex);
1671
8f8e00c1 1672 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 1673 adev->gfx.config.num_rbs = hweight32(active_rbs);
a2e73f56
AD		 1674}
1675
cd06bf68
BG		 1676/**
1677 * gmc_v7_0_init_compute_vmid - gart enable
1678 *
1679 * @rdev: amdgpu_device pointer
1680 *
1681 * Initialize compute vmid sh_mem registers
1682 *
1683 */
1684#define DEFAULT_SH_MEM_BASES (0x6000)
1685#define FIRST_COMPUTE_VMID (8)
1686#define LAST_COMPUTE_VMID (16)
1687static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1688{
1689 int i;
1690 uint32_t sh_mem_config;
1691 uint32_t sh_mem_bases;
1692
1693 /*
1694 * Configure apertures:
1695 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1696 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1697 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1698 */
1699 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1700 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1701 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1702 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1703 mutex_lock(&adev->srbm_mutex);
1704 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1705 cik_srbm_select(adev, 0, 0, 0, i);
1706 /* CP and shaders */
1707 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1708 WREG32(mmSH_MEM_APE1_BASE, 1);
1709 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1710 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1711 }
1712 cik_srbm_select(adev, 0, 0, 0, 0);
1713 mutex_unlock(&adev->srbm_mutex);
1714}
1715
a2e73f56
AD		 1716/**
1717 * gfx_v7_0_gpu_init - setup the 3D engine
1718 *
1719 * @adev: amdgpu_device pointer
1720 *
1721 * Configures the 3D engine and tiling configuration
1722 * registers so that the 3D engine is usable.
1723 */
1724static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1725{
d93f3ca7 1726 u32 tmp, sh_mem_cfg;
a2e73f56
AD		 1727 int i;
1728
a2e73f56
AD		 1729 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1730
d93f3ca7
AD		 1731 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1732 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1733 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1734
1735 gfx_v7_0_tiling_mode_table_init(adev);
1736
8f8e00c1 1737 gfx_v7_0_setup_rb(adev);
7dae69a2 1738 gfx_v7_0_get_cu_info(adev);
a2e73f56
AD		 1739
1740 /* set HW defaults for 3D engine */
1741 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1742 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1743 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1744
1745 mutex_lock(&adev->grbm_idx_mutex);
1746 /*
1747 * making sure that the following register writes will be broadcasted
1748 * to all the shaders
1749 */
1750 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1751
1752 /* XXX SH_MEM regs */
1753 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1754 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165
JX		 1755 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1756
a2e73f56
AD		 1757 mutex_lock(&adev->srbm_mutex);
1758 for (i = 0; i < 16; i++) {
1759 cik_srbm_select(adev, 0, 0, 0, i);
1760 /* CP and shaders */
74a5d165 1761 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1762 WREG32(mmSH_MEM_APE1_BASE, 1);
1763 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1764 WREG32(mmSH_MEM_BASES, 0);
1765 }
1766 cik_srbm_select(adev, 0, 0, 0, 0);
1767 mutex_unlock(&adev->srbm_mutex);
1768
cd06bf68
BG		 1769 gmc_v7_0_init_compute_vmid(adev);
1770
a2e73f56
AD		 1771 WREG32(mmSX_DEBUG_1, 0x20);
1772
1773 WREG32(mmTA_CNTL_AUX, 0x00010000);
1774
1775 tmp = RREG32(mmSPI_CONFIG_CNTL);
1776 tmp |= 0x03000000;
1777 WREG32(mmSPI_CONFIG_CNTL, tmp);
1778
1779 WREG32(mmSQ_CONFIG, 1);
1780
1781 WREG32(mmDB_DEBUG, 0);
1782
1783 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1784 tmp |= 0x00000400;
1785 WREG32(mmDB_DEBUG2, tmp);
1786
1787 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1788 tmp |= 0x00020200;
1789 WREG32(mmDB_DEBUG3, tmp);
1790
1791 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1792 tmp |= 0x00018208;
1793 WREG32(mmCB_HW_CONTROL, tmp);
1794
1795 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1796
1797 WREG32(mmPA_SC_FIFO_SIZE,
1798 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1799 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1800 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1801 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1802
1803 WREG32(mmVGT_NUM_INSTANCES, 1);
1804
1805 WREG32(mmCP_PERFMON_CNTL, 0);
1806
1807 WREG32(mmSQ_CONFIG, 0);
1808
1809 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1810 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1811 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1812
1813 WREG32(mmVGT_CACHE_INVALIDATION,
1814 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1815 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1816
1817 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1818 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1819
1820 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1821 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1822 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1823 mutex_unlock(&adev->grbm_idx_mutex);
1824
1825 udelay(50);
1826}
1827
1828/*
1829 * GPU scratch registers helpers function.
1830 */
1831/**
1832 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1833 *
1834 * @adev: amdgpu_device pointer
1835 *
1836 * Set up the number and offset of the CP scratch registers.
1837 * NOTE: use of CP scratch registers is a legacy inferface and
1838 * is not used by default on newer asics (r6xx+). On newer asics,
1839 * memory buffers are used for fences rather than scratch regs.
1840 */
1841static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1842{
1843 int i;
1844
1845 adev->gfx.scratch.num_reg = 7;
1846 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1847 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1848 adev->gfx.scratch.free[i] = true;
1849 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1850 }
1851}
1852
1853/**
1854 * gfx_v7_0_ring_test_ring - basic gfx ring test
1855 *
1856 * @adev: amdgpu_device pointer
1857 * @ring: amdgpu_ring structure holding ring information
1858 *
1859 * Allocate a scratch register and write to it using the gfx ring (CIK).
1860 * Provides a basic gfx ring test to verify that the ring is working.
1861 * Used by gfx_v7_0_cp_gfx_resume();
1862 * Returns 0 on success, error on failure.
1863 */
1864static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1865{
1866 struct amdgpu_device *adev = ring->adev;
1867 uint32_t scratch;
1868 uint32_t tmp = 0;
1869 unsigned i;
1870 int r;
1871
1872 r = amdgpu_gfx_scratch_get(adev, &scratch);
1873 if (r) {
1874 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1875 return r;
1876 }
1877 WREG32(scratch, 0xCAFEDEAD);
a27de35c 1878 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 1879 if (r) {
1880 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1881 amdgpu_gfx_scratch_free(adev, scratch);
1882 return r;
1883 }
1884 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1885 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1886 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 1887 amdgpu_ring_commit(ring);
a2e73f56
AD		 1888
1889 for (i = 0; i < adev->usec_timeout; i++) {
1890 tmp = RREG32(scratch);
1891 if (tmp == 0xDEADBEEF)
1892 break;
1893 DRM_UDELAY(1);
1894 }
1895 if (i < adev->usec_timeout) {
1896 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1897 } else {
1898 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1899 ring->idx, scratch, tmp);
1900 r = -EINVAL;
1901 }
1902 amdgpu_gfx_scratch_free(adev, scratch);
1903 return r;
1904}
1905
1906/**
d2edb07b 1907 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 1908 *
1909 * @adev: amdgpu_device pointer
1910 * @ridx: amdgpu ring index
1911 *
1912 * Emits an hdp flush on the cp.
1913 */
d2edb07b 1914static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 1915{
1916 u32 ref_and_mask;
d9b5327a 1917 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56
AD		 1918
1919 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1920 switch (ring->me) {
1921 case 1:
1922 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1923 break;
1924 case 2:
1925 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1926 break;
1927 default:
1928 return;
1929 }
1930 } else {
1931 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1932 }
1933
1934 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1935 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1936 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 1937 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 1938 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1939 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1940 amdgpu_ring_write(ring, ref_and_mask);
1941 amdgpu_ring_write(ring, ref_and_mask);
1942 amdgpu_ring_write(ring, 0x20); /* poll interval */
1943}
1944
0955860b
CZ		 1945/**
1946 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1947 *
1948 * @adev: amdgpu_device pointer
1949 * @ridx: amdgpu ring index
1950 *
1951 * Emits an hdp invalidate on the cp.
1952 */
1953static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1954{
1955 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1956 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1957 WRITE_DATA_DST_SEL(0) |
1958 WR_CONFIRM));
1959 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1960 amdgpu_ring_write(ring, 0);
1961 amdgpu_ring_write(ring, 1);
1962}
1963
a2e73f56
AD		 1964/**
1965 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1966 *
1967 * @adev: amdgpu_device pointer
1968 * @fence: amdgpu fence object
1969 *
1970 * Emits a fence sequnce number on the gfx ring and flushes
1971 * GPU caches.
1972 */
1973static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 1974 u64 seq, unsigned flags)
a2e73f56 1975{
890ee23f
CZ		 1976 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1977 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 1978 /* Workaround for cache flush problems. First send a dummy EOP
1979 * event down the pipe with seq one below.
1980 */
1981 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1982 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1983 EOP_TC_ACTION_EN |
1984 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1985 EVENT_INDEX(5)));
1986 amdgpu_ring_write(ring, addr & 0xfffffffc);
1987 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1988 DATA_SEL(1) | INT_SEL(0));
1989 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1990 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1991
1992 /* Then send the real EOP event down the pipe. */
1993 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1994 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1995 EOP_TC_ACTION_EN |
1996 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1997 EVENT_INDEX(5)));
1998 amdgpu_ring_write(ring, addr & 0xfffffffc);
1999 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 2000 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2001 amdgpu_ring_write(ring, lower_32_bits(seq));
2002 amdgpu_ring_write(ring, upper_32_bits(seq));
2003}
2004
2005/**
2006 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2007 *
2008 * @adev: amdgpu_device pointer
2009 * @fence: amdgpu fence object
2010 *
2011 * Emits a fence sequnce number on the compute ring and flushes
2012 * GPU caches.
2013 */
2014static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2015 u64 addr, u64 seq,
890ee23f 2016 unsigned flags)
a2e73f56 2017{
890ee23f
CZ		 2018 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2019 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2020
a2e73f56
AD		 2021 /* RELEASE_MEM - flush caches, send int */
2022 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2023 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2024 EOP_TC_ACTION_EN |
2025 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2026 EVENT_INDEX(5)));
890ee23f 2027 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2028 amdgpu_ring_write(ring, addr & 0xfffffffc);
2029 amdgpu_ring_write(ring, upper_32_bits(addr));
2030 amdgpu_ring_write(ring, lower_32_bits(seq));
2031 amdgpu_ring_write(ring, upper_32_bits(seq));
2032}
2033
a2e73f56
AD		 2034/*
2035 * IB stuff
2036 */
2037/**
2038 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2039 *
2040 * @ring: amdgpu_ring structure holding ring information
2041 * @ib: amdgpu indirect buffer object
2042 *
2043 * Emits an DE (drawing engine) or CE (constant engine) IB
2044 * on the gfx ring. IBs are usually generated by userspace
2045 * acceleration drivers and submitted to the kernel for
2046 * sheduling on the ring. This function schedules the IB
2047 * on the gfx ring for execution by the GPU.
2048 */
93323131 2049static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 2050 struct amdgpu_ib *ib,
2051 unsigned vm_id, bool ctx_switch)
a2e73f56
AD		 2052{
2053 u32 header, control = 0;
2054 u32 next_rptr = ring->wptr + 5;
aa2bdb24 2055
f153d286 2056 if (ctx_switch)
a2e73f56
AD		 2057 next_rptr += 2;
2058
2059 next_rptr += 4;
2060 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2061 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2062 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2063 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2064 amdgpu_ring_write(ring, next_rptr);
2065
a2e73f56 2066 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 2067 if (ctx_switch) {
a2e73f56
AD		 2068 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2069 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2070 }
2071
de807f81 2072 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2073 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2074 else
2075 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2076
d88bf583 2077 control |= ib->length_dw | (vm_id << 24);
a2e73f56
AD		 2078
2079 amdgpu_ring_write(ring, header);
2080 amdgpu_ring_write(ring,
2081#ifdef __BIG_ENDIAN
2082 (2 << 0) |
2083#endif
2084 (ib->gpu_addr & 0xFFFFFFFC));
2085 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2086 amdgpu_ring_write(ring, control);
2087}
2088
93323131 2089static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 2090 struct amdgpu_ib *ib,
2091 unsigned vm_id, bool ctx_switch)
93323131 2092{
2093 u32 header, control = 0;
2094 u32 next_rptr = ring->wptr + 5;
2095
2096 control |= INDIRECT_BUFFER_VALID;
2097 next_rptr += 4;
2098 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2099 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2100 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2101 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2102 amdgpu_ring_write(ring, next_rptr);
2103
2104 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2105
d88bf583 2106 control |= ib->length_dw | (vm_id << 24);
93323131 2107
2108 amdgpu_ring_write(ring, header);
2109 amdgpu_ring_write(ring,
2110#ifdef __BIG_ENDIAN
2111 (2 << 0) |
2112#endif
2113 (ib->gpu_addr & 0xFFFFFFFC));
2114 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2115 amdgpu_ring_write(ring, control);
2116}
2117
a2e73f56
AD		 2118/**
2119 * gfx_v7_0_ring_test_ib - basic ring IB test
2120 *
2121 * @ring: amdgpu_ring structure holding ring information
2122 *
2123 * Allocate an IB and execute it on the gfx ring (CIK).
2124 * Provides a basic gfx ring test to verify that IBs are working.
2125 * Returns 0 on success, error on failure.
2126 */
2127static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2128{
2129 struct amdgpu_device *adev = ring->adev;
2130 struct amdgpu_ib ib;
1763552e 2131 struct fence *f = NULL;
a2e73f56
AD		 2132 uint32_t scratch;
2133 uint32_t tmp = 0;
2134 unsigned i;
2135 int r;
2136
2137 r = amdgpu_gfx_scratch_get(adev, &scratch);
2138 if (r) {
2139 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2140 return r;
2141 }
2142 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2143 memset(&ib, 0, sizeof(ib));
b07c60c0 2144 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56
AD		 2145 if (r) {
2146 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 2147 goto err1;
a2e73f56
AD		 2148 }
2149 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2150 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2151 ib.ptr[2] = 0xDEADBEEF;
2152 ib.length_dw = 3;
42d13693 2153
c5637837 2154 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
42d13693
CZ		 2155 if (r)
2156 goto err2;
2157
1763552e 2158 r = fence_wait(f, false);
a2e73f56
AD		 2159 if (r) {
2160 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 2161 goto err2;
a2e73f56
AD		 2162 }
2163 for (i = 0; i < adev->usec_timeout; i++) {
2164 tmp = RREG32(scratch);
2165 if (tmp == 0xDEADBEEF)
2166 break;
2167 DRM_UDELAY(1);
2168 }
2169 if (i < adev->usec_timeout) {
2170 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 2171 ring->idx, i);
2172 goto err2;
a2e73f56
AD		 2173 } else {
2174 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2175 scratch, tmp);
2176 r = -EINVAL;
2177 }
42d13693
CZ		 2178
2179err2:
281b4223 2180 fence_put(f);
cc55c45d 2181 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 2182 fence_put(f);
42d13693
CZ		 2183err1:
2184 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2185 return r;
2186}
2187
2188/*
2189 * CP.
2190 * On CIK, gfx and compute now have independant command processors.
2191 *
2192 * GFX
2193 * Gfx consists of a single ring and can process both gfx jobs and
2194 * compute jobs. The gfx CP consists of three microengines (ME):
2195 * PFP - Pre-Fetch Parser
2196 * ME - Micro Engine
2197 * CE - Constant Engine
2198 * The PFP and ME make up what is considered the Drawing Engine (DE).
2199 * The CE is an asynchronous engine used for updating buffer desciptors
2200 * used by the DE so that they can be loaded into cache in parallel
2201 * while the DE is processing state update packets.
2202 *
2203 * Compute
2204 * The compute CP consists of two microengines (ME):
2205 * MEC1 - Compute MicroEngine 1
2206 * MEC2 - Compute MicroEngine 2
2207 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2208 * The queues are exposed to userspace and are programmed directly
2209 * by the compute runtime.
2210 */
2211/**
2212 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2213 *
2214 * @adev: amdgpu_device pointer
2215 * @enable: enable or disable the MEs
2216 *
2217 * Halts or unhalts the gfx MEs.
2218 */
2219static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2220{
2221 int i;
2222
2223 if (enable) {
2224 WREG32(mmCP_ME_CNTL, 0);
2225 } else {
2226 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2227 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2228 adev->gfx.gfx_ring[i].ready = false;
2229 }
2230 udelay(50);
2231}
2232
2233/**
2234 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2235 *
2236 * @adev: amdgpu_device pointer
2237 *
2238 * Loads the gfx PFP, ME, and CE ucode.
2239 * Returns 0 for success, -EINVAL if the ucode is not available.
2240 */
2241static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2242{
2243 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2244 const struct gfx_firmware_header_v1_0 *ce_hdr;
2245 const struct gfx_firmware_header_v1_0 *me_hdr;
2246 const __le32 *fw_data;
2247 unsigned i, fw_size;
2248
2249 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2250 return -EINVAL;
2251
2252 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2253 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2254 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2255
2256 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2257 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2258 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2259 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2260 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2261 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2262 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2263 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2264 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2265
2266 gfx_v7_0_cp_gfx_enable(adev, false);
2267
2268 /* PFP */
2269 fw_data = (const __le32 *)
2270 (adev->gfx.pfp_fw->data +
2271 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2272 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2273 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2274 for (i = 0; i < fw_size; i++)
2275 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2276 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2277
2278 /* CE */
2279 fw_data = (const __le32 *)
2280 (adev->gfx.ce_fw->data +
2281 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2282 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2283 WREG32(mmCP_CE_UCODE_ADDR, 0);
2284 for (i = 0; i < fw_size; i++)
2285 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2286 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2287
2288 /* ME */
2289 fw_data = (const __le32 *)
2290 (adev->gfx.me_fw->data +
2291 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2292 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2293 WREG32(mmCP_ME_RAM_WADDR, 0);
2294 for (i = 0; i < fw_size; i++)
2295 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2296 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2297
2298 return 0;
2299}
2300
2301/**
2302 * gfx_v7_0_cp_gfx_start - start the gfx ring
2303 *
2304 * @adev: amdgpu_device pointer
2305 *
2306 * Enables the ring and loads the clear state context and other
2307 * packets required to init the ring.
2308 * Returns 0 for success, error for failure.
2309 */
2310static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2311{
2312 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2313 const struct cs_section_def *sect = NULL;
2314 const struct cs_extent_def *ext = NULL;
2315 int r, i;
2316
2317 /* init the CP */
2318 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2319 WREG32(mmCP_ENDIAN_SWAP, 0);
2320 WREG32(mmCP_DEVICE_ID, 1);
2321
2322 gfx_v7_0_cp_gfx_enable(adev, true);
2323
a27de35c 2324 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2325 if (r) {
2326 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2327 return r;
2328 }
2329
2330 /* init the CE partitions. CE only used for gfx on CIK */
2331 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2332 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2333 amdgpu_ring_write(ring, 0x8000);
2334 amdgpu_ring_write(ring, 0x8000);
2335
2336 /* clear state buffer */
2337 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2338 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2339
2340 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2341 amdgpu_ring_write(ring, 0x80000000);
2342 amdgpu_ring_write(ring, 0x80000000);
2343
2344 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2345 for (ext = sect->section; ext->extent != NULL; ++ext) {
2346 if (sect->id == SECT_CONTEXT) {
2347 amdgpu_ring_write(ring,
2348 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2349 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2350 for (i = 0; i < ext->reg_count; i++)
2351 amdgpu_ring_write(ring, ext->extent[i]);
2352 }
2353 }
2354 }
2355
2356 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2357 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2358 switch (adev->asic_type) {
2359 case CHIP_BONAIRE:
2360 amdgpu_ring_write(ring, 0x16000012);
2361 amdgpu_ring_write(ring, 0x00000000);
2362 break;
2363 case CHIP_KAVERI:
2364 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2365 amdgpu_ring_write(ring, 0x00000000);
2366 break;
2367 case CHIP_KABINI:
2368 case CHIP_MULLINS:
2369 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2370 amdgpu_ring_write(ring, 0x00000000);
2371 break;
2372 case CHIP_HAWAII:
2373 amdgpu_ring_write(ring, 0x3a00161a);
2374 amdgpu_ring_write(ring, 0x0000002e);
2375 break;
2376 default:
2377 amdgpu_ring_write(ring, 0x00000000);
2378 amdgpu_ring_write(ring, 0x00000000);
2379 break;
2380 }
2381
2382 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2383 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2384
2385 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2386 amdgpu_ring_write(ring, 0);
2387
2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2389 amdgpu_ring_write(ring, 0x00000316);
2390 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2391 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2392
a27de35c 2393 amdgpu_ring_commit(ring);
a2e73f56
AD		 2394
2395 return 0;
2396}
2397
2398/**
2399 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2400 *
2401 * @adev: amdgpu_device pointer
2402 *
2403 * Program the location and size of the gfx ring buffer
2404 * and test it to make sure it's working.
2405 * Returns 0 for success, error for failure.
2406 */
2407static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2408{
2409 struct amdgpu_ring *ring;
2410 u32 tmp;
2411 u32 rb_bufsz;
2412 u64 rb_addr, rptr_addr;
2413 int r;
2414
2415 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2416 if (adev->asic_type != CHIP_HAWAII)
2417 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2418
2419 /* Set the write pointer delay */
2420 WREG32(mmCP_RB_WPTR_DELAY, 0);
2421
2422 /* set the RB to use vmid 0 */
2423 WREG32(mmCP_RB_VMID, 0);
2424
2425 WREG32(mmSCRATCH_ADDR, 0);
2426
2427 /* ring 0 - compute and gfx */
2428 /* Set ring buffer size */
2429 ring = &adev->gfx.gfx_ring[0];
2430 rb_bufsz = order_base_2(ring->ring_size / 8);
2431 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2432#ifdef __BIG_ENDIAN
454fc95e 2433 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2434#endif
2435 WREG32(mmCP_RB0_CNTL, tmp);
2436
2437 /* Initialize the ring buffer's read and write pointers */
2438 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2439 ring->wptr = 0;
2440 WREG32(mmCP_RB0_WPTR, ring->wptr);
2441
2442 /* set the wb address wether it's enabled or not */
2443 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2444 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2445 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2446
2447 /* scratch register shadowing is no longer supported */
2448 WREG32(mmSCRATCH_UMSK, 0);
2449
2450 mdelay(1);
2451 WREG32(mmCP_RB0_CNTL, tmp);
2452
2453 rb_addr = ring->gpu_addr >> 8;
2454 WREG32(mmCP_RB0_BASE, rb_addr);
2455 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2456
2457 /* start the ring */
2458 gfx_v7_0_cp_gfx_start(adev);
2459 ring->ready = true;
2460 r = amdgpu_ring_test_ring(ring);
2461 if (r) {
2462 ring->ready = false;
2463 return r;
2464 }
2465
2466 return 0;
2467}
2468
2469static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2470{
7edd6b2f 2471 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2472}
2473
2474static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2475{
2476 struct amdgpu_device *adev = ring->adev;
a2e73f56 2477
7edd6b2f 2478 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2479}
2480
2481static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2482{
2483 struct amdgpu_device *adev = ring->adev;
2484
2485 WREG32(mmCP_RB0_WPTR, ring->wptr);
2486 (void)RREG32(mmCP_RB0_WPTR);
2487}
2488
2489static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2490{
7edd6b2f 2491 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2492}
2493
2494static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2495{
a2e73f56 2496 /* XXX check if swapping is necessary on BE */
7edd6b2f 2497 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2498}
2499
2500static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2501{
2502 struct amdgpu_device *adev = ring->adev;
2503
2504 /* XXX check if swapping is necessary on BE */
2505 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2506 WDOORBELL32(ring->doorbell_index, ring->wptr);
2507}
2508
2509/**
2510 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2511 *
2512 * @adev: amdgpu_device pointer
2513 * @enable: enable or disable the MEs
2514 *
2515 * Halts or unhalts the compute MEs.
2516 */
2517static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2518{
2519 int i;
2520
2521 if (enable) {
2522 WREG32(mmCP_MEC_CNTL, 0);
2523 } else {
2524 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2525 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2526 adev->gfx.compute_ring[i].ready = false;
2527 }
2528 udelay(50);
2529}
2530
2531/**
2532 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2533 *
2534 * @adev: amdgpu_device pointer
2535 *
2536 * Loads the compute MEC1&2 ucode.
2537 * Returns 0 for success, -EINVAL if the ucode is not available.
2538 */
2539static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2540{
2541 const struct gfx_firmware_header_v1_0 *mec_hdr;
2542 const __le32 *fw_data;
2543 unsigned i, fw_size;
2544
2545 if (!adev->gfx.mec_fw)
2546 return -EINVAL;
2547
2548 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2549 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2550 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2551 adev->gfx.mec_feature_version = le32_to_cpu(
2552 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2553
2554 gfx_v7_0_cp_compute_enable(adev, false);
2555
2556 /* MEC1 */
2557 fw_data = (const __le32 *)
2558 (adev->gfx.mec_fw->data +
2559 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2560 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2561 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2562 for (i = 0; i < fw_size; i++)
2563 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2564 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2565
2566 if (adev->asic_type == CHIP_KAVERI) {
2567 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2568
2569 if (!adev->gfx.mec2_fw)
2570 return -EINVAL;
2571
2572 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2573 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2574 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2575 adev->gfx.mec2_feature_version = le32_to_cpu(
2576 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2577
2578 /* MEC2 */
2579 fw_data = (const __le32 *)
2580 (adev->gfx.mec2_fw->data +
2581 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2582 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2583 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2584 for (i = 0; i < fw_size; i++)
2585 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2586 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2587 }
2588
2589 return 0;
2590}
2591
a2e73f56
AD		 2592/**
2593 * gfx_v7_0_cp_compute_fini - stop the compute queues
2594 *
2595 * @adev: amdgpu_device pointer
2596 *
2597 * Stop the compute queues and tear down the driver queue
2598 * info.
2599 */
2600static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2601{
2602 int i, r;
2603
2604 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2605 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2606
2607 if (ring->mqd_obj) {
2608 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2609 if (unlikely(r != 0))
2610 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2611
2612 amdgpu_bo_unpin(ring->mqd_obj);
2613 amdgpu_bo_unreserve(ring->mqd_obj);
2614
2615 amdgpu_bo_unref(&ring->mqd_obj);
2616 ring->mqd_obj = NULL;
2617 }
2618 }
2619}
2620
2621static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2622{
2623 int r;
2624
2625 if (adev->gfx.mec.hpd_eop_obj) {
2626 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2627 if (unlikely(r != 0))
2628 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2629 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2630 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2631
2632 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2633 adev->gfx.mec.hpd_eop_obj = NULL;
2634 }
2635}
2636
2637#define MEC_HPD_SIZE 2048
2638
2639static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2640{
2641 int r;
2642 u32 *hpd;
2643
2644 /*
2645 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2646 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2647 * Nonetheless, we assign only 1 pipe because all other pipes will
2648 * be handled by KFD
2649 */
2650 adev->gfx.mec.num_mec = 1;
2651 adev->gfx.mec.num_pipe = 1;
2652 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2653
2654 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2655 r = amdgpu_bo_create(adev,
2656 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2657 PAGE_SIZE, true,
72d7668b 2658 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2659 &adev->gfx.mec.hpd_eop_obj);
2660 if (r) {
2661 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2662 return r;
2663 }
2664 }
2665
2666 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2667 if (unlikely(r != 0)) {
2668 gfx_v7_0_mec_fini(adev);
2669 return r;
2670 }
2671 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2672 &adev->gfx.mec.hpd_eop_gpu_addr);
2673 if (r) {
2674 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2675 gfx_v7_0_mec_fini(adev);
2676 return r;
2677 }
2678 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2679 if (r) {
2680 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2681 gfx_v7_0_mec_fini(adev);
2682 return r;
2683 }
2684
2685 /* clear memory. Not sure if this is required or not */
2686 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2687
2688 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2689 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2690
2691 return 0;
2692}
2693
2694struct hqd_registers
2695{
2696 u32 cp_mqd_base_addr;
2697 u32 cp_mqd_base_addr_hi;
2698 u32 cp_hqd_active;
2699 u32 cp_hqd_vmid;
2700 u32 cp_hqd_persistent_state;
2701 u32 cp_hqd_pipe_priority;
2702 u32 cp_hqd_queue_priority;
2703 u32 cp_hqd_quantum;
2704 u32 cp_hqd_pq_base;
2705 u32 cp_hqd_pq_base_hi;
2706 u32 cp_hqd_pq_rptr;
2707 u32 cp_hqd_pq_rptr_report_addr;
2708 u32 cp_hqd_pq_rptr_report_addr_hi;
2709 u32 cp_hqd_pq_wptr_poll_addr;
2710 u32 cp_hqd_pq_wptr_poll_addr_hi;
2711 u32 cp_hqd_pq_doorbell_control;
2712 u32 cp_hqd_pq_wptr;
2713 u32 cp_hqd_pq_control;
2714 u32 cp_hqd_ib_base_addr;
2715 u32 cp_hqd_ib_base_addr_hi;
2716 u32 cp_hqd_ib_rptr;
2717 u32 cp_hqd_ib_control;
2718 u32 cp_hqd_iq_timer;
2719 u32 cp_hqd_iq_rptr;
2720 u32 cp_hqd_dequeue_request;
2721 u32 cp_hqd_dma_offload;
2722 u32 cp_hqd_sema_cmd;
2723 u32 cp_hqd_msg_type;
2724 u32 cp_hqd_atomic0_preop_lo;
2725 u32 cp_hqd_atomic0_preop_hi;
2726 u32 cp_hqd_atomic1_preop_lo;
2727 u32 cp_hqd_atomic1_preop_hi;
2728 u32 cp_hqd_hq_scheduler0;
2729 u32 cp_hqd_hq_scheduler1;
2730 u32 cp_mqd_control;
2731};
2732
2733struct bonaire_mqd
2734{
2735 u32 header;
2736 u32 dispatch_initiator;
2737 u32 dimensions[3];
2738 u32 start_idx[3];
2739 u32 num_threads[3];
2740 u32 pipeline_stat_enable;
2741 u32 perf_counter_enable;
2742 u32 pgm[2];
2743 u32 tba[2];
2744 u32 tma[2];
2745 u32 pgm_rsrc[2];
2746 u32 vmid;
2747 u32 resource_limits;
2748 u32 static_thread_mgmt01[2];
2749 u32 tmp_ring_size;
2750 u32 static_thread_mgmt23[2];
2751 u32 restart[3];
2752 u32 thread_trace_enable;
2753 u32 reserved1;
2754 u32 user_data[16];
2755 u32 vgtcs_invoke_count[2];
2756 struct hqd_registers queue_state;
2757 u32 dequeue_cntr;
2758 u32 interrupt_queue[64];
2759};
2760
2761/**
2762 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2763 *
2764 * @adev: amdgpu_device pointer
2765 *
2766 * Program the compute queues and test them to make sure they
2767 * are working.
2768 * Returns 0 for success, error for failure.
2769 */
2770static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2771{
2772 int r, i, j;
2773 u32 tmp;
2774 bool use_doorbell = true;
2775 u64 hqd_gpu_addr;
2776 u64 mqd_gpu_addr;
2777 u64 eop_gpu_addr;
2778 u64 wb_gpu_addr;
2779 u32 *buf;
2780 struct bonaire_mqd *mqd;
2781
6e9821b2 2782 gfx_v7_0_cp_compute_enable(adev, true);
a2e73f56
AD		 2783
2784 /* fix up chicken bits */
2785 tmp = RREG32(mmCP_CPF_DEBUG);
2786 tmp |= (1 << 23);
2787 WREG32(mmCP_CPF_DEBUG, tmp);
2788
2789 /* init the pipes */
2790 mutex_lock(&adev->srbm_mutex);
2791 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2792 int me = (i < 4) ? 1 : 2;
2793 int pipe = (i < 4) ? i : (i - 4);
2794
2795 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2796
2797 cik_srbm_select(adev, me, pipe, 0, 0);
2798
2799 /* write the EOP addr */
2800 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2801 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2802
2803 /* set the VMID assigned */
2804 WREG32(mmCP_HPD_EOP_VMID, 0);
2805
2806 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2807 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2808 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2809 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2810 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2811 }
2812 cik_srbm_select(adev, 0, 0, 0, 0);
2813 mutex_unlock(&adev->srbm_mutex);
2814
2815 /* init the queues. Just two for now. */
2816 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2817 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2818
2819 if (ring->mqd_obj == NULL) {
2820 r = amdgpu_bo_create(adev,
2821 sizeof(struct bonaire_mqd),
2822 PAGE_SIZE, true,
72d7668b 2823 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2824 &ring->mqd_obj);
2825 if (r) {
2826 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2827 return r;
2828 }
2829 }
2830
2831 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2832 if (unlikely(r != 0)) {
2833 gfx_v7_0_cp_compute_fini(adev);
2834 return r;
2835 }
2836 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2837 &mqd_gpu_addr);
2838 if (r) {
2839 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2840 gfx_v7_0_cp_compute_fini(adev);
2841 return r;
2842 }
2843 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2844 if (r) {
2845 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2846 gfx_v7_0_cp_compute_fini(adev);
2847 return r;
2848 }
2849
2850 /* init the mqd struct */
2851 memset(buf, 0, sizeof(struct bonaire_mqd));
2852
2853 mqd = (struct bonaire_mqd *)buf;
2854 mqd->header = 0xC0310800;
2855 mqd->static_thread_mgmt01[0] = 0xffffffff;
2856 mqd->static_thread_mgmt01[1] = 0xffffffff;
2857 mqd->static_thread_mgmt23[0] = 0xffffffff;
2858 mqd->static_thread_mgmt23[1] = 0xffffffff;
2859
2860 mutex_lock(&adev->srbm_mutex);
2861 cik_srbm_select(adev, ring->me,
2862 ring->pipe,
2863 ring->queue, 0);
2864
2865 /* disable wptr polling */
2866 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2867 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2868 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2869
2870 /* enable doorbell? */
2871 mqd->queue_state.cp_hqd_pq_doorbell_control =
2872 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2873 if (use_doorbell)
2874 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2875 else
2876 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2877 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2878 mqd->queue_state.cp_hqd_pq_doorbell_control);
2879
2880 /* disable the queue if it's active */
2881 mqd->queue_state.cp_hqd_dequeue_request = 0;
2882 mqd->queue_state.cp_hqd_pq_rptr = 0;
2883 mqd->queue_state.cp_hqd_pq_wptr= 0;
2884 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2885 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2886 for (j = 0; j < adev->usec_timeout; j++) {
2887 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2888 break;
2889 udelay(1);
2890 }
2891 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2892 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2893 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2894 }
2895
2896 /* set the pointer to the MQD */
2897 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2898 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2899 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2900 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2901 /* set MQD vmid to 0 */
2902 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2903 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2904 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2905
2906 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2907 hqd_gpu_addr = ring->gpu_addr >> 8;
2908 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2909 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2910 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2911 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2912
2913 /* set up the HQD, this is similar to CP_RB0_CNTL */
2914 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2915 mqd->queue_state.cp_hqd_pq_control &=
2916 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2917 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2918
2919 mqd->queue_state.cp_hqd_pq_control |=
2920 order_base_2(ring->ring_size / 8);
2921 mqd->queue_state.cp_hqd_pq_control |=
2922 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2923#ifdef __BIG_ENDIAN
454fc95e
AD		 2924 mqd->queue_state.cp_hqd_pq_control |=
2925 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 2926#endif
2927 mqd->queue_state.cp_hqd_pq_control &=
2928 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2929 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2930 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2931 mqd->queue_state.cp_hqd_pq_control |=
2932 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2933 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2934 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2935
2936 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2937 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2938 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2939 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2940 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2941 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2942 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2943
2944 /* set the wb address wether it's enabled or not */
2945 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2946 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2947 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2948 upper_32_bits(wb_gpu_addr) & 0xffff;
2949 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2950 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2951 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2952 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2953
2954 /* enable the doorbell if requested */
2955 if (use_doorbell) {
2956 mqd->queue_state.cp_hqd_pq_doorbell_control =
2957 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2958 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2959 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2960 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2961 (ring->doorbell_index <<
2962 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2963 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2964 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2965 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2966 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2967 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2968
2969 } else {
2970 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2971 }
2972 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2973 mqd->queue_state.cp_hqd_pq_doorbell_control);
2974
2975 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2976 ring->wptr = 0;
2977 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2978 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2979 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2980
2981 /* set the vmid for the queue */
2982 mqd->queue_state.cp_hqd_vmid = 0;
2983 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2984
2985 /* activate the queue */
2986 mqd->queue_state.cp_hqd_active = 1;
2987 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2988
2989 cik_srbm_select(adev, 0, 0, 0, 0);
2990 mutex_unlock(&adev->srbm_mutex);
2991
2992 amdgpu_bo_kunmap(ring->mqd_obj);
2993 amdgpu_bo_unreserve(ring->mqd_obj);
2994
2995 ring->ready = true;
2996 r = amdgpu_ring_test_ring(ring);
2997 if (r)
2998 ring->ready = false;
2999 }
3000
3001 return 0;
3002}
3003
3004static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3005{
3006 gfx_v7_0_cp_gfx_enable(adev, enable);
3007 gfx_v7_0_cp_compute_enable(adev, enable);
3008}
3009
3010static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3011{
3012 int r;
3013
3014 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3015 if (r)
3016 return r;
3017 r = gfx_v7_0_cp_compute_load_microcode(adev);
3018 if (r)
3019 return r;
3020
3021 return 0;
3022}
3023
3024static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3025 bool enable)
3026{
3027 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3028
3029 if (enable)
3030 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3031 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3032 else
3033 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3034 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3035 WREG32(mmCP_INT_CNTL_RING0, tmp);
3036}
3037
3038static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3039{
3040 int r;
3041
3042 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3043
3044 r = gfx_v7_0_cp_load_microcode(adev);
3045 if (r)
3046 return r;
3047
3048 r = gfx_v7_0_cp_gfx_resume(adev);
3049 if (r)
3050 return r;
3051 r = gfx_v7_0_cp_compute_resume(adev);
3052 if (r)
3053 return r;
3054
3055 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3056
3057 return 0;
3058}
3059
b8c7b39e
CK		 3060/**
3061 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3062 *
3063 * @ring: the ring to emmit the commands to
3064 *
3065 * Sync the command pipeline with the PFP. E.g. wait for everything
3066 * to be completed.
3067 */
3068static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3069{
3070 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
914f9e18
CZ		 3071 uint32_t seq = ring->fence_drv.sync_seq;
3072 uint64_t addr = ring->fence_drv.gpu_addr;
3073
3074 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3075 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3076 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3077 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3078 amdgpu_ring_write(ring, addr & 0xfffffffc);
3079 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3080 amdgpu_ring_write(ring, seq);
3081 amdgpu_ring_write(ring, 0xffffffff);
3082 amdgpu_ring_write(ring, 4); /* poll interval */
3083
b8c7b39e
CK		 3084 if (usepfp) {
3085 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3086 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3087 amdgpu_ring_write(ring, 0);
3088 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3089 amdgpu_ring_write(ring, 0);
3090 }
3091}
3092
a2e73f56
AD		 3093/*
3094 * vm
3095 * VMID 0 is the physical GPU addresses as used by the kernel.
3096 * VMIDs 1-15 are used for userspace clients and are handled
3097 * by the amdgpu vm/hsa code.
3098 */
3099/**
3100 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3101 *
3102 * @adev: amdgpu_device pointer
3103 *
3104 * Update the page table base and flush the VM TLB
3105 * using the CP (CIK).
3106 */
3107static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3108 unsigned vm_id, uint64_t pd_addr)
3109{
3110 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
feebe91a 3111
a2e73f56
AD		 3112 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3113 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3114 WRITE_DATA_DST_SEL(0)));
3115 if (vm_id < 8) {
3116 amdgpu_ring_write(ring,
3117 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3118 } else {
3119 amdgpu_ring_write(ring,
3120 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3121 }
3122 amdgpu_ring_write(ring, 0);
3123 amdgpu_ring_write(ring, pd_addr >> 12);
3124
a2e73f56
AD		 3125 /* bits 0-15 are the VM contexts0-15 */
3126 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3127 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3128 WRITE_DATA_DST_SEL(0)));
3129 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3130 amdgpu_ring_write(ring, 0);
3131 amdgpu_ring_write(ring, 1 << vm_id);
3132
3133 /* wait for the invalidate to complete */
3134 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3135 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3136 WAIT_REG_MEM_FUNCTION(0) | /* always */
3137 WAIT_REG_MEM_ENGINE(0))); /* me */
3138 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3139 amdgpu_ring_write(ring, 0);
3140 amdgpu_ring_write(ring, 0); /* ref */
3141 amdgpu_ring_write(ring, 0); /* mask */
3142 amdgpu_ring_write(ring, 0x20); /* poll interval */
3143
3144 /* compute doesn't have PFP */
3145 if (usepfp) {
3146 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3147 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3148 amdgpu_ring_write(ring, 0x0);
3149
3150 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3151 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3152 amdgpu_ring_write(ring, 0);
3153 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3154 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3155 }
3156}
3157
3158/*
3159 * RLC
3160 * The RLC is a multi-purpose microengine that handles a
3161 * variety of functions.
3162 */
3163static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3164{
3165 int r;
3166
3167 /* save restore block */
3168 if (adev->gfx.rlc.save_restore_obj) {
3169 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3170 if (unlikely(r != 0))
3171 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3172 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3173 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3174
3175 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3176 adev->gfx.rlc.save_restore_obj = NULL;
3177 }
3178
3179 /* clear state block */
3180 if (adev->gfx.rlc.clear_state_obj) {
3181 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3182 if (unlikely(r != 0))
3183 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3184 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3185 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3186
3187 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3188 adev->gfx.rlc.clear_state_obj = NULL;
3189 }
3190
3191 /* clear state block */
3192 if (adev->gfx.rlc.cp_table_obj) {
3193 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3194 if (unlikely(r != 0))
3195 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3196 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3197 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3198
3199 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3200 adev->gfx.rlc.cp_table_obj = NULL;
3201 }
3202}
3203
3204static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3205{
3206 const u32 *src_ptr;
3207 volatile u32 *dst_ptr;
3208 u32 dws, i;
3209 const struct cs_section_def *cs_data;
3210 int r;
3211
3212 /* allocate rlc buffers */
2f7d10b3 3213 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3214 if (adev->asic_type == CHIP_KAVERI) {
3215 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3216 adev->gfx.rlc.reg_list_size =
3217 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3218 } else {
3219 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3220 adev->gfx.rlc.reg_list_size =
3221 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3222 }
3223 }
3224 adev->gfx.rlc.cs_data = ci_cs_data;
b58bc559 3225 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
e36091ed 3226 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
a2e73f56
AD		 3227
3228 src_ptr = adev->gfx.rlc.reg_list;
3229 dws = adev->gfx.rlc.reg_list_size;
3230 dws += (5 * 16) + 48 + 48 + 64;
3231
3232 cs_data = adev->gfx.rlc.cs_data;
3233
3234 if (src_ptr) {
3235 /* save restore block */
3236 if (adev->gfx.rlc.save_restore_obj == NULL) {
3237 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3238 AMDGPU_GEM_DOMAIN_VRAM,
3239 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3240 NULL, NULL,
3241 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3242 if (r) {
3243 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3244 return r;
3245 }
3246 }
3247
3248 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3249 if (unlikely(r != 0)) {
3250 gfx_v7_0_rlc_fini(adev);
3251 return r;
3252 }
3253 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3254 &adev->gfx.rlc.save_restore_gpu_addr);
3255 if (r) {
3256 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3257 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3258 gfx_v7_0_rlc_fini(adev);
3259 return r;
3260 }
3261
3262 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3263 if (r) {
3264 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3265 gfx_v7_0_rlc_fini(adev);
3266 return r;
3267 }
3268 /* write the sr buffer */
3269 dst_ptr = adev->gfx.rlc.sr_ptr;
3270 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3271 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3272 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3273 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3274 }
3275
3276 if (cs_data) {
3277 /* clear state block */
3278 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3279
3280 if (adev->gfx.rlc.clear_state_obj == NULL) {
3281 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3282 AMDGPU_GEM_DOMAIN_VRAM,
3283 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3284 NULL, NULL,
3285 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3286 if (r) {
3287 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3288 gfx_v7_0_rlc_fini(adev);
3289 return r;
3290 }
3291 }
3292 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3293 if (unlikely(r != 0)) {
3294 gfx_v7_0_rlc_fini(adev);
3295 return r;
3296 }
3297 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3298 &adev->gfx.rlc.clear_state_gpu_addr);
3299 if (r) {
3300 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3301 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3302 gfx_v7_0_rlc_fini(adev);
3303 return r;
3304 }
3305
3306 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3307 if (r) {
3308 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3309 gfx_v7_0_rlc_fini(adev);
3310 return r;
3311 }
3312 /* set up the cs buffer */
3313 dst_ptr = adev->gfx.rlc.cs_ptr;
3314 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3315 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3316 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3317 }
3318
3319 if (adev->gfx.rlc.cp_table_size) {
3320 if (adev->gfx.rlc.cp_table_obj == NULL) {
3321 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d
AD		 3322 AMDGPU_GEM_DOMAIN_VRAM,
3323 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3324 NULL, NULL,
3325 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3326 if (r) {
3327 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3328 gfx_v7_0_rlc_fini(adev);
3329 return r;
3330 }
3331 }
3332
3333 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3334 if (unlikely(r != 0)) {
3335 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3336 gfx_v7_0_rlc_fini(adev);
3337 return r;
3338 }
3339 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3340 &adev->gfx.rlc.cp_table_gpu_addr);
3341 if (r) {
3342 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3343 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3344 gfx_v7_0_rlc_fini(adev);
3345 return r;
3346 }
3347 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3348 if (r) {
3349 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3350 gfx_v7_0_rlc_fini(adev);
3351 return r;
3352 }
3353
3354 gfx_v7_0_init_cp_pg_table(adev);
3355
3356 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3357 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3358
3359 }
3360
3361 return 0;
3362}
3363
3364static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3365{
3366 u32 tmp;
3367
3368 tmp = RREG32(mmRLC_LB_CNTL);
3369 if (enable)
3370 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3371 else
3372 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3373 WREG32(mmRLC_LB_CNTL, tmp);
3374}
3375
3376static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3377{
3378 u32 i, j, k;
3379 u32 mask;
3380
3381 mutex_lock(&adev->grbm_idx_mutex);
3382 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3383 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3384 gfx_v7_0_select_se_sh(adev, i, j);
3385 for (k = 0; k < adev->usec_timeout; k++) {
3386 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3387 break;
3388 udelay(1);
3389 }
3390 }
3391 }
3392 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3393 mutex_unlock(&adev->grbm_idx_mutex);
3394
3395 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3396 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3397 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3398 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3399 for (k = 0; k < adev->usec_timeout; k++) {
3400 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3401 break;
3402 udelay(1);
3403 }
3404}
3405
3406static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3407{
3408 u32 tmp;
3409
3410 tmp = RREG32(mmRLC_CNTL);
3411 if (tmp != rlc)
3412 WREG32(mmRLC_CNTL, rlc);
3413}
3414
3415static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3416{
3417 u32 data, orig;
3418
3419 orig = data = RREG32(mmRLC_CNTL);
3420
3421 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3422 u32 i;
3423
3424 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3425 WREG32(mmRLC_CNTL, data);
3426
3427 for (i = 0; i < adev->usec_timeout; i++) {
3428 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3429 break;
3430 udelay(1);
3431 }
3432
3433 gfx_v7_0_wait_for_rlc_serdes(adev);
3434 }
3435
3436 return orig;
3437}
3438
06120a1e 3439static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3440{
3441 u32 tmp, i, mask;
3442
3443 tmp = 0x1 | (1 << 1);
3444 WREG32(mmRLC_GPR_REG2, tmp);
3445
3446 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3447 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3448 for (i = 0; i < adev->usec_timeout; i++) {
3449 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3450 break;
3451 udelay(1);
3452 }
3453
3454 for (i = 0; i < adev->usec_timeout; i++) {
3455 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3456 break;
3457 udelay(1);
3458 }
3459}
3460
06120a1e 3461static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3462{
3463 u32 tmp;
3464
3465 tmp = 0x1 | (0 << 1);
3466 WREG32(mmRLC_GPR_REG2, tmp);
3467}
3468
3469/**
3470 * gfx_v7_0_rlc_stop - stop the RLC ME
3471 *
3472 * @adev: amdgpu_device pointer
3473 *
3474 * Halt the RLC ME (MicroEngine) (CIK).
3475 */
3476void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3477{
3478 WREG32(mmRLC_CNTL, 0);
3479
3480 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3481
3482 gfx_v7_0_wait_for_rlc_serdes(adev);
3483}
3484
3485/**
3486 * gfx_v7_0_rlc_start - start the RLC ME
3487 *
3488 * @adev: amdgpu_device pointer
3489 *
3490 * Unhalt the RLC ME (MicroEngine) (CIK).
3491 */
3492static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3493{
3494 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3495
3496 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3497
3498 udelay(50);
3499}
3500
3501static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3502{
3503 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3504
3505 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3506 WREG32(mmGRBM_SOFT_RESET, tmp);
3507 udelay(50);
3508 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3509 WREG32(mmGRBM_SOFT_RESET, tmp);
3510 udelay(50);
3511}
3512
3513/**
3514 * gfx_v7_0_rlc_resume - setup the RLC hw
3515 *
3516 * @adev: amdgpu_device pointer
3517 *
3518 * Initialize the RLC registers, load the ucode,
3519 * and start the RLC (CIK).
3520 * Returns 0 for success, -EINVAL if the ucode is not available.
3521 */
3522static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3523{
3524 const struct rlc_firmware_header_v1_0 *hdr;
3525 const __le32 *fw_data;
3526 unsigned i, fw_size;
3527 u32 tmp;
3528
3529 if (!adev->gfx.rlc_fw)
3530 return -EINVAL;
3531
3532 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3533 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3534 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3535 adev->gfx.rlc_feature_version = le32_to_cpu(
3536 hdr->ucode_feature_version);
a2e73f56
AD		 3537
3538 gfx_v7_0_rlc_stop(adev);
3539
3540 /* disable CG */
3541 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3542 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3543
3544 gfx_v7_0_rlc_reset(adev);
3545
3546 gfx_v7_0_init_pg(adev);
3547
3548 WREG32(mmRLC_LB_CNTR_INIT, 0);
3549 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3550
3551 mutex_lock(&adev->grbm_idx_mutex);
3552 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3553 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3554 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3555 WREG32(mmRLC_LB_CNTL, 0x80000004);
3556 mutex_unlock(&adev->grbm_idx_mutex);
3557
3558 WREG32(mmRLC_MC_CNTL, 0);
3559 WREG32(mmRLC_UCODE_CNTL, 0);
3560
3561 fw_data = (const __le32 *)
3562 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3563 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3564 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3565 for (i = 0; i < fw_size; i++)
3566 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3567 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3568
3569 /* XXX - find out what chips support lbpw */
3570 gfx_v7_0_enable_lbpw(adev, false);
3571
3572 if (adev->asic_type == CHIP_BONAIRE)
3573 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3574
3575 gfx_v7_0_rlc_start(adev);
3576
3577 return 0;
3578}
3579
3580static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3581{
3582 u32 data, orig, tmp, tmp2;
3583
3584 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3585
e3b04bc7 3586 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
a2e73f56
AD		 3587 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3588
3589 tmp = gfx_v7_0_halt_rlc(adev);
3590
3591 mutex_lock(&adev->grbm_idx_mutex);
3592 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3593 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3594 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3595 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3596 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3597 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3598 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3599 mutex_unlock(&adev->grbm_idx_mutex);
3600
3601 gfx_v7_0_update_rlc(adev, tmp);
3602
3603 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3604 } else {
3605 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3606
3607 RREG32(mmCB_CGTT_SCLK_CTRL);
3608 RREG32(mmCB_CGTT_SCLK_CTRL);
3609 RREG32(mmCB_CGTT_SCLK_CTRL);
3610 RREG32(mmCB_CGTT_SCLK_CTRL);
3611
3612 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3613 }
3614
3615 if (orig != data)
3616 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3617
3618}
3619
3620static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3621{
3622 u32 data, orig, tmp = 0;
3623
e3b04bc7
AD		 3624 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3625 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3626 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
a2e73f56
AD		 3627 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3628 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3629 if (orig != data)
3630 WREG32(mmCP_MEM_SLP_CNTL, data);
3631 }
3632 }
3633
3634 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3635 data |= 0x00000001;
3636 data &= 0xfffffffd;
3637 if (orig != data)
3638 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3639
3640 tmp = gfx_v7_0_halt_rlc(adev);
3641
3642 mutex_lock(&adev->grbm_idx_mutex);
3643 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3644 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3645 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3646 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3647 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3648 WREG32(mmRLC_SERDES_WR_CTRL, data);
3649 mutex_unlock(&adev->grbm_idx_mutex);
3650
3651 gfx_v7_0_update_rlc(adev, tmp);
3652
e3b04bc7 3653 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
a2e73f56
AD		 3654 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3655 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3656 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3657 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3658 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
e3b04bc7
AD		 3659 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3660 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
a2e73f56
AD		 3661 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3662 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3663 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3664 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3665 if (orig != data)
3666 WREG32(mmCGTS_SM_CTRL_REG, data);
3667 }
3668 } else {
3669 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3670 data |= 0x00000003;
3671 if (orig != data)
3672 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3673
3674 data = RREG32(mmRLC_MEM_SLP_CNTL);
3675 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3676 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3677 WREG32(mmRLC_MEM_SLP_CNTL, data);
3678 }
3679
3680 data = RREG32(mmCP_MEM_SLP_CNTL);
3681 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3682 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3683 WREG32(mmCP_MEM_SLP_CNTL, data);
3684 }
3685
3686 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3687 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3688 if (orig != data)
3689 WREG32(mmCGTS_SM_CTRL_REG, data);
3690
3691 tmp = gfx_v7_0_halt_rlc(adev);
3692
3693 mutex_lock(&adev->grbm_idx_mutex);
3694 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3695 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3696 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3697 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3698 WREG32(mmRLC_SERDES_WR_CTRL, data);
3699 mutex_unlock(&adev->grbm_idx_mutex);
3700
3701 gfx_v7_0_update_rlc(adev, tmp);
3702 }
3703}
3704
3705static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3706 bool enable)
3707{
3708 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3709 /* order matters! */
3710 if (enable) {
3711 gfx_v7_0_enable_mgcg(adev, true);
3712 gfx_v7_0_enable_cgcg(adev, true);
3713 } else {
3714 gfx_v7_0_enable_cgcg(adev, false);
3715 gfx_v7_0_enable_mgcg(adev, false);
3716 }
3717 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3718}
3719
3720static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3721 bool enable)
3722{
3723 u32 data, orig;
3724
3725 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3726 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3727 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3728 else
3729 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3730 if (orig != data)
3731 WREG32(mmRLC_PG_CNTL, data);
3732}
3733
3734static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3735 bool enable)
3736{
3737 u32 data, orig;
3738
3739 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3740 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3741 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3742 else
3743 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3744 if (orig != data)
3745 WREG32(mmRLC_PG_CNTL, data);
3746}
3747
3748static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3749{
3750 u32 data, orig;
3751
3752 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3753 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
a2e73f56
AD		 3754 data &= ~0x8000;
3755 else
3756 data |= 0x8000;
3757 if (orig != data)
3758 WREG32(mmRLC_PG_CNTL, data);
3759}
3760
3761static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3762{
3763 u32 data, orig;
3764
3765 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3766 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
a2e73f56
AD		 3767 data &= ~0x2000;
3768 else
3769 data |= 0x2000;
3770 if (orig != data)
3771 WREG32(mmRLC_PG_CNTL, data);
3772}
3773
3774static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3775{
3776 const __le32 *fw_data;
3777 volatile u32 *dst_ptr;
3778 int me, i, max_me = 4;
3779 u32 bo_offset = 0;
3780 u32 table_offset, table_size;
3781
3782 if (adev->asic_type == CHIP_KAVERI)
3783 max_me = 5;
3784
3785 if (adev->gfx.rlc.cp_table_ptr == NULL)
3786 return;
3787
3788 /* write the cp table buffer */
3789 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3790 for (me = 0; me < max_me; me++) {
3791 if (me == 0) {
3792 const struct gfx_firmware_header_v1_0 *hdr =
3793 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3794 fw_data = (const __le32 *)
3795 (adev->gfx.ce_fw->data +
3796 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3797 table_offset = le32_to_cpu(hdr->jt_offset);
3798 table_size = le32_to_cpu(hdr->jt_size);
3799 } else if (me == 1) {
3800 const struct gfx_firmware_header_v1_0 *hdr =
3801 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3802 fw_data = (const __le32 *)
3803 (adev->gfx.pfp_fw->data +
3804 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3805 table_offset = le32_to_cpu(hdr->jt_offset);
3806 table_size = le32_to_cpu(hdr->jt_size);
3807 } else if (me == 2) {
3808 const struct gfx_firmware_header_v1_0 *hdr =
3809 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3810 fw_data = (const __le32 *)
3811 (adev->gfx.me_fw->data +
3812 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3813 table_offset = le32_to_cpu(hdr->jt_offset);
3814 table_size = le32_to_cpu(hdr->jt_size);
3815 } else if (me == 3) {
3816 const struct gfx_firmware_header_v1_0 *hdr =
3817 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3818 fw_data = (const __le32 *)
3819 (adev->gfx.mec_fw->data +
3820 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3821 table_offset = le32_to_cpu(hdr->jt_offset);
3822 table_size = le32_to_cpu(hdr->jt_size);
3823 } else {
3824 const struct gfx_firmware_header_v1_0 *hdr =
3825 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3826 fw_data = (const __le32 *)
3827 (adev->gfx.mec2_fw->data +
3828 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3829 table_offset = le32_to_cpu(hdr->jt_offset);
3830 table_size = le32_to_cpu(hdr->jt_size);
3831 }
3832
3833 for (i = 0; i < table_size; i ++) {
3834 dst_ptr[bo_offset + i] =
3835 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3836 }
3837
3838 bo_offset += table_size;
3839 }
3840}
3841
3842static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3843 bool enable)
3844{
3845 u32 data, orig;
3846
e3b04bc7 3847 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
a2e73f56
AD		 3848 orig = data = RREG32(mmRLC_PG_CNTL);
3849 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3850 if (orig != data)
3851 WREG32(mmRLC_PG_CNTL, data);
3852
3853 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3854 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3855 if (orig != data)
3856 WREG32(mmRLC_AUTO_PG_CTRL, data);
3857 } else {
3858 orig = data = RREG32(mmRLC_PG_CNTL);
3859 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3860 if (orig != data)
3861 WREG32(mmRLC_PG_CNTL, data);
3862
3863 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3864 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3865 if (orig != data)
3866 WREG32(mmRLC_AUTO_PG_CTRL, data);
3867
3868 data = RREG32(mmDB_RENDER_CONTROL);
3869 }
3870}
3871
324c614a
NH		 3872static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3873 u32 bitmap)
3874{
3875 u32 data;
3876
3877 if (!bitmap)
3878 return;
3879
3880 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3881 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3882
3883 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3884}
3885
8f8e00c1 3886static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 3887{
8f8e00c1 3888 u32 data, mask;
a2e73f56 3889
8f8e00c1
AD		 3890 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3891 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 3892
8f8e00c1
AD		 3893 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3894 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 3895
6157bd7a 3896 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
a2e73f56 3897
8f8e00c1 3898 return (~data) & mask;
a2e73f56
AD		 3899}
3900
3901static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3902{
7dae69a2 3903 u32 tmp;
a2e73f56 3904
7dae69a2 3905 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
a2e73f56
AD		 3906
3907 tmp = RREG32(mmRLC_MAX_PG_CU);
3908 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
7dae69a2 3909 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
a2e73f56
AD		 3910 WREG32(mmRLC_MAX_PG_CU, tmp);
3911}
3912
3913static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3914 bool enable)
3915{
3916 u32 data, orig;
3917
3918 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3919 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
a2e73f56
AD		 3920 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3921 else
3922 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3923 if (orig != data)
3924 WREG32(mmRLC_PG_CNTL, data);
3925}
3926
3927static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3928 bool enable)
3929{
3930 u32 data, orig;
3931
3932 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3933 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
a2e73f56
AD		 3934 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3935 else
3936 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3937 if (orig != data)
3938 WREG32(mmRLC_PG_CNTL, data);
3939}
3940
3941#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3942#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3943
3944static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3945{
3946 u32 data, orig;
3947 u32 i;
3948
3949 if (adev->gfx.rlc.cs_data) {
3950 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3951 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3952 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3953 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3954 } else {
3955 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3956 for (i = 0; i < 3; i++)
3957 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3958 }
3959 if (adev->gfx.rlc.reg_list) {
3960 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3961 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3962 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3963 }
3964
3965 orig = data = RREG32(mmRLC_PG_CNTL);
3966 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3967 if (orig != data)
3968 WREG32(mmRLC_PG_CNTL, data);
3969
3970 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3971 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3972
3973 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3974 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3975 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3976 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3977
3978 data = 0x10101010;
3979 WREG32(mmRLC_PG_DELAY, data);
3980
3981 data = RREG32(mmRLC_PG_DELAY_2);
3982 data &= ~0xff;
3983 data |= 0x3;
3984 WREG32(mmRLC_PG_DELAY_2, data);
3985
3986 data = RREG32(mmRLC_AUTO_PG_CTRL);
3987 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3988 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3989 WREG32(mmRLC_AUTO_PG_CTRL, data);
3990
3991}
3992
3993static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3994{
3995 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3996 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3997 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3998}
3999
4000static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4001{
4002 u32 count = 0;
4003 const struct cs_section_def *sect = NULL;
4004 const struct cs_extent_def *ext = NULL;
4005
4006 if (adev->gfx.rlc.cs_data == NULL)
4007 return 0;
4008
4009 /* begin clear state */
4010 count += 2;
4011 /* context control state */
4012 count += 3;
4013
4014 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4015 for (ext = sect->section; ext->extent != NULL; ++ext) {
4016 if (sect->id == SECT_CONTEXT)
4017 count += 2 + ext->reg_count;
4018 else
4019 return 0;
4020 }
4021 }
4022 /* pa_sc_raster_config/pa_sc_raster_config1 */
4023 count += 4;
4024 /* end clear state */
4025 count += 2;
4026 /* clear state */
4027 count += 2;
4028
4029 return count;
4030}
4031
4032static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4033 volatile u32 *buffer)
4034{
4035 u32 count = 0, i;
4036 const struct cs_section_def *sect = NULL;
4037 const struct cs_extent_def *ext = NULL;
4038
4039 if (adev->gfx.rlc.cs_data == NULL)
4040 return;
4041 if (buffer == NULL)
4042 return;
4043
4044 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4045 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4046
4047 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4048 buffer[count++] = cpu_to_le32(0x80000000);
4049 buffer[count++] = cpu_to_le32(0x80000000);
4050
4051 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4052 for (ext = sect->section; ext->extent != NULL; ++ext) {
4053 if (sect->id == SECT_CONTEXT) {
4054 buffer[count++] =
4055 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4056 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4057 for (i = 0; i < ext->reg_count; i++)
4058 buffer[count++] = cpu_to_le32(ext->extent[i]);
4059 } else {
4060 return;
4061 }
4062 }
4063 }
4064
4065 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4066 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4067 switch (adev->asic_type) {
4068 case CHIP_BONAIRE:
4069 buffer[count++] = cpu_to_le32(0x16000012);
4070 buffer[count++] = cpu_to_le32(0x00000000);
4071 break;
4072 case CHIP_KAVERI:
4073 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4074 buffer[count++] = cpu_to_le32(0x00000000);
4075 break;
4076 case CHIP_KABINI:
4077 case CHIP_MULLINS:
4078 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4079 buffer[count++] = cpu_to_le32(0x00000000);
4080 break;
4081 case CHIP_HAWAII:
4082 buffer[count++] = cpu_to_le32(0x3a00161a);
4083 buffer[count++] = cpu_to_le32(0x0000002e);
4084 break;
4085 default:
4086 buffer[count++] = cpu_to_le32(0x00000000);
4087 buffer[count++] = cpu_to_le32(0x00000000);
4088 break;
4089 }
4090
4091 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4092 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4093
4094 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4095 buffer[count++] = cpu_to_le32(0);
4096}
4097
4098static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4099{
e3b04bc7
AD		 4100 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4101 AMD_PG_SUPPORT_GFX_SMG |
4102 AMD_PG_SUPPORT_GFX_DMG |
4103 AMD_PG_SUPPORT_CP |
4104 AMD_PG_SUPPORT_GDS |
4105 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56
AD		 4106 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4107 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
e3b04bc7 4108 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4109 gfx_v7_0_init_gfx_cgpg(adev);
4110 gfx_v7_0_enable_cp_pg(adev, true);
4111 gfx_v7_0_enable_gds_pg(adev, true);
4112 }
4113 gfx_v7_0_init_ao_cu_mask(adev);
4114 gfx_v7_0_update_gfx_pg(adev, true);
4115 }
4116}
4117
4118static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4119{
e3b04bc7
AD		 4120 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4121 AMD_PG_SUPPORT_GFX_SMG |
4122 AMD_PG_SUPPORT_GFX_DMG |
4123 AMD_PG_SUPPORT_CP |
4124 AMD_PG_SUPPORT_GDS |
4125 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4126 gfx_v7_0_update_gfx_pg(adev, false);
e3b04bc7 4127 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4128 gfx_v7_0_enable_cp_pg(adev, false);
4129 gfx_v7_0_enable_gds_pg(adev, false);
4130 }
4131 }
4132}
4133
4134/**
4135 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4136 *
4137 * @adev: amdgpu_device pointer
4138 *
4139 * Fetches a GPU clock counter snapshot (SI).
4140 * Returns the 64 bit clock counter snapshot.
4141 */
b95e31fd 4142static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
a2e73f56
AD		 4143{
4144 uint64_t clock;
4145
4146 mutex_lock(&adev->gfx.gpu_clock_mutex);
4147 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4148 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4149 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4150 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4151 return clock;
4152}
4153
4154static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4155 uint32_t vmid,
4156 uint32_t gds_base, uint32_t gds_size,
4157 uint32_t gws_base, uint32_t gws_size,
4158 uint32_t oa_base, uint32_t oa_size)
4159{
4160 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4161 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4162
4163 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4164 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4165
4166 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4167 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4168
4169 /* GDS Base */
4170 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4171 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4172 WRITE_DATA_DST_SEL(0)));
4173 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4174 amdgpu_ring_write(ring, 0);
4175 amdgpu_ring_write(ring, gds_base);
4176
4177 /* GDS Size */
4178 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4179 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4180 WRITE_DATA_DST_SEL(0)));
4181 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4182 amdgpu_ring_write(ring, 0);
4183 amdgpu_ring_write(ring, gds_size);
4184
4185 /* GWS */
4186 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4187 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4188 WRITE_DATA_DST_SEL(0)));
4189 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4190 amdgpu_ring_write(ring, 0);
4191 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4192
4193 /* OA */
4194 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4195 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4196 WRITE_DATA_DST_SEL(0)));
4197 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4198 amdgpu_ring_write(ring, 0);
4199 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4200}
4201
b95e31fd
AD		 4202static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4203 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
05fb7291 4204 .select_se_sh = &gfx_v7_0_select_se_sh,
b95e31fd
AD		 4205};
4206
06120a1e
AD		 4207static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4208 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4209 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4210};
4211
5fc3aeeb 4212static int gfx_v7_0_early_init(void *handle)
a2e73f56 4213{
5fc3aeeb 4214 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4215
4216 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4217 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
b95e31fd 4218 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
06120a1e 4219 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
a2e73f56
AD		 4220 gfx_v7_0_set_ring_funcs(adev);
4221 gfx_v7_0_set_irq_funcs(adev);
4222 gfx_v7_0_set_gds_init(adev);
4223
4224 return 0;
4225}
4226
ef720532
AD		 4227static int gfx_v7_0_late_init(void *handle)
4228{
4229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4230 int r;
4231
4232 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4233 if (r)
4234 return r;
4235
4236 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4237 if (r)
4238 return r;
4239
4240 return 0;
4241}
4242
d93f3ca7
AD		 4243static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4244{
4245 u32 gb_addr_config;
4246 u32 mc_shared_chmap, mc_arb_ramcfg;
4247 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4248 u32 tmp;
4249
4250 switch (adev->asic_type) {
4251 case CHIP_BONAIRE:
4252 adev->gfx.config.max_shader_engines = 2;
4253 adev->gfx.config.max_tile_pipes = 4;
4254 adev->gfx.config.max_cu_per_sh = 7;
4255 adev->gfx.config.max_sh_per_se = 1;
4256 adev->gfx.config.max_backends_per_se = 2;
4257 adev->gfx.config.max_texture_channel_caches = 4;
4258 adev->gfx.config.max_gprs = 256;
4259 adev->gfx.config.max_gs_threads = 32;
4260 adev->gfx.config.max_hw_contexts = 8;
4261
4262 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4263 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4264 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4265 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4266 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4267 break;
4268 case CHIP_HAWAII:
4269 adev->gfx.config.max_shader_engines = 4;
4270 adev->gfx.config.max_tile_pipes = 16;
4271 adev->gfx.config.max_cu_per_sh = 11;
4272 adev->gfx.config.max_sh_per_se = 1;
4273 adev->gfx.config.max_backends_per_se = 4;
4274 adev->gfx.config.max_texture_channel_caches = 16;
4275 adev->gfx.config.max_gprs = 256;
4276 adev->gfx.config.max_gs_threads = 32;
4277 adev->gfx.config.max_hw_contexts = 8;
4278
4279 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4280 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4281 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4282 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4283 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4284 break;
4285 case CHIP_KAVERI:
4286 adev->gfx.config.max_shader_engines = 1;
4287 adev->gfx.config.max_tile_pipes = 4;
4288 if ((adev->pdev->device == 0x1304) ||
4289 (adev->pdev->device == 0x1305) ||
4290 (adev->pdev->device == 0x130C) ||
4291 (adev->pdev->device == 0x130F) ||
4292 (adev->pdev->device == 0x1310) ||
4293 (adev->pdev->device == 0x1311) ||
4294 (adev->pdev->device == 0x131C)) {
4295 adev->gfx.config.max_cu_per_sh = 8;
4296 adev->gfx.config.max_backends_per_se = 2;
4297 } else if ((adev->pdev->device == 0x1309) ||
4298 (adev->pdev->device == 0x130A) ||
4299 (adev->pdev->device == 0x130D) ||
4300 (adev->pdev->device == 0x1313) ||
4301 (adev->pdev->device == 0x131D)) {
4302 adev->gfx.config.max_cu_per_sh = 6;
4303 adev->gfx.config.max_backends_per_se = 2;
4304 } else if ((adev->pdev->device == 0x1306) ||
4305 (adev->pdev->device == 0x1307) ||
4306 (adev->pdev->device == 0x130B) ||
4307 (adev->pdev->device == 0x130E) ||
4308 (adev->pdev->device == 0x1315) ||
4309 (adev->pdev->device == 0x131B)) {
4310 adev->gfx.config.max_cu_per_sh = 4;
4311 adev->gfx.config.max_backends_per_se = 1;
4312 } else {
4313 adev->gfx.config.max_cu_per_sh = 3;
4314 adev->gfx.config.max_backends_per_se = 1;
4315 }
4316 adev->gfx.config.max_sh_per_se = 1;
4317 adev->gfx.config.max_texture_channel_caches = 4;
4318 adev->gfx.config.max_gprs = 256;
4319 adev->gfx.config.max_gs_threads = 16;
4320 adev->gfx.config.max_hw_contexts = 8;
4321
4322 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4323 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4324 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4325 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4326 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4327 break;
4328 case CHIP_KABINI:
4329 case CHIP_MULLINS:
4330 default:
4331 adev->gfx.config.max_shader_engines = 1;
4332 adev->gfx.config.max_tile_pipes = 2;
4333 adev->gfx.config.max_cu_per_sh = 2;
4334 adev->gfx.config.max_sh_per_se = 1;
4335 adev->gfx.config.max_backends_per_se = 1;
4336 adev->gfx.config.max_texture_channel_caches = 2;
4337 adev->gfx.config.max_gprs = 256;
4338 adev->gfx.config.max_gs_threads = 16;
4339 adev->gfx.config.max_hw_contexts = 8;
4340
4341 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4342 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4343 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4344 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4345 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4346 break;
4347 }
4348
4349 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4350 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4351 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4352
4353 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4354 adev->gfx.config.mem_max_burst_length_bytes = 256;
4355 if (adev->flags & AMD_IS_APU) {
4356 /* Get memory bank mapping mode. */
4357 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4358 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4359 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4360
4361 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4362 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4363 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4364
4365 /* Validate settings in case only one DIMM installed. */
4366 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4367 dimm00_addr_map = 0;
4368 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4369 dimm01_addr_map = 0;
4370 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4371 dimm10_addr_map = 0;
4372 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4373 dimm11_addr_map = 0;
4374
4375 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4376 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4377 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4378 adev->gfx.config.mem_row_size_in_kb = 2;
4379 else
4380 adev->gfx.config.mem_row_size_in_kb = 1;
4381 } else {
4382 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4383 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4384 if (adev->gfx.config.mem_row_size_in_kb > 4)
4385 adev->gfx.config.mem_row_size_in_kb = 4;
4386 }
4387 /* XXX use MC settings? */
4388 adev->gfx.config.shader_engine_tile_size = 32;
4389 adev->gfx.config.num_gpus = 1;
4390 adev->gfx.config.multi_gpu_tile_size = 64;
4391
4392 /* fix up row size */
4393 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4394 switch (adev->gfx.config.mem_row_size_in_kb) {
4395 case 1:
4396 default:
4397 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4398 break;
4399 case 2:
4400 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4401 break;
4402 case 4:
4403 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4404 break;
4405 }
4406 adev->gfx.config.gb_addr_config = gb_addr_config;
4407}
4408
5fc3aeeb 4409static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4410{
4411 struct amdgpu_ring *ring;
5fc3aeeb 4412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4413 int i, r;
4414
4415 /* EOP Event */
4416 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4417 if (r)
4418 return r;
4419
4420 /* Privileged reg */
4421 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4422 if (r)
4423 return r;
4424
4425 /* Privileged inst */
4426 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4427 if (r)
4428 return r;
4429
4430 gfx_v7_0_scratch_init(adev);
4431
4432 r = gfx_v7_0_init_microcode(adev);
4433 if (r) {
4434 DRM_ERROR("Failed to load gfx firmware!\n");
4435 return r;
4436 }
4437
4438 r = gfx_v7_0_rlc_init(adev);
4439 if (r) {
4440 DRM_ERROR("Failed to init rlc BOs!\n");
4441 return r;
4442 }
4443
4444 /* allocate mec buffers */
4445 r = gfx_v7_0_mec_init(adev);
4446 if (r) {
4447 DRM_ERROR("Failed to init MEC BOs!\n");
4448 return r;
4449 }
4450
a2e73f56
AD		 4451 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4452 ring = &adev->gfx.gfx_ring[i];
4453 ring->ring_obj = NULL;
4454 sprintf(ring->name, "gfx");
2800de2e 4455 r = amdgpu_ring_init(adev, ring, 1024,
a2e73f56
AD		 4456 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4457 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4458 AMDGPU_RING_TYPE_GFX);
4459 if (r)
4460 return r;
4461 }
4462
4463 /* set up the compute queues */
4464 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4465 unsigned irq_type;
4466
4467 /* max 32 queues per MEC */
4468 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4469 DRM_ERROR("Too many (%d) compute rings!\n", i);
4470 break;
4471 }
4472 ring = &adev->gfx.compute_ring[i];
4473 ring->ring_obj = NULL;
4474 ring->use_doorbell = true;
4475 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4476 ring->me = 1; /* first MEC */
4477 ring->pipe = i / 8;
4478 ring->queue = i % 8;
771c8ec1 4479 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
a2e73f56
AD		 4480 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4481 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 4482 r = amdgpu_ring_init(adev, ring, 1024,
a2e73f56
AD		 4483 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4484 &adev->gfx.eop_irq, irq_type,
4485 AMDGPU_RING_TYPE_COMPUTE);
4486 if (r)
4487 return r;
4488 }
4489
4490 /* reserve GDS, GWS and OA resource for gfx */
4491 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4492 PAGE_SIZE, true,
4493 AMDGPU_GEM_DOMAIN_GDS, 0,
72d7668b 4494 NULL, NULL, &adev->gds.gds_gfx_bo);
a2e73f56
AD		 4495 if (r)
4496 return r;
4497
4498 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4499 PAGE_SIZE, true,
4500 AMDGPU_GEM_DOMAIN_GWS, 0,
72d7668b 4501 NULL, NULL, &adev->gds.gws_gfx_bo);
a2e73f56
AD		 4502 if (r)
4503 return r;
4504
4505 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4506 PAGE_SIZE, true,
4507 AMDGPU_GEM_DOMAIN_OA, 0,
72d7668b 4508 NULL, NULL, &adev->gds.oa_gfx_bo);
a2e73f56
AD		 4509 if (r)
4510 return r;
4511
d93f3ca7
AD		 4512 adev->gfx.ce_ram_size = 0x8000;
4513
4514 gfx_v7_0_gpu_early_init(adev);
4515
a2e73f56
AD		 4516 return r;
4517}
4518
5fc3aeeb 4519static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4520{
4521 int i;
5fc3aeeb 4522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4523
4524 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4525 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4526 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4527
4528 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4529 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4530 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4531 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4532
a2e73f56
AD		 4533 gfx_v7_0_cp_compute_fini(adev);
4534 gfx_v7_0_rlc_fini(adev);
4535 gfx_v7_0_mec_fini(adev);
e517cd77 4536 gfx_v7_0_free_microcode(adev);
a2e73f56
AD		 4537
4538 return 0;
4539}
4540
5fc3aeeb 4541static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4542{
4543 int r;
5fc3aeeb 4544 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4545
4546 gfx_v7_0_gpu_init(adev);
4547
4548 /* init rlc */
4549 r = gfx_v7_0_rlc_resume(adev);
4550 if (r)
4551 return r;
4552
4553 r = gfx_v7_0_cp_resume(adev);
4554 if (r)
4555 return r;
4556
4557 return r;
4558}
4559
5fc3aeeb 4560static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4561{
5fc3aeeb 4562 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4563
ef720532
AD		 4564 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4565 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4566 gfx_v7_0_cp_enable(adev, false);
4567 gfx_v7_0_rlc_stop(adev);
4568 gfx_v7_0_fini_pg(adev);
4569
4570 return 0;
4571}
4572
5fc3aeeb 4573static int gfx_v7_0_suspend(void *handle)
a2e73f56 4574{
5fc3aeeb 4575 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4576
a2e73f56
AD		 4577 return gfx_v7_0_hw_fini(adev);
4578}
4579
5fc3aeeb 4580static int gfx_v7_0_resume(void *handle)
a2e73f56 4581{
5fc3aeeb 4582 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4583
a2e73f56
AD		 4584 return gfx_v7_0_hw_init(adev);
4585}
4586
5fc3aeeb 4587static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4588{
5fc3aeeb 4589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4590
a2e73f56
AD		 4591 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4592 return false;
4593 else
4594 return true;
4595}
4596
5fc3aeeb 4597static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4598{
4599 unsigned i;
4600 u32 tmp;
5fc3aeeb 4601 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4602
4603 for (i = 0; i < adev->usec_timeout; i++) {
4604 /* read MC_STATUS */
4605 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4606
4607 if (!tmp)
4608 return 0;
4609 udelay(1);
4610 }
4611 return -ETIMEDOUT;
4612}
4613
5fc3aeeb 4614static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4615{
4616 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4617 u32 tmp;
5fc3aeeb 4618 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4619
4620 /* GRBM_STATUS */
4621 tmp = RREG32(mmGRBM_STATUS);
4622 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4623 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4624 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4625 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4626 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4627 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4628 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4629 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4630
4631 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4632 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4633 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4634 }
4635
4636 /* GRBM_STATUS2 */
4637 tmp = RREG32(mmGRBM_STATUS2);
4638 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4639 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4640
4641 /* SRBM_STATUS */
4642 tmp = RREG32(mmSRBM_STATUS);
4643 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4644 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4645
4646 if (grbm_soft_reset || srbm_soft_reset) {
a2e73f56
AD		 4647 /* disable CG/PG */
4648 gfx_v7_0_fini_pg(adev);
4649 gfx_v7_0_update_cg(adev, false);
4650
4651 /* stop the rlc */
4652 gfx_v7_0_rlc_stop(adev);
4653
4654 /* Disable GFX parsing/prefetching */
4655 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4656
4657 /* Disable MEC parsing/prefetching */
4658 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4659
4660 if (grbm_soft_reset) {
4661 tmp = RREG32(mmGRBM_SOFT_RESET);
4662 tmp |= grbm_soft_reset;
4663 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4664 WREG32(mmGRBM_SOFT_RESET, tmp);
4665 tmp = RREG32(mmGRBM_SOFT_RESET);
4666
4667 udelay(50);
4668
4669 tmp &= ~grbm_soft_reset;
4670 WREG32(mmGRBM_SOFT_RESET, tmp);
4671 tmp = RREG32(mmGRBM_SOFT_RESET);
4672 }
4673
4674 if (srbm_soft_reset) {
4675 tmp = RREG32(mmSRBM_SOFT_RESET);
4676 tmp |= srbm_soft_reset;
4677 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4678 WREG32(mmSRBM_SOFT_RESET, tmp);
4679 tmp = RREG32(mmSRBM_SOFT_RESET);
4680
4681 udelay(50);
4682
4683 tmp &= ~srbm_soft_reset;
4684 WREG32(mmSRBM_SOFT_RESET, tmp);
4685 tmp = RREG32(mmSRBM_SOFT_RESET);
4686 }
4687 /* Wait a little for things to settle down */
4688 udelay(50);
a2e73f56
AD		 4689 }
4690 return 0;
4691}
4692
4693static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4694 enum amdgpu_interrupt_state state)
4695{
4696 u32 cp_int_cntl;
4697
4698 switch (state) {
4699 case AMDGPU_IRQ_STATE_DISABLE:
4700 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4701 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4702 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4703 break;
4704 case AMDGPU_IRQ_STATE_ENABLE:
4705 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4706 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4707 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4708 break;
4709 default:
4710 break;
4711 }
4712}
4713
4714static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4715 int me, int pipe,
4716 enum amdgpu_interrupt_state state)
4717{
4718 u32 mec_int_cntl, mec_int_cntl_reg;
4719
4720 /*
4721 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4722 * handles the setting of interrupts for this specific pipe. All other
4723 * pipes' interrupts are set by amdkfd.
4724 */
4725
4726 if (me == 1) {
4727 switch (pipe) {
4728 case 0:
4729 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4730 break;
4731 default:
4732 DRM_DEBUG("invalid pipe %d\n", pipe);
4733 return;
4734 }
4735 } else {
4736 DRM_DEBUG("invalid me %d\n", me);
4737 return;
4738 }
4739
4740 switch (state) {
4741 case AMDGPU_IRQ_STATE_DISABLE:
4742 mec_int_cntl = RREG32(mec_int_cntl_reg);
4743 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4744 WREG32(mec_int_cntl_reg, mec_int_cntl);
4745 break;
4746 case AMDGPU_IRQ_STATE_ENABLE:
4747 mec_int_cntl = RREG32(mec_int_cntl_reg);
4748 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4749 WREG32(mec_int_cntl_reg, mec_int_cntl);
4750 break;
4751 default:
4752 break;
4753 }
4754}
4755
4756static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4757 struct amdgpu_irq_src *src,
4758 unsigned type,
4759 enum amdgpu_interrupt_state state)
4760{
4761 u32 cp_int_cntl;
4762
4763 switch (state) {
4764 case AMDGPU_IRQ_STATE_DISABLE:
4765 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4766 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4767 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4768 break;
4769 case AMDGPU_IRQ_STATE_ENABLE:
4770 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4771 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4772 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4773 break;
4774 default:
4775 break;
4776 }
4777
4778 return 0;
4779}
4780
4781static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4782 struct amdgpu_irq_src *src,
4783 unsigned type,
4784 enum amdgpu_interrupt_state state)
4785{
4786 u32 cp_int_cntl;
4787
4788 switch (state) {
4789 case AMDGPU_IRQ_STATE_DISABLE:
4790 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4791 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4792 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4793 break;
4794 case AMDGPU_IRQ_STATE_ENABLE:
4795 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4796 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4797 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4798 break;
4799 default:
4800 break;
4801 }
4802
4803 return 0;
4804}
4805
4806static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4807 struct amdgpu_irq_src *src,
4808 unsigned type,
4809 enum amdgpu_interrupt_state state)
4810{
4811 switch (type) {
4812 case AMDGPU_CP_IRQ_GFX_EOP:
4813 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4814 break;
4815 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4816 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4817 break;
4818 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4819 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4820 break;
4821 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4822 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4823 break;
4824 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4825 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4826 break;
4827 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4828 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4829 break;
4830 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4831 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4832 break;
4833 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4834 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4835 break;
4836 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4837 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4838 break;
4839 default:
4840 break;
4841 }
4842 return 0;
4843}
4844
4845static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4846 struct amdgpu_irq_src *source,
4847 struct amdgpu_iv_entry *entry)
4848{
4849 u8 me_id, pipe_id;
4850 struct amdgpu_ring *ring;
4851 int i;
4852
4853 DRM_DEBUG("IH: CP EOP\n");
4854 me_id = (entry->ring_id & 0x0c) >> 2;
4855 pipe_id = (entry->ring_id & 0x03) >> 0;
4856 switch (me_id) {
4857 case 0:
4858 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4859 break;
4860 case 1:
4861 case 2:
4862 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4863 ring = &adev->gfx.compute_ring[i];
8b18300c 4864 if ((ring->me == me_id) && (ring->pipe == pipe_id))
a2e73f56
AD		 4865 amdgpu_fence_process(ring);
4866 }
4867 break;
4868 }
4869 return 0;
4870}
4871
4872static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4873 struct amdgpu_irq_src *source,
4874 struct amdgpu_iv_entry *entry)
4875{
4876 DRM_ERROR("Illegal register access in command stream\n");
4877 schedule_work(&adev->reset_work);
4878 return 0;
4879}
4880
4881static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4882 struct amdgpu_irq_src *source,
4883 struct amdgpu_iv_entry *entry)
4884{
4885 DRM_ERROR("Illegal instruction in command stream\n");
4886 // XXX soft reset the gfx block only
4887 schedule_work(&adev->reset_work);
4888 return 0;
4889}
4890
5fc3aeeb 4891static int gfx_v7_0_set_clockgating_state(void *handle,
4892 enum amd_clockgating_state state)
a2e73f56
AD		 4893{
4894 bool gate = false;
5fc3aeeb 4895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4896
5fc3aeeb 4897 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 4898 gate = true;
4899
4900 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4901 /* order matters! */
4902 if (gate) {
4903 gfx_v7_0_enable_mgcg(adev, true);
4904 gfx_v7_0_enable_cgcg(adev, true);
4905 } else {
4906 gfx_v7_0_enable_cgcg(adev, false);
4907 gfx_v7_0_enable_mgcg(adev, false);
4908 }
4909 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4910
4911 return 0;
4912}
4913
5fc3aeeb 4914static int gfx_v7_0_set_powergating_state(void *handle,
4915 enum amd_powergating_state state)
a2e73f56
AD		 4916{
4917 bool gate = false;
5fc3aeeb 4918 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4919
5fc3aeeb 4920 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 4921 gate = true;
4922
e3b04bc7
AD		 4923 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4924 AMD_PG_SUPPORT_GFX_SMG |
4925 AMD_PG_SUPPORT_GFX_DMG |
4926 AMD_PG_SUPPORT_CP |
4927 AMD_PG_SUPPORT_GDS |
4928 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4929 gfx_v7_0_update_gfx_pg(adev, gate);
e3b04bc7 4930 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4931 gfx_v7_0_enable_cp_pg(adev, gate);
4932 gfx_v7_0_enable_gds_pg(adev, gate);
4933 }
4934 }
4935
4936 return 0;
4937}
4938
5fc3aeeb 4939const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
88a907d6 4940 .name = "gfx_v7_0",
a2e73f56 4941 .early_init = gfx_v7_0_early_init,
ef720532 4942 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 4943 .sw_init = gfx_v7_0_sw_init,
4944 .sw_fini = gfx_v7_0_sw_fini,
4945 .hw_init = gfx_v7_0_hw_init,
4946 .hw_fini = gfx_v7_0_hw_fini,
4947 .suspend = gfx_v7_0_suspend,
4948 .resume = gfx_v7_0_resume,
4949 .is_idle = gfx_v7_0_is_idle,
4950 .wait_for_idle = gfx_v7_0_wait_for_idle,
4951 .soft_reset = gfx_v7_0_soft_reset,
a2e73f56
AD		 4952 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4953 .set_powergating_state = gfx_v7_0_set_powergating_state,
4954};
4955
a2e73f56
AD		 4956static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4957 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
4958 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4959 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4960 .parse_cs = NULL,
93323131 4961 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 4962 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
b8c7b39e 4963 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 4964 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4965 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 4966 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 4967 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 4968 .test_ring = gfx_v7_0_ring_test_ring,
4969 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 4970 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 4971 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 4972};
4973
4974static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4975 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
4976 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
4977 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
4978 .parse_cs = NULL,
93323131 4979 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 4980 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
b8c7b39e 4981 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 4982 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4983 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 4984 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 4985 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 4986 .test_ring = gfx_v7_0_ring_test_ring,
4987 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 4988 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 4989 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 4990};
4991
4992static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4993{
4994 int i;
4995
4996 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4997 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
4998 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4999 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5000}
5001
5002static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5003 .set = gfx_v7_0_set_eop_interrupt_state,
5004 .process = gfx_v7_0_eop_irq,
5005};
5006
5007static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5008 .set = gfx_v7_0_set_priv_reg_fault_state,
5009 .process = gfx_v7_0_priv_reg_irq,
5010};
5011
5012static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5013 .set = gfx_v7_0_set_priv_inst_fault_state,
5014 .process = gfx_v7_0_priv_inst_irq,
5015};
5016
5017static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5018{
5019 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5020 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5021
5022 adev->gfx.priv_reg_irq.num_types = 1;
5023 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5024
5025 adev->gfx.priv_inst_irq.num_types = 1;
5026 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5027}
5028
5029static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5030{
5031 /* init asci gds info */
5032 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5033 adev->gds.gws.total_size = 64;
5034 adev->gds.oa.total_size = 16;
5035
5036 if (adev->gds.mem.total_size == 64 * 1024) {
5037 adev->gds.mem.gfx_partition_size = 4096;
5038 adev->gds.mem.cs_partition_size = 4096;
5039
5040 adev->gds.gws.gfx_partition_size = 4;
5041 adev->gds.gws.cs_partition_size = 4;
5042
5043 adev->gds.oa.gfx_partition_size = 4;
5044 adev->gds.oa.cs_partition_size = 1;
5045 } else {
5046 adev->gds.mem.gfx_partition_size = 1024;
5047 adev->gds.mem.cs_partition_size = 1024;
5048
5049 adev->gds.gws.gfx_partition_size = 16;
5050 adev->gds.gws.cs_partition_size = 16;
5051
5052 adev->gds.oa.gfx_partition_size = 4;
5053 adev->gds.oa.cs_partition_size = 4;
5054 }
5055}
5056
5057
7dae69a2 5058static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
a2e73f56
AD		 5059{
5060 int i, j, k, counter, active_cu_number = 0;
5061 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 5062 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
324c614a 5063 unsigned disable_masks[4 * 2];
a2e73f56 5064
6157bd7a
FC		 5065 memset(cu_info, 0, sizeof(*cu_info));
5066
324c614a
NH		 5067 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5068
a2e73f56
AD		 5069 mutex_lock(&adev->grbm_idx_mutex);
5070 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5071 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5072 mask = 1;
5073 ao_bitmap = 0;
5074 counter = 0;
8f8e00c1 5075 gfx_v7_0_select_se_sh(adev, i, j);
324c614a
NH		 5076 if (i < 4 && j < 2)
5077 gfx_v7_0_set_user_cu_inactive_bitmap(
5078 adev, disable_masks[i * 2 + j]);
8f8e00c1 5079 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5080 cu_info->bitmap[i][j] = bitmap;
5081
8f8e00c1 5082 for (k = 0; k < 16; k ++) {
a2e73f56
AD		 5083 if (bitmap & mask) {
5084 if (counter < 2)
5085 ao_bitmap |= mask;
5086 counter ++;
5087 }
5088 mask <<= 1;
5089 }
5090 active_cu_number += counter;
5091 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5092 }
5093 }
8f8e00c1
AD		 5094 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5095 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5096
5097 cu_info->number = active_cu_number;
5098 cu_info->ao_cu_mask = ao_cu_mask;
a2e73f56 5099}
Linux 6.x block layer and io_uring tree(s)