projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
a2e73f56
AD		 34#include "dce/dce_8_0_d.h"
35#include "dce/dce_8_0_sh_mask.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gca/gfx_7_0_d.h"
41#include "gca/gfx_7_2_enum.h"
42#include "gca/gfx_7_2_sh_mask.h"
43
44#include "gmc/gmc_7_0_d.h"
45#include "gmc/gmc_7_0_sh_mask.h"
46
47#include "oss/oss_2_0_d.h"
48#include "oss/oss_2_0_sh_mask.h"
49
50#define GFX7_NUM_GFX_RINGS 1
51#define GFX7_NUM_COMPUTE_RINGS 8
52
53static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
a2e73f56
AD		 56
57MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58MODULE_FIRMWARE("radeon/bonaire_me.bin");
59MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61MODULE_FIRMWARE("radeon/bonaire_mec.bin");
62
63MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64MODULE_FIRMWARE("radeon/hawaii_me.bin");
65MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68
69MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70MODULE_FIRMWARE("radeon/kaveri_me.bin");
71MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
75
76MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77MODULE_FIRMWARE("radeon/kabini_me.bin");
78MODULE_FIRMWARE("radeon/kabini_ce.bin");
79MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80MODULE_FIRMWARE("radeon/kabini_mec.bin");
81
82MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83MODULE_FIRMWARE("radeon/mullins_me.bin");
84MODULE_FIRMWARE("radeon/mullins_ce.bin");
85MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86MODULE_FIRMWARE("radeon/mullins_mec.bin");
87
88static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
89{
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
106};
107
108static const u32 spectre_rlc_save_restore_register_list[] =
109{
110 (0x0e00 << 16) | (0xc12c >> 2),
111 0x00000000,
112 (0x0e00 << 16) | (0xc140 >> 2),
113 0x00000000,
114 (0x0e00 << 16) | (0xc150 >> 2),
115 0x00000000,
116 (0x0e00 << 16) | (0xc15c >> 2),
117 0x00000000,
118 (0x0e00 << 16) | (0xc168 >> 2),
119 0x00000000,
120 (0x0e00 << 16) | (0xc170 >> 2),
121 0x00000000,
122 (0x0e00 << 16) | (0xc178 >> 2),
123 0x00000000,
124 (0x0e00 << 16) | (0xc204 >> 2),
125 0x00000000,
126 (0x0e00 << 16) | (0xc2b4 >> 2),
127 0x00000000,
128 (0x0e00 << 16) | (0xc2b8 >> 2),
129 0x00000000,
130 (0x0e00 << 16) | (0xc2bc >> 2),
131 0x00000000,
132 (0x0e00 << 16) | (0xc2c0 >> 2),
133 0x00000000,
134 (0x0e00 << 16) | (0x8228 >> 2),
135 0x00000000,
136 (0x0e00 << 16) | (0x829c >> 2),
137 0x00000000,
138 (0x0e00 << 16) | (0x869c >> 2),
139 0x00000000,
140 (0x0600 << 16) | (0x98f4 >> 2),
141 0x00000000,
142 (0x0e00 << 16) | (0x98f8 >> 2),
143 0x00000000,
144 (0x0e00 << 16) | (0x9900 >> 2),
145 0x00000000,
146 (0x0e00 << 16) | (0xc260 >> 2),
147 0x00000000,
148 (0x0e00 << 16) | (0x90e8 >> 2),
149 0x00000000,
150 (0x0e00 << 16) | (0x3c000 >> 2),
151 0x00000000,
152 (0x0e00 << 16) | (0x3c00c >> 2),
153 0x00000000,
154 (0x0e00 << 16) | (0x8c1c >> 2),
155 0x00000000,
156 (0x0e00 << 16) | (0x9700 >> 2),
157 0x00000000,
158 (0x0e00 << 16) | (0xcd20 >> 2),
159 0x00000000,
160 (0x4e00 << 16) | (0xcd20 >> 2),
161 0x00000000,
162 (0x5e00 << 16) | (0xcd20 >> 2),
163 0x00000000,
164 (0x6e00 << 16) | (0xcd20 >> 2),
165 0x00000000,
166 (0x7e00 << 16) | (0xcd20 >> 2),
167 0x00000000,
168 (0x8e00 << 16) | (0xcd20 >> 2),
169 0x00000000,
170 (0x9e00 << 16) | (0xcd20 >> 2),
171 0x00000000,
172 (0xae00 << 16) | (0xcd20 >> 2),
173 0x00000000,
174 (0xbe00 << 16) | (0xcd20 >> 2),
175 0x00000000,
176 (0x0e00 << 16) | (0x89bc >> 2),
177 0x00000000,
178 (0x0e00 << 16) | (0x8900 >> 2),
179 0x00000000,
180 0x3,
181 (0x0e00 << 16) | (0xc130 >> 2),
182 0x00000000,
183 (0x0e00 << 16) | (0xc134 >> 2),
184 0x00000000,
185 (0x0e00 << 16) | (0xc1fc >> 2),
186 0x00000000,
187 (0x0e00 << 16) | (0xc208 >> 2),
188 0x00000000,
189 (0x0e00 << 16) | (0xc264 >> 2),
190 0x00000000,
191 (0x0e00 << 16) | (0xc268 >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc26c >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc270 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc274 >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc278 >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc27c >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc280 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc284 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc288 >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc28c >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc290 >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc294 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0xc298 >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0xc29c >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0xc2a0 >> 2),
220 0x00000000,
221 (0x0e00 << 16) | (0xc2a4 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0xc2a8 >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0xc2ac >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc2b0 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0x301d0 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0x30238 >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0x30250 >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x30254 >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x30258 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0x3025c >> 2),
240 0x00000000,
241 (0x4e00 << 16) | (0xc900 >> 2),
242 0x00000000,
243 (0x5e00 << 16) | (0xc900 >> 2),
244 0x00000000,
245 (0x6e00 << 16) | (0xc900 >> 2),
246 0x00000000,
247 (0x7e00 << 16) | (0xc900 >> 2),
248 0x00000000,
249 (0x8e00 << 16) | (0xc900 >> 2),
250 0x00000000,
251 (0x9e00 << 16) | (0xc900 >> 2),
252 0x00000000,
253 (0xae00 << 16) | (0xc900 >> 2),
254 0x00000000,
255 (0xbe00 << 16) | (0xc900 >> 2),
256 0x00000000,
257 (0x4e00 << 16) | (0xc904 >> 2),
258 0x00000000,
259 (0x5e00 << 16) | (0xc904 >> 2),
260 0x00000000,
261 (0x6e00 << 16) | (0xc904 >> 2),
262 0x00000000,
263 (0x7e00 << 16) | (0xc904 >> 2),
264 0x00000000,
265 (0x8e00 << 16) | (0xc904 >> 2),
266 0x00000000,
267 (0x9e00 << 16) | (0xc904 >> 2),
268 0x00000000,
269 (0xae00 << 16) | (0xc904 >> 2),
270 0x00000000,
271 (0xbe00 << 16) | (0xc904 >> 2),
272 0x00000000,
273 (0x4e00 << 16) | (0xc908 >> 2),
274 0x00000000,
275 (0x5e00 << 16) | (0xc908 >> 2),
276 0x00000000,
277 (0x6e00 << 16) | (0xc908 >> 2),
278 0x00000000,
279 (0x7e00 << 16) | (0xc908 >> 2),
280 0x00000000,
281 (0x8e00 << 16) | (0xc908 >> 2),
282 0x00000000,
283 (0x9e00 << 16) | (0xc908 >> 2),
284 0x00000000,
285 (0xae00 << 16) | (0xc908 >> 2),
286 0x00000000,
287 (0xbe00 << 16) | (0xc908 >> 2),
288 0x00000000,
289 (0x4e00 << 16) | (0xc90c >> 2),
290 0x00000000,
291 (0x5e00 << 16) | (0xc90c >> 2),
292 0x00000000,
293 (0x6e00 << 16) | (0xc90c >> 2),
294 0x00000000,
295 (0x7e00 << 16) | (0xc90c >> 2),
296 0x00000000,
297 (0x8e00 << 16) | (0xc90c >> 2),
298 0x00000000,
299 (0x9e00 << 16) | (0xc90c >> 2),
300 0x00000000,
301 (0xae00 << 16) | (0xc90c >> 2),
302 0x00000000,
303 (0xbe00 << 16) | (0xc90c >> 2),
304 0x00000000,
305 (0x4e00 << 16) | (0xc910 >> 2),
306 0x00000000,
307 (0x5e00 << 16) | (0xc910 >> 2),
308 0x00000000,
309 (0x6e00 << 16) | (0xc910 >> 2),
310 0x00000000,
311 (0x7e00 << 16) | (0xc910 >> 2),
312 0x00000000,
313 (0x8e00 << 16) | (0xc910 >> 2),
314 0x00000000,
315 (0x9e00 << 16) | (0xc910 >> 2),
316 0x00000000,
317 (0xae00 << 16) | (0xc910 >> 2),
318 0x00000000,
319 (0xbe00 << 16) | (0xc910 >> 2),
320 0x00000000,
321 (0x0e00 << 16) | (0xc99c >> 2),
322 0x00000000,
323 (0x0e00 << 16) | (0x9834 >> 2),
324 0x00000000,
325 (0x0000 << 16) | (0x30f00 >> 2),
326 0x00000000,
327 (0x0001 << 16) | (0x30f00 >> 2),
328 0x00000000,
329 (0x0000 << 16) | (0x30f04 >> 2),
330 0x00000000,
331 (0x0001 << 16) | (0x30f04 >> 2),
332 0x00000000,
333 (0x0000 << 16) | (0x30f08 >> 2),
334 0x00000000,
335 (0x0001 << 16) | (0x30f08 >> 2),
336 0x00000000,
337 (0x0000 << 16) | (0x30f0c >> 2),
338 0x00000000,
339 (0x0001 << 16) | (0x30f0c >> 2),
340 0x00000000,
341 (0x0600 << 16) | (0x9b7c >> 2),
342 0x00000000,
343 (0x0e00 << 16) | (0x8a14 >> 2),
344 0x00000000,
345 (0x0e00 << 16) | (0x8a18 >> 2),
346 0x00000000,
347 (0x0600 << 16) | (0x30a00 >> 2),
348 0x00000000,
349 (0x0e00 << 16) | (0x8bf0 >> 2),
350 0x00000000,
351 (0x0e00 << 16) | (0x8bcc >> 2),
352 0x00000000,
353 (0x0e00 << 16) | (0x8b24 >> 2),
354 0x00000000,
355 (0x0e00 << 16) | (0x30a04 >> 2),
356 0x00000000,
357 (0x0600 << 16) | (0x30a10 >> 2),
358 0x00000000,
359 (0x0600 << 16) | (0x30a14 >> 2),
360 0x00000000,
361 (0x0600 << 16) | (0x30a18 >> 2),
362 0x00000000,
363 (0x0600 << 16) | (0x30a2c >> 2),
364 0x00000000,
365 (0x0e00 << 16) | (0xc700 >> 2),
366 0x00000000,
367 (0x0e00 << 16) | (0xc704 >> 2),
368 0x00000000,
369 (0x0e00 << 16) | (0xc708 >> 2),
370 0x00000000,
371 (0x0e00 << 16) | (0xc768 >> 2),
372 0x00000000,
373 (0x0400 << 16) | (0xc770 >> 2),
374 0x00000000,
375 (0x0400 << 16) | (0xc774 >> 2),
376 0x00000000,
377 (0x0400 << 16) | (0xc778 >> 2),
378 0x00000000,
379 (0x0400 << 16) | (0xc77c >> 2),
380 0x00000000,
381 (0x0400 << 16) | (0xc780 >> 2),
382 0x00000000,
383 (0x0400 << 16) | (0xc784 >> 2),
384 0x00000000,
385 (0x0400 << 16) | (0xc788 >> 2),
386 0x00000000,
387 (0x0400 << 16) | (0xc78c >> 2),
388 0x00000000,
389 (0x0400 << 16) | (0xc798 >> 2),
390 0x00000000,
391 (0x0400 << 16) | (0xc79c >> 2),
392 0x00000000,
393 (0x0400 << 16) | (0xc7a0 >> 2),
394 0x00000000,
395 (0x0400 << 16) | (0xc7a4 >> 2),
396 0x00000000,
397 (0x0400 << 16) | (0xc7a8 >> 2),
398 0x00000000,
399 (0x0400 << 16) | (0xc7ac >> 2),
400 0x00000000,
401 (0x0400 << 16) | (0xc7b0 >> 2),
402 0x00000000,
403 (0x0400 << 16) | (0xc7b4 >> 2),
404 0x00000000,
405 (0x0e00 << 16) | (0x9100 >> 2),
406 0x00000000,
407 (0x0e00 << 16) | (0x3c010 >> 2),
408 0x00000000,
409 (0x0e00 << 16) | (0x92a8 >> 2),
410 0x00000000,
411 (0x0e00 << 16) | (0x92ac >> 2),
412 0x00000000,
413 (0x0e00 << 16) | (0x92b4 >> 2),
414 0x00000000,
415 (0x0e00 << 16) | (0x92b8 >> 2),
416 0x00000000,
417 (0x0e00 << 16) | (0x92bc >> 2),
418 0x00000000,
419 (0x0e00 << 16) | (0x92c0 >> 2),
420 0x00000000,
421 (0x0e00 << 16) | (0x92c4 >> 2),
422 0x00000000,
423 (0x0e00 << 16) | (0x92c8 >> 2),
424 0x00000000,
425 (0x0e00 << 16) | (0x92cc >> 2),
426 0x00000000,
427 (0x0e00 << 16) | (0x92d0 >> 2),
428 0x00000000,
429 (0x0e00 << 16) | (0x8c00 >> 2),
430 0x00000000,
431 (0x0e00 << 16) | (0x8c04 >> 2),
432 0x00000000,
433 (0x0e00 << 16) | (0x8c20 >> 2),
434 0x00000000,
435 (0x0e00 << 16) | (0x8c38 >> 2),
436 0x00000000,
437 (0x0e00 << 16) | (0x8c3c >> 2),
438 0x00000000,
439 (0x0e00 << 16) | (0xae00 >> 2),
440 0x00000000,
441 (0x0e00 << 16) | (0x9604 >> 2),
442 0x00000000,
443 (0x0e00 << 16) | (0xac08 >> 2),
444 0x00000000,
445 (0x0e00 << 16) | (0xac0c >> 2),
446 0x00000000,
447 (0x0e00 << 16) | (0xac10 >> 2),
448 0x00000000,
449 (0x0e00 << 16) | (0xac14 >> 2),
450 0x00000000,
451 (0x0e00 << 16) | (0xac58 >> 2),
452 0x00000000,
453 (0x0e00 << 16) | (0xac68 >> 2),
454 0x00000000,
455 (0x0e00 << 16) | (0xac6c >> 2),
456 0x00000000,
457 (0x0e00 << 16) | (0xac70 >> 2),
458 0x00000000,
459 (0x0e00 << 16) | (0xac74 >> 2),
460 0x00000000,
461 (0x0e00 << 16) | (0xac78 >> 2),
462 0x00000000,
463 (0x0e00 << 16) | (0xac7c >> 2),
464 0x00000000,
465 (0x0e00 << 16) | (0xac80 >> 2),
466 0x00000000,
467 (0x0e00 << 16) | (0xac84 >> 2),
468 0x00000000,
469 (0x0e00 << 16) | (0xac88 >> 2),
470 0x00000000,
471 (0x0e00 << 16) | (0xac8c >> 2),
472 0x00000000,
473 (0x0e00 << 16) | (0x970c >> 2),
474 0x00000000,
475 (0x0e00 << 16) | (0x9714 >> 2),
476 0x00000000,
477 (0x0e00 << 16) | (0x9718 >> 2),
478 0x00000000,
479 (0x0e00 << 16) | (0x971c >> 2),
480 0x00000000,
481 (0x0e00 << 16) | (0x31068 >> 2),
482 0x00000000,
483 (0x4e00 << 16) | (0x31068 >> 2),
484 0x00000000,
485 (0x5e00 << 16) | (0x31068 >> 2),
486 0x00000000,
487 (0x6e00 << 16) | (0x31068 >> 2),
488 0x00000000,
489 (0x7e00 << 16) | (0x31068 >> 2),
490 0x00000000,
491 (0x8e00 << 16) | (0x31068 >> 2),
492 0x00000000,
493 (0x9e00 << 16) | (0x31068 >> 2),
494 0x00000000,
495 (0xae00 << 16) | (0x31068 >> 2),
496 0x00000000,
497 (0xbe00 << 16) | (0x31068 >> 2),
498 0x00000000,
499 (0x0e00 << 16) | (0xcd10 >> 2),
500 0x00000000,
501 (0x0e00 << 16) | (0xcd14 >> 2),
502 0x00000000,
503 (0x0e00 << 16) | (0x88b0 >> 2),
504 0x00000000,
505 (0x0e00 << 16) | (0x88b4 >> 2),
506 0x00000000,
507 (0x0e00 << 16) | (0x88b8 >> 2),
508 0x00000000,
509 (0x0e00 << 16) | (0x88bc >> 2),
510 0x00000000,
511 (0x0400 << 16) | (0x89c0 >> 2),
512 0x00000000,
513 (0x0e00 << 16) | (0x88c4 >> 2),
514 0x00000000,
515 (0x0e00 << 16) | (0x88c8 >> 2),
516 0x00000000,
517 (0x0e00 << 16) | (0x88d0 >> 2),
518 0x00000000,
519 (0x0e00 << 16) | (0x88d4 >> 2),
520 0x00000000,
521 (0x0e00 << 16) | (0x88d8 >> 2),
522 0x00000000,
523 (0x0e00 << 16) | (0x8980 >> 2),
524 0x00000000,
525 (0x0e00 << 16) | (0x30938 >> 2),
526 0x00000000,
527 (0x0e00 << 16) | (0x3093c >> 2),
528 0x00000000,
529 (0x0e00 << 16) | (0x30940 >> 2),
530 0x00000000,
531 (0x0e00 << 16) | (0x89a0 >> 2),
532 0x00000000,
533 (0x0e00 << 16) | (0x30900 >> 2),
534 0x00000000,
535 (0x0e00 << 16) | (0x30904 >> 2),
536 0x00000000,
537 (0x0e00 << 16) | (0x89b4 >> 2),
538 0x00000000,
539 (0x0e00 << 16) | (0x3c210 >> 2),
540 0x00000000,
541 (0x0e00 << 16) | (0x3c214 >> 2),
542 0x00000000,
543 (0x0e00 << 16) | (0x3c218 >> 2),
544 0x00000000,
545 (0x0e00 << 16) | (0x8904 >> 2),
546 0x00000000,
547 0x5,
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
553};
554
555static const u32 kalindi_rlc_save_restore_register_list[] =
556{
557 (0x0e00 << 16) | (0xc12c >> 2),
558 0x00000000,
559 (0x0e00 << 16) | (0xc140 >> 2),
560 0x00000000,
561 (0x0e00 << 16) | (0xc150 >> 2),
562 0x00000000,
563 (0x0e00 << 16) | (0xc15c >> 2),
564 0x00000000,
565 (0x0e00 << 16) | (0xc168 >> 2),
566 0x00000000,
567 (0x0e00 << 16) | (0xc170 >> 2),
568 0x00000000,
569 (0x0e00 << 16) | (0xc204 >> 2),
570 0x00000000,
571 (0x0e00 << 16) | (0xc2b4 >> 2),
572 0x00000000,
573 (0x0e00 << 16) | (0xc2b8 >> 2),
574 0x00000000,
575 (0x0e00 << 16) | (0xc2bc >> 2),
576 0x00000000,
577 (0x0e00 << 16) | (0xc2c0 >> 2),
578 0x00000000,
579 (0x0e00 << 16) | (0x8228 >> 2),
580 0x00000000,
581 (0x0e00 << 16) | (0x829c >> 2),
582 0x00000000,
583 (0x0e00 << 16) | (0x869c >> 2),
584 0x00000000,
585 (0x0600 << 16) | (0x98f4 >> 2),
586 0x00000000,
587 (0x0e00 << 16) | (0x98f8 >> 2),
588 0x00000000,
589 (0x0e00 << 16) | (0x9900 >> 2),
590 0x00000000,
591 (0x0e00 << 16) | (0xc260 >> 2),
592 0x00000000,
593 (0x0e00 << 16) | (0x90e8 >> 2),
594 0x00000000,
595 (0x0e00 << 16) | (0x3c000 >> 2),
596 0x00000000,
597 (0x0e00 << 16) | (0x3c00c >> 2),
598 0x00000000,
599 (0x0e00 << 16) | (0x8c1c >> 2),
600 0x00000000,
601 (0x0e00 << 16) | (0x9700 >> 2),
602 0x00000000,
603 (0x0e00 << 16) | (0xcd20 >> 2),
604 0x00000000,
605 (0x4e00 << 16) | (0xcd20 >> 2),
606 0x00000000,
607 (0x5e00 << 16) | (0xcd20 >> 2),
608 0x00000000,
609 (0x6e00 << 16) | (0xcd20 >> 2),
610 0x00000000,
611 (0x7e00 << 16) | (0xcd20 >> 2),
612 0x00000000,
613 (0x0e00 << 16) | (0x89bc >> 2),
614 0x00000000,
615 (0x0e00 << 16) | (0x8900 >> 2),
616 0x00000000,
617 0x3,
618 (0x0e00 << 16) | (0xc130 >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0xc134 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xc1fc >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xc208 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xc264 >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xc268 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xc26c >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xc270 >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xc274 >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0xc28c >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0xc290 >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0xc294 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0xc298 >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0xc2a0 >> 2),
645 0x00000000,
646 (0x0e00 << 16) | (0xc2a4 >> 2),
647 0x00000000,
648 (0x0e00 << 16) | (0xc2a8 >> 2),
649 0x00000000,
650 (0x0e00 << 16) | (0xc2ac >> 2),
651 0x00000000,
652 (0x0e00 << 16) | (0x301d0 >> 2),
653 0x00000000,
654 (0x0e00 << 16) | (0x30238 >> 2),
655 0x00000000,
656 (0x0e00 << 16) | (0x30250 >> 2),
657 0x00000000,
658 (0x0e00 << 16) | (0x30254 >> 2),
659 0x00000000,
660 (0x0e00 << 16) | (0x30258 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0x3025c >> 2),
663 0x00000000,
664 (0x4e00 << 16) | (0xc900 >> 2),
665 0x00000000,
666 (0x5e00 << 16) | (0xc900 >> 2),
667 0x00000000,
668 (0x6e00 << 16) | (0xc900 >> 2),
669 0x00000000,
670 (0x7e00 << 16) | (0xc900 >> 2),
671 0x00000000,
672 (0x4e00 << 16) | (0xc904 >> 2),
673 0x00000000,
674 (0x5e00 << 16) | (0xc904 >> 2),
675 0x00000000,
676 (0x6e00 << 16) | (0xc904 >> 2),
677 0x00000000,
678 (0x7e00 << 16) | (0xc904 >> 2),
679 0x00000000,
680 (0x4e00 << 16) | (0xc908 >> 2),
681 0x00000000,
682 (0x5e00 << 16) | (0xc908 >> 2),
683 0x00000000,
684 (0x6e00 << 16) | (0xc908 >> 2),
685 0x00000000,
686 (0x7e00 << 16) | (0xc908 >> 2),
687 0x00000000,
688 (0x4e00 << 16) | (0xc90c >> 2),
689 0x00000000,
690 (0x5e00 << 16) | (0xc90c >> 2),
691 0x00000000,
692 (0x6e00 << 16) | (0xc90c >> 2),
693 0x00000000,
694 (0x7e00 << 16) | (0xc90c >> 2),
695 0x00000000,
696 (0x4e00 << 16) | (0xc910 >> 2),
697 0x00000000,
698 (0x5e00 << 16) | (0xc910 >> 2),
699 0x00000000,
700 (0x6e00 << 16) | (0xc910 >> 2),
701 0x00000000,
702 (0x7e00 << 16) | (0xc910 >> 2),
703 0x00000000,
704 (0x0e00 << 16) | (0xc99c >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0x9834 >> 2),
707 0x00000000,
708 (0x0000 << 16) | (0x30f00 >> 2),
709 0x00000000,
710 (0x0000 << 16) | (0x30f04 >> 2),
711 0x00000000,
712 (0x0000 << 16) | (0x30f08 >> 2),
713 0x00000000,
714 (0x0000 << 16) | (0x30f0c >> 2),
715 0x00000000,
716 (0x0600 << 16) | (0x9b7c >> 2),
717 0x00000000,
718 (0x0e00 << 16) | (0x8a14 >> 2),
719 0x00000000,
720 (0x0e00 << 16) | (0x8a18 >> 2),
721 0x00000000,
722 (0x0600 << 16) | (0x30a00 >> 2),
723 0x00000000,
724 (0x0e00 << 16) | (0x8bf0 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0x8bcc >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0x8b24 >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0x30a04 >> 2),
731 0x00000000,
732 (0x0600 << 16) | (0x30a10 >> 2),
733 0x00000000,
734 (0x0600 << 16) | (0x30a14 >> 2),
735 0x00000000,
736 (0x0600 << 16) | (0x30a18 >> 2),
737 0x00000000,
738 (0x0600 << 16) | (0x30a2c >> 2),
739 0x00000000,
740 (0x0e00 << 16) | (0xc700 >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0xc704 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0xc708 >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0xc768 >> 2),
747 0x00000000,
748 (0x0400 << 16) | (0xc770 >> 2),
749 0x00000000,
750 (0x0400 << 16) | (0xc774 >> 2),
751 0x00000000,
752 (0x0400 << 16) | (0xc798 >> 2),
753 0x00000000,
754 (0x0400 << 16) | (0xc79c >> 2),
755 0x00000000,
756 (0x0e00 << 16) | (0x9100 >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x3c010 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x8c00 >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c04 >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x8c20 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0x8c38 >> 2),
767 0x00000000,
768 (0x0e00 << 16) | (0x8c3c >> 2),
769 0x00000000,
770 (0x0e00 << 16) | (0xae00 >> 2),
771 0x00000000,
772 (0x0e00 << 16) | (0x9604 >> 2),
773 0x00000000,
774 (0x0e00 << 16) | (0xac08 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0xac0c >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0xac10 >> 2),
779 0x00000000,
780 (0x0e00 << 16) | (0xac14 >> 2),
781 0x00000000,
782 (0x0e00 << 16) | (0xac58 >> 2),
783 0x00000000,
784 (0x0e00 << 16) | (0xac68 >> 2),
785 0x00000000,
786 (0x0e00 << 16) | (0xac6c >> 2),
787 0x00000000,
788 (0x0e00 << 16) | (0xac70 >> 2),
789 0x00000000,
790 (0x0e00 << 16) | (0xac74 >> 2),
791 0x00000000,
792 (0x0e00 << 16) | (0xac78 >> 2),
793 0x00000000,
794 (0x0e00 << 16) | (0xac7c >> 2),
795 0x00000000,
796 (0x0e00 << 16) | (0xac80 >> 2),
797 0x00000000,
798 (0x0e00 << 16) | (0xac84 >> 2),
799 0x00000000,
800 (0x0e00 << 16) | (0xac88 >> 2),
801 0x00000000,
802 (0x0e00 << 16) | (0xac8c >> 2),
803 0x00000000,
804 (0x0e00 << 16) | (0x970c >> 2),
805 0x00000000,
806 (0x0e00 << 16) | (0x9714 >> 2),
807 0x00000000,
808 (0x0e00 << 16) | (0x9718 >> 2),
809 0x00000000,
810 (0x0e00 << 16) | (0x971c >> 2),
811 0x00000000,
812 (0x0e00 << 16) | (0x31068 >> 2),
813 0x00000000,
814 (0x4e00 << 16) | (0x31068 >> 2),
815 0x00000000,
816 (0x5e00 << 16) | (0x31068 >> 2),
817 0x00000000,
818 (0x6e00 << 16) | (0x31068 >> 2),
819 0x00000000,
820 (0x7e00 << 16) | (0x31068 >> 2),
821 0x00000000,
822 (0x0e00 << 16) | (0xcd10 >> 2),
823 0x00000000,
824 (0x0e00 << 16) | (0xcd14 >> 2),
825 0x00000000,
826 (0x0e00 << 16) | (0x88b0 >> 2),
827 0x00000000,
828 (0x0e00 << 16) | (0x88b4 >> 2),
829 0x00000000,
830 (0x0e00 << 16) | (0x88b8 >> 2),
831 0x00000000,
832 (0x0e00 << 16) | (0x88bc >> 2),
833 0x00000000,
834 (0x0400 << 16) | (0x89c0 >> 2),
835 0x00000000,
836 (0x0e00 << 16) | (0x88c4 >> 2),
837 0x00000000,
838 (0x0e00 << 16) | (0x88c8 >> 2),
839 0x00000000,
840 (0x0e00 << 16) | (0x88d0 >> 2),
841 0x00000000,
842 (0x0e00 << 16) | (0x88d4 >> 2),
843 0x00000000,
844 (0x0e00 << 16) | (0x88d8 >> 2),
845 0x00000000,
846 (0x0e00 << 16) | (0x8980 >> 2),
847 0x00000000,
848 (0x0e00 << 16) | (0x30938 >> 2),
849 0x00000000,
850 (0x0e00 << 16) | (0x3093c >> 2),
851 0x00000000,
852 (0x0e00 << 16) | (0x30940 >> 2),
853 0x00000000,
854 (0x0e00 << 16) | (0x89a0 >> 2),
855 0x00000000,
856 (0x0e00 << 16) | (0x30900 >> 2),
857 0x00000000,
858 (0x0e00 << 16) | (0x30904 >> 2),
859 0x00000000,
860 (0x0e00 << 16) | (0x89b4 >> 2),
861 0x00000000,
862 (0x0e00 << 16) | (0x3e1fc >> 2),
863 0x00000000,
864 (0x0e00 << 16) | (0x3c210 >> 2),
865 0x00000000,
866 (0x0e00 << 16) | (0x3c214 >> 2),
867 0x00000000,
868 (0x0e00 << 16) | (0x3c218 >> 2),
869 0x00000000,
870 (0x0e00 << 16) | (0x8904 >> 2),
871 0x00000000,
872 0x5,
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
878};
879
880static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
7dae69a2 884static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
a2e73f56
AD		 885
886/*
887 * Core functions
888 */
889/**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899{
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992}
993
e517cd77
ML		 994static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
995{
996 release_firmware(adev->gfx.pfp_fw);
997 adev->gfx.pfp_fw = NULL;
998 release_firmware(adev->gfx.me_fw);
999 adev->gfx.me_fw = NULL;
1000 release_firmware(adev->gfx.ce_fw);
1001 adev->gfx.ce_fw = NULL;
1002 release_firmware(adev->gfx.mec_fw);
1003 adev->gfx.mec_fw = NULL;
1004 release_firmware(adev->gfx.mec2_fw);
1005 adev->gfx.mec2_fw = NULL;
1006 release_firmware(adev->gfx.rlc_fw);
1007 adev->gfx.rlc_fw = NULL;
1008}
1009
a2e73f56
AD		 1010/**
1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1012 *
1013 * @adev: amdgpu_device pointer
1014 *
1015 * Starting with SI, the tiling setup is done globally in a
1016 * set of 32 tiling modes. Rather than selecting each set of
1017 * parameters per surface as on older asics, we just select
1018 * which index in the tiling table we want to use, and the
1019 * surface uses those parameters (CIK).
1020 */
1021static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1022{
840a20d3
TSD		 1023 const u32 num_tile_mode_states =
1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1025 const u32 num_secondary_tile_mode_states =
1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1027 u32 reg_offset, split_equal_to_row_size;
1028 uint32_t *tile, *macrotile;
1029
1030 tile = adev->gfx.config.tile_mode_array;
1031 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1032
1033 switch (adev->gfx.config.mem_row_size_in_kb) {
1034 case 1:
1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1036 break;
1037 case 2:
1038 default:
1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1040 break;
1041 case 4:
1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1043 break;
1044 }
1045
840a20d3
TSD		 1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1047 tile[reg_offset] = 0;
1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1049 macrotile[reg_offset] = 0;
1050
a2e73f56
AD		 1051 switch (adev->asic_type) {
1052 case CHIP_BONAIRE:
840a20d3
TSD		 1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1072 TILE_SPLIT(split_equal_to_row_size));
1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1079 TILE_SPLIT(split_equal_to_row_size));
1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1155
1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163 NUM_BANKS(ADDR_SURF_16_BANK));
1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167 NUM_BANKS(ADDR_SURF_16_BANK));
1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_4_BANK));
1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191 NUM_BANKS(ADDR_SURF_16_BANK));
1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1195 NUM_BANKS(ADDR_SURF_16_BANK));
1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1203 NUM_BANKS(ADDR_SURF_16_BANK));
1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1207 NUM_BANKS(ADDR_SURF_8_BANK));
1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1212
840a20d3
TSD		 1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1216 if (reg_offset != 7)
1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1218 break;
1219 case CHIP_HAWAII:
840a20d3
TSD		 1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1239 TILE_SPLIT(split_equal_to_row_size));
1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1243 TILE_SPLIT(split_equal_to_row_size));
1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1247 TILE_SPLIT(split_equal_to_row_size));
1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1251 TILE_SPLIT(split_equal_to_row_size));
1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1338
840a20d3
TSD		 1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342 NUM_BANKS(ADDR_SURF_16_BANK));
1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346 NUM_BANKS(ADDR_SURF_16_BANK));
1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_16_BANK));
1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1358 NUM_BANKS(ADDR_SURF_8_BANK));
1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_4_BANK));
1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_4_BANK));
1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_16_BANK));
1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_16_BANK));
1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1382 NUM_BANKS(ADDR_SURF_8_BANK));
1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1386 NUM_BANKS(ADDR_SURF_16_BANK));
1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1390 NUM_BANKS(ADDR_SURF_8_BANK));
1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1394 NUM_BANKS(ADDR_SURF_4_BANK));
1395
1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1399 if (reg_offset != 7)
1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1401 break;
1402 case CHIP_KABINI:
1403 case CHIP_KAVERI:
1404 case CHIP_MULLINS:
1405 default:
840a20d3
TSD		 1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415 PIPE_CONFIG(ADDR_SURF_P2) |
1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P2) |
1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 PIPE_CONFIG(ADDR_SURF_P2) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1425 TILE_SPLIT(split_equal_to_row_size));
1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1427 PIPE_CONFIG(ADDR_SURF_P2) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430 PIPE_CONFIG(ADDR_SURF_P2) |
1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1432 TILE_SPLIT(split_equal_to_row_size));
1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1435 PIPE_CONFIG(ADDR_SURF_P2));
1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452 PIPE_CONFIG(ADDR_SURF_P2) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1465 PIPE_CONFIG(ADDR_SURF_P2) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472 PIPE_CONFIG(ADDR_SURF_P2) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1476 PIPE_CONFIG(ADDR_SURF_P2) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1480 PIPE_CONFIG(ADDR_SURF_P2) |
1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1485 PIPE_CONFIG(ADDR_SURF_P2) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1489 PIPE_CONFIG(ADDR_SURF_P2) |
1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1493 PIPE_CONFIG(ADDR_SURF_P2) |
1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P2) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500 PIPE_CONFIG(ADDR_SURF_P2) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1504 PIPE_CONFIG(ADDR_SURF_P2) |
1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1508
1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1524 NUM_BANKS(ADDR_SURF_8_BANK));
1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1528 NUM_BANKS(ADDR_SURF_8_BANK));
1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532 NUM_BANKS(ADDR_SURF_8_BANK));
1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536 NUM_BANKS(ADDR_SURF_8_BANK));
1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548 NUM_BANKS(ADDR_SURF_16_BANK));
1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1552 NUM_BANKS(ADDR_SURF_16_BANK));
1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1556 NUM_BANKS(ADDR_SURF_16_BANK));
1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1560 NUM_BANKS(ADDR_SURF_16_BANK));
1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1564 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1565
840a20d3
TSD		 1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1569 if (reg_offset != 7)
1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1571 break;
1572 }
1573}
1574
1575/**
1576 * gfx_v7_0_select_se_sh - select which SE, SH to address
1577 *
1578 * @adev: amdgpu_device pointer
1579 * @se_num: shader engine to address
1580 * @sh_num: sh block to address
1581 *
1582 * Select which SE, SH combinations to address. Certain
1583 * registers are instanced per SE or SH. 0xffffffff means
1584 * broadcast to all SEs or SHs (CIK).
1585 */
05fb7291 1586static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
9559ef5b 1587 u32 se_num, u32 sh_num, u32 instance)
a2e73f56 1588{
9559ef5b
TSD		 1589 u32 data;
1590
1591 if (instance == 0xffffffff)
1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1593 else
1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
a2e73f56
AD		 1595
1596 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1597 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1598 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1599 else if (se_num == 0xffffffff)
1600 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1601 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1602 else if (sh_num == 0xffffffff)
1603 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1604 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1605 else
1606 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1607 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1608 WREG32(mmGRBM_GFX_INDEX, data);
1609}
1610
1611/**
1612 * gfx_v7_0_create_bitmask - create a bitmask
1613 *
1614 * @bit_width: length of the mask
1615 *
1616 * create a variable length bit mask (CIK).
1617 * Returns the bitmask.
1618 */
1619static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1620{
8f8e00c1 1621 return (u32)((1ULL << bit_width) - 1);
a2e73f56
AD		 1622}
1623
1624/**
8f8e00c1 1625 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1626 *
1627 * @adev: amdgpu_device pointer
a2e73f56 1628 *
8f8e00c1
AD		 1629 * Calculates the bitmask of enabled RBs (CIK).
1630 * Returns the enabled RB bitmask.
a2e73f56 1631 */
8f8e00c1 1632static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1633{
1634 u32 data, mask;
1635
1636 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1637 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1638
8f8e00c1 1639 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1640 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1641
8f8e00c1
AD		 1642 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1643 adev->gfx.config.max_sh_per_se);
a2e73f56 1644
8f8e00c1 1645 return (~data) & mask;
a2e73f56
AD		 1646}
1647
0b2138a4
HR		 1648static void
1649gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1650{
1651 switch (adev->asic_type) {
1652 case CHIP_BONAIRE:
1653 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1654 SE_XSEL(1) | SE_YSEL(1);
1655 *rconf1 |= 0x0;
1656 break;
1657 case CHIP_HAWAII:
1658 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1659 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1660 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1661 SE_YSEL(3);
1662 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1663 SE_PAIR_YSEL(2);
1664 break;
1665 case CHIP_KAVERI:
1666 *rconf |= RB_MAP_PKR0(2);
1667 *rconf1 |= 0x0;
1668 break;
1669 case CHIP_KABINI:
1670 case CHIP_MULLINS:
1671 *rconf |= 0x0;
1672 *rconf1 |= 0x0;
1673 break;
1674 default:
1675 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1676 break;
1677 }
1678}
1679
1680static void
1681gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1682 u32 raster_config, u32 raster_config_1,
1683 unsigned rb_mask, unsigned num_rb)
1684{
1685 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1686 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1687 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1688 unsigned rb_per_se = num_rb / num_se;
1689 unsigned se_mask[4];
1690 unsigned se;
1691
1692 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1693 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1694 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1695 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1696
1697 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1698 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1699 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1700
1701 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1702 (!se_mask[2] && !se_mask[3]))) {
1703 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1704
1705 if (!se_mask[0] && !se_mask[1]) {
1706 raster_config_1 |=
1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1708 } else {
1709 raster_config_1 |=
1710 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1711 }
1712 }
1713
1714 for (se = 0; se < num_se; se++) {
1715 unsigned raster_config_se = raster_config;
1716 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1717 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1718 int idx = (se / 2) * 2;
1719
1720 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1721 raster_config_se &= ~SE_MAP_MASK;
1722
1723 if (!se_mask[idx]) {
1724 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1725 } else {
1726 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1727 }
1728 }
1729
1730 pkr0_mask &= rb_mask;
1731 pkr1_mask &= rb_mask;
1732 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1733 raster_config_se &= ~PKR_MAP_MASK;
1734
1735 if (!pkr0_mask) {
1736 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1737 } else {
1738 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1739 }
1740 }
1741
1742 if (rb_per_se >= 2) {
1743 unsigned rb0_mask = 1 << (se * rb_per_se);
1744 unsigned rb1_mask = rb0_mask << 1;
1745
1746 rb0_mask &= rb_mask;
1747 rb1_mask &= rb_mask;
1748 if (!rb0_mask || !rb1_mask) {
1749 raster_config_se &= ~RB_MAP_PKR0_MASK;
1750
1751 if (!rb0_mask) {
1752 raster_config_se |=
1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1754 } else {
1755 raster_config_se |=
1756 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1757 }
1758 }
1759
1760 if (rb_per_se > 2) {
1761 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1762 rb1_mask = rb0_mask << 1;
1763 rb0_mask &= rb_mask;
1764 rb1_mask &= rb_mask;
1765 if (!rb0_mask || !rb1_mask) {
1766 raster_config_se &= ~RB_MAP_PKR1_MASK;
1767
1768 if (!rb0_mask) {
1769 raster_config_se |=
1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1771 } else {
1772 raster_config_se |=
1773 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1774 }
1775 }
1776 }
1777 }
1778
1779 /* GRBM_GFX_INDEX has a different offset on CI+ */
1780 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1781 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1782 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1783 }
1784
1785 /* GRBM_GFX_INDEX has a different offset on CI+ */
1786 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1787}
1788
a2e73f56
AD		 1789/**
1790 * gfx_v7_0_setup_rb - setup the RBs on the asic
1791 *
1792 * @adev: amdgpu_device pointer
1793 * @se_num: number of SEs (shader engines) for the asic
1794 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1795 *
1796 * Configures per-SE/SH RB registers (CIK).
1797 */
8f8e00c1 1798static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1799{
1800 int i, j;
aac1e3ca 1801 u32 data;
0b2138a4 1802 u32 raster_config = 0, raster_config_1 = 0;
8f8e00c1 1803 u32 active_rbs = 0;
6157bd7a
FC		 1804 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1805 adev->gfx.config.max_sh_per_se;
0b2138a4 1806 unsigned num_rb_pipes;
a2e73f56
AD		 1807
1808 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1809 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1810 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 1811 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
8f8e00c1 1812 data = gfx_v7_0_get_rb_active_bitmap(adev);
6157bd7a
FC		 1813 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1814 rb_bitmap_width_per_sh);
a2e73f56
AD		 1815 }
1816 }
9559ef5b 1817 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56 1818
8f8e00c1 1819 adev->gfx.config.backend_enable_mask = active_rbs;
aac1e3ca 1820 adev->gfx.config.num_rbs = hweight32(active_rbs);
0b2138a4
HR		 1821
1822 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1823 adev->gfx.config.max_shader_engines, 16);
1824
1825 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1826
1827 if (!adev->gfx.config.backend_enable_mask ||
1828 adev->gfx.config.num_rbs >= num_rb_pipes) {
1829 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1830 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1831 } else {
1832 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1833 adev->gfx.config.backend_enable_mask,
1834 num_rb_pipes);
1835 }
1836 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 1837}
1838
cd06bf68
BG		 1839/**
1840 * gmc_v7_0_init_compute_vmid - gart enable
1841 *
1842 * @rdev: amdgpu_device pointer
1843 *
1844 * Initialize compute vmid sh_mem registers
1845 *
1846 */
1847#define DEFAULT_SH_MEM_BASES (0x6000)
1848#define FIRST_COMPUTE_VMID (8)
1849#define LAST_COMPUTE_VMID (16)
1850static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1851{
1852 int i;
1853 uint32_t sh_mem_config;
1854 uint32_t sh_mem_bases;
1855
1856 /*
1857 * Configure apertures:
1858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1861 */
1862 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1863 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1864 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1865 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1866 mutex_lock(&adev->srbm_mutex);
1867 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1868 cik_srbm_select(adev, 0, 0, 0, i);
1869 /* CP and shaders */
1870 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1871 WREG32(mmSH_MEM_APE1_BASE, 1);
1872 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1873 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1874 }
1875 cik_srbm_select(adev, 0, 0, 0, 0);
1876 mutex_unlock(&adev->srbm_mutex);
1877}
1878
a2e73f56
AD		 1879/**
1880 * gfx_v7_0_gpu_init - setup the 3D engine
1881 *
1882 * @adev: amdgpu_device pointer
1883 *
1884 * Configures the 3D engine and tiling configuration
1885 * registers so that the 3D engine is usable.
1886 */
1887static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1888{
d93f3ca7 1889 u32 tmp, sh_mem_cfg;
a2e73f56
AD		 1890 int i;
1891
a2e73f56
AD		 1892 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1893
d93f3ca7
AD		 1894 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1895 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1896 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1897
1898 gfx_v7_0_tiling_mode_table_init(adev);
1899
8f8e00c1 1900 gfx_v7_0_setup_rb(adev);
7dae69a2 1901 gfx_v7_0_get_cu_info(adev);
a2e73f56
AD		 1902
1903 /* set HW defaults for 3D engine */
1904 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1905 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1906 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1907
1908 mutex_lock(&adev->grbm_idx_mutex);
1909 /*
1910 * making sure that the following register writes will be broadcasted
1911 * to all the shaders
1912 */
9559ef5b 1913 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 1914
1915 /* XXX SH_MEM regs */
1916 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1917 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165
JX		 1918 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1919
a2e73f56
AD		 1920 mutex_lock(&adev->srbm_mutex);
1921 for (i = 0; i < 16; i++) {
1922 cik_srbm_select(adev, 0, 0, 0, i);
1923 /* CP and shaders */
74a5d165 1924 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1925 WREG32(mmSH_MEM_APE1_BASE, 1);
1926 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1927 WREG32(mmSH_MEM_BASES, 0);
1928 }
1929 cik_srbm_select(adev, 0, 0, 0, 0);
1930 mutex_unlock(&adev->srbm_mutex);
1931
cd06bf68
BG		 1932 gmc_v7_0_init_compute_vmid(adev);
1933
a2e73f56
AD		 1934 WREG32(mmSX_DEBUG_1, 0x20);
1935
1936 WREG32(mmTA_CNTL_AUX, 0x00010000);
1937
1938 tmp = RREG32(mmSPI_CONFIG_CNTL);
1939 tmp |= 0x03000000;
1940 WREG32(mmSPI_CONFIG_CNTL, tmp);
1941
1942 WREG32(mmSQ_CONFIG, 1);
1943
1944 WREG32(mmDB_DEBUG, 0);
1945
1946 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1947 tmp |= 0x00000400;
1948 WREG32(mmDB_DEBUG2, tmp);
1949
1950 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1951 tmp |= 0x00020200;
1952 WREG32(mmDB_DEBUG3, tmp);
1953
1954 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1955 tmp |= 0x00018208;
1956 WREG32(mmCB_HW_CONTROL, tmp);
1957
1958 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1959
1960 WREG32(mmPA_SC_FIFO_SIZE,
1961 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1962 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1963 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1964 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1965
1966 WREG32(mmVGT_NUM_INSTANCES, 1);
1967
1968 WREG32(mmCP_PERFMON_CNTL, 0);
1969
1970 WREG32(mmSQ_CONFIG, 0);
1971
1972 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1973 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1974 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1975
1976 WREG32(mmVGT_CACHE_INVALIDATION,
1977 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1978 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1979
1980 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1981 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1982
1983 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1984 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1985 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1986 mutex_unlock(&adev->grbm_idx_mutex);
1987
1988 udelay(50);
1989}
1990
1991/*
1992 * GPU scratch registers helpers function.
1993 */
1994/**
1995 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1996 *
1997 * @adev: amdgpu_device pointer
1998 *
1999 * Set up the number and offset of the CP scratch registers.
2000 * NOTE: use of CP scratch registers is a legacy inferface and
2001 * is not used by default on newer asics (r6xx+). On newer asics,
2002 * memory buffers are used for fences rather than scratch regs.
2003 */
2004static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2005{
2006 int i;
2007
2008 adev->gfx.scratch.num_reg = 7;
2009 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2010 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
2011 adev->gfx.scratch.free[i] = true;
2012 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
2013 }
2014}
2015
2016/**
2017 * gfx_v7_0_ring_test_ring - basic gfx ring test
2018 *
2019 * @adev: amdgpu_device pointer
2020 * @ring: amdgpu_ring structure holding ring information
2021 *
2022 * Allocate a scratch register and write to it using the gfx ring (CIK).
2023 * Provides a basic gfx ring test to verify that the ring is working.
2024 * Used by gfx_v7_0_cp_gfx_resume();
2025 * Returns 0 on success, error on failure.
2026 */
2027static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2028{
2029 struct amdgpu_device *adev = ring->adev;
2030 uint32_t scratch;
2031 uint32_t tmp = 0;
2032 unsigned i;
2033 int r;
2034
2035 r = amdgpu_gfx_scratch_get(adev, &scratch);
2036 if (r) {
2037 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2038 return r;
2039 }
2040 WREG32(scratch, 0xCAFEDEAD);
a27de35c 2041 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 2042 if (r) {
2043 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2044 amdgpu_gfx_scratch_free(adev, scratch);
2045 return r;
2046 }
2047 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2048 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2049 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 2050 amdgpu_ring_commit(ring);
a2e73f56
AD		 2051
2052 for (i = 0; i < adev->usec_timeout; i++) {
2053 tmp = RREG32(scratch);
2054 if (tmp == 0xDEADBEEF)
2055 break;
2056 DRM_UDELAY(1);
2057 }
2058 if (i < adev->usec_timeout) {
2059 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2060 } else {
2061 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2062 ring->idx, scratch, tmp);
2063 r = -EINVAL;
2064 }
2065 amdgpu_gfx_scratch_free(adev, scratch);
2066 return r;
2067}
2068
2069/**
d2edb07b 2070 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 2071 *
2072 * @adev: amdgpu_device pointer
2073 * @ridx: amdgpu ring index
2074 *
2075 * Emits an hdp flush on the cp.
2076 */
d2edb07b 2077static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 2078{
2079 u32 ref_and_mask;
d9b5327a 2080 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56
AD		 2081
2082 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
2083 switch (ring->me) {
2084 case 1:
2085 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2086 break;
2087 case 2:
2088 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2089 break;
2090 default:
2091 return;
2092 }
2093 } else {
2094 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2095 }
2096
2097 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2098 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2099 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 2100 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 2101 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2102 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2103 amdgpu_ring_write(ring, ref_and_mask);
2104 amdgpu_ring_write(ring, ref_and_mask);
2105 amdgpu_ring_write(ring, 0x20); /* poll interval */
2106}
2107
0955860b
CZ		 2108/**
2109 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2110 *
2111 * @adev: amdgpu_device pointer
2112 * @ridx: amdgpu ring index
2113 *
2114 * Emits an hdp invalidate on the cp.
2115 */
2116static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2117{
2118 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2119 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2120 WRITE_DATA_DST_SEL(0) |
2121 WR_CONFIRM));
2122 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2123 amdgpu_ring_write(ring, 0);
2124 amdgpu_ring_write(ring, 1);
2125}
2126
a2e73f56
AD		 2127/**
2128 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2129 *
2130 * @adev: amdgpu_device pointer
2131 * @fence: amdgpu fence object
2132 *
2133 * Emits a fence sequnce number on the gfx ring and flushes
2134 * GPU caches.
2135 */
2136static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 2137 u64 seq, unsigned flags)
a2e73f56 2138{
890ee23f
CZ		 2139 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2140 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 2141 /* Workaround for cache flush problems. First send a dummy EOP
2142 * event down the pipe with seq one below.
2143 */
2144 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2145 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2146 EOP_TC_ACTION_EN |
2147 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2148 EVENT_INDEX(5)));
2149 amdgpu_ring_write(ring, addr & 0xfffffffc);
2150 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2151 DATA_SEL(1) | INT_SEL(0));
2152 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2153 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2154
2155 /* Then send the real EOP event down the pipe. */
2156 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2157 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2158 EOP_TC_ACTION_EN |
2159 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2160 EVENT_INDEX(5)));
2161 amdgpu_ring_write(ring, addr & 0xfffffffc);
2162 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 2163 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2164 amdgpu_ring_write(ring, lower_32_bits(seq));
2165 amdgpu_ring_write(ring, upper_32_bits(seq));
2166}
2167
2168/**
2169 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2170 *
2171 * @adev: amdgpu_device pointer
2172 * @fence: amdgpu fence object
2173 *
2174 * Emits a fence sequnce number on the compute ring and flushes
2175 * GPU caches.
2176 */
2177static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2178 u64 addr, u64 seq,
890ee23f 2179 unsigned flags)
a2e73f56 2180{
890ee23f
CZ		 2181 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2182 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2183
a2e73f56
AD		 2184 /* RELEASE_MEM - flush caches, send int */
2185 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2186 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2187 EOP_TC_ACTION_EN |
2188 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2189 EVENT_INDEX(5)));
890ee23f 2190 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 2191 amdgpu_ring_write(ring, addr & 0xfffffffc);
2192 amdgpu_ring_write(ring, upper_32_bits(addr));
2193 amdgpu_ring_write(ring, lower_32_bits(seq));
2194 amdgpu_ring_write(ring, upper_32_bits(seq));
2195}
2196
a2e73f56
AD		 2197/*
2198 * IB stuff
2199 */
2200/**
2201 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2202 *
2203 * @ring: amdgpu_ring structure holding ring information
2204 * @ib: amdgpu indirect buffer object
2205 *
2206 * Emits an DE (drawing engine) or CE (constant engine) IB
2207 * on the gfx ring. IBs are usually generated by userspace
2208 * acceleration drivers and submitted to the kernel for
2209 * sheduling on the ring. This function schedules the IB
2210 * on the gfx ring for execution by the GPU.
2211 */
93323131 2212static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
d88bf583
CK		 2213 struct amdgpu_ib *ib,
2214 unsigned vm_id, bool ctx_switch)
a2e73f56
AD		 2215{
2216 u32 header, control = 0;
a2e73f56 2217
a2e73f56 2218 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
f153d286 2219 if (ctx_switch) {
a2e73f56
AD		 2220 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2221 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2222 }
2223
de807f81 2224 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2225 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2226 else
2227 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2228
d88bf583 2229 control |= ib->length_dw | (vm_id << 24);
a2e73f56
AD		 2230
2231 amdgpu_ring_write(ring, header);
2232 amdgpu_ring_write(ring,
2233#ifdef __BIG_ENDIAN
2234 (2 << 0) |
2235#endif
2236 (ib->gpu_addr & 0xFFFFFFFC));
2237 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2238 amdgpu_ring_write(ring, control);
2239}
2240
93323131 2241static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
d88bf583
CK		 2242 struct amdgpu_ib *ib,
2243 unsigned vm_id, bool ctx_switch)
93323131 2244{
33b7ed01 2245 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
93323131 2246
33b7ed01 2247 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
93323131 2248 amdgpu_ring_write(ring,
2249#ifdef __BIG_ENDIAN
2250 (2 << 0) |
2251#endif
2252 (ib->gpu_addr & 0xFFFFFFFC));
2253 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2254 amdgpu_ring_write(ring, control);
2255}
2256
753ad49c
ML		 2257static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2258{
2259 uint32_t dw2 = 0;
2260
2261 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2262 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2263 /* set load_global_config & load_global_uconfig */
2264 dw2 |= 0x8001;
2265 /* set load_cs_sh_regs */
2266 dw2 |= 0x01000000;
2267 /* set load_per_context_state & load_gfx_sh_regs */
2268 dw2 |= 0x10002;
2269 }
2270
2271 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2272 amdgpu_ring_write(ring, dw2);
2273 amdgpu_ring_write(ring, 0);
2274}
2275
a2e73f56
AD		 2276/**
2277 * gfx_v7_0_ring_test_ib - basic ring IB test
2278 *
2279 * @ring: amdgpu_ring structure holding ring information
2280 *
2281 * Allocate an IB and execute it on the gfx ring (CIK).
2282 * Provides a basic gfx ring test to verify that IBs are working.
2283 * Returns 0 on success, error on failure.
2284 */
bbec97aa 2285static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
a2e73f56
AD		 2286{
2287 struct amdgpu_device *adev = ring->adev;
2288 struct amdgpu_ib ib;
1763552e 2289 struct fence *f = NULL;
a2e73f56
AD		 2290 uint32_t scratch;
2291 uint32_t tmp = 0;
bbec97aa 2292 long r;
a2e73f56
AD		 2293
2294 r = amdgpu_gfx_scratch_get(adev, &scratch);
2295 if (r) {
bbec97aa 2296 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
a2e73f56
AD		 2297 return r;
2298 }
2299 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2300 memset(&ib, 0, sizeof(ib));
b07c60c0 2301 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56 2302 if (r) {
bbec97aa 2303 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
42d13693 2304 goto err1;
a2e73f56
AD		 2305 }
2306 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2307 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2308 ib.ptr[2] = 0xDEADBEEF;
2309 ib.length_dw = 3;
42d13693 2310
c5637837 2311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
42d13693
CZ		 2312 if (r)
2313 goto err2;
2314
bbec97aa
CK		 2315 r = fence_wait_timeout(f, false, timeout);
2316 if (r == 0) {
2317 DRM_ERROR("amdgpu: IB test timed out\n");
2318 r = -ETIMEDOUT;
2319 goto err2;
2320 } else if (r < 0) {
2321 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
42d13693 2322 goto err2;
a2e73f56 2323 }
6d44565d
CK		 2324 tmp = RREG32(scratch);
2325 if (tmp == 0xDEADBEEF) {
2326 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
bbec97aa 2327 r = 0;
a2e73f56
AD		 2328 } else {
2329 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2330 scratch, tmp);
2331 r = -EINVAL;
2332 }
42d13693
CZ		 2333
2334err2:
cc55c45d 2335 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 2336 fence_put(f);
42d13693
CZ		 2337err1:
2338 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2339 return r;
2340}
2341
2342/*
2343 * CP.
2344 * On CIK, gfx and compute now have independant command processors.
2345 *
2346 * GFX
2347 * Gfx consists of a single ring and can process both gfx jobs and
2348 * compute jobs. The gfx CP consists of three microengines (ME):
2349 * PFP - Pre-Fetch Parser
2350 * ME - Micro Engine
2351 * CE - Constant Engine
2352 * The PFP and ME make up what is considered the Drawing Engine (DE).
2353 * The CE is an asynchronous engine used for updating buffer desciptors
2354 * used by the DE so that they can be loaded into cache in parallel
2355 * while the DE is processing state update packets.
2356 *
2357 * Compute
2358 * The compute CP consists of two microengines (ME):
2359 * MEC1 - Compute MicroEngine 1
2360 * MEC2 - Compute MicroEngine 2
2361 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2362 * The queues are exposed to userspace and are programmed directly
2363 * by the compute runtime.
2364 */
2365/**
2366 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2367 *
2368 * @adev: amdgpu_device pointer
2369 * @enable: enable or disable the MEs
2370 *
2371 * Halts or unhalts the gfx MEs.
2372 */
2373static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2374{
2375 int i;
2376
2377 if (enable) {
2378 WREG32(mmCP_ME_CNTL, 0);
2379 } else {
2380 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2381 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2382 adev->gfx.gfx_ring[i].ready = false;
2383 }
2384 udelay(50);
2385}
2386
2387/**
2388 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2389 *
2390 * @adev: amdgpu_device pointer
2391 *
2392 * Loads the gfx PFP, ME, and CE ucode.
2393 * Returns 0 for success, -EINVAL if the ucode is not available.
2394 */
2395static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2396{
2397 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2398 const struct gfx_firmware_header_v1_0 *ce_hdr;
2399 const struct gfx_firmware_header_v1_0 *me_hdr;
2400 const __le32 *fw_data;
2401 unsigned i, fw_size;
2402
2403 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2404 return -EINVAL;
2405
2406 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2407 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2408 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2409
2410 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2411 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2412 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2413 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2414 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2415 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2416 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2417 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2418 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2419
2420 gfx_v7_0_cp_gfx_enable(adev, false);
2421
2422 /* PFP */
2423 fw_data = (const __le32 *)
2424 (adev->gfx.pfp_fw->data +
2425 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2426 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2427 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2428 for (i = 0; i < fw_size; i++)
2429 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2430 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2431
2432 /* CE */
2433 fw_data = (const __le32 *)
2434 (adev->gfx.ce_fw->data +
2435 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2436 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2437 WREG32(mmCP_CE_UCODE_ADDR, 0);
2438 for (i = 0; i < fw_size; i++)
2439 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2440 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2441
2442 /* ME */
2443 fw_data = (const __le32 *)
2444 (adev->gfx.me_fw->data +
2445 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2446 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2447 WREG32(mmCP_ME_RAM_WADDR, 0);
2448 for (i = 0; i < fw_size; i++)
2449 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2450 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2451
2452 return 0;
2453}
2454
2455/**
2456 * gfx_v7_0_cp_gfx_start - start the gfx ring
2457 *
2458 * @adev: amdgpu_device pointer
2459 *
2460 * Enables the ring and loads the clear state context and other
2461 * packets required to init the ring.
2462 * Returns 0 for success, error for failure.
2463 */
2464static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2465{
2466 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2467 const struct cs_section_def *sect = NULL;
2468 const struct cs_extent_def *ext = NULL;
2469 int r, i;
2470
2471 /* init the CP */
2472 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2473 WREG32(mmCP_ENDIAN_SWAP, 0);
2474 WREG32(mmCP_DEVICE_ID, 1);
2475
2476 gfx_v7_0_cp_gfx_enable(adev, true);
2477
a27de35c 2478 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2479 if (r) {
2480 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2481 return r;
2482 }
2483
2484 /* init the CE partitions. CE only used for gfx on CIK */
2485 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2486 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2487 amdgpu_ring_write(ring, 0x8000);
2488 amdgpu_ring_write(ring, 0x8000);
2489
2490 /* clear state buffer */
2491 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2492 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2493
2494 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2495 amdgpu_ring_write(ring, 0x80000000);
2496 amdgpu_ring_write(ring, 0x80000000);
2497
2498 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2499 for (ext = sect->section; ext->extent != NULL; ++ext) {
2500 if (sect->id == SECT_CONTEXT) {
2501 amdgpu_ring_write(ring,
2502 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2503 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2504 for (i = 0; i < ext->reg_count; i++)
2505 amdgpu_ring_write(ring, ext->extent[i]);
2506 }
2507 }
2508 }
2509
2510 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2511 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2512 switch (adev->asic_type) {
2513 case CHIP_BONAIRE:
2514 amdgpu_ring_write(ring, 0x16000012);
2515 amdgpu_ring_write(ring, 0x00000000);
2516 break;
2517 case CHIP_KAVERI:
2518 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2519 amdgpu_ring_write(ring, 0x00000000);
2520 break;
2521 case CHIP_KABINI:
2522 case CHIP_MULLINS:
2523 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2524 amdgpu_ring_write(ring, 0x00000000);
2525 break;
2526 case CHIP_HAWAII:
2527 amdgpu_ring_write(ring, 0x3a00161a);
2528 amdgpu_ring_write(ring, 0x0000002e);
2529 break;
2530 default:
2531 amdgpu_ring_write(ring, 0x00000000);
2532 amdgpu_ring_write(ring, 0x00000000);
2533 break;
2534 }
2535
2536 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2537 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2538
2539 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2540 amdgpu_ring_write(ring, 0);
2541
2542 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2543 amdgpu_ring_write(ring, 0x00000316);
2544 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2545 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2546
a27de35c 2547 amdgpu_ring_commit(ring);
a2e73f56
AD		 2548
2549 return 0;
2550}
2551
2552/**
2553 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2554 *
2555 * @adev: amdgpu_device pointer
2556 *
2557 * Program the location and size of the gfx ring buffer
2558 * and test it to make sure it's working.
2559 * Returns 0 for success, error for failure.
2560 */
2561static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2562{
2563 struct amdgpu_ring *ring;
2564 u32 tmp;
2565 u32 rb_bufsz;
2566 u64 rb_addr, rptr_addr;
2567 int r;
2568
2569 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2570 if (adev->asic_type != CHIP_HAWAII)
2571 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2572
2573 /* Set the write pointer delay */
2574 WREG32(mmCP_RB_WPTR_DELAY, 0);
2575
2576 /* set the RB to use vmid 0 */
2577 WREG32(mmCP_RB_VMID, 0);
2578
2579 WREG32(mmSCRATCH_ADDR, 0);
2580
2581 /* ring 0 - compute and gfx */
2582 /* Set ring buffer size */
2583 ring = &adev->gfx.gfx_ring[0];
2584 rb_bufsz = order_base_2(ring->ring_size / 8);
2585 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2586#ifdef __BIG_ENDIAN
454fc95e 2587 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2588#endif
2589 WREG32(mmCP_RB0_CNTL, tmp);
2590
2591 /* Initialize the ring buffer's read and write pointers */
2592 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2593 ring->wptr = 0;
2594 WREG32(mmCP_RB0_WPTR, ring->wptr);
2595
2596 /* set the wb address wether it's enabled or not */
2597 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2598 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2599 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2600
2601 /* scratch register shadowing is no longer supported */
2602 WREG32(mmSCRATCH_UMSK, 0);
2603
2604 mdelay(1);
2605 WREG32(mmCP_RB0_CNTL, tmp);
2606
2607 rb_addr = ring->gpu_addr >> 8;
2608 WREG32(mmCP_RB0_BASE, rb_addr);
2609 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2610
2611 /* start the ring */
2612 gfx_v7_0_cp_gfx_start(adev);
2613 ring->ready = true;
2614 r = amdgpu_ring_test_ring(ring);
2615 if (r) {
2616 ring->ready = false;
2617 return r;
2618 }
2619
2620 return 0;
2621}
2622
f1c0efc5 2623static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
a2e73f56 2624{
7edd6b2f 2625 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2626}
2627
2628static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2629{
2630 struct amdgpu_device *adev = ring->adev;
a2e73f56 2631
7edd6b2f 2632 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2633}
2634
2635static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2636{
2637 struct amdgpu_device *adev = ring->adev;
2638
2639 WREG32(mmCP_RB0_WPTR, ring->wptr);
2640 (void)RREG32(mmCP_RB0_WPTR);
2641}
2642
a2e73f56
AD		 2643static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2644{
a2e73f56 2645 /* XXX check if swapping is necessary on BE */
7edd6b2f 2646 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2647}
2648
2649static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2650{
2651 struct amdgpu_device *adev = ring->adev;
2652
2653 /* XXX check if swapping is necessary on BE */
2654 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2655 WDOORBELL32(ring->doorbell_index, ring->wptr);
2656}
2657
2658/**
2659 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2660 *
2661 * @adev: amdgpu_device pointer
2662 * @enable: enable or disable the MEs
2663 *
2664 * Halts or unhalts the compute MEs.
2665 */
2666static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2667{
2668 int i;
2669
2670 if (enable) {
2671 WREG32(mmCP_MEC_CNTL, 0);
2672 } else {
2673 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2674 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2675 adev->gfx.compute_ring[i].ready = false;
2676 }
2677 udelay(50);
2678}
2679
2680/**
2681 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2682 *
2683 * @adev: amdgpu_device pointer
2684 *
2685 * Loads the compute MEC1&2 ucode.
2686 * Returns 0 for success, -EINVAL if the ucode is not available.
2687 */
2688static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2689{
2690 const struct gfx_firmware_header_v1_0 *mec_hdr;
2691 const __le32 *fw_data;
2692 unsigned i, fw_size;
2693
2694 if (!adev->gfx.mec_fw)
2695 return -EINVAL;
2696
2697 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2698 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2699 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2700 adev->gfx.mec_feature_version = le32_to_cpu(
2701 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2702
2703 gfx_v7_0_cp_compute_enable(adev, false);
2704
2705 /* MEC1 */
2706 fw_data = (const __le32 *)
2707 (adev->gfx.mec_fw->data +
2708 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2709 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2710 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2711 for (i = 0; i < fw_size; i++)
2712 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2713 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2714
2715 if (adev->asic_type == CHIP_KAVERI) {
2716 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2717
2718 if (!adev->gfx.mec2_fw)
2719 return -EINVAL;
2720
2721 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2722 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2723 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2724 adev->gfx.mec2_feature_version = le32_to_cpu(
2725 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2726
2727 /* MEC2 */
2728 fw_data = (const __le32 *)
2729 (adev->gfx.mec2_fw->data +
2730 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2731 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2732 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2733 for (i = 0; i < fw_size; i++)
2734 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2735 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2736 }
2737
2738 return 0;
2739}
2740
a2e73f56
AD		 2741/**
2742 * gfx_v7_0_cp_compute_fini - stop the compute queues
2743 *
2744 * @adev: amdgpu_device pointer
2745 *
2746 * Stop the compute queues and tear down the driver queue
2747 * info.
2748 */
2749static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2750{
2751 int i, r;
2752
2753 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2754 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2755
2756 if (ring->mqd_obj) {
2757 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2758 if (unlikely(r != 0))
2759 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2760
2761 amdgpu_bo_unpin(ring->mqd_obj);
2762 amdgpu_bo_unreserve(ring->mqd_obj);
2763
2764 amdgpu_bo_unref(&ring->mqd_obj);
2765 ring->mqd_obj = NULL;
2766 }
2767 }
2768}
2769
2770static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2771{
2772 int r;
2773
2774 if (adev->gfx.mec.hpd_eop_obj) {
2775 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2776 if (unlikely(r != 0))
2777 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2778 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2779 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2780
2781 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2782 adev->gfx.mec.hpd_eop_obj = NULL;
2783 }
2784}
2785
2786#define MEC_HPD_SIZE 2048
2787
2788static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2789{
2790 int r;
2791 u32 *hpd;
2792
2793 /*
2794 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2795 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2796 * Nonetheless, we assign only 1 pipe because all other pipes will
2797 * be handled by KFD
2798 */
2799 adev->gfx.mec.num_mec = 1;
2800 adev->gfx.mec.num_pipe = 1;
2801 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2802
2803 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2804 r = amdgpu_bo_create(adev,
2805 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2806 PAGE_SIZE, true,
72d7668b 2807 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2808 &adev->gfx.mec.hpd_eop_obj);
2809 if (r) {
2810 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2811 return r;
2812 }
2813 }
2814
2815 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2816 if (unlikely(r != 0)) {
2817 gfx_v7_0_mec_fini(adev);
2818 return r;
2819 }
2820 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2821 &adev->gfx.mec.hpd_eop_gpu_addr);
2822 if (r) {
2823 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2824 gfx_v7_0_mec_fini(adev);
2825 return r;
2826 }
2827 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2828 if (r) {
2829 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2830 gfx_v7_0_mec_fini(adev);
2831 return r;
2832 }
2833
2834 /* clear memory. Not sure if this is required or not */
2835 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2836
2837 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2838 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2839
2840 return 0;
2841}
2842
2843struct hqd_registers
2844{
2845 u32 cp_mqd_base_addr;
2846 u32 cp_mqd_base_addr_hi;
2847 u32 cp_hqd_active;
2848 u32 cp_hqd_vmid;
2849 u32 cp_hqd_persistent_state;
2850 u32 cp_hqd_pipe_priority;
2851 u32 cp_hqd_queue_priority;
2852 u32 cp_hqd_quantum;
2853 u32 cp_hqd_pq_base;
2854 u32 cp_hqd_pq_base_hi;
2855 u32 cp_hqd_pq_rptr;
2856 u32 cp_hqd_pq_rptr_report_addr;
2857 u32 cp_hqd_pq_rptr_report_addr_hi;
2858 u32 cp_hqd_pq_wptr_poll_addr;
2859 u32 cp_hqd_pq_wptr_poll_addr_hi;
2860 u32 cp_hqd_pq_doorbell_control;
2861 u32 cp_hqd_pq_wptr;
2862 u32 cp_hqd_pq_control;
2863 u32 cp_hqd_ib_base_addr;
2864 u32 cp_hqd_ib_base_addr_hi;
2865 u32 cp_hqd_ib_rptr;
2866 u32 cp_hqd_ib_control;
2867 u32 cp_hqd_iq_timer;
2868 u32 cp_hqd_iq_rptr;
2869 u32 cp_hqd_dequeue_request;
2870 u32 cp_hqd_dma_offload;
2871 u32 cp_hqd_sema_cmd;
2872 u32 cp_hqd_msg_type;
2873 u32 cp_hqd_atomic0_preop_lo;
2874 u32 cp_hqd_atomic0_preop_hi;
2875 u32 cp_hqd_atomic1_preop_lo;
2876 u32 cp_hqd_atomic1_preop_hi;
2877 u32 cp_hqd_hq_scheduler0;
2878 u32 cp_hqd_hq_scheduler1;
2879 u32 cp_mqd_control;
2880};
2881
2882struct bonaire_mqd
2883{
2884 u32 header;
2885 u32 dispatch_initiator;
2886 u32 dimensions[3];
2887 u32 start_idx[3];
2888 u32 num_threads[3];
2889 u32 pipeline_stat_enable;
2890 u32 perf_counter_enable;
2891 u32 pgm[2];
2892 u32 tba[2];
2893 u32 tma[2];
2894 u32 pgm_rsrc[2];
2895 u32 vmid;
2896 u32 resource_limits;
2897 u32 static_thread_mgmt01[2];
2898 u32 tmp_ring_size;
2899 u32 static_thread_mgmt23[2];
2900 u32 restart[3];
2901 u32 thread_trace_enable;
2902 u32 reserved1;
2903 u32 user_data[16];
2904 u32 vgtcs_invoke_count[2];
2905 struct hqd_registers queue_state;
2906 u32 dequeue_cntr;
2907 u32 interrupt_queue[64];
2908};
2909
2910/**
2911 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2912 *
2913 * @adev: amdgpu_device pointer
2914 *
2915 * Program the compute queues and test them to make sure they
2916 * are working.
2917 * Returns 0 for success, error for failure.
2918 */
2919static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2920{
2921 int r, i, j;
2922 u32 tmp;
2923 bool use_doorbell = true;
2924 u64 hqd_gpu_addr;
2925 u64 mqd_gpu_addr;
2926 u64 eop_gpu_addr;
2927 u64 wb_gpu_addr;
2928 u32 *buf;
2929 struct bonaire_mqd *mqd;
53960b4f 2930 struct amdgpu_ring *ring;
a2e73f56
AD		 2931
2932 /* fix up chicken bits */
2933 tmp = RREG32(mmCP_CPF_DEBUG);
2934 tmp |= (1 << 23);
2935 WREG32(mmCP_CPF_DEBUG, tmp);
2936
2937 /* init the pipes */
2938 mutex_lock(&adev->srbm_mutex);
2939 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2940 int me = (i < 4) ? 1 : 2;
2941 int pipe = (i < 4) ? i : (i - 4);
2942
2943 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2944
2945 cik_srbm_select(adev, me, pipe, 0, 0);
2946
2947 /* write the EOP addr */
2948 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2949 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2950
2951 /* set the VMID assigned */
2952 WREG32(mmCP_HPD_EOP_VMID, 0);
2953
2954 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2955 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2956 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2957 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2958 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2959 }
2960 cik_srbm_select(adev, 0, 0, 0, 0);
2961 mutex_unlock(&adev->srbm_mutex);
2962
2963 /* init the queues. Just two for now. */
2964 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
53960b4f 2965 ring = &adev->gfx.compute_ring[i];
a2e73f56
AD		 2966
2967 if (ring->mqd_obj == NULL) {
2968 r = amdgpu_bo_create(adev,
2969 sizeof(struct bonaire_mqd),
2970 PAGE_SIZE, true,
72d7668b 2971 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2972 &ring->mqd_obj);
2973 if (r) {
2974 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2975 return r;
2976 }
2977 }
2978
2979 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2980 if (unlikely(r != 0)) {
2981 gfx_v7_0_cp_compute_fini(adev);
2982 return r;
2983 }
2984 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2985 &mqd_gpu_addr);
2986 if (r) {
2987 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2988 gfx_v7_0_cp_compute_fini(adev);
2989 return r;
2990 }
2991 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2992 if (r) {
2993 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2994 gfx_v7_0_cp_compute_fini(adev);
2995 return r;
2996 }
2997
2998 /* init the mqd struct */
2999 memset(buf, 0, sizeof(struct bonaire_mqd));
3000
3001 mqd = (struct bonaire_mqd *)buf;
3002 mqd->header = 0xC0310800;
3003 mqd->static_thread_mgmt01[0] = 0xffffffff;
3004 mqd->static_thread_mgmt01[1] = 0xffffffff;
3005 mqd->static_thread_mgmt23[0] = 0xffffffff;
3006 mqd->static_thread_mgmt23[1] = 0xffffffff;
3007
3008 mutex_lock(&adev->srbm_mutex);
3009 cik_srbm_select(adev, ring->me,
3010 ring->pipe,
3011 ring->queue, 0);
3012
3013 /* disable wptr polling */
3014 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3015 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3016 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3017
3018 /* enable doorbell? */
3019 mqd->queue_state.cp_hqd_pq_doorbell_control =
3020 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3021 if (use_doorbell)
3022 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3023 else
3024 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3025 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3026 mqd->queue_state.cp_hqd_pq_doorbell_control);
3027
3028 /* disable the queue if it's active */
3029 mqd->queue_state.cp_hqd_dequeue_request = 0;
3030 mqd->queue_state.cp_hqd_pq_rptr = 0;
3031 mqd->queue_state.cp_hqd_pq_wptr= 0;
3032 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3033 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3034 for (j = 0; j < adev->usec_timeout; j++) {
3035 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3036 break;
3037 udelay(1);
3038 }
3039 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3040 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3041 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3042 }
3043
3044 /* set the pointer to the MQD */
3045 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3046 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3047 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3048 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3049 /* set MQD vmid to 0 */
3050 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3051 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3052 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3053
3054 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3055 hqd_gpu_addr = ring->gpu_addr >> 8;
3056 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3057 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3058 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3059 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3060
3061 /* set up the HQD, this is similar to CP_RB0_CNTL */
3062 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3063 mqd->queue_state.cp_hqd_pq_control &=
3064 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3065 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3066
3067 mqd->queue_state.cp_hqd_pq_control |=
3068 order_base_2(ring->ring_size / 8);
3069 mqd->queue_state.cp_hqd_pq_control |=
3070 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3071#ifdef __BIG_ENDIAN
454fc95e
AD		 3072 mqd->queue_state.cp_hqd_pq_control |=
3073 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 3074#endif
3075 mqd->queue_state.cp_hqd_pq_control &=
3076 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3077 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3078 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3079 mqd->queue_state.cp_hqd_pq_control |=
3080 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3081 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3082 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3083
3084 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3085 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3086 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3087 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3088 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3089 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3090 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3091
3092 /* set the wb address wether it's enabled or not */
3093 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3094 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3095 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3096 upper_32_bits(wb_gpu_addr) & 0xffff;
3097 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3098 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3099 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3100 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3101
3102 /* enable the doorbell if requested */
3103 if (use_doorbell) {
3104 mqd->queue_state.cp_hqd_pq_doorbell_control =
3105 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3106 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3107 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3108 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3109 (ring->doorbell_index <<
3110 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3111 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3112 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3113 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3114 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3115 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3116
3117 } else {
3118 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3119 }
3120 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3121 mqd->queue_state.cp_hqd_pq_doorbell_control);
3122
3123 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3124 ring->wptr = 0;
3125 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3126 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3127 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3128
3129 /* set the vmid for the queue */
3130 mqd->queue_state.cp_hqd_vmid = 0;
3131 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3132
3133 /* activate the queue */
3134 mqd->queue_state.cp_hqd_active = 1;
3135 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3136
3137 cik_srbm_select(adev, 0, 0, 0, 0);
3138 mutex_unlock(&adev->srbm_mutex);
3139
3140 amdgpu_bo_kunmap(ring->mqd_obj);
3141 amdgpu_bo_unreserve(ring->mqd_obj);
3142
3143 ring->ready = true;
53960b4f 3144 }
3145
3146 gfx_v7_0_cp_compute_enable(adev, true);
3147
3148 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3149 ring = &adev->gfx.compute_ring[i];
3150
a2e73f56
AD		 3151 r = amdgpu_ring_test_ring(ring);
3152 if (r)
3153 ring->ready = false;
3154 }
3155
3156 return 0;
3157}
3158
3159static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3160{
3161 gfx_v7_0_cp_gfx_enable(adev, enable);
3162 gfx_v7_0_cp_compute_enable(adev, enable);
3163}
3164
3165static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3166{
3167 int r;
3168
3169 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3170 if (r)
3171 return r;
3172 r = gfx_v7_0_cp_compute_load_microcode(adev);
3173 if (r)
3174 return r;
3175
3176 return 0;
3177}
3178
3179static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3180 bool enable)
3181{
3182 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3183
3184 if (enable)
3185 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3186 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3187 else
3188 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3189 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3190 WREG32(mmCP_INT_CNTL_RING0, tmp);
3191}
3192
3193static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3194{
3195 int r;
3196
3197 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3198
3199 r = gfx_v7_0_cp_load_microcode(adev);
3200 if (r)
3201 return r;
3202
3203 r = gfx_v7_0_cp_gfx_resume(adev);
3204 if (r)
3205 return r;
3206 r = gfx_v7_0_cp_compute_resume(adev);
3207 if (r)
3208 return r;
3209
3210 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3211
3212 return 0;
3213}
3214
b8c7b39e
CK		 3215/**
3216 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3217 *
3218 * @ring: the ring to emmit the commands to
3219 *
3220 * Sync the command pipeline with the PFP. E.g. wait for everything
3221 * to be completed.
3222 */
3223static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3224{
3225 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
914f9e18
CZ		 3226 uint32_t seq = ring->fence_drv.sync_seq;
3227 uint64_t addr = ring->fence_drv.gpu_addr;
3228
3229 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3230 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3231 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3232 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3233 amdgpu_ring_write(ring, addr & 0xfffffffc);
3234 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3235 amdgpu_ring_write(ring, seq);
3236 amdgpu_ring_write(ring, 0xffffffff);
3237 amdgpu_ring_write(ring, 4); /* poll interval */
3238
b8c7b39e
CK		 3239 if (usepfp) {
3240 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3241 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3242 amdgpu_ring_write(ring, 0);
3243 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3244 amdgpu_ring_write(ring, 0);
3245 }
3246}
3247
a2e73f56
AD		 3248/*
3249 * vm
3250 * VMID 0 is the physical GPU addresses as used by the kernel.
3251 * VMIDs 1-15 are used for userspace clients and are handled
3252 * by the amdgpu vm/hsa code.
3253 */
3254/**
3255 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3256 *
3257 * @adev: amdgpu_device pointer
3258 *
3259 * Update the page table base and flush the VM TLB
3260 * using the CP (CIK).
3261 */
3262static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3263 unsigned vm_id, uint64_t pd_addr)
3264{
3265 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
feebe91a 3266
a2e73f56
AD		 3267 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3268 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3269 WRITE_DATA_DST_SEL(0)));
3270 if (vm_id < 8) {
3271 amdgpu_ring_write(ring,
3272 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3273 } else {
3274 amdgpu_ring_write(ring,
3275 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3276 }
3277 amdgpu_ring_write(ring, 0);
3278 amdgpu_ring_write(ring, pd_addr >> 12);
3279
a2e73f56
AD		 3280 /* bits 0-15 are the VM contexts0-15 */
3281 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3282 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3283 WRITE_DATA_DST_SEL(0)));
3284 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3285 amdgpu_ring_write(ring, 0);
3286 amdgpu_ring_write(ring, 1 << vm_id);
3287
3288 /* wait for the invalidate to complete */
3289 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3290 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3291 WAIT_REG_MEM_FUNCTION(0) | /* always */
3292 WAIT_REG_MEM_ENGINE(0))); /* me */
3293 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3294 amdgpu_ring_write(ring, 0);
3295 amdgpu_ring_write(ring, 0); /* ref */
3296 amdgpu_ring_write(ring, 0); /* mask */
3297 amdgpu_ring_write(ring, 0x20); /* poll interval */
3298
3299 /* compute doesn't have PFP */
3300 if (usepfp) {
3301 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3302 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3303 amdgpu_ring_write(ring, 0x0);
3304
3305 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3306 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3307 amdgpu_ring_write(ring, 0);
3308 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3309 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3310 }
3311}
3312
3313/*
3314 * RLC
3315 * The RLC is a multi-purpose microengine that handles a
3316 * variety of functions.
3317 */
3318static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3319{
3320 int r;
3321
3322 /* save restore block */
3323 if (adev->gfx.rlc.save_restore_obj) {
3324 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3325 if (unlikely(r != 0))
3326 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3327 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3328 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3329
3330 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3331 adev->gfx.rlc.save_restore_obj = NULL;
3332 }
3333
3334 /* clear state block */
3335 if (adev->gfx.rlc.clear_state_obj) {
3336 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3337 if (unlikely(r != 0))
3338 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3339 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3340 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3341
3342 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3343 adev->gfx.rlc.clear_state_obj = NULL;
3344 }
3345
3346 /* clear state block */
3347 if (adev->gfx.rlc.cp_table_obj) {
3348 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3349 if (unlikely(r != 0))
3350 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3351 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3352 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3353
3354 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3355 adev->gfx.rlc.cp_table_obj = NULL;
3356 }
3357}
3358
3359static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3360{
3361 const u32 *src_ptr;
3362 volatile u32 *dst_ptr;
3363 u32 dws, i;
3364 const struct cs_section_def *cs_data;
3365 int r;
3366
3367 /* allocate rlc buffers */
2f7d10b3 3368 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3369 if (adev->asic_type == CHIP_KAVERI) {
3370 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3371 adev->gfx.rlc.reg_list_size =
3372 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3373 } else {
3374 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3375 adev->gfx.rlc.reg_list_size =
3376 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3377 }
3378 }
3379 adev->gfx.rlc.cs_data = ci_cs_data;
b58bc559 3380 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
e36091ed 3381 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
a2e73f56
AD		 3382
3383 src_ptr = adev->gfx.rlc.reg_list;
3384 dws = adev->gfx.rlc.reg_list_size;
3385 dws += (5 * 16) + 48 + 48 + 64;
3386
3387 cs_data = adev->gfx.rlc.cs_data;
3388
3389 if (src_ptr) {
3390 /* save restore block */
3391 if (adev->gfx.rlc.save_restore_obj == NULL) {
3392 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3393 AMDGPU_GEM_DOMAIN_VRAM,
3394 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3395 NULL, NULL,
3396 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3397 if (r) {
3398 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3399 return r;
3400 }
3401 }
3402
3403 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3404 if (unlikely(r != 0)) {
3405 gfx_v7_0_rlc_fini(adev);
3406 return r;
3407 }
3408 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3409 &adev->gfx.rlc.save_restore_gpu_addr);
3410 if (r) {
3411 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3412 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3413 gfx_v7_0_rlc_fini(adev);
3414 return r;
3415 }
3416
3417 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3418 if (r) {
3419 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3420 gfx_v7_0_rlc_fini(adev);
3421 return r;
3422 }
3423 /* write the sr buffer */
3424 dst_ptr = adev->gfx.rlc.sr_ptr;
3425 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3426 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3427 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3428 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3429 }
3430
3431 if (cs_data) {
3432 /* clear state block */
3433 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3434
3435 if (adev->gfx.rlc.clear_state_obj == NULL) {
3436 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3437 AMDGPU_GEM_DOMAIN_VRAM,
3438 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3439 NULL, NULL,
3440 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3441 if (r) {
3442 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3443 gfx_v7_0_rlc_fini(adev);
3444 return r;
3445 }
3446 }
3447 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3448 if (unlikely(r != 0)) {
3449 gfx_v7_0_rlc_fini(adev);
3450 return r;
3451 }
3452 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3453 &adev->gfx.rlc.clear_state_gpu_addr);
3454 if (r) {
3455 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3456 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3457 gfx_v7_0_rlc_fini(adev);
3458 return r;
3459 }
3460
3461 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3462 if (r) {
3463 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3464 gfx_v7_0_rlc_fini(adev);
3465 return r;
3466 }
3467 /* set up the cs buffer */
3468 dst_ptr = adev->gfx.rlc.cs_ptr;
3469 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3470 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3471 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3472 }
3473
3474 if (adev->gfx.rlc.cp_table_size) {
3475 if (adev->gfx.rlc.cp_table_obj == NULL) {
3476 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d
AD		 3477 AMDGPU_GEM_DOMAIN_VRAM,
3478 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3479 NULL, NULL,
3480 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3481 if (r) {
3482 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3483 gfx_v7_0_rlc_fini(adev);
3484 return r;
3485 }
3486 }
3487
3488 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3489 if (unlikely(r != 0)) {
3490 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3491 gfx_v7_0_rlc_fini(adev);
3492 return r;
3493 }
3494 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3495 &adev->gfx.rlc.cp_table_gpu_addr);
3496 if (r) {
3497 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3498 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3499 gfx_v7_0_rlc_fini(adev);
3500 return r;
3501 }
3502 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3503 if (r) {
3504 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3505 gfx_v7_0_rlc_fini(adev);
3506 return r;
3507 }
3508
3509 gfx_v7_0_init_cp_pg_table(adev);
3510
3511 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3512 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3513
3514 }
3515
3516 return 0;
3517}
3518
3519static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3520{
3521 u32 tmp;
3522
3523 tmp = RREG32(mmRLC_LB_CNTL);
3524 if (enable)
3525 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3526 else
3527 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3528 WREG32(mmRLC_LB_CNTL, tmp);
3529}
3530
3531static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3532{
3533 u32 i, j, k;
3534 u32 mask;
3535
3536 mutex_lock(&adev->grbm_idx_mutex);
3537 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3538 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9559ef5b 3539 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
a2e73f56
AD		 3540 for (k = 0; k < adev->usec_timeout; k++) {
3541 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3542 break;
3543 udelay(1);
3544 }
3545 }
3546 }
9559ef5b 3547 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3548 mutex_unlock(&adev->grbm_idx_mutex);
3549
3550 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3551 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3552 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3553 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3554 for (k = 0; k < adev->usec_timeout; k++) {
3555 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3556 break;
3557 udelay(1);
3558 }
3559}
3560
3561static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3562{
3563 u32 tmp;
3564
3565 tmp = RREG32(mmRLC_CNTL);
3566 if (tmp != rlc)
3567 WREG32(mmRLC_CNTL, rlc);
3568}
3569
3570static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3571{
3572 u32 data, orig;
3573
3574 orig = data = RREG32(mmRLC_CNTL);
3575
3576 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3577 u32 i;
3578
3579 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3580 WREG32(mmRLC_CNTL, data);
3581
3582 for (i = 0; i < adev->usec_timeout; i++) {
3583 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3584 break;
3585 udelay(1);
3586 }
3587
3588 gfx_v7_0_wait_for_rlc_serdes(adev);
3589 }
3590
3591 return orig;
3592}
3593
06120a1e 3594static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3595{
3596 u32 tmp, i, mask;
3597
3598 tmp = 0x1 | (1 << 1);
3599 WREG32(mmRLC_GPR_REG2, tmp);
3600
3601 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3602 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3603 for (i = 0; i < adev->usec_timeout; i++) {
3604 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3605 break;
3606 udelay(1);
3607 }
3608
3609 for (i = 0; i < adev->usec_timeout; i++) {
3610 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3611 break;
3612 udelay(1);
3613 }
3614}
3615
06120a1e 3616static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
a2e73f56
AD		 3617{
3618 u32 tmp;
3619
3620 tmp = 0x1 | (0 << 1);
3621 WREG32(mmRLC_GPR_REG2, tmp);
3622}
3623
3624/**
3625 * gfx_v7_0_rlc_stop - stop the RLC ME
3626 *
3627 * @adev: amdgpu_device pointer
3628 *
3629 * Halt the RLC ME (MicroEngine) (CIK).
3630 */
4d54588e 3631static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
a2e73f56
AD		 3632{
3633 WREG32(mmRLC_CNTL, 0);
3634
3635 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3636
3637 gfx_v7_0_wait_for_rlc_serdes(adev);
3638}
3639
3640/**
3641 * gfx_v7_0_rlc_start - start the RLC ME
3642 *
3643 * @adev: amdgpu_device pointer
3644 *
3645 * Unhalt the RLC ME (MicroEngine) (CIK).
3646 */
3647static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3648{
3649 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3650
3651 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3652
3653 udelay(50);
3654}
3655
3656static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3657{
3658 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3659
3660 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3661 WREG32(mmGRBM_SOFT_RESET, tmp);
3662 udelay(50);
3663 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3664 WREG32(mmGRBM_SOFT_RESET, tmp);
3665 udelay(50);
3666}
3667
3668/**
3669 * gfx_v7_0_rlc_resume - setup the RLC hw
3670 *
3671 * @adev: amdgpu_device pointer
3672 *
3673 * Initialize the RLC registers, load the ucode,
3674 * and start the RLC (CIK).
3675 * Returns 0 for success, -EINVAL if the ucode is not available.
3676 */
3677static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3678{
3679 const struct rlc_firmware_header_v1_0 *hdr;
3680 const __le32 *fw_data;
3681 unsigned i, fw_size;
3682 u32 tmp;
3683
3684 if (!adev->gfx.rlc_fw)
3685 return -EINVAL;
3686
3687 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3688 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3689 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3690 adev->gfx.rlc_feature_version = le32_to_cpu(
3691 hdr->ucode_feature_version);
a2e73f56
AD		 3692
3693 gfx_v7_0_rlc_stop(adev);
3694
3695 /* disable CG */
3696 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3697 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3698
3699 gfx_v7_0_rlc_reset(adev);
3700
3701 gfx_v7_0_init_pg(adev);
3702
3703 WREG32(mmRLC_LB_CNTR_INIT, 0);
3704 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3705
3706 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3707 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3708 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3709 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3710 WREG32(mmRLC_LB_CNTL, 0x80000004);
3711 mutex_unlock(&adev->grbm_idx_mutex);
3712
3713 WREG32(mmRLC_MC_CNTL, 0);
3714 WREG32(mmRLC_UCODE_CNTL, 0);
3715
3716 fw_data = (const __le32 *)
3717 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3718 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3719 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3720 for (i = 0; i < fw_size; i++)
3721 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3722 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3723
3724 /* XXX - find out what chips support lbpw */
3725 gfx_v7_0_enable_lbpw(adev, false);
3726
3727 if (adev->asic_type == CHIP_BONAIRE)
3728 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3729
3730 gfx_v7_0_rlc_start(adev);
3731
3732 return 0;
3733}
3734
3735static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3736{
3737 u32 data, orig, tmp, tmp2;
3738
3739 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3740
e3b04bc7 3741 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
a2e73f56
AD		 3742 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3743
3744 tmp = gfx_v7_0_halt_rlc(adev);
3745
3746 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3747 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3748 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3749 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3750 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3751 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3752 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3753 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3754 mutex_unlock(&adev->grbm_idx_mutex);
3755
3756 gfx_v7_0_update_rlc(adev, tmp);
3757
3758 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3759 } else {
3760 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3761
3762 RREG32(mmCB_CGTT_SCLK_CTRL);
3763 RREG32(mmCB_CGTT_SCLK_CTRL);
3764 RREG32(mmCB_CGTT_SCLK_CTRL);
3765 RREG32(mmCB_CGTT_SCLK_CTRL);
3766
3767 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3768 }
3769
3770 if (orig != data)
3771 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3772
3773}
3774
3775static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3776{
3777 u32 data, orig, tmp = 0;
3778
e3b04bc7
AD		 3779 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3780 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3781 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
a2e73f56
AD		 3782 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3783 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3784 if (orig != data)
3785 WREG32(mmCP_MEM_SLP_CNTL, data);
3786 }
3787 }
3788
3789 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3790 data |= 0x00000001;
3791 data &= 0xfffffffd;
3792 if (orig != data)
3793 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3794
3795 tmp = gfx_v7_0_halt_rlc(adev);
3796
3797 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3798 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3799 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3800 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3801 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3802 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3803 WREG32(mmRLC_SERDES_WR_CTRL, data);
3804 mutex_unlock(&adev->grbm_idx_mutex);
3805
3806 gfx_v7_0_update_rlc(adev, tmp);
3807
e3b04bc7 3808 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
a2e73f56
AD		 3809 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3810 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3811 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3812 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3813 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
e3b04bc7
AD		 3814 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3815 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
a2e73f56
AD		 3816 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3817 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3818 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3819 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3820 if (orig != data)
3821 WREG32(mmCGTS_SM_CTRL_REG, data);
3822 }
3823 } else {
3824 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3825 data |= 0x00000003;
3826 if (orig != data)
3827 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3828
3829 data = RREG32(mmRLC_MEM_SLP_CNTL);
3830 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3831 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3832 WREG32(mmRLC_MEM_SLP_CNTL, data);
3833 }
3834
3835 data = RREG32(mmCP_MEM_SLP_CNTL);
3836 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3837 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3838 WREG32(mmCP_MEM_SLP_CNTL, data);
3839 }
3840
3841 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3842 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3843 if (orig != data)
3844 WREG32(mmCGTS_SM_CTRL_REG, data);
3845
3846 tmp = gfx_v7_0_halt_rlc(adev);
3847
3848 mutex_lock(&adev->grbm_idx_mutex);
9559ef5b 3849 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
a2e73f56
AD		 3850 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3851 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3852 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3853 WREG32(mmRLC_SERDES_WR_CTRL, data);
3854 mutex_unlock(&adev->grbm_idx_mutex);
3855
3856 gfx_v7_0_update_rlc(adev, tmp);
3857 }
3858}
3859
3860static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3861 bool enable)
3862{
3863 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3864 /* order matters! */
3865 if (enable) {
3866 gfx_v7_0_enable_mgcg(adev, true);
3867 gfx_v7_0_enable_cgcg(adev, true);
3868 } else {
3869 gfx_v7_0_enable_cgcg(adev, false);
3870 gfx_v7_0_enable_mgcg(adev, false);
3871 }
3872 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3873}
3874
3875static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3876 bool enable)
3877{
3878 u32 data, orig;
3879
3880 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3881 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3882 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3883 else
3884 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3885 if (orig != data)
3886 WREG32(mmRLC_PG_CNTL, data);
3887}
3888
3889static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3890 bool enable)
3891{
3892 u32 data, orig;
3893
3894 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3895 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
a2e73f56
AD		 3896 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3897 else
3898 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3899 if (orig != data)
3900 WREG32(mmRLC_PG_CNTL, data);
3901}
3902
3903static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3904{
3905 u32 data, orig;
3906
3907 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3908 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
a2e73f56
AD		 3909 data &= ~0x8000;
3910 else
3911 data |= 0x8000;
3912 if (orig != data)
3913 WREG32(mmRLC_PG_CNTL, data);
3914}
3915
3916static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3917{
3918 u32 data, orig;
3919
3920 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 3921 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
a2e73f56
AD		 3922 data &= ~0x2000;
3923 else
3924 data |= 0x2000;
3925 if (orig != data)
3926 WREG32(mmRLC_PG_CNTL, data);
3927}
3928
3929static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3930{
3931 const __le32 *fw_data;
3932 volatile u32 *dst_ptr;
3933 int me, i, max_me = 4;
3934 u32 bo_offset = 0;
3935 u32 table_offset, table_size;
3936
3937 if (adev->asic_type == CHIP_KAVERI)
3938 max_me = 5;
3939
3940 if (adev->gfx.rlc.cp_table_ptr == NULL)
3941 return;
3942
3943 /* write the cp table buffer */
3944 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3945 for (me = 0; me < max_me; me++) {
3946 if (me == 0) {
3947 const struct gfx_firmware_header_v1_0 *hdr =
3948 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3949 fw_data = (const __le32 *)
3950 (adev->gfx.ce_fw->data +
3951 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3952 table_offset = le32_to_cpu(hdr->jt_offset);
3953 table_size = le32_to_cpu(hdr->jt_size);
3954 } else if (me == 1) {
3955 const struct gfx_firmware_header_v1_0 *hdr =
3956 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3957 fw_data = (const __le32 *)
3958 (adev->gfx.pfp_fw->data +
3959 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3960 table_offset = le32_to_cpu(hdr->jt_offset);
3961 table_size = le32_to_cpu(hdr->jt_size);
3962 } else if (me == 2) {
3963 const struct gfx_firmware_header_v1_0 *hdr =
3964 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3965 fw_data = (const __le32 *)
3966 (adev->gfx.me_fw->data +
3967 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3968 table_offset = le32_to_cpu(hdr->jt_offset);
3969 table_size = le32_to_cpu(hdr->jt_size);
3970 } else if (me == 3) {
3971 const struct gfx_firmware_header_v1_0 *hdr =
3972 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3973 fw_data = (const __le32 *)
3974 (adev->gfx.mec_fw->data +
3975 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3976 table_offset = le32_to_cpu(hdr->jt_offset);
3977 table_size = le32_to_cpu(hdr->jt_size);
3978 } else {
3979 const struct gfx_firmware_header_v1_0 *hdr =
3980 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3981 fw_data = (const __le32 *)
3982 (adev->gfx.mec2_fw->data +
3983 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3984 table_offset = le32_to_cpu(hdr->jt_offset);
3985 table_size = le32_to_cpu(hdr->jt_size);
3986 }
3987
3988 for (i = 0; i < table_size; i ++) {
3989 dst_ptr[bo_offset + i] =
3990 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3991 }
3992
3993 bo_offset += table_size;
3994 }
3995}
3996
3997static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3998 bool enable)
3999{
4000 u32 data, orig;
4001
e3b04bc7 4002 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
a2e73f56
AD		 4003 orig = data = RREG32(mmRLC_PG_CNTL);
4004 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4005 if (orig != data)
4006 WREG32(mmRLC_PG_CNTL, data);
4007
4008 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4009 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4010 if (orig != data)
4011 WREG32(mmRLC_AUTO_PG_CTRL, data);
4012 } else {
4013 orig = data = RREG32(mmRLC_PG_CNTL);
4014 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4015 if (orig != data)
4016 WREG32(mmRLC_PG_CNTL, data);
4017
4018 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4019 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4020 if (orig != data)
4021 WREG32(mmRLC_AUTO_PG_CTRL, data);
4022
4023 data = RREG32(mmDB_RENDER_CONTROL);
4024 }
4025}
4026
324c614a
NH		 4027static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4028 u32 bitmap)
4029{
4030 u32 data;
4031
4032 if (!bitmap)
4033 return;
4034
4035 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4036 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4037
4038 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
4039}
4040
8f8e00c1 4041static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 4042{
8f8e00c1 4043 u32 data, mask;
a2e73f56 4044
8f8e00c1
AD		 4045 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4046 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 4047
8f8e00c1
AD		 4048 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4049 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 4050
6157bd7a 4051 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
a2e73f56 4052
8f8e00c1 4053 return (~data) & mask;
a2e73f56
AD		 4054}
4055
4056static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4057{
7dae69a2 4058 u32 tmp;
a2e73f56 4059
7dae69a2 4060 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
a2e73f56
AD		 4061
4062 tmp = RREG32(mmRLC_MAX_PG_CU);
4063 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
7dae69a2 4064 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
a2e73f56
AD		 4065 WREG32(mmRLC_MAX_PG_CU, tmp);
4066}
4067
4068static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4069 bool enable)
4070{
4071 u32 data, orig;
4072
4073 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 4074 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
a2e73f56
AD		 4075 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4076 else
4077 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4078 if (orig != data)
4079 WREG32(mmRLC_PG_CNTL, data);
4080}
4081
4082static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4083 bool enable)
4084{
4085 u32 data, orig;
4086
4087 orig = data = RREG32(mmRLC_PG_CNTL);
e3b04bc7 4088 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
a2e73f56
AD		 4089 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4090 else
4091 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4092 if (orig != data)
4093 WREG32(mmRLC_PG_CNTL, data);
4094}
4095
4096#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4097#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4098
4099static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4100{
4101 u32 data, orig;
4102 u32 i;
4103
4104 if (adev->gfx.rlc.cs_data) {
4105 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4106 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4107 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4108 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4109 } else {
4110 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4111 for (i = 0; i < 3; i++)
4112 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4113 }
4114 if (adev->gfx.rlc.reg_list) {
4115 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4116 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4117 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4118 }
4119
4120 orig = data = RREG32(mmRLC_PG_CNTL);
4121 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4122 if (orig != data)
4123 WREG32(mmRLC_PG_CNTL, data);
4124
4125 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4126 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4127
4128 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4129 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4130 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4131 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4132
4133 data = 0x10101010;
4134 WREG32(mmRLC_PG_DELAY, data);
4135
4136 data = RREG32(mmRLC_PG_DELAY_2);
4137 data &= ~0xff;
4138 data |= 0x3;
4139 WREG32(mmRLC_PG_DELAY_2, data);
4140
4141 data = RREG32(mmRLC_AUTO_PG_CTRL);
4142 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4143 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4144 WREG32(mmRLC_AUTO_PG_CTRL, data);
4145
4146}
4147
4148static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4149{
4150 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4151 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4152 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4153}
4154
4155static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4156{
4157 u32 count = 0;
4158 const struct cs_section_def *sect = NULL;
4159 const struct cs_extent_def *ext = NULL;
4160
4161 if (adev->gfx.rlc.cs_data == NULL)
4162 return 0;
4163
4164 /* begin clear state */
4165 count += 2;
4166 /* context control state */
4167 count += 3;
4168
4169 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4170 for (ext = sect->section; ext->extent != NULL; ++ext) {
4171 if (sect->id == SECT_CONTEXT)
4172 count += 2 + ext->reg_count;
4173 else
4174 return 0;
4175 }
4176 }
4177 /* pa_sc_raster_config/pa_sc_raster_config1 */
4178 count += 4;
4179 /* end clear state */
4180 count += 2;
4181 /* clear state */
4182 count += 2;
4183
4184 return count;
4185}
4186
4187static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4188 volatile u32 *buffer)
4189{
4190 u32 count = 0, i;
4191 const struct cs_section_def *sect = NULL;
4192 const struct cs_extent_def *ext = NULL;
4193
4194 if (adev->gfx.rlc.cs_data == NULL)
4195 return;
4196 if (buffer == NULL)
4197 return;
4198
4199 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4200 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4201
4202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4203 buffer[count++] = cpu_to_le32(0x80000000);
4204 buffer[count++] = cpu_to_le32(0x80000000);
4205
4206 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4207 for (ext = sect->section; ext->extent != NULL; ++ext) {
4208 if (sect->id == SECT_CONTEXT) {
4209 buffer[count++] =
4210 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4211 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4212 for (i = 0; i < ext->reg_count; i++)
4213 buffer[count++] = cpu_to_le32(ext->extent[i]);
4214 } else {
4215 return;
4216 }
4217 }
4218 }
4219
4220 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4221 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4222 switch (adev->asic_type) {
4223 case CHIP_BONAIRE:
4224 buffer[count++] = cpu_to_le32(0x16000012);
4225 buffer[count++] = cpu_to_le32(0x00000000);
4226 break;
4227 case CHIP_KAVERI:
4228 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4229 buffer[count++] = cpu_to_le32(0x00000000);
4230 break;
4231 case CHIP_KABINI:
4232 case CHIP_MULLINS:
4233 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4234 buffer[count++] = cpu_to_le32(0x00000000);
4235 break;
4236 case CHIP_HAWAII:
4237 buffer[count++] = cpu_to_le32(0x3a00161a);
4238 buffer[count++] = cpu_to_le32(0x0000002e);
4239 break;
4240 default:
4241 buffer[count++] = cpu_to_le32(0x00000000);
4242 buffer[count++] = cpu_to_le32(0x00000000);
4243 break;
4244 }
4245
4246 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4247 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4248
4249 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4250 buffer[count++] = cpu_to_le32(0);
4251}
4252
4253static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4254{
e3b04bc7
AD		 4255 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4256 AMD_PG_SUPPORT_GFX_SMG |
4257 AMD_PG_SUPPORT_GFX_DMG |
4258 AMD_PG_SUPPORT_CP |
4259 AMD_PG_SUPPORT_GDS |
4260 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56
AD		 4261 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4262 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
e3b04bc7 4263 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4264 gfx_v7_0_init_gfx_cgpg(adev);
4265 gfx_v7_0_enable_cp_pg(adev, true);
4266 gfx_v7_0_enable_gds_pg(adev, true);
4267 }
4268 gfx_v7_0_init_ao_cu_mask(adev);
4269 gfx_v7_0_update_gfx_pg(adev, true);
4270 }
4271}
4272
4273static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4274{
e3b04bc7
AD		 4275 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4276 AMD_PG_SUPPORT_GFX_SMG |
4277 AMD_PG_SUPPORT_GFX_DMG |
4278 AMD_PG_SUPPORT_CP |
4279 AMD_PG_SUPPORT_GDS |
4280 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 4281 gfx_v7_0_update_gfx_pg(adev, false);
e3b04bc7 4282 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 4283 gfx_v7_0_enable_cp_pg(adev, false);
4284 gfx_v7_0_enable_gds_pg(adev, false);
4285 }
4286 }
4287}
4288
4289/**
4290 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4291 *
4292 * @adev: amdgpu_device pointer
4293 *
4294 * Fetches a GPU clock counter snapshot (SI).
4295 * Returns the 64 bit clock counter snapshot.
4296 */
b95e31fd 4297static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
a2e73f56
AD		 4298{
4299 uint64_t clock;
4300
4301 mutex_lock(&adev->gfx.gpu_clock_mutex);
4302 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4303 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4304 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4305 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4306 return clock;
4307}
4308
4309static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4310 uint32_t vmid,
4311 uint32_t gds_base, uint32_t gds_size,
4312 uint32_t gws_base, uint32_t gws_size,
4313 uint32_t oa_base, uint32_t oa_size)
4314{
4315 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4316 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4317
4318 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4319 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4320
4321 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4322 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4323
4324 /* GDS Base */
4325 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4326 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4327 WRITE_DATA_DST_SEL(0)));
4328 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4329 amdgpu_ring_write(ring, 0);
4330 amdgpu_ring_write(ring, gds_base);
4331
4332 /* GDS Size */
4333 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4334 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4335 WRITE_DATA_DST_SEL(0)));
4336 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4337 amdgpu_ring_write(ring, 0);
4338 amdgpu_ring_write(ring, gds_size);
4339
4340 /* GWS */
4341 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4342 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4343 WRITE_DATA_DST_SEL(0)));
4344 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4345 amdgpu_ring_write(ring, 0);
4346 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4347
4348 /* OA */
4349 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4350 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4351 WRITE_DATA_DST_SEL(0)));
4352 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4353 amdgpu_ring_write(ring, 0);
4354 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4355}
4356
b04e26b3
AD		 4357static unsigned gfx_v7_0_ring_get_emit_ib_size_gfx(struct amdgpu_ring *ring)
4358{
4359 return
4360 4; /* gfx_v7_0_ring_emit_ib_gfx */
4361}
4362
4363static unsigned gfx_v7_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring)
4364{
4365 return
4366 20 + /* gfx_v7_0_ring_emit_gds_switch */
4367 7 + /* gfx_v7_0_ring_emit_hdp_flush */
4368 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
4369 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
4370 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
4371 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
4372 3; /* gfx_v7_ring_emit_cntxcntl */
4373}
4374
4375static unsigned gfx_v7_0_ring_get_emit_ib_size_compute(struct amdgpu_ring *ring)
4376{
4377 return
4378 4; /* gfx_v7_0_ring_emit_ib_compute */
4379}
4380
4381static unsigned gfx_v7_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring)
4382{
4383 return
4384 20 + /* gfx_v7_0_ring_emit_gds_switch */
4385 7 + /* gfx_v7_0_ring_emit_hdp_flush */
4386 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
4387 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
4388 17 + /* gfx_v7_0_ring_emit_vm_flush */
4389 7 + 7 + 7; /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
4390}
4391
b95e31fd
AD		 4392static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4393 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
05fb7291 4394 .select_se_sh = &gfx_v7_0_select_se_sh,
b95e31fd
AD		 4395};
4396
06120a1e
AD		 4397static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4398 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4399 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4400};
4401
5fc3aeeb 4402static int gfx_v7_0_early_init(void *handle)
a2e73f56 4403{
5fc3aeeb 4404 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4405
4406 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4407 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
b95e31fd 4408 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
06120a1e 4409 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
a2e73f56
AD		 4410 gfx_v7_0_set_ring_funcs(adev);
4411 gfx_v7_0_set_irq_funcs(adev);
4412 gfx_v7_0_set_gds_init(adev);
4413
4414 return 0;
4415}
4416
ef720532
AD		 4417static int gfx_v7_0_late_init(void *handle)
4418{
4419 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4420 int r;
4421
4422 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4423 if (r)
4424 return r;
4425
4426 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4427 if (r)
4428 return r;
4429
4430 return 0;
4431}
4432
d93f3ca7
AD		 4433static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4434{
4435 u32 gb_addr_config;
4436 u32 mc_shared_chmap, mc_arb_ramcfg;
4437 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4438 u32 tmp;
4439
4440 switch (adev->asic_type) {
4441 case CHIP_BONAIRE:
4442 adev->gfx.config.max_shader_engines = 2;
4443 adev->gfx.config.max_tile_pipes = 4;
4444 adev->gfx.config.max_cu_per_sh = 7;
4445 adev->gfx.config.max_sh_per_se = 1;
4446 adev->gfx.config.max_backends_per_se = 2;
4447 adev->gfx.config.max_texture_channel_caches = 4;
4448 adev->gfx.config.max_gprs = 256;
4449 adev->gfx.config.max_gs_threads = 32;
4450 adev->gfx.config.max_hw_contexts = 8;
4451
4452 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4453 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4454 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4455 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4456 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4457 break;
4458 case CHIP_HAWAII:
4459 adev->gfx.config.max_shader_engines = 4;
4460 adev->gfx.config.max_tile_pipes = 16;
4461 adev->gfx.config.max_cu_per_sh = 11;
4462 adev->gfx.config.max_sh_per_se = 1;
4463 adev->gfx.config.max_backends_per_se = 4;
4464 adev->gfx.config.max_texture_channel_caches = 16;
4465 adev->gfx.config.max_gprs = 256;
4466 adev->gfx.config.max_gs_threads = 32;
4467 adev->gfx.config.max_hw_contexts = 8;
4468
4469 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4470 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4471 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4472 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4473 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4474 break;
4475 case CHIP_KAVERI:
4476 adev->gfx.config.max_shader_engines = 1;
4477 adev->gfx.config.max_tile_pipes = 4;
4478 if ((adev->pdev->device == 0x1304) ||
4479 (adev->pdev->device == 0x1305) ||
4480 (adev->pdev->device == 0x130C) ||
4481 (adev->pdev->device == 0x130F) ||
4482 (adev->pdev->device == 0x1310) ||
4483 (adev->pdev->device == 0x1311) ||
4484 (adev->pdev->device == 0x131C)) {
4485 adev->gfx.config.max_cu_per_sh = 8;
4486 adev->gfx.config.max_backends_per_se = 2;
4487 } else if ((adev->pdev->device == 0x1309) ||
4488 (adev->pdev->device == 0x130A) ||
4489 (adev->pdev->device == 0x130D) ||
4490 (adev->pdev->device == 0x1313) ||
4491 (adev->pdev->device == 0x131D)) {
4492 adev->gfx.config.max_cu_per_sh = 6;
4493 adev->gfx.config.max_backends_per_se = 2;
4494 } else if ((adev->pdev->device == 0x1306) ||
4495 (adev->pdev->device == 0x1307) ||
4496 (adev->pdev->device == 0x130B) ||
4497 (adev->pdev->device == 0x130E) ||
4498 (adev->pdev->device == 0x1315) ||
4499 (adev->pdev->device == 0x131B)) {
4500 adev->gfx.config.max_cu_per_sh = 4;
4501 adev->gfx.config.max_backends_per_se = 1;
4502 } else {
4503 adev->gfx.config.max_cu_per_sh = 3;
4504 adev->gfx.config.max_backends_per_se = 1;
4505 }
4506 adev->gfx.config.max_sh_per_se = 1;
4507 adev->gfx.config.max_texture_channel_caches = 4;
4508 adev->gfx.config.max_gprs = 256;
4509 adev->gfx.config.max_gs_threads = 16;
4510 adev->gfx.config.max_hw_contexts = 8;
4511
4512 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4513 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4514 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4515 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4516 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4517 break;
4518 case CHIP_KABINI:
4519 case CHIP_MULLINS:
4520 default:
4521 adev->gfx.config.max_shader_engines = 1;
4522 adev->gfx.config.max_tile_pipes = 2;
4523 adev->gfx.config.max_cu_per_sh = 2;
4524 adev->gfx.config.max_sh_per_se = 1;
4525 adev->gfx.config.max_backends_per_se = 1;
4526 adev->gfx.config.max_texture_channel_caches = 2;
4527 adev->gfx.config.max_gprs = 256;
4528 adev->gfx.config.max_gs_threads = 16;
4529 adev->gfx.config.max_hw_contexts = 8;
4530
4531 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4532 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4533 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4534 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4535 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4536 break;
4537 }
4538
4539 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4540 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4541 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4542
4543 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4544 adev->gfx.config.mem_max_burst_length_bytes = 256;
4545 if (adev->flags & AMD_IS_APU) {
4546 /* Get memory bank mapping mode. */
4547 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4548 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4549 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4550
4551 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4552 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4553 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4554
4555 /* Validate settings in case only one DIMM installed. */
4556 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4557 dimm00_addr_map = 0;
4558 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4559 dimm01_addr_map = 0;
4560 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4561 dimm10_addr_map = 0;
4562 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4563 dimm11_addr_map = 0;
4564
4565 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4566 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4567 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4568 adev->gfx.config.mem_row_size_in_kb = 2;
4569 else
4570 adev->gfx.config.mem_row_size_in_kb = 1;
4571 } else {
4572 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4573 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4574 if (adev->gfx.config.mem_row_size_in_kb > 4)
4575 adev->gfx.config.mem_row_size_in_kb = 4;
4576 }
4577 /* XXX use MC settings? */
4578 adev->gfx.config.shader_engine_tile_size = 32;
4579 adev->gfx.config.num_gpus = 1;
4580 adev->gfx.config.multi_gpu_tile_size = 64;
4581
4582 /* fix up row size */
4583 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4584 switch (adev->gfx.config.mem_row_size_in_kb) {
4585 case 1:
4586 default:
4587 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4588 break;
4589 case 2:
4590 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4591 break;
4592 case 4:
4593 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4594 break;
4595 }
4596 adev->gfx.config.gb_addr_config = gb_addr_config;
4597}
4598
5fc3aeeb 4599static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4600{
4601 struct amdgpu_ring *ring;
5fc3aeeb 4602 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4603 int i, r;
4604
4605 /* EOP Event */
4606 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4607 if (r)
4608 return r;
4609
4610 /* Privileged reg */
4611 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4612 if (r)
4613 return r;
4614
4615 /* Privileged inst */
4616 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4617 if (r)
4618 return r;
4619
4620 gfx_v7_0_scratch_init(adev);
4621
4622 r = gfx_v7_0_init_microcode(adev);
4623 if (r) {
4624 DRM_ERROR("Failed to load gfx firmware!\n");
4625 return r;
4626 }
4627
4628 r = gfx_v7_0_rlc_init(adev);
4629 if (r) {
4630 DRM_ERROR("Failed to init rlc BOs!\n");
4631 return r;
4632 }
4633
4634 /* allocate mec buffers */
4635 r = gfx_v7_0_mec_init(adev);
4636 if (r) {
4637 DRM_ERROR("Failed to init MEC BOs!\n");
4638 return r;
4639 }
4640
a2e73f56
AD		 4641 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4642 ring = &adev->gfx.gfx_ring[i];
4643 ring->ring_obj = NULL;
4644 sprintf(ring->name, "gfx");
2800de2e 4645 r = amdgpu_ring_init(adev, ring, 1024,
a2e73f56
AD		 4646 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4647 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4648 AMDGPU_RING_TYPE_GFX);
4649 if (r)
4650 return r;
4651 }
4652
4653 /* set up the compute queues */
4654 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4655 unsigned irq_type;
4656
4657 /* max 32 queues per MEC */
4658 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4659 DRM_ERROR("Too many (%d) compute rings!\n", i);
4660 break;
4661 }
4662 ring = &adev->gfx.compute_ring[i];
4663 ring->ring_obj = NULL;
4664 ring->use_doorbell = true;
4665 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4666 ring->me = 1; /* first MEC */
4667 ring->pipe = i / 8;
4668 ring->queue = i % 8;
771c8ec1 4669 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
a2e73f56
AD		 4670 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4671 /* type-2 packets are deprecated on MEC, use type-3 instead */
2800de2e 4672 r = amdgpu_ring_init(adev, ring, 1024,
a2e73f56
AD		 4673 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4674 &adev->gfx.eop_irq, irq_type,
4675 AMDGPU_RING_TYPE_COMPUTE);
4676 if (r)
4677 return r;
4678 }
4679
4680 /* reserve GDS, GWS and OA resource for gfx */
78bbbd9c
CK		 4681 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4682 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4683 &adev->gds.gds_gfx_bo, NULL, NULL);
a2e73f56
AD		 4684 if (r)
4685 return r;
4686
78bbbd9c
CK		 4687 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4688 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4689 &adev->gds.gws_gfx_bo, NULL, NULL);
a2e73f56
AD		 4690 if (r)
4691 return r;
4692
78bbbd9c
CK		 4693 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4694 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4695 &adev->gds.oa_gfx_bo, NULL, NULL);
a2e73f56
AD		 4696 if (r)
4697 return r;
4698
d93f3ca7
AD		 4699 adev->gfx.ce_ram_size = 0x8000;
4700
4701 gfx_v7_0_gpu_early_init(adev);
4702
a2e73f56
AD		 4703 return r;
4704}
4705
5fc3aeeb 4706static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4707{
4708 int i;
5fc3aeeb 4709 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 4710
8640faed
JZ		 4711 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4712 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4713 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
a2e73f56
AD		 4714
4715 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4716 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4717 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4718 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4719
a2e73f56
AD		 4720 gfx_v7_0_cp_compute_fini(adev);
4721 gfx_v7_0_rlc_fini(adev);
4722 gfx_v7_0_mec_fini(adev);
e517cd77 4723 gfx_v7_0_free_microcode(adev);
a2e73f56
AD		 4724
4725 return 0;
4726}
4727
5fc3aeeb 4728static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4729{
4730 int r;
5fc3aeeb 4731 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4732
4733 gfx_v7_0_gpu_init(adev);
4734
4735 /* init rlc */
4736 r = gfx_v7_0_rlc_resume(adev);
4737 if (r)
4738 return r;
4739
4740 r = gfx_v7_0_cp_resume(adev);
4741 if (r)
4742 return r;
4743
4744 return r;
4745}
4746
5fc3aeeb 4747static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4748{
5fc3aeeb 4749 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4750
ef720532
AD		 4751 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4752 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4753 gfx_v7_0_cp_enable(adev, false);
4754 gfx_v7_0_rlc_stop(adev);
4755 gfx_v7_0_fini_pg(adev);
4756
4757 return 0;
4758}
4759
5fc3aeeb 4760static int gfx_v7_0_suspend(void *handle)
a2e73f56 4761{
5fc3aeeb 4762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4763
a2e73f56
AD		 4764 return gfx_v7_0_hw_fini(adev);
4765}
4766
5fc3aeeb 4767static int gfx_v7_0_resume(void *handle)
a2e73f56 4768{
5fc3aeeb 4769 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4770
a2e73f56
AD		 4771 return gfx_v7_0_hw_init(adev);
4772}
4773
5fc3aeeb 4774static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4775{
5fc3aeeb 4776 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4777
a2e73f56
AD		 4778 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4779 return false;
4780 else
4781 return true;
4782}
4783
5fc3aeeb 4784static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4785{
4786 unsigned i;
4787 u32 tmp;
5fc3aeeb 4788 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4789
4790 for (i = 0; i < adev->usec_timeout; i++) {
4791 /* read MC_STATUS */
4792 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4793
4794 if (!tmp)
4795 return 0;
4796 udelay(1);
4797 }
4798 return -ETIMEDOUT;
4799}
4800
5fc3aeeb 4801static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4802{
4803 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4804 u32 tmp;
5fc3aeeb 4805 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4806
4807 /* GRBM_STATUS */
4808 tmp = RREG32(mmGRBM_STATUS);
4809 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4810 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4811 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4812 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4813 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4814 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4815 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4816 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4817
4818 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4819 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4820 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4821 }
4822
4823 /* GRBM_STATUS2 */
4824 tmp = RREG32(mmGRBM_STATUS2);
4825 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4826 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4827
4828 /* SRBM_STATUS */
4829 tmp = RREG32(mmSRBM_STATUS);
4830 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4831 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4832
4833 if (grbm_soft_reset || srbm_soft_reset) {
a2e73f56
AD		 4834 /* disable CG/PG */
4835 gfx_v7_0_fini_pg(adev);
4836 gfx_v7_0_update_cg(adev, false);
4837
4838 /* stop the rlc */
4839 gfx_v7_0_rlc_stop(adev);
4840
4841 /* Disable GFX parsing/prefetching */
4842 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4843
4844 /* Disable MEC parsing/prefetching */
4845 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4846
4847 if (grbm_soft_reset) {
4848 tmp = RREG32(mmGRBM_SOFT_RESET);
4849 tmp |= grbm_soft_reset;
4850 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4851 WREG32(mmGRBM_SOFT_RESET, tmp);
4852 tmp = RREG32(mmGRBM_SOFT_RESET);
4853
4854 udelay(50);
4855
4856 tmp &= ~grbm_soft_reset;
4857 WREG32(mmGRBM_SOFT_RESET, tmp);
4858 tmp = RREG32(mmGRBM_SOFT_RESET);
4859 }
4860
4861 if (srbm_soft_reset) {
4862 tmp = RREG32(mmSRBM_SOFT_RESET);
4863 tmp |= srbm_soft_reset;
4864 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4865 WREG32(mmSRBM_SOFT_RESET, tmp);
4866 tmp = RREG32(mmSRBM_SOFT_RESET);
4867
4868 udelay(50);
4869
4870 tmp &= ~srbm_soft_reset;
4871 WREG32(mmSRBM_SOFT_RESET, tmp);
4872 tmp = RREG32(mmSRBM_SOFT_RESET);
4873 }
4874 /* Wait a little for things to settle down */
4875 udelay(50);
a2e73f56
AD		 4876 }
4877 return 0;
4878}
4879
4880static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4881 enum amdgpu_interrupt_state state)
4882{
4883 u32 cp_int_cntl;
4884
4885 switch (state) {
4886 case AMDGPU_IRQ_STATE_DISABLE:
4887 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4888 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4889 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4890 break;
4891 case AMDGPU_IRQ_STATE_ENABLE:
4892 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4893 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4894 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4895 break;
4896 default:
4897 break;
4898 }
4899}
4900
4901static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4902 int me, int pipe,
4903 enum amdgpu_interrupt_state state)
4904{
4905 u32 mec_int_cntl, mec_int_cntl_reg;
4906
4907 /*
4908 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4909 * handles the setting of interrupts for this specific pipe. All other
4910 * pipes' interrupts are set by amdkfd.
4911 */
4912
4913 if (me == 1) {
4914 switch (pipe) {
4915 case 0:
4916 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4917 break;
4918 default:
4919 DRM_DEBUG("invalid pipe %d\n", pipe);
4920 return;
4921 }
4922 } else {
4923 DRM_DEBUG("invalid me %d\n", me);
4924 return;
4925 }
4926
4927 switch (state) {
4928 case AMDGPU_IRQ_STATE_DISABLE:
4929 mec_int_cntl = RREG32(mec_int_cntl_reg);
4930 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4931 WREG32(mec_int_cntl_reg, mec_int_cntl);
4932 break;
4933 case AMDGPU_IRQ_STATE_ENABLE:
4934 mec_int_cntl = RREG32(mec_int_cntl_reg);
4935 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4936 WREG32(mec_int_cntl_reg, mec_int_cntl);
4937 break;
4938 default:
4939 break;
4940 }
4941}
4942
4943static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4944 struct amdgpu_irq_src *src,
4945 unsigned type,
4946 enum amdgpu_interrupt_state state)
4947{
4948 u32 cp_int_cntl;
4949
4950 switch (state) {
4951 case AMDGPU_IRQ_STATE_DISABLE:
4952 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4953 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4954 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4955 break;
4956 case AMDGPU_IRQ_STATE_ENABLE:
4957 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4958 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4959 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4960 break;
4961 default:
4962 break;
4963 }
4964
4965 return 0;
4966}
4967
4968static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4969 struct amdgpu_irq_src *src,
4970 unsigned type,
4971 enum amdgpu_interrupt_state state)
4972{
4973 u32 cp_int_cntl;
4974
4975 switch (state) {
4976 case AMDGPU_IRQ_STATE_DISABLE:
4977 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4978 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4979 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4980 break;
4981 case AMDGPU_IRQ_STATE_ENABLE:
4982 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4983 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4984 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4985 break;
4986 default:
4987 break;
4988 }
4989
4990 return 0;
4991}
4992
4993static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4994 struct amdgpu_irq_src *src,
4995 unsigned type,
4996 enum amdgpu_interrupt_state state)
4997{
4998 switch (type) {
4999 case AMDGPU_CP_IRQ_GFX_EOP:
5000 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5001 break;
5002 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5003 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5004 break;
5005 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5006 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5007 break;
5008 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5009 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5010 break;
5011 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5012 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5013 break;
5014 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5015 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5016 break;
5017 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5018 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5019 break;
5020 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5021 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5022 break;
5023 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5024 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5025 break;
5026 default:
5027 break;
5028 }
5029 return 0;
5030}
5031
5032static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5033 struct amdgpu_irq_src *source,
5034 struct amdgpu_iv_entry *entry)
5035{
5036 u8 me_id, pipe_id;
5037 struct amdgpu_ring *ring;
5038 int i;
5039
5040 DRM_DEBUG("IH: CP EOP\n");
5041 me_id = (entry->ring_id & 0x0c) >> 2;
5042 pipe_id = (entry->ring_id & 0x03) >> 0;
5043 switch (me_id) {
5044 case 0:
5045 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5046 break;
5047 case 1:
5048 case 2:
5049 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5050 ring = &adev->gfx.compute_ring[i];
8b18300c 5051 if ((ring->me == me_id) && (ring->pipe == pipe_id))
a2e73f56
AD		 5052 amdgpu_fence_process(ring);
5053 }
5054 break;
5055 }
5056 return 0;
5057}
5058
5059static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5060 struct amdgpu_irq_src *source,
5061 struct amdgpu_iv_entry *entry)
5062{
5063 DRM_ERROR("Illegal register access in command stream\n");
5064 schedule_work(&adev->reset_work);
5065 return 0;
5066}
5067
5068static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5069 struct amdgpu_irq_src *source,
5070 struct amdgpu_iv_entry *entry)
5071{
5072 DRM_ERROR("Illegal instruction in command stream\n");
5073 // XXX soft reset the gfx block only
5074 schedule_work(&adev->reset_work);
5075 return 0;
5076}
5077
5fc3aeeb 5078static int gfx_v7_0_set_clockgating_state(void *handle,
5079 enum amd_clockgating_state state)
a2e73f56
AD		 5080{
5081 bool gate = false;
5fc3aeeb 5082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5083
5fc3aeeb 5084 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 5085 gate = true;
5086
5087 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5088 /* order matters! */
5089 if (gate) {
5090 gfx_v7_0_enable_mgcg(adev, true);
5091 gfx_v7_0_enable_cgcg(adev, true);
5092 } else {
5093 gfx_v7_0_enable_cgcg(adev, false);
5094 gfx_v7_0_enable_mgcg(adev, false);
5095 }
5096 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5097
5098 return 0;
5099}
5100
5fc3aeeb 5101static int gfx_v7_0_set_powergating_state(void *handle,
5102 enum amd_powergating_state state)
a2e73f56
AD		 5103{
5104 bool gate = false;
5fc3aeeb 5105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5106
5fc3aeeb 5107 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 5108 gate = true;
5109
e3b04bc7
AD		 5110 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5111 AMD_PG_SUPPORT_GFX_SMG |
5112 AMD_PG_SUPPORT_GFX_DMG |
5113 AMD_PG_SUPPORT_CP |
5114 AMD_PG_SUPPORT_GDS |
5115 AMD_PG_SUPPORT_RLC_SMU_HS)) {
a2e73f56 5116 gfx_v7_0_update_gfx_pg(adev, gate);
e3b04bc7 5117 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
a2e73f56
AD		 5118 gfx_v7_0_enable_cp_pg(adev, gate);
5119 gfx_v7_0_enable_gds_pg(adev, gate);
5120 }
5121 }
5122
5123 return 0;
5124}
5125
5fc3aeeb 5126const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
88a907d6 5127 .name = "gfx_v7_0",
a2e73f56 5128 .early_init = gfx_v7_0_early_init,
ef720532 5129 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 5130 .sw_init = gfx_v7_0_sw_init,
5131 .sw_fini = gfx_v7_0_sw_fini,
5132 .hw_init = gfx_v7_0_hw_init,
5133 .hw_fini = gfx_v7_0_hw_fini,
5134 .suspend = gfx_v7_0_suspend,
5135 .resume = gfx_v7_0_resume,
5136 .is_idle = gfx_v7_0_is_idle,
5137 .wait_for_idle = gfx_v7_0_wait_for_idle,
5138 .soft_reset = gfx_v7_0_soft_reset,
a2e73f56
AD		 5139 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5140 .set_powergating_state = gfx_v7_0_set_powergating_state,
5141};
5142
a2e73f56 5143static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
f1c0efc5 5144 .get_rptr = gfx_v7_0_ring_get_rptr,
a2e73f56
AD		 5145 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5146 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5147 .parse_cs = NULL,
93323131 5148 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 5149 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
b8c7b39e 5150 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 5151 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5152 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 5153 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 5154 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 5155 .test_ring = gfx_v7_0_ring_test_ring,
5156 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5157 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5158 .pad_ib = amdgpu_ring_generic_pad_ib,
753ad49c 5159 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
b04e26b3
AD		 5160 .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_gfx,
5161 .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_gfx,
a2e73f56
AD		 5162};
5163
5164static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
f1c0efc5 5165 .get_rptr = gfx_v7_0_ring_get_rptr,
a2e73f56
AD		 5166 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5167 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5168 .parse_cs = NULL,
93323131 5169 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 5170 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
b8c7b39e 5171 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
a2e73f56
AD		 5172 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5173 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 5174 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
0955860b 5175 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
a2e73f56
AD		 5176 .test_ring = gfx_v7_0_ring_test_ring,
5177 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5178 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5179 .pad_ib = amdgpu_ring_generic_pad_ib,
b04e26b3
AD		 5180 .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_compute,
5181 .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_compute,
a2e73f56
AD		 5182};
5183
5184static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5185{
5186 int i;
5187
5188 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5189 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5190 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5191 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5192}
5193
5194static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5195 .set = gfx_v7_0_set_eop_interrupt_state,
5196 .process = gfx_v7_0_eop_irq,
5197};
5198
5199static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5200 .set = gfx_v7_0_set_priv_reg_fault_state,
5201 .process = gfx_v7_0_priv_reg_irq,
5202};
5203
5204static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5205 .set = gfx_v7_0_set_priv_inst_fault_state,
5206 .process = gfx_v7_0_priv_inst_irq,
5207};
5208
5209static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5210{
5211 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5212 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5213
5214 adev->gfx.priv_reg_irq.num_types = 1;
5215 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5216
5217 adev->gfx.priv_inst_irq.num_types = 1;
5218 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5219}
5220
5221static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5222{
5223 /* init asci gds info */
5224 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5225 adev->gds.gws.total_size = 64;
5226 adev->gds.oa.total_size = 16;
5227
5228 if (adev->gds.mem.total_size == 64 * 1024) {
5229 adev->gds.mem.gfx_partition_size = 4096;
5230 adev->gds.mem.cs_partition_size = 4096;
5231
5232 adev->gds.gws.gfx_partition_size = 4;
5233 adev->gds.gws.cs_partition_size = 4;
5234
5235 adev->gds.oa.gfx_partition_size = 4;
5236 adev->gds.oa.cs_partition_size = 1;
5237 } else {
5238 adev->gds.mem.gfx_partition_size = 1024;
5239 adev->gds.mem.cs_partition_size = 1024;
5240
5241 adev->gds.gws.gfx_partition_size = 16;
5242 adev->gds.gws.cs_partition_size = 16;
5243
5244 adev->gds.oa.gfx_partition_size = 4;
5245 adev->gds.oa.cs_partition_size = 4;
5246 }
5247}
5248
5249
7dae69a2 5250static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
a2e73f56
AD		 5251{
5252 int i, j, k, counter, active_cu_number = 0;
5253 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7dae69a2 5254 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
324c614a 5255 unsigned disable_masks[4 * 2];
a2e73f56 5256
6157bd7a
FC		 5257 memset(cu_info, 0, sizeof(*cu_info));
5258
324c614a
NH		 5259 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5260
a2e73f56
AD		 5261 mutex_lock(&adev->grbm_idx_mutex);
5262 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5263 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5264 mask = 1;
5265 ao_bitmap = 0;
5266 counter = 0;
9559ef5b 5267 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
324c614a
NH		 5268 if (i < 4 && j < 2)
5269 gfx_v7_0_set_user_cu_inactive_bitmap(
5270 adev, disable_masks[i * 2 + j]);
8f8e00c1 5271 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5272 cu_info->bitmap[i][j] = bitmap;
5273
8f8e00c1 5274 for (k = 0; k < 16; k ++) {
a2e73f56
AD		 5275 if (bitmap & mask) {
5276 if (counter < 2)
5277 ao_bitmap |= mask;
5278 counter ++;
5279 }
5280 mask <<= 1;
5281 }
5282 active_cu_number += counter;
5283 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5284 }
5285 }
9559ef5b 5286 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8f8e00c1 5287 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5288
5289 cu_info->number = active_cu_number;
5290 cu_info->ao_cu_mask = ao_cu_mask;
a2e73f56 5291}
Linux 6.x block layer and io_uring tree(s)