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drm/amdgpu: update tile table for oland/hainan
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / gfx_v6_0.c
CommitLineData
2cd46ad2
KW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "si/clearstate_si.h"
25069e06
TSD		 29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
2cd46ad2
KW		 41
42static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
43static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
45
46MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
47MODULE_FIRMWARE("radeon/tahiti_me.bin");
48MODULE_FIRMWARE("radeon/tahiti_ce.bin");
49MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
50
51MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
52MODULE_FIRMWARE("radeon/pitcairn_me.bin");
53MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
54MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
55
56MODULE_FIRMWARE("radeon/verde_pfp.bin");
57MODULE_FIRMWARE("radeon/verde_me.bin");
58MODULE_FIRMWARE("radeon/verde_ce.bin");
59MODULE_FIRMWARE("radeon/verde_rlc.bin");
60
61MODULE_FIRMWARE("radeon/oland_pfp.bin");
62MODULE_FIRMWARE("radeon/oland_me.bin");
63MODULE_FIRMWARE("radeon/oland_ce.bin");
64MODULE_FIRMWARE("radeon/oland_rlc.bin");
65
66MODULE_FIRMWARE("radeon/hainan_pfp.bin");
67MODULE_FIRMWARE("radeon/hainan_me.bin");
68MODULE_FIRMWARE("radeon/hainan_ce.bin");
69MODULE_FIRMWARE("radeon/hainan_rlc.bin");
70
71static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
72static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
73//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
74static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
75
25069e06
TSD		 76#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
77#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
78#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
79#define MICRO_TILE_MODE(x) ((x) << 0)
80#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
81#define BANK_WIDTH(x) ((x) << 14)
82#define BANK_HEIGHT(x) ((x) << 16)
83#define MACRO_TILE_ASPECT(x) ((x) << 18)
84#define NUM_BANKS(x) ((x) << 20)
2cd46ad2
KW		 85
86static const u32 verde_rlc_save_restore_register_list[] =
87{
88 (0x8000 << 16) | (0x98f4 >> 2),
89 0x00000000,
90 (0x8040 << 16) | (0x98f4 >> 2),
91 0x00000000,
92 (0x8000 << 16) | (0xe80 >> 2),
93 0x00000000,
94 (0x8040 << 16) | (0xe80 >> 2),
95 0x00000000,
96 (0x8000 << 16) | (0x89bc >> 2),
97 0x00000000,
98 (0x8040 << 16) | (0x89bc >> 2),
99 0x00000000,
100 (0x8000 << 16) | (0x8c1c >> 2),
101 0x00000000,
102 (0x8040 << 16) | (0x8c1c >> 2),
103 0x00000000,
104 (0x9c00 << 16) | (0x98f0 >> 2),
105 0x00000000,
106 (0x9c00 << 16) | (0xe7c >> 2),
107 0x00000000,
108 (0x8000 << 16) | (0x9148 >> 2),
109 0x00000000,
110 (0x8040 << 16) | (0x9148 >> 2),
111 0x00000000,
112 (0x9c00 << 16) | (0x9150 >> 2),
113 0x00000000,
114 (0x9c00 << 16) | (0x897c >> 2),
115 0x00000000,
116 (0x9c00 << 16) | (0x8d8c >> 2),
117 0x00000000,
118 (0x9c00 << 16) | (0xac54 >> 2),
119 0X00000000,
120 0x3,
121 (0x9c00 << 16) | (0x98f8 >> 2),
122 0x00000000,
123 (0x9c00 << 16) | (0x9910 >> 2),
124 0x00000000,
125 (0x9c00 << 16) | (0x9914 >> 2),
126 0x00000000,
127 (0x9c00 << 16) | (0x9918 >> 2),
128 0x00000000,
129 (0x9c00 << 16) | (0x991c >> 2),
130 0x00000000,
131 (0x9c00 << 16) | (0x9920 >> 2),
132 0x00000000,
133 (0x9c00 << 16) | (0x9924 >> 2),
134 0x00000000,
135 (0x9c00 << 16) | (0x9928 >> 2),
136 0x00000000,
137 (0x9c00 << 16) | (0x992c >> 2),
138 0x00000000,
139 (0x9c00 << 16) | (0x9930 >> 2),
140 0x00000000,
141 (0x9c00 << 16) | (0x9934 >> 2),
142 0x00000000,
143 (0x9c00 << 16) | (0x9938 >> 2),
144 0x00000000,
145 (0x9c00 << 16) | (0x993c >> 2),
146 0x00000000,
147 (0x9c00 << 16) | (0x9940 >> 2),
148 0x00000000,
149 (0x9c00 << 16) | (0x9944 >> 2),
150 0x00000000,
151 (0x9c00 << 16) | (0x9948 >> 2),
152 0x00000000,
153 (0x9c00 << 16) | (0x994c >> 2),
154 0x00000000,
155 (0x9c00 << 16) | (0x9950 >> 2),
156 0x00000000,
157 (0x9c00 << 16) | (0x9954 >> 2),
158 0x00000000,
159 (0x9c00 << 16) | (0x9958 >> 2),
160 0x00000000,
161 (0x9c00 << 16) | (0x995c >> 2),
162 0x00000000,
163 (0x9c00 << 16) | (0x9960 >> 2),
164 0x00000000,
165 (0x9c00 << 16) | (0x9964 >> 2),
166 0x00000000,
167 (0x9c00 << 16) | (0x9968 >> 2),
168 0x00000000,
169 (0x9c00 << 16) | (0x996c >> 2),
170 0x00000000,
171 (0x9c00 << 16) | (0x9970 >> 2),
172 0x00000000,
173 (0x9c00 << 16) | (0x9974 >> 2),
174 0x00000000,
175 (0x9c00 << 16) | (0x9978 >> 2),
176 0x00000000,
177 (0x9c00 << 16) | (0x997c >> 2),
178 0x00000000,
179 (0x9c00 << 16) | (0x9980 >> 2),
180 0x00000000,
181 (0x9c00 << 16) | (0x9984 >> 2),
182 0x00000000,
183 (0x9c00 << 16) | (0x9988 >> 2),
184 0x00000000,
185 (0x9c00 << 16) | (0x998c >> 2),
186 0x00000000,
187 (0x9c00 << 16) | (0x8c00 >> 2),
188 0x00000000,
189 (0x9c00 << 16) | (0x8c14 >> 2),
190 0x00000000,
191 (0x9c00 << 16) | (0x8c04 >> 2),
192 0x00000000,
193 (0x9c00 << 16) | (0x8c08 >> 2),
194 0x00000000,
195 (0x8000 << 16) | (0x9b7c >> 2),
196 0x00000000,
197 (0x8040 << 16) | (0x9b7c >> 2),
198 0x00000000,
199 (0x8000 << 16) | (0xe84 >> 2),
200 0x00000000,
201 (0x8040 << 16) | (0xe84 >> 2),
202 0x00000000,
203 (0x8000 << 16) | (0x89c0 >> 2),
204 0x00000000,
205 (0x8040 << 16) | (0x89c0 >> 2),
206 0x00000000,
207 (0x8000 << 16) | (0x914c >> 2),
208 0x00000000,
209 (0x8040 << 16) | (0x914c >> 2),
210 0x00000000,
211 (0x8000 << 16) | (0x8c20 >> 2),
212 0x00000000,
213 (0x8040 << 16) | (0x8c20 >> 2),
214 0x00000000,
215 (0x8000 << 16) | (0x9354 >> 2),
216 0x00000000,
217 (0x8040 << 16) | (0x9354 >> 2),
218 0x00000000,
219 (0x9c00 << 16) | (0x9060 >> 2),
220 0x00000000,
221 (0x9c00 << 16) | (0x9364 >> 2),
222 0x00000000,
223 (0x9c00 << 16) | (0x9100 >> 2),
224 0x00000000,
225 (0x9c00 << 16) | (0x913c >> 2),
226 0x00000000,
227 (0x8000 << 16) | (0x90e0 >> 2),
228 0x00000000,
229 (0x8000 << 16) | (0x90e4 >> 2),
230 0x00000000,
231 (0x8000 << 16) | (0x90e8 >> 2),
232 0x00000000,
233 (0x8040 << 16) | (0x90e0 >> 2),
234 0x00000000,
235 (0x8040 << 16) | (0x90e4 >> 2),
236 0x00000000,
237 (0x8040 << 16) | (0x90e8 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x8bcc >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x8b24 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x88c4 >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x8e50 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0x8c0c >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0x8e58 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0x8e5c >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x9508 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x950c >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x9494 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0xac0c >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0xac10 >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0xac14 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0xae00 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0xac08 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x88d4 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x88c8 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x88cc >> 2),
274 0x00000000,
275 (0x9c00 << 16) | (0x89b0 >> 2),
276 0x00000000,
277 (0x9c00 << 16) | (0x8b10 >> 2),
278 0x00000000,
279 (0x9c00 << 16) | (0x8a14 >> 2),
280 0x00000000,
281 (0x9c00 << 16) | (0x9830 >> 2),
282 0x00000000,
283 (0x9c00 << 16) | (0x9834 >> 2),
284 0x00000000,
285 (0x9c00 << 16) | (0x9838 >> 2),
286 0x00000000,
287 (0x9c00 << 16) | (0x9a10 >> 2),
288 0x00000000,
289 (0x8000 << 16) | (0x9870 >> 2),
290 0x00000000,
291 (0x8000 << 16) | (0x9874 >> 2),
292 0x00000000,
293 (0x8001 << 16) | (0x9870 >> 2),
294 0x00000000,
295 (0x8001 << 16) | (0x9874 >> 2),
296 0x00000000,
297 (0x8040 << 16) | (0x9870 >> 2),
298 0x00000000,
299 (0x8040 << 16) | (0x9874 >> 2),
300 0x00000000,
301 (0x8041 << 16) | (0x9870 >> 2),
302 0x00000000,
303 (0x8041 << 16) | (0x9874 >> 2),
304 0x00000000,
305 0x00000000
306};
307
308static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
309{
310 const char *chip_name;
311 char fw_name[30];
312 int err;
313 const struct gfx_firmware_header_v1_0 *cp_hdr;
314 const struct rlc_firmware_header_v1_0 *rlc_hdr;
315
316 DRM_DEBUG("\n");
317
318 switch (adev->asic_type) {
319 case CHIP_TAHITI:
320 chip_name = "tahiti";
321 break;
322 case CHIP_PITCAIRN:
323 chip_name = "pitcairn";
324 break;
325 case CHIP_VERDE:
326 chip_name = "verde";
327 break;
328 case CHIP_OLAND:
329 chip_name = "oland";
330 break;
331 case CHIP_HAINAN:
332 chip_name = "hainan";
333 break;
334 default: BUG();
335 }
336
337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
339 if (err)
340 goto out;
341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
342 if (err)
343 goto out;
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
347
348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
350 if (err)
351 goto out;
352 err = amdgpu_ucode_validate(adev->gfx.me_fw);
353 if (err)
354 goto out;
355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
358
359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
361 if (err)
362 goto out;
363 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
364 if (err)
365 goto out;
366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
369
370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
372 if (err)
373 goto out;
374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
378
379out:
380 if (err) {
381 printk(KERN_ERR
382 "gfx6: Failed to load firmware \"%s\"\n",
383 fw_name);
384 release_firmware(adev->gfx.pfp_fw);
385 adev->gfx.pfp_fw = NULL;
386 release_firmware(adev->gfx.me_fw);
387 adev->gfx.me_fw = NULL;
388 release_firmware(adev->gfx.ce_fw);
389 adev->gfx.ce_fw = NULL;
390 release_firmware(adev->gfx.rlc_fw);
391 adev->gfx.rlc_fw = NULL;
392 }
393 return err;
394}
395
396static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
397{
398 const u32 num_tile_mode_states = 32;
399 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
400
401 switch (adev->gfx.config.mem_row_size_in_kb) {
402 case 1:
403 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
404 break;
405 case 2:
406 default:
407 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
408 break;
409 case 4:
410 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
411 break;
412 }
413
3548f9a8
FC		 414 if (adev->asic_type == CHIP_VERDE) {
415 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
416 switch (reg_offset) {
417 case 0:
418 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
419 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
420 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
422 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
423 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
424 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
425 NUM_BANKS(ADDR_SURF_16_BANK));
426 break;
427 case 1:
428 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
429 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
435 NUM_BANKS(ADDR_SURF_16_BANK));
436 break;
437 case 2:
438 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
439 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
440 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
441 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
442 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
443 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
444 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
445 NUM_BANKS(ADDR_SURF_16_BANK));
446 break;
447 case 3:
448 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
454 NUM_BANKS(ADDR_SURF_8_BANK) |
455 TILE_SPLIT(split_equal_to_row_size));
456 break;
457 case 4:
458 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
459 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
460 PIPE_CONFIG(ADDR_SURF_P4_8x16));
461 break;
462 case 5:
463 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
464 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
465 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
466 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
467 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
468 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
469 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
470 NUM_BANKS(ADDR_SURF_4_BANK));
471 break;
472 case 6:
473 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
475 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
476 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
477 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
480 NUM_BANKS(ADDR_SURF_4_BANK));
481 break;
482 case 7:
483 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
484 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
485 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
488 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
489 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
490 NUM_BANKS(ADDR_SURF_2_BANK));
491 break;
492 case 8:
493 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
494 break;
495 case 9:
496 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16));
499 break;
500 case 10:
501 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
502 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
503 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
505 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
508 NUM_BANKS(ADDR_SURF_16_BANK));
509 break;
510 case 11:
511 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
512 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
518 NUM_BANKS(ADDR_SURF_16_BANK));
519 break;
520 case 12:
521 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
522 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
523 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
525 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
528 NUM_BANKS(ADDR_SURF_16_BANK));
529 break;
530 case 13:
531 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16));
534 break;
535 case 14:
536 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
537 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
538 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
543 NUM_BANKS(ADDR_SURF_16_BANK));
544 break;
545 case 15:
546 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
547 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
548 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
553 NUM_BANKS(ADDR_SURF_16_BANK));
554 break;
555 case 16:
556 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
557 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
558 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
559 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
563 NUM_BANKS(ADDR_SURF_16_BANK));
564 break;
565 case 17:
566 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
572 NUM_BANKS(ADDR_SURF_16_BANK) |
573 TILE_SPLIT(split_equal_to_row_size));
574 break;
575 case 18:
576 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
577 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
578 PIPE_CONFIG(ADDR_SURF_P4_8x16));
579 break;
580 case 19:
581 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
582 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
583 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
584 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
587 NUM_BANKS(ADDR_SURF_16_BANK) |
588 TILE_SPLIT(split_equal_to_row_size));
589 break;
590 case 20:
591 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
592 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
593 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
597 NUM_BANKS(ADDR_SURF_16_BANK) |
598 TILE_SPLIT(split_equal_to_row_size));
599 break;
600 case 21:
601 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
603 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
608 NUM_BANKS(ADDR_SURF_8_BANK));
609 break;
610 case 22:
611 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
612 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
613 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
614 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
615 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
616 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
617 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
618 NUM_BANKS(ADDR_SURF_8_BANK));
619 break;
620 case 23:
621 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
623 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
628 NUM_BANKS(ADDR_SURF_4_BANK));
629 break;
630 case 24:
631 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
632 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
633 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
634 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
638 NUM_BANKS(ADDR_SURF_4_BANK));
639 break;
640 case 25:
641 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
645 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
648 NUM_BANKS(ADDR_SURF_2_BANK));
649 break;
650 case 26:
651 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
652 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
653 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
655 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
658 NUM_BANKS(ADDR_SURF_2_BANK));
659 break;
660 case 27:
661 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
662 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
663 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
668 NUM_BANKS(ADDR_SURF_2_BANK));
669 break;
670 case 28:
671 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
672 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
673 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
674 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
678 NUM_BANKS(ADDR_SURF_2_BANK));
679 break;
680 case 29:
681 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
688 NUM_BANKS(ADDR_SURF_2_BANK));
689 break;
690 case 30:
691 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
692 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
693 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
694 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
695 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
696 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
697 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
698 NUM_BANKS(ADDR_SURF_2_BANK));
699 break;
700 default:
701 continue;
702 }
703 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
704 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
705 }
706 } else if (adev->asic_type == CHIP_OLAND ||
25069e06 707 adev->asic_type == CHIP_HAINAN) {
2cd46ad2
KW		 708 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
709 switch (reg_offset) {
710 case 0:
f8d9422e
FC		 711 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
712 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
713 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2cd46ad2
KW		 715 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
716 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 717 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
718 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 719 break;
45682886 720 case 1:
f8d9422e
FC		 721 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2cd46ad2
KW		 725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
728 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2
KW		 729 break;
730 case 2:
f8d9422e
FC		 731 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
732 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
733 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 734 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 735 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
736 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 737 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
738 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 739 break;
45682886 740 case 3:
f8d9422e
FC		 741 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
742 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
743 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 744 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
746 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
747 NUM_BANKS(ADDR_SURF_8_BANK) |
748 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 749 break;
45682886 750 case 4:
f8d9422e
FC		 751 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
752 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
753 PIPE_CONFIG(ADDR_SURF_P2));
2cd46ad2 754 break;
45682886 755 case 5:
f8d9422e
FC		 756 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
757 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
758 PIPE_CONFIG(ADDR_SURF_P2) |
759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2 760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
763 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 764 break;
45682886 765 case 6:
f8d9422e
FC		 766 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
767 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
768 PIPE_CONFIG(ADDR_SURF_P2) |
769 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2 770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
773 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 774 break;
45682886 775 case 7:
f8d9422e
FC		 776 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
778 PIPE_CONFIG(ADDR_SURF_P2) |
779 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2cd46ad2 780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
f8d9422e
FC		 781 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
782 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
783 NUM_BANKS(ADDR_SURF_4_BANK));
2cd46ad2 784 break;
45682886 785 case 8:
f8d9422e 786 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
2cd46ad2 787 break;
45682886 788 case 9:
f8d9422e
FC		 789 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
790 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
791 PIPE_CONFIG(ADDR_SURF_P2));
2cd46ad2 792 break;
45682886 793 case 10:
f8d9422e
FC		 794 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
795 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
796 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 797 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
801 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 802 break;
45682886 803 case 11:
f8d9422e
FC		 804 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
805 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
806 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 807 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 808 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
f8d9422e
FC		 810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
811 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 812 break;
45682886 813 case 12:
f8d9422e
FC		 814 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
815 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
816 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 817 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 818 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
821 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 822 break;
45682886 823 case 13:
f8d9422e
FC		 824 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
825 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
826 PIPE_CONFIG(ADDR_SURF_P2));
2cd46ad2 827 break;
45682886 828 case 14:
f8d9422e
FC		 829 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
830 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
831 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 832 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
836 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 837 break;
45682886 838 case 15:
f8d9422e
FC		 839 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
840 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
841 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 842 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 843 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
f8d9422e
FC		 845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
846 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 847 break;
45682886 848 case 16:
f8d9422e
FC		 849 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
850 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
851 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
856 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 857 break;
45682886 858 case 17:
f8d9422e
FC		 859 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2) |
862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2cd46ad2 865 NUM_BANKS(ADDR_SURF_16_BANK) |
f8d9422e
FC		 866 TILE_SPLIT(split_equal_to_row_size));
867 break;
868 case 18:
869 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
870 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
871 PIPE_CONFIG(ADDR_SURF_P2));
872 break;
873 case 19:
874 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
875 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
876 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2
KW		 877 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
878 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 879 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
880 NUM_BANKS(ADDR_SURF_16_BANK) |
881 TILE_SPLIT(split_equal_to_row_size));
882 break;
883 case 20:
884 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
885 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
886 PIPE_CONFIG(ADDR_SURF_P2) |
887 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
888 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
889 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
890 NUM_BANKS(ADDR_SURF_16_BANK) |
891 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 892 break;
45682886 893 case 21:
f8d9422e
FC		 894 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
895 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
896 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
f8d9422e
FC		 900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
901 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 902 break;
45682886 903 case 22:
f8d9422e
FC		 904 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
905 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
906 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 907 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
f8d9422e
FC		 908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
911 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 912 break;
45682886 913 case 23:
f8d9422e
FC		 914 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
915 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
f8d9422e
FC		 920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
921 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 922 break;
45682886 923 case 24:
f8d9422e
FC		 924 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
931 NUM_BANKS(ADDR_SURF_8_BANK));
2cd46ad2 932 break;
45682886 933 case 25:
f8d9422e
FC		 934 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
936 PIPE_CONFIG(ADDR_SURF_P2) |
937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
941 NUM_BANKS(ADDR_SURF_4_BANK));
942 break;
943 case 26:
944 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
945 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
946 PIPE_CONFIG(ADDR_SURF_P2) |
947 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
951 NUM_BANKS(ADDR_SURF_4_BANK));
952 break;
953 case 27:
954 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
955 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
956 PIPE_CONFIG(ADDR_SURF_P2) |
2cd46ad2 957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
f8d9422e
FC		 958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
961 NUM_BANKS(ADDR_SURF_4_BANK));
962 break;
963 case 28:
964 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
965 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
966 PIPE_CONFIG(ADDR_SURF_P2) |
967 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
968 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
971 NUM_BANKS(ADDR_SURF_4_BANK));
972 break;
973 case 29:
974 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
975 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
976 PIPE_CONFIG(ADDR_SURF_P2) |
977 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
981 NUM_BANKS(ADDR_SURF_4_BANK));
982 break;
983 case 30:
984 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2cd46ad2
KW		 988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
f8d9422e
FC		 990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_4_BANK));
2cd46ad2
KW		 992 break;
993 default:
f8d9422e 994 continue;
2cd46ad2
KW		 995 }
996 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
25069e06 997 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2cd46ad2
KW		 998 }
999 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1000 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1001 switch (reg_offset) {
7c0a705e
FC		 1002 case 0:
1003 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1004 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1005 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2cd46ad2
KW		 1007 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1008 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1009 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1010 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1011 break;
7c0a705e
FC		 1012 case 1:
1013 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1014 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2cd46ad2
KW		 1017 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1018 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1019 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1020 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1021 break;
7c0a705e
FC		 1022 case 2:
1023 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1024 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1025 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1030 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1031 break;
7c0a705e
FC		 1032 case 3:
1033 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1035 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2cd46ad2
KW		 1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK) |
1040 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 1041 break;
7c0a705e
FC		 1042 case 4:
1043 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1044 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1045 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
2cd46ad2 1046 break;
7c0a705e
FC		 1047 case 5:
1048 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1049 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1050 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e 1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2 1052 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1053 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1054 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1055 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1056 break;
7c0a705e
FC		 1057 case 6:
1058 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1060 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1065 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1066 break;
7c0a705e
FC		 1067 case 7:
1068 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2cd46ad2
KW		 1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1075 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1076 break;
7c0a705e
FC		 1077 case 8:
1078 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
2cd46ad2 1079 break;
7c0a705e
FC		 1080 case 9:
1081 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1082 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
2cd46ad2 1084 break;
7c0a705e
FC		 1085 case 10:
1086 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1093 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1094 break;
7c0a705e
FC		 1095 case 11:
1096 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1097 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1098 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1100 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
7c0a705e
FC		 1102 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1103 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1104 break;
7c0a705e
FC		 1105 case 12:
1106 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1107 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1108 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1109 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 1110 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
7c0a705e
FC		 1112 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1113 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1114 break;
7c0a705e
FC		 1115 case 13:
1116 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1117 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1118 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
2cd46ad2 1119 break;
7c0a705e
FC		 1120 case 14:
1121 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1128 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1129 break;
7c0a705e
FC		 1130 case 15:
1131 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
7c0a705e
FC		 1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1139 break;
7c0a705e
FC		 1140 case 16:
1141 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2
KW		 1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
7c0a705e
FC		 1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1148 NUM_BANKS(ADDR_SURF_16_BANK));
2cd46ad2 1149 break;
7c0a705e
FC		 1150 case 17:
1151 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1152 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2 1153 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e
FC		 1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2cd46ad2 1157 NUM_BANKS(ADDR_SURF_16_BANK) |
7c0a705e
FC		 1158 TILE_SPLIT(split_equal_to_row_size));
1159 break;
1160 case 18:
1161 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1162 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1163 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
1164 break;
1165 case 19:
1166 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2cd46ad2
KW		 1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
7c0a705e
FC		 1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 1174 break;
7c0a705e
FC		 1175 case 20:
1176 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1177 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2cd46ad2 1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
7c0a705e
FC		 1179 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2cd46ad2 1182 NUM_BANKS(ADDR_SURF_16_BANK) |
7c0a705e 1183 TILE_SPLIT(split_equal_to_row_size));
2cd46ad2 1184 break;
7c0a705e
FC		 1185 case 21:
1186 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1187 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1188 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1189 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1190 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1193 NUM_BANKS(ADDR_SURF_4_BANK));
1194 break;
1195 case 22:
1196 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1197 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1198 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1199 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2
KW		 1200 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
7c0a705e
FC		 1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1203 NUM_BANKS(ADDR_SURF_4_BANK));
2cd46ad2 1204 break;
7c0a705e
FC		 1205 case 23:
1206 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1207 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1208 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1209 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2cd46ad2 1210 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1212 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1213 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1214 break;
7c0a705e
FC		 1215 case 24:
1216 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2cd46ad2
KW		 1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2cd46ad2 1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1224 break;
7c0a705e
FC		 1225 case 25:
1226 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1227 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2cd46ad2 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2cd46ad2 1230 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
7c0a705e
FC		 1231 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1232 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1233 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1234 break;
7c0a705e
FC		 1235 case 26:
1236 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1237 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1238 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1239 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1240 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1243 NUM_BANKS(ADDR_SURF_2_BANK));
1244 break;
1245 case 27:
1246 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1247 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1248 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1250 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1253 NUM_BANKS(ADDR_SURF_2_BANK));
2cd46ad2 1254 break;
7c0a705e
FC		 1255 case 28:
1256 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK));
1264 break;
1265 case 29:
1266 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1267 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1270 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1273 NUM_BANKS(ADDR_SURF_2_BANK));
1274 break;
1275 case 30:
1276 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1277 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1278 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1279 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1280 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1281 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1282 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1283 NUM_BANKS(ADDR_SURF_2_BANK));
1284 break;
1285 default:
1286 continue;
2cd46ad2
KW		 1287 }
1288 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
25069e06 1289 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2cd46ad2
KW		 1290 }
1291 } else{
1292
1293 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1294 }
1295
1296}
1297
1298static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1299 u32 sh_num, u32 instance)
1300{
1301 u32 data;
1302
1303 if (instance == 0xffffffff)
25069e06 1304 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2cd46ad2 1305 else
25069e06 1306 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2cd46ad2
KW		 1307
1308 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
25069e06
TSD		 1309 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1310 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
2cd46ad2 1311 else if (se_num == 0xffffffff)
25069e06
TSD		 1312 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1313 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
2cd46ad2 1314 else if (sh_num == 0xffffffff)
25069e06
TSD		 1315 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1316 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
2cd46ad2 1317 else
25069e06
TSD		 1318 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1320 WREG32(mmGRBM_GFX_INDEX, data);
2cd46ad2
KW		 1321}
1322
1323static u32 gfx_v6_0_create_bitmask(u32 bit_width)
1324{
142333db 1325 return (u32)(((u64)1 << bit_width) - 1);
2cd46ad2
KW		 1326}
1327
1328static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
1329 u32 max_rb_num_per_se,
1330 u32 sh_per_se)
1331{
1332 u32 data, mask;
1333
25069e06
TSD		 1334 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1335 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1336 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2cd46ad2 1337
25069e06 1338 data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2cd46ad2
KW		 1339
1340 mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1341
1342 return data & mask;
1343}
1344
865ab832
HR		 1345static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1346{
1347 switch (adev->asic_type) {
1348 case CHIP_TAHITI:
1349 case CHIP_PITCAIRN:
25069e06
TSD		 1350 *rconf |=
1351 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1352 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1353 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1354 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1355 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1356 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1357 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
865ab832
HR		 1358 break;
1359 case CHIP_VERDE:
25069e06
TSD		 1360 *rconf |=
1361 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1362 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1363 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
865ab832
HR		 1364 break;
1365 case CHIP_OLAND:
25069e06 1366 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
865ab832
HR		 1367 break;
1368 case CHIP_HAINAN:
1369 *rconf |= 0x0;
1370 break;
1371 default:
1372 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1373 break;
1374 }
1375}
1376
1377static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1378 u32 raster_config, unsigned rb_mask,
1379 unsigned num_rb)
1380{
1381 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1382 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1383 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1384 unsigned rb_per_se = num_rb / num_se;
1385 unsigned se_mask[4];
1386 unsigned se;
1387
1388 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1389 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1390 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1391 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1392
1393 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1394 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1395 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1396
1397 for (se = 0; se < num_se; se++) {
1398 unsigned raster_config_se = raster_config;
1399 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1400 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1401 int idx = (se / 2) * 2;
1402
1403 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
25069e06 1404 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
865ab832
HR		 1405
1406 if (!se_mask[idx]) {
25069e06 1407 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
865ab832 1408 } else {
25069e06 1409 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
865ab832
HR		 1410 }
1411 }
1412
1413 pkr0_mask &= rb_mask;
1414 pkr1_mask &= rb_mask;
1415 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
25069e06 1416 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
865ab832
HR		 1417
1418 if (!pkr0_mask) {
25069e06 1419 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
865ab832 1420 } else {
25069e06 1421 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
865ab832
HR		 1422 }
1423 }
1424
1425 if (rb_per_se >= 2) {
1426 unsigned rb0_mask = 1 << (se * rb_per_se);
1427 unsigned rb1_mask = rb0_mask << 1;
1428
1429 rb0_mask &= rb_mask;
1430 rb1_mask &= rb_mask;
1431 if (!rb0_mask || !rb1_mask) {
25069e06 1432 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
865ab832
HR		 1433
1434 if (!rb0_mask) {
1435 raster_config_se |=
25069e06 1436 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
865ab832
HR		 1437 } else {
1438 raster_config_se |=
25069e06 1439 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
865ab832
HR		 1440 }
1441 }
1442
1443 if (rb_per_se > 2) {
1444 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1445 rb1_mask = rb0_mask << 1;
1446 rb0_mask &= rb_mask;
1447 rb1_mask &= rb_mask;
1448 if (!rb0_mask || !rb1_mask) {
25069e06 1449 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
865ab832
HR		 1450
1451 if (!rb0_mask) {
1452 raster_config_se |=
25069e06 1453 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
865ab832
HR		 1454 } else {
1455 raster_config_se |=
25069e06 1456 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
865ab832
HR		 1457 }
1458 }
1459 }
1460 }
1461
1462 /* GRBM_GFX_INDEX has a different offset on SI */
1463 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
25069e06 1464 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
865ab832
HR		 1465 }
1466
1467 /* GRBM_GFX_INDEX has a different offset on SI */
1468 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1469}
1470
2cd46ad2
KW		 1471static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
1472 u32 se_num, u32 sh_per_se,
1473 u32 max_rb_num_per_se)
1474{
1475 int i, j;
1476 u32 data, mask;
1477 u32 disabled_rbs = 0;
1478 u32 enabled_rbs = 0;
865ab832 1479 unsigned num_rb_pipes;
2cd46ad2 1480
deca1d1f 1481 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1482 for (i = 0; i < se_num; i++) {
1483 for (j = 0; j < sh_per_se; j++) {
1484 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1485 data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
25069e06 1486 disabled_rbs |= data << ((i * sh_per_se + j) * 2);
2cd46ad2
KW		 1487 }
1488 }
1489 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1490 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1491
1492 mask = 1;
1493 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1494 if (!(disabled_rbs & mask))
1495 enabled_rbs |= mask;
1496 mask <<= 1;
1497 }
1498
1499 adev->gfx.config.backend_enable_mask = enabled_rbs;
1500 adev->gfx.config.num_rbs = hweight32(enabled_rbs);
1501
865ab832
HR		 1502 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1503 adev->gfx.config.max_shader_engines, 16);
1504
deca1d1f 1505 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1506 for (i = 0; i < se_num; i++) {
1507 gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1508 data = 0;
1509 for (j = 0; j < sh_per_se; j++) {
1510 switch (enabled_rbs & 3) {
1511 case 1:
1512 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1513 break;
1514 case 2:
1515 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1516 break;
1517 case 3:
1518 default:
1519 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1520 break;
1521 }
1522 enabled_rbs >>= 2;
1523 }
865ab832
HR		 1524 gfx_v6_0_raster_config(adev, &data);
1525
1526 if (!adev->gfx.config.backend_enable_mask ||
1527 adev->gfx.config.num_rbs >= num_rb_pipes)
25069e06 1528 WREG32(mmPA_SC_RASTER_CONFIG, data);
865ab832
HR		 1529 else
1530 gfx_v6_0_write_harvested_raster_configs(adev, data,
1531 adev->gfx.config.backend_enable_mask,
1532 num_rb_pipes);
2cd46ad2
KW		 1533 }
1534 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1535 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1536}
1537/*
1538static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
1539{
1540}
1541*/
1542
1543static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh)
1544{
1545 u32 data, mask;
1546
25069e06
TSD		 1547 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
1548 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1549 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
2cd46ad2 1550
25069e06 1551 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
2cd46ad2
KW		 1552
1553 mask = gfx_v6_0_create_bitmask(cu_per_sh);
1554
1555 return ~data & mask;
1556}
1557
1558
1559static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
1560 u32 se_num, u32 sh_per_se,
1561 u32 cu_per_sh)
1562{
1563 int i, j, k;
1564 u32 data, mask;
1565 u32 active_cu = 0;
1566
deca1d1f 1567 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1568 for (i = 0; i < se_num; i++) {
1569 for (j = 0; j < sh_per_se; j++) {
1570 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
25069e06 1571 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
2cd46ad2
KW		 1572 active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh);
1573
1574 mask = 1;
1575 for (k = 0; k < 16; k++) {
1576 mask <<= k;
1577 if (active_cu & mask) {
1578 data &= ~mask;
25069e06 1579 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
2cd46ad2
KW		 1580 break;
1581 }
1582 }
1583 }
1584 }
1585 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 1586 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 1587}
1588
1589static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1590{
1591 u32 gb_addr_config = 0;
1592 u32 mc_shared_chmap, mc_arb_ramcfg;
1593 u32 sx_debug_1;
1594 u32 hdp_host_path_cntl;
1595 u32 tmp;
1596
1597 switch (adev->asic_type) {
1598 case CHIP_TAHITI:
1599 adev->gfx.config.max_shader_engines = 2;
1600 adev->gfx.config.max_tile_pipes = 12;
1601 adev->gfx.config.max_cu_per_sh = 8;
1602 adev->gfx.config.max_sh_per_se = 2;
1603 adev->gfx.config.max_backends_per_se = 4;
1604 adev->gfx.config.max_texture_channel_caches = 12;
1605 adev->gfx.config.max_gprs = 256;
1606 adev->gfx.config.max_gs_threads = 32;
1607 adev->gfx.config.max_hw_contexts = 8;
1608
1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1613 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1614 break;
1615 case CHIP_PITCAIRN:
1616 adev->gfx.config.max_shader_engines = 2;
1617 adev->gfx.config.max_tile_pipes = 8;
1618 adev->gfx.config.max_cu_per_sh = 5;
1619 adev->gfx.config.max_sh_per_se = 2;
1620 adev->gfx.config.max_backends_per_se = 4;
1621 adev->gfx.config.max_texture_channel_caches = 8;
1622 adev->gfx.config.max_gprs = 256;
1623 adev->gfx.config.max_gs_threads = 32;
1624 adev->gfx.config.max_hw_contexts = 8;
1625
1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1630 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1631 break;
2cd46ad2
KW		 1632 case CHIP_VERDE:
1633 adev->gfx.config.max_shader_engines = 1;
1634 adev->gfx.config.max_tile_pipes = 4;
1635 adev->gfx.config.max_cu_per_sh = 5;
1636 adev->gfx.config.max_sh_per_se = 2;
1637 adev->gfx.config.max_backends_per_se = 4;
1638 adev->gfx.config.max_texture_channel_caches = 4;
1639 adev->gfx.config.max_gprs = 256;
1640 adev->gfx.config.max_gs_threads = 32;
1641 adev->gfx.config.max_hw_contexts = 8;
1642
1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1647 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1648 break;
1649 case CHIP_OLAND:
1650 adev->gfx.config.max_shader_engines = 1;
1651 adev->gfx.config.max_tile_pipes = 4;
1652 adev->gfx.config.max_cu_per_sh = 6;
1653 adev->gfx.config.max_sh_per_se = 1;
1654 adev->gfx.config.max_backends_per_se = 2;
1655 adev->gfx.config.max_texture_channel_caches = 4;
1656 adev->gfx.config.max_gprs = 256;
1657 adev->gfx.config.max_gs_threads = 16;
1658 adev->gfx.config.max_hw_contexts = 8;
1659
1660 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1661 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1662 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1663 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1664 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1665 break;
1666 case CHIP_HAINAN:
1667 adev->gfx.config.max_shader_engines = 1;
1668 adev->gfx.config.max_tile_pipes = 4;
1669 adev->gfx.config.max_cu_per_sh = 5;
1670 adev->gfx.config.max_sh_per_se = 1;
1671 adev->gfx.config.max_backends_per_se = 1;
1672 adev->gfx.config.max_texture_channel_caches = 2;
1673 adev->gfx.config.max_gprs = 256;
1674 adev->gfx.config.max_gs_threads = 16;
1675 adev->gfx.config.max_hw_contexts = 8;
1676
1677 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1678 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1679 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1680 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1681 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1682 break;
1683 default:
1684 BUG();
1685 break;
1686 }
1687
25069e06
TSD		 1688 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1689 WREG32(mmSRBM_INT_CNTL, 1);
1690 WREG32(mmSRBM_INT_ACK, 1);
2cd46ad2 1691
25069e06 1692 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
2cd46ad2 1693
25069e06
TSD		 1694 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1695 mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2cd46ad2
KW		 1696
1697 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1698 adev->gfx.config.mem_max_burst_length_bytes = 256;
25069e06 1699 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
2cd46ad2
KW		 1700 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1701 if (adev->gfx.config.mem_row_size_in_kb > 4)
1702 adev->gfx.config.mem_row_size_in_kb = 4;
1703 adev->gfx.config.shader_engine_tile_size = 32;
1704 adev->gfx.config.num_gpus = 1;
1705 adev->gfx.config.multi_gpu_tile_size = 64;
1706
25069e06 1707 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
2cd46ad2
KW		 1708 switch (adev->gfx.config.mem_row_size_in_kb) {
1709 case 1:
1710 default:
25069e06 1711 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1712 break;
1713 case 2:
25069e06 1714 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1715 break;
1716 case 4:
25069e06 1717 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
2cd46ad2
KW		 1718 break;
1719 }
1720 adev->gfx.config.gb_addr_config = gb_addr_config;
1721
25069e06
TSD		 1722 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1723 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1724 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1725 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1726 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1727 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1728
2cd46ad2
KW		 1729#if 0
1730 if (adev->has_uvd) {
25069e06
TSD		 1731 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1732 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1733 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2cd46ad2
KW		 1734 }
1735#endif
1736 gfx_v6_0_tiling_mode_table_init(adev);
1737
1738 gfx_v6_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
1739 adev->gfx.config.max_sh_per_se,
1740 adev->gfx.config.max_backends_per_se);
1741
1742 gfx_v6_0_setup_spi(adev, adev->gfx.config.max_shader_engines,
1743 adev->gfx.config.max_sh_per_se,
1744 adev->gfx.config.max_cu_per_sh);
1745
1746 gfx_v6_0_get_cu_info(adev);
1747
25069e06
TSD		 1748 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1749 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1750 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1751 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
2cd46ad2 1752
25069e06
TSD		 1753 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1754 WREG32(mmSX_DEBUG_1, sx_debug_1);
2cd46ad2 1755
25069e06 1756 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
2cd46ad2 1757
25069e06
TSD		 1758 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1759 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1760 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1761 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2cd46ad2 1762
25069e06
TSD		 1763 WREG32(mmVGT_NUM_INSTANCES, 1);
1764 WREG32(mmCP_PERFMON_CNTL, 0);
1765 WREG32(mmSQ_CONFIG, 0);
1766 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1767 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2cd46ad2 1768
25069e06
TSD		 1769 WREG32(mmVGT_CACHE_INVALIDATION,
1770 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1771 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2cd46ad2 1772
25069e06
TSD		 1773 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1774 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2cd46ad2 1775
25069e06
TSD		 1776 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1777 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1778 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1779 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1780 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1781 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1782 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1783 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
2cd46ad2 1784
25069e06
TSD		 1785 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1786 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2cd46ad2 1787
25069e06
TSD		 1788 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1789 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2cd46ad2
KW		 1790
1791 udelay(50);
2cd46ad2
KW		 1792}
1793
1794
1795static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1796{
1797 int i;
1798
1799 adev->gfx.scratch.num_reg = 7;
25069e06 1800 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2cd46ad2
KW		 1801 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1802 adev->gfx.scratch.free[i] = true;
1803 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1804 }
1805}
1806
1807static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1808{
1809 struct amdgpu_device *adev = ring->adev;
1810 uint32_t scratch;
1811 uint32_t tmp = 0;
1812 unsigned i;
1813 int r;
1814
1815 r = amdgpu_gfx_scratch_get(adev, &scratch);
1816 if (r) {
1817 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1818 return r;
1819 }
1820 WREG32(scratch, 0xCAFEDEAD);
1821
1822 r = amdgpu_ring_alloc(ring, 3);
1823 if (r) {
1824 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1825 amdgpu_gfx_scratch_free(adev, scratch);
1826 return r;
1827 }
1828 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1829 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1830 amdgpu_ring_write(ring, 0xDEADBEEF);
1831 amdgpu_ring_commit(ring);
1832
1833 for (i = 0; i < adev->usec_timeout; i++) {
1834 tmp = RREG32(scratch);
1835 if (tmp == 0xDEADBEEF)
1836 break;
1837 DRM_UDELAY(1);
1838 }
1839 if (i < adev->usec_timeout) {
1840 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1841 } else {
1842 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1843 ring->idx, scratch, tmp);
1844 r = -EINVAL;
1845 }
1846 amdgpu_gfx_scratch_free(adev, scratch);
1847 return r;
1848}
1849
1850static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1851{
1852 /* flush hdp cache */
1853 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1854 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1855 WRITE_DATA_DST_SEL(0)));
25069e06 1856 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
2cd46ad2
KW		 1857 amdgpu_ring_write(ring, 0);
1858 amdgpu_ring_write(ring, 0x1);
1859}
1860
45682886
ML		 1861static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1862{
1863 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1864 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1865 EVENT_INDEX(0));
1866}
1867
2cd46ad2
KW		 1868/**
1869 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1870 *
1871 * @adev: amdgpu_device pointer
1872 * @ridx: amdgpu ring index
1873 *
1874 * Emits an hdp invalidate on the cp.
1875 */
1876static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1877{
1878 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1879 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
1880 WRITE_DATA_DST_SEL(0)));
25069e06 1881 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2cd46ad2
KW		 1882 amdgpu_ring_write(ring, 0);
1883 amdgpu_ring_write(ring, 0x1);
1884}
1885
668f52c3
AD		 1886static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1887 u64 seq, unsigned flags)
2cd46ad2
KW		 1888{
1889 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1890 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1891 /* flush read cache over gart */
1892 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
25069e06 1893 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
2cd46ad2
KW		 1894 amdgpu_ring_write(ring, 0);
1895 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1896 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1897 PACKET3_TC_ACTION_ENA |
1898 PACKET3_SH_KCACHE_ACTION_ENA |
1899 PACKET3_SH_ICACHE_ACTION_ENA);
1900 amdgpu_ring_write(ring, 0xFFFFFFFF);
1901 amdgpu_ring_write(ring, 0);
1902 amdgpu_ring_write(ring, 10); /* poll interval */
1903 /* EVENT_WRITE_EOP - flush caches, send int */
1904 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1905 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1906 amdgpu_ring_write(ring, addr & 0xfffffffc);
1907 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
25069e06
TSD		 1908 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1909 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
2cd46ad2
KW		 1910 amdgpu_ring_write(ring, lower_32_bits(seq));
1911 amdgpu_ring_write(ring, upper_32_bits(seq));
1912}
1913
668f52c3
AD		 1914static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1915 struct amdgpu_ib *ib,
1916 unsigned vm_id, bool ctx_switch)
2cd46ad2
KW		 1917{
1918 u32 header, control = 0;
1919
1920 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1921 if (ctx_switch) {
1922 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1923 amdgpu_ring_write(ring, 0);
1924 }
1925
1926 if (ib->flags & AMDGPU_IB_FLAG_CE)
1927 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1928 else
1929 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1930
1931 control |= ib->length_dw | (vm_id << 24);
1932
1933 amdgpu_ring_write(ring, header);
1934 amdgpu_ring_write(ring,
1935#ifdef __BIG_ENDIAN
1936 (2 << 0) |
1937#endif
1938 (ib->gpu_addr & 0xFFFFFFFC));
1939 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1940 amdgpu_ring_write(ring, control);
1941}
1942
2cd46ad2
KW		 1943/**
1944 * gfx_v6_0_ring_test_ib - basic ring IB test
1945 *
1946 * @ring: amdgpu_ring structure holding ring information
1947 *
1948 * Allocate an IB and execute it on the gfx ring (SI).
1949 * Provides a basic gfx ring test to verify that IBs are working.
1950 * Returns 0 on success, error on failure.
1951 */
1952static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1953{
1954 struct amdgpu_device *adev = ring->adev;
1955 struct amdgpu_ib ib;
f54d1867 1956 struct dma_fence *f = NULL;
2cd46ad2
KW		 1957 uint32_t scratch;
1958 uint32_t tmp = 0;
1959 long r;
1960
1961 r = amdgpu_gfx_scratch_get(adev, &scratch);
1962 if (r) {
1963 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1964 return r;
1965 }
1966 WREG32(scratch, 0xCAFEDEAD);
1967 memset(&ib, 0, sizeof(ib));
1968 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1969 if (r) {
1970 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1971 goto err1;
1972 }
1973 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1974 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1975 ib.ptr[2] = 0xDEADBEEF;
1976 ib.length_dw = 3;
1977
1978 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
1979 if (r)
1980 goto err2;
1981
f54d1867 1982 r = dma_fence_wait_timeout(f, false, timeout);
2cd46ad2
KW		 1983 if (r == 0) {
1984 DRM_ERROR("amdgpu: IB test timed out\n");
1985 r = -ETIMEDOUT;
1986 goto err2;
1987 } else if (r < 0) {
1988 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1989 goto err2;
1990 }
1991 tmp = RREG32(scratch);
1992 if (tmp == 0xDEADBEEF) {
1993 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
1994 r = 0;
1995 } else {
1996 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1997 scratch, tmp);
1998 r = -EINVAL;
1999 }
2000
2001err2:
2002 amdgpu_ib_free(adev, &ib, NULL);
f54d1867 2003 dma_fence_put(f);
2cd46ad2
KW		 2004err1:
2005 amdgpu_gfx_scratch_free(adev, scratch);
2006 return r;
2007}
2008
2009static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2010{
2011 int i;
25069e06
TSD		 2012 if (enable) {
2013 WREG32(mmCP_ME_CNTL, 0);
2014 } else {
2015 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
2016 CP_ME_CNTL__PFP_HALT_MASK |
2017 CP_ME_CNTL__CE_HALT_MASK));
2018 WREG32(mmSCRATCH_UMSK, 0);
2cd46ad2
KW		 2019 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2020 adev->gfx.gfx_ring[i].ready = false;
2021 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2022 adev->gfx.compute_ring[i].ready = false;
2023 }
2024 udelay(50);
2025}
2026
2027static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2028{
2029 unsigned i;
2030 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2031 const struct gfx_firmware_header_v1_0 *ce_hdr;
2032 const struct gfx_firmware_header_v1_0 *me_hdr;
2033 const __le32 *fw_data;
2034 u32 fw_size;
2035
2036 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2037 return -EINVAL;
2038
2039 gfx_v6_0_cp_gfx_enable(adev, false);
2040 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2041 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2042 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2043
2044 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2045 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2046 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2047
2048 /* PFP */
2049 fw_data = (const __le32 *)
2050 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2051 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
25069e06 2052 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2cd46ad2 2053 for (i = 0; i < fw_size; i++)
25069e06
TSD		 2054 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2055 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2cd46ad2
KW		 2056
2057 /* CE */
2058 fw_data = (const __le32 *)
2059 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2060 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
25069e06 2061 WREG32(mmCP_CE_UCODE_ADDR, 0);
2cd46ad2 2062 for (i = 0; i < fw_size; i++)
25069e06
TSD		 2063 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2064 WREG32(mmCP_CE_UCODE_ADDR, 0);
2cd46ad2
KW		 2065
2066 /* ME */
2067 fw_data = (const __be32 *)
2068 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2069 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
25069e06 2070 WREG32(mmCP_ME_RAM_WADDR, 0);
2cd46ad2 2071 for (i = 0; i < fw_size; i++)
25069e06
TSD		 2072 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2073 WREG32(mmCP_ME_RAM_WADDR, 0);
2cd46ad2 2074
25069e06
TSD		 2075 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2076 WREG32(mmCP_CE_UCODE_ADDR, 0);
2077 WREG32(mmCP_ME_RAM_WADDR, 0);
2078 WREG32(mmCP_ME_RAM_RADDR, 0);
2cd46ad2
KW		 2079 return 0;
2080}
2081
2082static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2083{
2084 const struct cs_section_def *sect = NULL;
2085 const struct cs_extent_def *ext = NULL;
2086 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2087 int r, i;
2088
2089 r = amdgpu_ring_alloc(ring, 7 + 4);
2090 if (r) {
2091 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2092 return r;
2093 }
2094 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2095 amdgpu_ring_write(ring, 0x1);
2096 amdgpu_ring_write(ring, 0x0);
2097 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2098 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2099 amdgpu_ring_write(ring, 0);
2100 amdgpu_ring_write(ring, 0);
2101
2102 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2103 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2104 amdgpu_ring_write(ring, 0xc000);
2105 amdgpu_ring_write(ring, 0xe000);
2106 amdgpu_ring_commit(ring);
2107
2108 gfx_v6_0_cp_gfx_enable(adev, true);
2109
2110 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2111 if (r) {
2112 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2113 return r;
2114 }
2115
2116 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2117 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2118
2119 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2120 for (ext = sect->section; ext->extent != NULL; ++ext) {
2121 if (sect->id == SECT_CONTEXT) {
2122 amdgpu_ring_write(ring,
2123 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2124 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2125 for (i = 0; i < ext->reg_count; i++)
2126 amdgpu_ring_write(ring, ext->extent[i]);
2127 }
2128 }
2129 }
2130
2131 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2132 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2133
2134 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2135 amdgpu_ring_write(ring, 0);
2136
2137 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2138 amdgpu_ring_write(ring, 0x00000316);
2139 amdgpu_ring_write(ring, 0x0000000e);
2140 amdgpu_ring_write(ring, 0x00000010);
2141
2142 amdgpu_ring_commit(ring);
2143
2144 return 0;
2145}
2146
2147static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2148{
2149 struct amdgpu_ring *ring;
2150 u32 tmp;
2151 u32 rb_bufsz;
2152 int r;
2153 u64 rptr_addr;
2154
25069e06
TSD		 2155 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2156 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2cd46ad2
KW		 2157
2158 /* Set the write pointer delay */
25069e06 2159 WREG32(mmCP_RB_WPTR_DELAY, 0);
2cd46ad2 2160
25069e06
TSD		 2161 WREG32(mmCP_DEBUG, 0);
2162 WREG32(mmSCRATCH_ADDR, 0);
2cd46ad2
KW		 2163
2164 /* ring 0 - compute and gfx */
2165 /* Set ring buffer size */
2166 ring = &adev->gfx.gfx_ring[0];
2167 rb_bufsz = order_base_2(ring->ring_size / 8);
2168 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2169
2170#ifdef __BIG_ENDIAN
2171 tmp |= BUF_SWAP_32BIT;
2172#endif
25069e06 2173 WREG32(mmCP_RB0_CNTL, tmp);
2cd46ad2
KW		 2174
2175 /* Initialize the ring buffer's read and write pointers */
25069e06 2176 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2177 ring->wptr = 0;
25069e06 2178 WREG32(mmCP_RB0_WPTR, ring->wptr);
2cd46ad2
KW		 2179
2180 /* set the wb address whether it's enabled or not */
2181 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2182 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2183 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2 2184
25069e06 2185 WREG32(mmSCRATCH_UMSK, 0);
2cd46ad2
KW		 2186
2187 mdelay(1);
25069e06 2188 WREG32(mmCP_RB0_CNTL, tmp);
2cd46ad2 2189
25069e06 2190 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2cd46ad2
KW		 2191
2192 /* start the rings */
2193 gfx_v6_0_cp_gfx_start(adev);
2194 ring->ready = true;
2195 r = amdgpu_ring_test_ring(ring);
2196 if (r) {
2197 ring->ready = false;
2198 return r;
2199 }
2200
2201 return 0;
2202}
2203
6f924e20 2204static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2cd46ad2 2205{
4aeacf0f 2206 return ring->adev->wb.wb[ring->rptr_offs];
2cd46ad2
KW		 2207}
2208
832c6ef7 2209static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2cd46ad2
KW		 2210{
2211 struct amdgpu_device *adev = ring->adev;
2cd46ad2 2212
832c6ef7 2213 if (ring == &adev->gfx.gfx_ring[0])
25069e06 2214 return RREG32(mmCP_RB0_WPTR);
832c6ef7 2215 else if (ring == &adev->gfx.compute_ring[0])
25069e06 2216 return RREG32(mmCP_RB1_WPTR);
832c6ef7 2217 else if (ring == &adev->gfx.compute_ring[1])
25069e06 2218 return RREG32(mmCP_RB2_WPTR);
832c6ef7
TSD		 2219 else
2220 BUG();
2cd46ad2
KW		 2221}
2222
2223static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2224{
2225 struct amdgpu_device *adev = ring->adev;
2226
25069e06
TSD		 2227 WREG32(mmCP_RB0_WPTR, ring->wptr);
2228 (void)RREG32(mmCP_RB0_WPTR);
2cd46ad2
KW		 2229}
2230
2cd46ad2
KW		 2231static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2232{
2233 struct amdgpu_device *adev = ring->adev;
2234
2235 if (ring == &adev->gfx.compute_ring[0]) {
25069e06
TSD		 2236 WREG32(mmCP_RB1_WPTR, ring->wptr);
2237 (void)RREG32(mmCP_RB1_WPTR);
2cd46ad2 2238 } else if (ring == &adev->gfx.compute_ring[1]) {
25069e06
TSD		 2239 WREG32(mmCP_RB2_WPTR, ring->wptr);
2240 (void)RREG32(mmCP_RB2_WPTR);
2cd46ad2
KW		 2241 } else {
2242 BUG();
2243 }
2244
2245}
2246
2cd46ad2
KW		 2247static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2248{
2249 struct amdgpu_ring *ring;
2250 u32 tmp;
2251 u32 rb_bufsz;
25069e06 2252 int i, r;
2cd46ad2
KW		 2253 u64 rptr_addr;
2254
2255 /* ring1 - compute only */
2256 /* Set ring buffer size */
2257
2258 ring = &adev->gfx.compute_ring[0];
2259 rb_bufsz = order_base_2(ring->ring_size / 8);
2260 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2261#ifdef __BIG_ENDIAN
2262 tmp |= BUF_SWAP_32BIT;
2263#endif
25069e06 2264 WREG32(mmCP_RB1_CNTL, tmp);
2cd46ad2 2265
25069e06 2266 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2267 ring->wptr = 0;
25069e06 2268 WREG32(mmCP_RB1_WPTR, ring->wptr);
2cd46ad2 2269
2cd46ad2 2270 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2271 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2272 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2
KW		 2273
2274 mdelay(1);
25069e06
TSD		 2275 WREG32(mmCP_RB1_CNTL, tmp);
2276 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2cd46ad2
KW		 2277
2278 ring = &adev->gfx.compute_ring[1];
2279 rb_bufsz = order_base_2(ring->ring_size / 8);
2280 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2281#ifdef __BIG_ENDIAN
2282 tmp |= BUF_SWAP_32BIT;
2283#endif
25069e06 2284 WREG32(mmCP_RB2_CNTL, tmp);
2cd46ad2 2285
25069e06 2286 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2cd46ad2 2287 ring->wptr = 0;
25069e06 2288 WREG32(mmCP_RB2_WPTR, ring->wptr);
2cd46ad2 2289 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
25069e06
TSD		 2290 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2291 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2cd46ad2
KW		 2292
2293 mdelay(1);
25069e06
TSD		 2294 WREG32(mmCP_RB2_CNTL, tmp);
2295 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2cd46ad2 2296
25069e06
TSD		 2297 adev->gfx.compute_ring[0].ready = false;
2298 adev->gfx.compute_ring[1].ready = false;
2cd46ad2 2299
25069e06
TSD		 2300 for (i = 0; i < 2; i++) {
2301 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2302 if (r)
2303 return r;
2304 adev->gfx.compute_ring[i].ready = true;
2cd46ad2
KW		 2305 }
2306
2307 return 0;
2308}
2309
2310static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2311{
2312 gfx_v6_0_cp_gfx_enable(adev, enable);
2313}
2314
2315static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2316{
4aeacf0f 2317 return gfx_v6_0_cp_gfx_load_microcode(adev);
2cd46ad2
KW		 2318}
2319
2320static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2321 bool enable)
45682886 2322{
25069e06 2323 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2
KW		 2324 u32 mask;
2325 int i;
2326
2327 if (enable)
25069e06
TSD		 2328 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2329 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2cd46ad2 2330 else
25069e06
TSD		 2331 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2332 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2333 WREG32(mmCP_INT_CNTL_RING0, tmp);
2cd46ad2
KW		 2334
2335 if (!enable) {
2336 /* read a gfx register */
25069e06 2337 tmp = RREG32(mmDB_DEPTH_INFO);
2cd46ad2
KW		 2338
2339 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2340 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2341 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2cd46ad2
KW		 2342 break;
2343 udelay(1);
2344 }
2345 }
2346}
2347
2348static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2349{
2350 int r;
2351
2352 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2353
2354 r = gfx_v6_0_cp_load_microcode(adev);
2355 if (r)
2356 return r;
2357
2358 r = gfx_v6_0_cp_gfx_resume(adev);
2359 if (r)
2360 return r;
2361 r = gfx_v6_0_cp_compute_resume(adev);
2362 if (r)
2363 return r;
2364
2365 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2366
2367 return 0;
2368}
2369
2370static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2371{
21cd942e 2372 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2cd46ad2
KW		 2373 uint32_t seq = ring->fence_drv.sync_seq;
2374 uint64_t addr = ring->fence_drv.gpu_addr;
2375
2376 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2377 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2378 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2379 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2380 amdgpu_ring_write(ring, addr & 0xfffffffc);
2381 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2382 amdgpu_ring_write(ring, seq);
2383 amdgpu_ring_write(ring, 0xffffffff);
2384 amdgpu_ring_write(ring, 4); /* poll interval */
2385
2386 if (usepfp) {
2387 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2389 amdgpu_ring_write(ring, 0);
2390 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2391 amdgpu_ring_write(ring, 0);
2392 }
2393}
2394
2395static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2396 unsigned vm_id, uint64_t pd_addr)
2397{
21cd942e 2398 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2cd46ad2
KW		 2399
2400 /* write new base address */
2401 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2402 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2403 WRITE_DATA_DST_SEL(0)));
2404 if (vm_id < 8) {
25069e06 2405 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
2cd46ad2 2406 } else {
25069e06 2407 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
2cd46ad2
KW		 2408 }
2409 amdgpu_ring_write(ring, 0);
2410 amdgpu_ring_write(ring, pd_addr >> 12);
2411
2412 /* bits 0-15 are the VM contexts0-15 */
2413 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2414 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
2415 WRITE_DATA_DST_SEL(0)));
25069e06 2416 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2cd46ad2
KW		 2417 amdgpu_ring_write(ring, 0);
2418 amdgpu_ring_write(ring, 1 << vm_id);
2419
2420 /* wait for the invalidate to complete */
2421 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2422 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2423 WAIT_REG_MEM_ENGINE(0))); /* me */
25069e06 2424 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2cd46ad2
KW		 2425 amdgpu_ring_write(ring, 0);
2426 amdgpu_ring_write(ring, 0); /* ref */
2427 amdgpu_ring_write(ring, 0); /* mask */
2428 amdgpu_ring_write(ring, 0x20); /* poll interval */
2429
2430 if (usepfp) {
2431 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2432 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2433 amdgpu_ring_write(ring, 0x0);
2434
2435 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2436 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2437 amdgpu_ring_write(ring, 0);
2438 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2439 amdgpu_ring_write(ring, 0);
2440 }
2441}
2442
2443
2444static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2445{
2446 int r;
2447
2448 if (adev->gfx.rlc.save_restore_obj) {
2449 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2450 if (unlikely(r != 0))
2451 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
2452 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
2453 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2454
2455 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
2456 adev->gfx.rlc.save_restore_obj = NULL;
2457 }
2458
2459 if (adev->gfx.rlc.clear_state_obj) {
2460 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2461 if (unlikely(r != 0))
2462 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
2463 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
2464 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2465
2466 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2467 adev->gfx.rlc.clear_state_obj = NULL;
2468 }
2469
2470 if (adev->gfx.rlc.cp_table_obj) {
2471 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
2472 if (unlikely(r != 0))
2473 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
2474 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
2475 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
2476
2477 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
2478 adev->gfx.rlc.cp_table_obj = NULL;
2479 }
2480}
2481
2482static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2483{
2484 const u32 *src_ptr;
2485 volatile u32 *dst_ptr;
2486 u32 dws, i;
2487 u64 reg_list_mc_addr;
2488 const struct cs_section_def *cs_data;
2489 int r;
2490
2491 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2492 adev->gfx.rlc.reg_list_size =
2493 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2494
2495 adev->gfx.rlc.cs_data = si_cs_data;
2496 src_ptr = adev->gfx.rlc.reg_list;
2497 dws = adev->gfx.rlc.reg_list_size;
2498 cs_data = adev->gfx.rlc.cs_data;
2499
2500 if (src_ptr) {
2501 /* save restore block */
2502 if (adev->gfx.rlc.save_restore_obj == NULL) {
2cd46ad2
KW		 2503 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2504 AMDGPU_GEM_DOMAIN_VRAM,
2505 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2506 NULL, NULL,
2507 &adev->gfx.rlc.save_restore_obj);
2508
2509 if (r) {
2510 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
2511 return r;
2512 }
2513 }
2514
2515 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
2516 if (unlikely(r != 0)) {
2517 gfx_v6_0_rlc_fini(adev);
2518 return r;
2519 }
2520 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
2521 &adev->gfx.rlc.save_restore_gpu_addr);
2522 if (r) {
2523 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2524 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
2525 gfx_v6_0_rlc_fini(adev);
2526 return r;
2527 }
2528
2529 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
2530 if (r) {
2531 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
2532 gfx_v6_0_rlc_fini(adev);
2533 return r;
2534 }
2535 /* write the sr buffer */
2536 dst_ptr = adev->gfx.rlc.sr_ptr;
2537 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2538 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2539 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2540 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2541 }
2542
2543 if (cs_data) {
2544 /* clear state block */
2545 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2546 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2547
2548 if (adev->gfx.rlc.clear_state_obj == NULL) {
2549 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
2550 AMDGPU_GEM_DOMAIN_VRAM,
2551 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
2552 NULL, NULL,
2553 &adev->gfx.rlc.clear_state_obj);
2554
2555 if (r) {
2556 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2557 gfx_v6_0_rlc_fini(adev);
2558 return r;
2559 }
2560 }
2561 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
2562 if (unlikely(r != 0)) {
2563 gfx_v6_0_rlc_fini(adev);
2564 return r;
2565 }
2566 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
2567 &adev->gfx.rlc.clear_state_gpu_addr);
2568 if (r) {
2569 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2570 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
2571 gfx_v6_0_rlc_fini(adev);
2572 return r;
2573 }
2574
2575 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
2576 if (r) {
2577 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
2578 gfx_v6_0_rlc_fini(adev);
2579 return r;
2580 }
2581 /* set up the cs buffer */
2582 dst_ptr = adev->gfx.rlc.cs_ptr;
2583 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2584 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2585 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2586 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2587 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2588 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2589 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2590 }
2591
2592 return 0;
2593}
2594
2595static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2596{
25069e06 2597 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2cd46ad2
KW		 2598
2599 if (!enable) {
2600 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
25069e06 2601 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2cd46ad2 2602 }
2cd46ad2
KW		 2603}
2604
2605static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2606{
2607 int i;
2608
2609 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2610 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2cd46ad2
KW		 2611 break;
2612 udelay(1);
2613 }
2614
2615 for (i = 0; i < adev->usec_timeout; i++) {
25069e06 2616 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2cd46ad2
KW		 2617 break;
2618 udelay(1);
2619 }
2620}
2621
2622static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2623{
2624 u32 tmp;
2625
25069e06 2626 tmp = RREG32(mmRLC_CNTL);
2cd46ad2 2627 if (tmp != rlc)
25069e06 2628 WREG32(mmRLC_CNTL, rlc);
2cd46ad2
KW		 2629}
2630
2631static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2632{
2633 u32 data, orig;
2634
25069e06 2635 orig = data = RREG32(mmRLC_CNTL);
2cd46ad2 2636
25069e06
TSD		 2637 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2638 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2639 WREG32(mmRLC_CNTL, data);
2cd46ad2
KW		 2640
2641 gfx_v6_0_wait_for_rlc_serdes(adev);
2642 }
2643
2644 return orig;
2645}
2646
2647static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2648{
25069e06 2649 WREG32(mmRLC_CNTL, 0);
2cd46ad2
KW		 2650
2651 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2cd46ad2
KW		 2652 gfx_v6_0_wait_for_rlc_serdes(adev);
2653}
2654
2655static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2656{
25069e06 2657 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2cd46ad2
KW		 2658
2659 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2660
2661 udelay(50);
2662}
2663
2664static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2665{
25069e06 2666 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2cd46ad2 2667 udelay(50);
25069e06 2668 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2cd46ad2
KW		 2669 udelay(50);
2670}
2671
2672static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2673{
2674 u32 tmp;
2675
2676 /* Enable LBPW only for DDR3 */
25069e06 2677 tmp = RREG32(mmMC_SEQ_MISC0);
2cd46ad2
KW		 2678 if ((tmp & 0xF0000000) == 0xB0000000)
2679 return true;
2680 return false;
2681}
25069e06 2682
2cd46ad2
KW		 2683static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2684{
2685}
2686
2687static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2688{
2689 u32 i;
2690 const struct rlc_firmware_header_v1_0 *hdr;
2691 const __le32 *fw_data;
2692 u32 fw_size;
2693
2694
2695 if (!adev->gfx.rlc_fw)
2696 return -EINVAL;
2697
2698 gfx_v6_0_rlc_stop(adev);
2cd46ad2 2699 gfx_v6_0_rlc_reset(adev);
2cd46ad2 2700 gfx_v6_0_init_pg(adev);
2cd46ad2
KW		 2701 gfx_v6_0_init_cg(adev);
2702
25069e06
TSD		 2703 WREG32(mmRLC_RL_BASE, 0);
2704 WREG32(mmRLC_RL_SIZE, 0);
2705 WREG32(mmRLC_LB_CNTL, 0);
2706 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2707 WREG32(mmRLC_LB_CNTR_INIT, 0);
2708 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2cd46ad2 2709
25069e06
TSD		 2710 WREG32(mmRLC_MC_CNTL, 0);
2711 WREG32(mmRLC_UCODE_CNTL, 0);
2cd46ad2
KW		 2712
2713 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2714 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2715 fw_data = (const __le32 *)
2716 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2717
2718 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2719
2720 for (i = 0; i < fw_size; i++) {
25069e06
TSD		 2721 WREG32(mmRLC_UCODE_ADDR, i);
2722 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2cd46ad2 2723 }
25069e06 2724 WREG32(mmRLC_UCODE_ADDR, 0);
2cd46ad2
KW		 2725
2726 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2cd46ad2
KW		 2727 gfx_v6_0_rlc_start(adev);
2728
2729 return 0;
2730}
2731
2732static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2733{
2734 u32 data, orig, tmp;
2735
25069e06 2736 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2cd46ad2
KW		 2737
2738 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2739 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2740
25069e06 2741 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2cd46ad2
KW		 2742
2743 tmp = gfx_v6_0_halt_rlc(adev);
2744
25069e06
TSD		 2745 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2746 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2747 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2cd46ad2
KW		 2748
2749 gfx_v6_0_wait_for_rlc_serdes(adev);
2cd46ad2
KW		 2750 gfx_v6_0_update_rlc(adev, tmp);
2751
25069e06 2752 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2cd46ad2 2753
25069e06 2754 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2cd46ad2
KW		 2755 } else {
2756 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2757
25069e06
TSD		 2758 RREG32(mmCB_CGTT_SCLK_CTRL);
2759 RREG32(mmCB_CGTT_SCLK_CTRL);
2760 RREG32(mmCB_CGTT_SCLK_CTRL);
2761 RREG32(mmCB_CGTT_SCLK_CTRL);
2cd46ad2 2762
25069e06 2763 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2cd46ad2
KW		 2764 }
2765
2766 if (orig != data)
25069e06 2767 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2cd46ad2
KW		 2768
2769}
2770
2771static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2772{
2773
2774 u32 data, orig, tmp = 0;
2775
2776 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
25069e06 2777 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2cd46ad2
KW		 2778 data = 0x96940200;
2779 if (orig != data)
25069e06 2780 WREG32(mmCGTS_SM_CTRL_REG, data);
2cd46ad2
KW		 2781
2782 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
25069e06
TSD		 2783 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2784 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2cd46ad2 2785 if (orig != data)
25069e06 2786 WREG32(mmCP_MEM_SLP_CNTL, data);
2cd46ad2
KW		 2787 }
2788
25069e06 2789 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2cd46ad2
KW		 2790 data &= 0xffffffc0;
2791 if (orig != data)
25069e06 2792 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2cd46ad2
KW		 2793
2794 tmp = gfx_v6_0_halt_rlc(adev);
2795
25069e06
TSD		 2796 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2797 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2798 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2cd46ad2
KW		 2799
2800 gfx_v6_0_update_rlc(adev, tmp);
2801 } else {
25069e06 2802 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2cd46ad2
KW		 2803 data |= 0x00000003;
2804 if (orig != data)
25069e06 2805 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2cd46ad2 2806
25069e06
TSD		 2807 data = RREG32(mmCP_MEM_SLP_CNTL);
2808 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2809 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2810 WREG32(mmCP_MEM_SLP_CNTL, data);
2cd46ad2 2811 }
25069e06
TSD		 2812 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2813 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2cd46ad2 2814 if (orig != data)
25069e06 2815 WREG32(mmCGTS_SM_CTRL_REG, data);
2cd46ad2
KW		 2816
2817 tmp = gfx_v6_0_halt_rlc(adev);
2818
25069e06
TSD		 2819 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2820 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2821 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2cd46ad2
KW		 2822
2823 gfx_v6_0_update_rlc(adev, tmp);
2824 }
2825}
2826/*
2827static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2828 bool enable)
2829{
2830 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2831 if (enable) {
2832 gfx_v6_0_enable_mgcg(adev, true);
2833 gfx_v6_0_enable_cgcg(adev, true);
2834 } else {
2835 gfx_v6_0_enable_cgcg(adev, false);
2836 gfx_v6_0_enable_mgcg(adev, false);
2837 }
2838 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2839}
2840*/
25069e06 2841
2cd46ad2
KW		 2842static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2843 bool enable)
2844{
2845}
2846
2847static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2848 bool enable)
2849{
2850}
2851
2852static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2853{
2854 u32 data, orig;
2855
25069e06 2856 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2
KW		 2857 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2858 data &= ~0x8000;
2859 else
2860 data |= 0x8000;
2861 if (orig != data)
25069e06 2862 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 2863}
2864
2865static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2866{
2867}
2868/*
2869static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2870{
2871 const __le32 *fw_data;
2872 volatile u32 *dst_ptr;
2873 int me, i, max_me = 4;
2874 u32 bo_offset = 0;
2875 u32 table_offset, table_size;
2876
2877 if (adev->asic_type == CHIP_KAVERI)
2878 max_me = 5;
2879
2880 if (adev->gfx.rlc.cp_table_ptr == NULL)
2881 return;
2882
2883 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2884 for (me = 0; me < max_me; me++) {
2885 if (me == 0) {
2886 const struct gfx_firmware_header_v1_0 *hdr =
2887 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2888 fw_data = (const __le32 *)
2889 (adev->gfx.ce_fw->data +
2890 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2891 table_offset = le32_to_cpu(hdr->jt_offset);
2892 table_size = le32_to_cpu(hdr->jt_size);
2893 } else if (me == 1) {
2894 const struct gfx_firmware_header_v1_0 *hdr =
2895 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2896 fw_data = (const __le32 *)
2897 (adev->gfx.pfp_fw->data +
2898 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2899 table_offset = le32_to_cpu(hdr->jt_offset);
2900 table_size = le32_to_cpu(hdr->jt_size);
2901 } else if (me == 2) {
2902 const struct gfx_firmware_header_v1_0 *hdr =
2903 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2904 fw_data = (const __le32 *)
2905 (adev->gfx.me_fw->data +
2906 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2907 table_offset = le32_to_cpu(hdr->jt_offset);
2908 table_size = le32_to_cpu(hdr->jt_size);
2909 } else if (me == 3) {
2910 const struct gfx_firmware_header_v1_0 *hdr =
2911 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2912 fw_data = (const __le32 *)
2913 (adev->gfx.mec_fw->data +
2914 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2915 table_offset = le32_to_cpu(hdr->jt_offset);
2916 table_size = le32_to_cpu(hdr->jt_size);
2917 } else {
2918 const struct gfx_firmware_header_v1_0 *hdr =
2919 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2920 fw_data = (const __le32 *)
2921 (adev->gfx.mec2_fw->data +
2922 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2923 table_offset = le32_to_cpu(hdr->jt_offset);
2924 table_size = le32_to_cpu(hdr->jt_size);
2925 }
2926
2927 for (i = 0; i < table_size; i ++) {
2928 dst_ptr[bo_offset + i] =
2929 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2930 }
2931
2932 bo_offset += table_size;
2933 }
2934}
2935*/
2936static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2937 bool enable)
2938{
2cd46ad2 2939 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
25069e06
TSD		 2940 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2941 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2942 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2cd46ad2 2943 } else {
25069e06
TSD		 2944 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2945 (void)RREG32(mmDB_RENDER_CONTROL);
2cd46ad2
KW		 2946 }
2947}
2948
2949static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
2950 u32 se, u32 sh)
2951{
2952
2953 u32 mask = 0, tmp, tmp1;
2954 int i;
2955
deca1d1f 2956 mutex_lock(&adev->grbm_idx_mutex);
2cd46ad2 2957 gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
25069e06
TSD		 2958 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
2959 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
2cd46ad2 2960 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
deca1d1f 2961 mutex_unlock(&adev->grbm_idx_mutex);
2cd46ad2
KW		 2962
2963 tmp &= 0xffff0000;
2964
2965 tmp |= tmp1;
2966 tmp >>= 16;
2967
2968 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
2969 mask <<= 1;
2970 mask |= 1;
2971 }
2972
2973 return (~tmp) & mask;
2974}
2975
2976static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2977{
2978 u32 i, j, k, active_cu_number = 0;
2979
2980 u32 mask, counter, cu_bitmap;
2981 u32 tmp = 0;
2982
2983 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2984 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2985 mask = 1;
2986 cu_bitmap = 0;
2987 counter = 0;
2988 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
2989 if (gfx_v6_0_get_cu_active_bitmap(adev, i, j) & mask) {
2990 if (counter < 2)
2991 cu_bitmap |= mask;
2992 counter++;
2993 }
2994 mask <<= 1;
2995 }
2996
2997 active_cu_number += counter;
2998 tmp |= (cu_bitmap << (i * 16 + j * 8));
2999 }
3000 }
3001
25069e06
TSD		 3002 WREG32(mmRLC_PG_AO_CU_MASK, tmp);
3003 WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number);
2cd46ad2
KW		 3004}
3005
3006static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3007 bool enable)
3008{
3009 u32 data, orig;
3010
25069e06 3011 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2 3012 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
25069e06 3013 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2cd46ad2 3014 else
25069e06 3015 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2cd46ad2 3016 if (orig != data)
25069e06 3017 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 3018}
3019
3020static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3021 bool enable)
3022{
3023 u32 data, orig;
3024
25069e06 3025 orig = data = RREG32(mmRLC_PG_CNTL);
2cd46ad2 3026 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
25069e06 3027 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2cd46ad2 3028 else
25069e06 3029 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2cd46ad2 3030 if (orig != data)
25069e06 3031 WREG32(mmRLC_PG_CNTL, data);
2cd46ad2
KW		 3032}
3033
3034static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
3035{
3036 u32 tmp;
3037
25069e06
TSD		 3038 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3039 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
3040 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2 3041
25069e06
TSD		 3042 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
3043 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3044 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3045 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
3046 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2cd46ad2
KW		 3047}
3048
3049static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3050{
3051 gfx_v6_0_enable_gfx_cgpg(adev, enable);
3052 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
3053 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
3054}
3055
3056static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
3057{
3058 u32 count = 0;
3059 const struct cs_section_def *sect = NULL;
3060 const struct cs_extent_def *ext = NULL;
3061
3062 if (adev->gfx.rlc.cs_data == NULL)
3063 return 0;
3064
3065 /* begin clear state */
3066 count += 2;
3067 /* context control state */
3068 count += 3;
3069
3070 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3071 for (ext = sect->section; ext->extent != NULL; ++ext) {
3072 if (sect->id == SECT_CONTEXT)
3073 count += 2 + ext->reg_count;
3074 else
3075 return 0;
3076 }
3077 }
3078 /* pa_sc_raster_config */
3079 count += 3;
3080 /* end clear state */
3081 count += 2;
3082 /* clear state */
3083 count += 2;
3084
3085 return count;
3086}
3087
3088static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
3089 volatile u32 *buffer)
3090{
3091 u32 count = 0, i;
3092 const struct cs_section_def *sect = NULL;
3093 const struct cs_extent_def *ext = NULL;
3094
3095 if (adev->gfx.rlc.cs_data == NULL)
3096 return;
3097 if (buffer == NULL)
3098 return;
3099
3100 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3101 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2cd46ad2
KW		 3102 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3103 buffer[count++] = cpu_to_le32(0x80000000);
3104 buffer[count++] = cpu_to_le32(0x80000000);
3105
3106 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3107 for (ext = sect->section; ext->extent != NULL; ++ext) {
3108 if (sect->id == SECT_CONTEXT) {
3109 buffer[count++] =
3110 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3111 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
3112 for (i = 0; i < ext->reg_count; i++)
3113 buffer[count++] = cpu_to_le32(ext->extent[i]);
3114 } else {
3115 return;
3116 }
3117 }
3118 }
3119
3120 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
25069e06 3121 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2cd46ad2
KW		 3122
3123 switch (adev->asic_type) {
3124 case CHIP_TAHITI:
3125 case CHIP_PITCAIRN:
3126 buffer[count++] = cpu_to_le32(0x2a00126a);
3127 break;
3128 case CHIP_VERDE:
3129 buffer[count++] = cpu_to_le32(0x0000124a);
3130 break;
3131 case CHIP_OLAND:
3132 buffer[count++] = cpu_to_le32(0x00000082);
3133 break;
3134 case CHIP_HAINAN:
3135 buffer[count++] = cpu_to_le32(0x00000000);
3136 break;
3137 default:
3138 buffer[count++] = cpu_to_le32(0x00000000);
3139 break;
3140 }
3141
3142 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3143 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3144
3145 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3146 buffer[count++] = cpu_to_le32(0);
3147}
3148
3149static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
3150{
3151 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3152 AMD_PG_SUPPORT_GFX_SMG |
3153 AMD_PG_SUPPORT_GFX_DMG |
3154 AMD_PG_SUPPORT_CP |
3155 AMD_PG_SUPPORT_GDS |
3156 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3157 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
3158 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
3159 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3160 gfx_v6_0_init_gfx_cgpg(adev);
3161 gfx_v6_0_enable_cp_pg(adev, true);
3162 gfx_v6_0_enable_gds_pg(adev, true);
3163 } else {
25069e06
TSD		 3164 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3165 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2
KW		 3166
3167 }
3168 gfx_v6_0_init_ao_cu_mask(adev);
3169 gfx_v6_0_update_gfx_pg(adev, true);
3170 } else {
3171
25069e06
TSD		 3172 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3173 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2cd46ad2
KW		 3174 }
3175}
3176
3177static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
3178{
3179 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3180 AMD_PG_SUPPORT_GFX_SMG |
3181 AMD_PG_SUPPORT_GFX_DMG |
3182 AMD_PG_SUPPORT_CP |
3183 AMD_PG_SUPPORT_GDS |
3184 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3185 gfx_v6_0_update_gfx_pg(adev, false);
3186 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3187 gfx_v6_0_enable_cp_pg(adev, false);
3188 gfx_v6_0_enable_gds_pg(adev, false);
3189 }
3190 }
3191}
3192
3193static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3194{
3195 uint64_t clock;
3196
3197 mutex_lock(&adev->gfx.gpu_clock_mutex);
25069e06
TSD		 3198 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3199 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3200 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2cd46ad2
KW		 3201 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3202 return clock;
3203}
3204
0f444c24
AD		 3205static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
3206{
45682886
ML		 3207 if (flags & AMDGPU_HAVE_CTX_SWITCH)
3208 gfx_v6_0_ring_emit_vgt_flush(ring);
0f444c24
AD		 3209 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3210 amdgpu_ring_write(ring, 0x80000000);
3211 amdgpu_ring_write(ring, 0);
3212}
3213
3ee73ed8
TSD		 3214
3215static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3216{
3217 WREG32(mmSQ_IND_INDEX,
3218 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3219 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3220 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3221 (SQ_IND_INDEX__FORCE_READ_MASK));
3222 return RREG32(mmSQ_IND_DATA);
3223}
3224
34e646f4
TSD		 3225static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3226 uint32_t wave, uint32_t thread,
3227 uint32_t regno, uint32_t num, uint32_t *out)
3228{
3229 WREG32(mmSQ_IND_INDEX,
3230 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3231 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3232 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3233 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3234 (SQ_IND_INDEX__FORCE_READ_MASK) |
3235 (SQ_IND_INDEX__AUTO_INCR_MASK));
3236 while (num--)
3237 *(out++) = RREG32(mmSQ_IND_DATA);
3238}
3239
3ee73ed8
TSD		 3240static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3241{
3242 /* type 0 wave data */
3243 dst[(*no_fields)++] = 0;
3244 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3245 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3246 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3247 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3248 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3249 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3250 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3251 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3252 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3253 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3254 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3255 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3256 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3257 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3258 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3259 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3260 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3261 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3262}
3263
34e646f4
TSD		 3264static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3265 uint32_t wave, uint32_t start,
3266 uint32_t size, uint32_t *dst)
3267{
3268 wave_read_regs(
3269 adev, simd, wave, 0,
3270 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3271}
3272
2cd46ad2
KW		 3273static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3274 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3275 .select_se_sh = &gfx_v6_0_select_se_sh,
3ee73ed8 3276 .read_wave_data = &gfx_v6_0_read_wave_data,
34e646f4 3277 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
2cd46ad2
KW		 3278};
3279
3280static int gfx_v6_0_early_init(void *handle)
3281{
3282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3283
3284 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3285 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3286 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3287 gfx_v6_0_set_ring_funcs(adev);
3288 gfx_v6_0_set_irq_funcs(adev);
3289
3290 return 0;
3291}
3292
3293static int gfx_v6_0_sw_init(void *handle)
3294{
3295 struct amdgpu_ring *ring;
3296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3297 int i, r;
3298
3299 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
3300 if (r)
3301 return r;
3302
3303 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
3304 if (r)
3305 return r;
3306
3307 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
3308 if (r)
3309 return r;
3310
3311 gfx_v6_0_scratch_init(adev);
3312
3313 r = gfx_v6_0_init_microcode(adev);
3314 if (r) {
3315 DRM_ERROR("Failed to load gfx firmware!\n");
3316 return r;
3317 }
3318
3319 r = gfx_v6_0_rlc_init(adev);
3320 if (r) {
3321 DRM_ERROR("Failed to init rlc BOs!\n");
3322 return r;
3323 }
3324
3325 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3326 ring = &adev->gfx.gfx_ring[i];
3327 ring->ring_obj = NULL;
3328 sprintf(ring->name, "gfx");
3329 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 3330 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
2cd46ad2
KW		 3331 if (r)
3332 return r;
3333 }
3334
3335 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3336 unsigned irq_type;
3337
3338 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3339 DRM_ERROR("Too many (%d) compute rings!\n", i);
3340 break;
3341 }
3342 ring = &adev->gfx.compute_ring[i];
3343 ring->ring_obj = NULL;
3344 ring->use_doorbell = false;
3345 ring->doorbell_index = 0;
3346 ring->me = 1;
3347 ring->pipe = i;
3348 ring->queue = i;
3349 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
3350 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
2255e8c1 3351 r = amdgpu_ring_init(adev, ring, 1024,
21cd942e 3352 &adev->gfx.eop_irq, irq_type);
2cd46ad2
KW		 3353 if (r)
3354 return r;
3355 }
3356
3357 return r;
3358}
3359
3360static int gfx_v6_0_sw_fini(void *handle)
3361{
3362 int i;
3363 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3364
3365 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
3366 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
3367 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
3368
3369 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3370 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3371 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3372 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3373
2cd46ad2
KW		 3374 gfx_v6_0_rlc_fini(adev);
3375
3376 return 0;
3377}
3378
3379static int gfx_v6_0_hw_init(void *handle)
3380{
3381 int r;
3382 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3383
3384 gfx_v6_0_gpu_init(adev);
3385
3386 r = gfx_v6_0_rlc_resume(adev);
3387 if (r)
3388 return r;
3389
3390 r = gfx_v6_0_cp_resume(adev);
3391 if (r)
3392 return r;
3393
3394 adev->gfx.ce_ram_size = 0x8000;
3395
3396 return r;
3397}
3398
3399static int gfx_v6_0_hw_fini(void *handle)
3400{
3401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3402
3403 gfx_v6_0_cp_enable(adev, false);
3404 gfx_v6_0_rlc_stop(adev);
3405 gfx_v6_0_fini_pg(adev);
3406
3407 return 0;
3408}
3409
3410static int gfx_v6_0_suspend(void *handle)
3411{
3412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3413
3414 return gfx_v6_0_hw_fini(adev);
3415}
3416
3417static int gfx_v6_0_resume(void *handle)
3418{
3419 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3420
3421 return gfx_v6_0_hw_init(adev);
3422}
3423
3424static bool gfx_v6_0_is_idle(void *handle)
3425{
3426 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3427
25069e06 3428 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
2cd46ad2
KW		 3429 return false;
3430 else
3431 return true;
3432}
3433
3434static int gfx_v6_0_wait_for_idle(void *handle)
3435{
3436 unsigned i;
2cd46ad2
KW		 3437 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3438
3439 for (i = 0; i < adev->usec_timeout; i++) {
4aeacf0f 3440 if (gfx_v6_0_is_idle(handle))
2cd46ad2
KW		 3441 return 0;
3442 udelay(1);
3443 }
3444 return -ETIMEDOUT;
3445}
3446
3447static int gfx_v6_0_soft_reset(void *handle)
3448{
3449 return 0;
3450}
3451
3452static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3453 enum amdgpu_interrupt_state state)
3454{
3455 u32 cp_int_cntl;
3456
3457 switch (state) {
3458 case AMDGPU_IRQ_STATE_DISABLE:
25069e06
TSD		 3459 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3460 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3461 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3462 break;
3463 case AMDGPU_IRQ_STATE_ENABLE:
25069e06
TSD		 3464 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3465 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3466 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3467 break;
3468 default:
3469 break;
3470 }
3471}
3472
3473static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3474 int ring,
3475 enum amdgpu_interrupt_state state)
3476{
3477 u32 cp_int_cntl;
3478 switch (state){
3479 case AMDGPU_IRQ_STATE_DISABLE:
3480 if (ring == 0) {
25069e06
TSD		 3481 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3482 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3483 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
2cd46ad2
KW		 3484 break;
3485 } else {
25069e06
TSD		 3486 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3487 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3488 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
2cd46ad2
KW		 3489 break;
3490
3491 }
3492 case AMDGPU_IRQ_STATE_ENABLE:
3493 if (ring == 0) {
25069e06
TSD		 3494 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3495 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3496 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
2cd46ad2
KW		 3497 break;
3498 } else {
25069e06
TSD		 3499 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3500 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3501 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
2cd46ad2
KW		 3502 break;
3503
3504 }
3505
3506 default:
3507 BUG();
3508 break;
3509
3510 }
3511}
3512
3513static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3514 struct amdgpu_irq_src *src,
3515 unsigned type,
3516 enum amdgpu_interrupt_state state)
3517{
3518 u32 cp_int_cntl;
3519
3520 switch (state) {
3521 case AMDGPU_IRQ_STATE_DISABLE:
25069e06 3522 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3523 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
25069e06 3524 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3525 break;
3526 case AMDGPU_IRQ_STATE_ENABLE:
25069e06 3527 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3528 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
25069e06 3529 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3530 break;
3531 default:
3532 break;
3533 }
3534
3535 return 0;
3536}
3537
3538static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3539 struct amdgpu_irq_src *src,
3540 unsigned type,
3541 enum amdgpu_interrupt_state state)
3542{
3543 u32 cp_int_cntl;
3544
3545 switch (state) {
3546 case AMDGPU_IRQ_STATE_DISABLE:
25069e06 3547 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3548 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
25069e06 3549 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3550 break;
3551 case AMDGPU_IRQ_STATE_ENABLE:
25069e06 3552 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
2cd46ad2 3553 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
25069e06 3554 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
2cd46ad2
KW		 3555 break;
3556 default:
3557 break;
3558 }
3559
3560 return 0;
3561}
3562
3563static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3564 struct amdgpu_irq_src *src,
3565 unsigned type,
3566 enum amdgpu_interrupt_state state)
3567{
3568 switch (type) {
3569 case AMDGPU_CP_IRQ_GFX_EOP:
3570 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3571 break;
3572 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3573 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3574 break;
3575 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3576 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3577 break;
3578 default:
3579 break;
3580 }
3581 return 0;
3582}
3583
3584static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3585 struct amdgpu_irq_src *source,
3586 struct amdgpu_iv_entry *entry)
3587{
3588 switch (entry->ring_id) {
3589 case 0:
3590 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3591 break;
3592 case 1:
3593 case 2:
25069e06 3594 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
2cd46ad2
KW		 3595 break;
3596 default:
3597 break;
3598 }
3599 return 0;
3600}
3601
3602static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3603 struct amdgpu_irq_src *source,
3604 struct amdgpu_iv_entry *entry)
3605{
3606 DRM_ERROR("Illegal register access in command stream\n");
3607 schedule_work(&adev->reset_work);
3608 return 0;
3609}
3610
3611static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3612 struct amdgpu_irq_src *source,
3613 struct amdgpu_iv_entry *entry)
3614{
3615 DRM_ERROR("Illegal instruction in command stream\n");
3616 schedule_work(&adev->reset_work);
3617 return 0;
3618}
3619
3620static int gfx_v6_0_set_clockgating_state(void *handle,
3621 enum amd_clockgating_state state)
3622{
3623 bool gate = false;
3624 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3625
3626 if (state == AMD_CG_STATE_GATE)
3627 gate = true;
3628
3629 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3630 if (gate) {
3631 gfx_v6_0_enable_mgcg(adev, true);
3632 gfx_v6_0_enable_cgcg(adev, true);
3633 } else {
3634 gfx_v6_0_enable_cgcg(adev, false);
3635 gfx_v6_0_enable_mgcg(adev, false);
3636 }
3637 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3638
3639 return 0;
3640}
3641
3642static int gfx_v6_0_set_powergating_state(void *handle,
3643 enum amd_powergating_state state)
3644{
3645 bool gate = false;
3646 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3647
3648 if (state == AMD_PG_STATE_GATE)
3649 gate = true;
3650
3651 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3652 AMD_PG_SUPPORT_GFX_SMG |
3653 AMD_PG_SUPPORT_GFX_DMG |
3654 AMD_PG_SUPPORT_CP |
3655 AMD_PG_SUPPORT_GDS |
3656 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3657 gfx_v6_0_update_gfx_pg(adev, gate);
3658 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3659 gfx_v6_0_enable_cp_pg(adev, gate);
3660 gfx_v6_0_enable_gds_pg(adev, gate);
3661 }
3662 }
3663
3664 return 0;
3665}
3666
a1255107 3667static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
2cd46ad2
KW		 3668 .name = "gfx_v6_0",
3669 .early_init = gfx_v6_0_early_init,
3670 .late_init = NULL,
3671 .sw_init = gfx_v6_0_sw_init,
3672 .sw_fini = gfx_v6_0_sw_fini,
3673 .hw_init = gfx_v6_0_hw_init,
3674 .hw_fini = gfx_v6_0_hw_fini,
3675 .suspend = gfx_v6_0_suspend,
3676 .resume = gfx_v6_0_resume,
3677 .is_idle = gfx_v6_0_is_idle,
3678 .wait_for_idle = gfx_v6_0_wait_for_idle,
3679 .soft_reset = gfx_v6_0_soft_reset,
3680 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3681 .set_powergating_state = gfx_v6_0_set_powergating_state,
3682};
3683
3684static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
21cd942e 3685 .type = AMDGPU_RING_TYPE_GFX,
79887142
CK		 3686 .align_mask = 0xff,
3687 .nop = 0x80000000,
6f924e20 3688 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3689 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2 3690 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
e12f3d7a
CK		 3691 .emit_frame_size =
3692 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3693 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3694 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3695 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3696 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
45682886 3697 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
e12f3d7a 3698 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
668f52c3
AD		 3699 .emit_ib = gfx_v6_0_ring_emit_ib,
3700 .emit_fence = gfx_v6_0_ring_emit_fence,
2cd46ad2
KW		 3701 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3702 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
2cd46ad2
KW		 3703 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3704 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3705 .test_ring = gfx_v6_0_ring_test_ring,
3706 .test_ib = gfx_v6_0_ring_test_ib,
3707 .insert_nop = amdgpu_ring_insert_nop,
0f444c24 3708 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
2cd46ad2
KW		 3709};
3710
3711static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
21cd942e 3712 .type = AMDGPU_RING_TYPE_COMPUTE,
79887142
CK		 3713 .align_mask = 0xff,
3714 .nop = 0x80000000,
6f924e20 3715 .get_rptr = gfx_v6_0_ring_get_rptr,
832c6ef7 3716 .get_wptr = gfx_v6_0_ring_get_wptr,
2cd46ad2 3717 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
e12f3d7a
CK		 3718 .emit_frame_size =
3719 5 + /* gfx_v6_0_ring_emit_hdp_flush */
3720 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
3721 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3722 17 + /* gfx_v6_0_ring_emit_vm_flush */
3723 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3724 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
668f52c3
AD		 3725 .emit_ib = gfx_v6_0_ring_emit_ib,
3726 .emit_fence = gfx_v6_0_ring_emit_fence,
2cd46ad2
KW		 3727 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3728 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
2cd46ad2
KW		 3729 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
3730 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
3731 .test_ring = gfx_v6_0_ring_test_ring,
3732 .test_ib = gfx_v6_0_ring_test_ib,
3733 .insert_nop = amdgpu_ring_insert_nop,
3734};
3735
3736static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3737{
3738 int i;
3739
3740 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3741 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3742 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3743 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3744}
3745
3746static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3747 .set = gfx_v6_0_set_eop_interrupt_state,
3748 .process = gfx_v6_0_eop_irq,
3749};
3750
3751static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3752 .set = gfx_v6_0_set_priv_reg_fault_state,
3753 .process = gfx_v6_0_priv_reg_irq,
3754};
3755
3756static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3757 .set = gfx_v6_0_set_priv_inst_fault_state,
3758 .process = gfx_v6_0_priv_inst_irq,
3759};
3760
3761static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3762{
3763 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3764 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3765
3766 adev->gfx.priv_reg_irq.num_types = 1;
3767 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3768
3769 adev->gfx.priv_inst_irq.num_types = 1;
3770 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3771}
3772
3773static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3774{
3775 int i, j, k, counter, active_cu_number = 0;
3776 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3777 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3778
3779 memset(cu_info, 0, sizeof(*cu_info));
3780
2cd46ad2
KW		 3781 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3782 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3783 mask = 1;
3784 ao_bitmap = 0;
3785 counter = 0;
2cd46ad2
KW		 3786 bitmap = gfx_v6_0_get_cu_active_bitmap(adev, i, j);
3787 cu_info->bitmap[i][j] = bitmap;
3788
3789 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
3790 if (bitmap & mask) {
3791 if (counter < 2)
3792 ao_bitmap |= mask;
3793 counter ++;
3794 }
3795 mask <<= 1;
3796 }
3797 active_cu_number += counter;
3798 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3799 }
3800 }
2cd46ad2
KW		 3801
3802 cu_info->number = active_cu_number;
3803 cu_info->ao_cu_mask = ao_cu_mask;
3804}
a1255107
AD		 3805
3806const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3807{
3808 .type = AMD_IP_BLOCK_TYPE_GFX,
3809 .major = 6,
3810 .minor = 0,
3811 .rev = 0,
3812 .funcs = &gfx_v6_0_ip_funcs,
3813};
Linux 6.x block layer and io_uring tree(s)