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drm/amdgpu/dce8: optimize pageflip
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / dce_v8_0.c
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a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "cikd.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_8_0_d.h"
36#include "dce/dce_8_0_sh_mask.h"
37
38#include "gca/gfx_7_2_enum.h"
39
40#include "gmc/gmc_7_1_d.h"
41#include "gmc/gmc_7_1_sh_mask.h"
42
43#include "oss/oss_2_0_d.h"
44#include "oss/oss_2_0_sh_mask.h"
45
46static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
47static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
48
49static const u32 crtc_offsets[6] =
50{
51 CRTC0_REGISTER_OFFSET,
52 CRTC1_REGISTER_OFFSET,
53 CRTC2_REGISTER_OFFSET,
54 CRTC3_REGISTER_OFFSET,
55 CRTC4_REGISTER_OFFSET,
56 CRTC5_REGISTER_OFFSET
57};
58
59static const uint32_t dig_offsets[] = {
60 CRTC0_REGISTER_OFFSET,
61 CRTC1_REGISTER_OFFSET,
62 CRTC2_REGISTER_OFFSET,
63 CRTC3_REGISTER_OFFSET,
64 CRTC4_REGISTER_OFFSET,
65 CRTC5_REGISTER_OFFSET,
66 (0x13830 - 0x7030) >> 2,
67};
68
69static const struct {
70 uint32_t reg;
71 uint32_t vblank;
72 uint32_t vline;
73 uint32_t hpd;
74
75} interrupt_status_offsets[6] = { {
76 .reg = mmDISP_INTERRUPT_STATUS,
77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
80}, {
81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
85}, {
86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
90}, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
105} };
106
107static const uint32_t hpd_int_control_offsets[6] = {
108 mmDC_HPD1_INT_CONTROL,
109 mmDC_HPD2_INT_CONTROL,
110 mmDC_HPD3_INT_CONTROL,
111 mmDC_HPD4_INT_CONTROL,
112 mmDC_HPD5_INT_CONTROL,
113 mmDC_HPD6_INT_CONTROL,
114};
115
116static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
117 u32 block_offset, u32 reg)
118{
119 unsigned long flags;
120 u32 r;
121
122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
126
127 return r;
128}
129
130static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
131 u32 block_offset, u32 reg, u32 v)
132{
133 unsigned long flags;
134
135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
139}
140
141static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
142{
143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
145 return true;
146 else
147 return false;
148}
149
150static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
151{
152 u32 pos1, pos2;
153
154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
156
157 if (pos1 != pos2)
158 return true;
159 else
160 return false;
161}
162
163/**
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
165 *
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
168 *
169 * Wait for vblank on the requested crtc (evergreen+).
170 */
171static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
172{
173 unsigned i = 0;
174
175 if (crtc >= adev->mode_info.num_crtc)
176 return;
177
178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
179 return;
180
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
183 */
184 while (dce_v8_0_is_in_vblank(adev, crtc)) {
185 if (i++ % 100 == 0) {
186 if (!dce_v8_0_is_counter_moving(adev, crtc))
187 break;
188 }
189 }
190
191 while (!dce_v8_0_is_in_vblank(adev, crtc)) {
192 if (i++ % 100 == 0) {
193 if (!dce_v8_0_is_counter_moving(adev, crtc))
194 break;
195 }
196 }
197}
198
199static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
200{
201 if (crtc >= adev->mode_info.num_crtc)
202 return 0;
203 else
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
205}
206
207/**
208 * dce_v8_0_page_flip - pageflip callback.
209 *
210 * @adev: amdgpu_device pointer
211 * @crtc_id: crtc to cleanup pageflip on
212 * @crtc_base: new address of the crtc (GPU MC address)
213 *
82326860
AD		 214 * Triggers the actual pageflip by updating the primary
215 * surface base address.
a2e73f56
AD		 216 */
217static void dce_v8_0_page_flip(struct amdgpu_device *adev,
218 int crtc_id, u64 crtc_base)
219{
220 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
a2e73f56 221
82326860 222 /* update the primary scanout addresses */
a2e73f56
AD		 223 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
224 upper_32_bits(crtc_base));
82326860 225 /* writing to the low address triggers the update */
a2e73f56 226 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
82326860
AD		 227 lower_32_bits(crtc_base));
228 /* post the write */
229 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
a2e73f56
AD		 230}
231
232static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
233 u32 *vbl, u32 *position)
234{
235 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
236 return -EINVAL;
237
238 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
239 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
240
241 return 0;
242}
243
244/**
245 * dce_v8_0_hpd_sense - hpd sense callback.
246 *
247 * @adev: amdgpu_device pointer
248 * @hpd: hpd (hotplug detect) pin
249 *
250 * Checks if a digital monitor is connected (evergreen+).
251 * Returns true if connected, false if not connected.
252 */
253static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
254 enum amdgpu_hpd_id hpd)
255{
256 bool connected = false;
257
258 switch (hpd) {
259 case AMDGPU_HPD_1:
260 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
261 connected = true;
262 break;
263 case AMDGPU_HPD_2:
264 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
265 connected = true;
266 break;
267 case AMDGPU_HPD_3:
268 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
269 connected = true;
270 break;
271 case AMDGPU_HPD_4:
272 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
273 connected = true;
274 break;
275 case AMDGPU_HPD_5:
276 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
277 connected = true;
278 break;
279 case AMDGPU_HPD_6:
280 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
281 connected = true;
282 break;
283 default:
284 break;
285 }
286
287 return connected;
288}
289
290/**
291 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
292 *
293 * @adev: amdgpu_device pointer
294 * @hpd: hpd (hotplug detect) pin
295 *
296 * Set the polarity of the hpd pin (evergreen+).
297 */
298static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
299 enum amdgpu_hpd_id hpd)
300{
301 u32 tmp;
302 bool connected = dce_v8_0_hpd_sense(adev, hpd);
303
304 switch (hpd) {
305 case AMDGPU_HPD_1:
306 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
307 if (connected)
308 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
309 else
310 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
311 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
312 break;
313 case AMDGPU_HPD_2:
314 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
315 if (connected)
316 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
317 else
318 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
319 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
320 break;
321 case AMDGPU_HPD_3:
322 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
323 if (connected)
324 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
325 else
326 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
327 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
328 break;
329 case AMDGPU_HPD_4:
330 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
331 if (connected)
332 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
333 else
334 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
335 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
336 break;
337 case AMDGPU_HPD_5:
338 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
339 if (connected)
340 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
341 else
342 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
343 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
344 break;
345 case AMDGPU_HPD_6:
346 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
347 if (connected)
348 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
349 else
350 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
351 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
352 break;
353 default:
354 break;
355 }
356}
357
358/**
359 * dce_v8_0_hpd_init - hpd setup callback.
360 *
361 * @adev: amdgpu_device pointer
362 *
363 * Setup the hpd pins used by the card (evergreen+).
364 * Enable the pin, set the polarity, and enable the hpd interrupts.
365 */
366static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
367{
368 struct drm_device *dev = adev->ddev;
369 struct drm_connector *connector;
370 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
371 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
372 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
373
374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
375 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
376
377 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
378 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
379 /* don't try to enable hpd on eDP or LVDS avoid breaking the
380 * aux dp channel on imac and help (but not completely fix)
381 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
382 * also avoid interrupt storms during dpms.
383 */
384 continue;
385 }
386 switch (amdgpu_connector->hpd.hpd) {
387 case AMDGPU_HPD_1:
388 WREG32(mmDC_HPD1_CONTROL, tmp);
389 break;
390 case AMDGPU_HPD_2:
391 WREG32(mmDC_HPD2_CONTROL, tmp);
392 break;
393 case AMDGPU_HPD_3:
394 WREG32(mmDC_HPD3_CONTROL, tmp);
395 break;
396 case AMDGPU_HPD_4:
397 WREG32(mmDC_HPD4_CONTROL, tmp);
398 break;
399 case AMDGPU_HPD_5:
400 WREG32(mmDC_HPD5_CONTROL, tmp);
401 break;
402 case AMDGPU_HPD_6:
403 WREG32(mmDC_HPD6_CONTROL, tmp);
404 break;
405 default:
406 break;
407 }
408 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
409 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
410 }
411}
412
413/**
414 * dce_v8_0_hpd_fini - hpd tear down callback.
415 *
416 * @adev: amdgpu_device pointer
417 *
418 * Tear down the hpd pins used by the card (evergreen+).
419 * Disable the hpd interrupts.
420 */
421static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
422{
423 struct drm_device *dev = adev->ddev;
424 struct drm_connector *connector;
425
426 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
427 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
428
429 switch (amdgpu_connector->hpd.hpd) {
430 case AMDGPU_HPD_1:
431 WREG32(mmDC_HPD1_CONTROL, 0);
432 break;
433 case AMDGPU_HPD_2:
434 WREG32(mmDC_HPD2_CONTROL, 0);
435 break;
436 case AMDGPU_HPD_3:
437 WREG32(mmDC_HPD3_CONTROL, 0);
438 break;
439 case AMDGPU_HPD_4:
440 WREG32(mmDC_HPD4_CONTROL, 0);
441 break;
442 case AMDGPU_HPD_5:
443 WREG32(mmDC_HPD5_CONTROL, 0);
444 break;
445 case AMDGPU_HPD_6:
446 WREG32(mmDC_HPD6_CONTROL, 0);
447 break;
448 default:
449 break;
450 }
451 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
452 }
453}
454
455static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
456{
457 return mmDC_GPIO_HPD_A;
458}
459
460static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
461{
462 u32 crtc_hung = 0;
463 u32 crtc_status[6];
464 u32 i, j, tmp;
465
466 for (i = 0; i < adev->mode_info.num_crtc; i++) {
467 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
468 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
469 crtc_hung |= (1 << i);
470 }
471 }
472
473 for (j = 0; j < 10; j++) {
474 for (i = 0; i < adev->mode_info.num_crtc; i++) {
475 if (crtc_hung & (1 << i)) {
476 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
477 if (tmp != crtc_status[i])
478 crtc_hung &= ~(1 << i);
479 }
480 }
481 if (crtc_hung == 0)
482 return false;
483 udelay(100);
484 }
485
486 return true;
487}
488
489static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
490 struct amdgpu_mode_mc_save *save)
491{
492 u32 crtc_enabled, tmp;
493 int i;
494
495 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
496 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
497
498 /* disable VGA render */
499 tmp = RREG32(mmVGA_RENDER_CONTROL);
500 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
501 WREG32(mmVGA_RENDER_CONTROL, tmp);
502
503 /* blank the display controllers */
504 for (i = 0; i < adev->mode_info.num_crtc; i++) {
505 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
506 CRTC_CONTROL, CRTC_MASTER_EN);
507 if (crtc_enabled) {
508#if 0
509 u32 frame_count;
510 int j;
511
512 save->crtc_enabled[i] = true;
513 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
514 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
515 amdgpu_display_vblank_wait(adev, i);
516 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
517 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
518 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
519 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
520 }
521 /* wait for the next frame */
522 frame_count = amdgpu_display_vblank_get_counter(adev, i);
523 for (j = 0; j < adev->usec_timeout; j++) {
524 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
525 break;
526 udelay(1);
527 }
528 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
529 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
530 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
531 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
532 }
533 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
534 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
535 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
536 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
537 }
538#else
539 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
540 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
541 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
542 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
543 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
544 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
545 save->crtc_enabled[i] = false;
546 /* ***** */
547#endif
548 } else {
549 save->crtc_enabled[i] = false;
550 }
551 }
552}
553
554static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
555 struct amdgpu_mode_mc_save *save)
556{
557 u32 tmp, frame_count;
558 int i, j;
559
560 /* update crtc base addresses */
561 for (i = 0; i < adev->mode_info.num_crtc; i++) {
562 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
563 upper_32_bits(adev->mc.vram_start));
564 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
565 upper_32_bits(adev->mc.vram_start));
566 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
567 (u32)adev->mc.vram_start);
568 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
569 (u32)adev->mc.vram_start);
570
571 if (save->crtc_enabled[i]) {
572 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
573 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
574 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
575 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
576 }
577 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
578 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
579 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
580 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
581 }
582 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
583 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
584 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
585 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
586 }
587 for (j = 0; j < adev->usec_timeout; j++) {
588 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
589 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
590 break;
591 udelay(1);
592 }
593 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
594 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
595 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
596 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
597 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
598 /* wait for the next frame */
599 frame_count = amdgpu_display_vblank_get_counter(adev, i);
600 for (j = 0; j < adev->usec_timeout; j++) {
601 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
602 break;
603 udelay(1);
604 }
605 }
606 }
607
608 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
609 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
610
611 /* Unlock vga access */
612 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
613 mdelay(1);
614 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
615}
616
617static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
618 bool render)
619{
620 u32 tmp;
621
622 /* Lockout access through VGA aperture*/
623 tmp = RREG32(mmVGA_HDP_CONTROL);
624 if (render)
625 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
626 else
627 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
628 WREG32(mmVGA_HDP_CONTROL, tmp);
629
630 /* disable VGA render */
631 tmp = RREG32(mmVGA_RENDER_CONTROL);
632 if (render)
633 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
634 else
635 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
636 WREG32(mmVGA_RENDER_CONTROL, tmp);
637}
638
639static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
640{
641 struct drm_device *dev = encoder->dev;
642 struct amdgpu_device *adev = dev->dev_private;
643 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
644 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
645 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
646 int bpc = 0;
647 u32 tmp = 0;
648 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
649
650 if (connector) {
651 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
652 bpc = amdgpu_connector_get_monitor_bpc(connector);
653 dither = amdgpu_connector->dither;
654 }
655
656 /* LVDS/eDP FMT is set up by atom */
657 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
658 return;
659
660 /* not needed for analog */
661 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
662 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
663 return;
664
665 if (bpc == 0)
666 return;
667
668 switch (bpc) {
669 case 6:
670 if (dither == AMDGPU_FMT_DITHER_ENABLE)
671 /* XXX sort out optimal dither settings */
672 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
673 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
674 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
675 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
676 else
677 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
678 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
679 break;
680 case 8:
681 if (dither == AMDGPU_FMT_DITHER_ENABLE)
682 /* XXX sort out optimal dither settings */
683 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
684 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
685 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
686 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
687 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
688 else
689 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
690 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
691 break;
692 case 10:
693 if (dither == AMDGPU_FMT_DITHER_ENABLE)
694 /* XXX sort out optimal dither settings */
695 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
696 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
697 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
698 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
699 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
700 else
701 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
702 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
703 break;
704 default:
705 /* not needed */
706 break;
707 }
708
709 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
710}
711
712
713/* display watermark setup */
714/**
715 * dce_v8_0_line_buffer_adjust - Set up the line buffer
716 *
717 * @adev: amdgpu_device pointer
718 * @amdgpu_crtc: the selected display controller
719 * @mode: the current display mode on the selected display
720 * controller
721 *
722 * Setup up the line buffer allocation for
723 * the selected display controller (CIK).
724 * Returns the line buffer size in pixels.
725 */
726static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
727 struct amdgpu_crtc *amdgpu_crtc,
728 struct drm_display_mode *mode)
729{
730 u32 tmp, buffer_alloc, i;
731 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
732 /*
733 * Line Buffer Setup
734 * There are 6 line buffers, one for each display controllers.
735 * There are 3 partitions per LB. Select the number of partitions
736 * to enable based on the display width. For display widths larger
737 * than 4096, you need use to use 2 display controllers and combine
738 * them using the stereo blender.
739 */
740 if (amdgpu_crtc->base.enabled && mode) {
741 if (mode->crtc_hdisplay < 1920) {
742 tmp = 1;
743 buffer_alloc = 2;
744 } else if (mode->crtc_hdisplay < 2560) {
745 tmp = 2;
746 buffer_alloc = 2;
747 } else if (mode->crtc_hdisplay < 4096) {
748 tmp = 0;
2f7d10b3 749 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 750 } else {
751 DRM_DEBUG_KMS("Mode too big for LB!\n");
752 tmp = 0;
2f7d10b3 753 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
a2e73f56
AD		 754 }
755 } else {
756 tmp = 1;
757 buffer_alloc = 0;
758 }
759
760 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
761 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
762 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
763
764 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
765 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
766 for (i = 0; i < adev->usec_timeout; i++) {
767 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
768 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
769 break;
770 udelay(1);
771 }
772
773 if (amdgpu_crtc->base.enabled && mode) {
774 switch (tmp) {
775 case 0:
776 default:
777 return 4096 * 2;
778 case 1:
779 return 1920 * 2;
780 case 2:
781 return 2560 * 2;
782 }
783 }
784
785 /* controller not enabled, so no lb used */
786 return 0;
787}
788
789/**
790 * cik_get_number_of_dram_channels - get the number of dram channels
791 *
792 * @adev: amdgpu_device pointer
793 *
794 * Look up the number of video ram channels (CIK).
795 * Used for display watermark bandwidth calculations
796 * Returns the number of dram channels
797 */
798static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
799{
800 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
801
802 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
803 case 0:
804 default:
805 return 1;
806 case 1:
807 return 2;
808 case 2:
809 return 4;
810 case 3:
811 return 8;
812 case 4:
813 return 3;
814 case 5:
815 return 6;
816 case 6:
817 return 10;
818 case 7:
819 return 12;
820 case 8:
821 return 16;
822 }
823}
824
825struct dce8_wm_params {
826 u32 dram_channels; /* number of dram channels */
827 u32 yclk; /* bandwidth per dram data pin in kHz */
828 u32 sclk; /* engine clock in kHz */
829 u32 disp_clk; /* display clock in kHz */
830 u32 src_width; /* viewport width */
831 u32 active_time; /* active display time in ns */
832 u32 blank_time; /* blank time in ns */
833 bool interlaced; /* mode is interlaced */
834 fixed20_12 vsc; /* vertical scale ratio */
835 u32 num_heads; /* number of active crtcs */
836 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
837 u32 lb_size; /* line buffer allocated to pipe */
838 u32 vtaps; /* vertical scaler taps */
839};
840
841/**
842 * dce_v8_0_dram_bandwidth - get the dram bandwidth
843 *
844 * @wm: watermark calculation data
845 *
846 * Calculate the raw dram bandwidth (CIK).
847 * Used for display watermark bandwidth calculations
848 * Returns the dram bandwidth in MBytes/s
849 */
850static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
851{
852 /* Calculate raw DRAM Bandwidth */
853 fixed20_12 dram_efficiency; /* 0.7 */
854 fixed20_12 yclk, dram_channels, bandwidth;
855 fixed20_12 a;
856
857 a.full = dfixed_const(1000);
858 yclk.full = dfixed_const(wm->yclk);
859 yclk.full = dfixed_div(yclk, a);
860 dram_channels.full = dfixed_const(wm->dram_channels * 4);
861 a.full = dfixed_const(10);
862 dram_efficiency.full = dfixed_const(7);
863 dram_efficiency.full = dfixed_div(dram_efficiency, a);
864 bandwidth.full = dfixed_mul(dram_channels, yclk);
865 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
866
867 return dfixed_trunc(bandwidth);
868}
869
870/**
871 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
872 *
873 * @wm: watermark calculation data
874 *
875 * Calculate the dram bandwidth used for display (CIK).
876 * Used for display watermark bandwidth calculations
877 * Returns the dram bandwidth for display in MBytes/s
878 */
879static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
880{
881 /* Calculate DRAM Bandwidth and the part allocated to display. */
882 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
883 fixed20_12 yclk, dram_channels, bandwidth;
884 fixed20_12 a;
885
886 a.full = dfixed_const(1000);
887 yclk.full = dfixed_const(wm->yclk);
888 yclk.full = dfixed_div(yclk, a);
889 dram_channels.full = dfixed_const(wm->dram_channels * 4);
890 a.full = dfixed_const(10);
891 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
892 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
893 bandwidth.full = dfixed_mul(dram_channels, yclk);
894 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
895
896 return dfixed_trunc(bandwidth);
897}
898
899/**
900 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
901 *
902 * @wm: watermark calculation data
903 *
904 * Calculate the data return bandwidth used for display (CIK).
905 * Used for display watermark bandwidth calculations
906 * Returns the data return bandwidth in MBytes/s
907 */
908static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
909{
910 /* Calculate the display Data return Bandwidth */
911 fixed20_12 return_efficiency; /* 0.8 */
912 fixed20_12 sclk, bandwidth;
913 fixed20_12 a;
914
915 a.full = dfixed_const(1000);
916 sclk.full = dfixed_const(wm->sclk);
917 sclk.full = dfixed_div(sclk, a);
918 a.full = dfixed_const(10);
919 return_efficiency.full = dfixed_const(8);
920 return_efficiency.full = dfixed_div(return_efficiency, a);
921 a.full = dfixed_const(32);
922 bandwidth.full = dfixed_mul(a, sclk);
923 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
924
925 return dfixed_trunc(bandwidth);
926}
927
928/**
929 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
930 *
931 * @wm: watermark calculation data
932 *
933 * Calculate the dmif bandwidth used for display (CIK).
934 * Used for display watermark bandwidth calculations
935 * Returns the dmif bandwidth in MBytes/s
936 */
937static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
938{
939 /* Calculate the DMIF Request Bandwidth */
940 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
941 fixed20_12 disp_clk, bandwidth;
942 fixed20_12 a, b;
943
944 a.full = dfixed_const(1000);
945 disp_clk.full = dfixed_const(wm->disp_clk);
946 disp_clk.full = dfixed_div(disp_clk, a);
947 a.full = dfixed_const(32);
948 b.full = dfixed_mul(a, disp_clk);
949
950 a.full = dfixed_const(10);
951 disp_clk_request_efficiency.full = dfixed_const(8);
952 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
953
954 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
955
956 return dfixed_trunc(bandwidth);
957}
958
959/**
960 * dce_v8_0_available_bandwidth - get the min available bandwidth
961 *
962 * @wm: watermark calculation data
963 *
964 * Calculate the min available bandwidth used for display (CIK).
965 * Used for display watermark bandwidth calculations
966 * Returns the min available bandwidth in MBytes/s
967 */
968static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
969{
970 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
971 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
972 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
973 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
974
975 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
976}
977
978/**
979 * dce_v8_0_average_bandwidth - get the average available bandwidth
980 *
981 * @wm: watermark calculation data
982 *
983 * Calculate the average available bandwidth used for display (CIK).
984 * Used for display watermark bandwidth calculations
985 * Returns the average available bandwidth in MBytes/s
986 */
987static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
988{
989 /* Calculate the display mode Average Bandwidth
990 * DisplayMode should contain the source and destination dimensions,
991 * timing, etc.
992 */
993 fixed20_12 bpp;
994 fixed20_12 line_time;
995 fixed20_12 src_width;
996 fixed20_12 bandwidth;
997 fixed20_12 a;
998
999 a.full = dfixed_const(1000);
1000 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1001 line_time.full = dfixed_div(line_time, a);
1002 bpp.full = dfixed_const(wm->bytes_per_pixel);
1003 src_width.full = dfixed_const(wm->src_width);
1004 bandwidth.full = dfixed_mul(src_width, bpp);
1005 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1006 bandwidth.full = dfixed_div(bandwidth, line_time);
1007
1008 return dfixed_trunc(bandwidth);
1009}
1010
1011/**
1012 * dce_v8_0_latency_watermark - get the latency watermark
1013 *
1014 * @wm: watermark calculation data
1015 *
1016 * Calculate the latency watermark (CIK).
1017 * Used for display watermark bandwidth calculations
1018 * Returns the latency watermark in ns
1019 */
1020static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
1021{
1022 /* First calculate the latency in ns */
1023 u32 mc_latency = 2000; /* 2000 ns. */
1024 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
1025 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1026 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1027 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1028 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1029 (wm->num_heads * cursor_line_pair_return_time);
1030 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1031 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1032 u32 tmp, dmif_size = 12288;
1033 fixed20_12 a, b, c;
1034
1035 if (wm->num_heads == 0)
1036 return 0;
1037
1038 a.full = dfixed_const(2);
1039 b.full = dfixed_const(1);
1040 if ((wm->vsc.full > a.full) ||
1041 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1042 (wm->vtaps >= 5) ||
1043 ((wm->vsc.full >= a.full) && wm->interlaced))
1044 max_src_lines_per_dst_line = 4;
1045 else
1046 max_src_lines_per_dst_line = 2;
1047
1048 a.full = dfixed_const(available_bandwidth);
1049 b.full = dfixed_const(wm->num_heads);
1050 a.full = dfixed_div(a, b);
1051
1052 b.full = dfixed_const(mc_latency + 512);
1053 c.full = dfixed_const(wm->disp_clk);
1054 b.full = dfixed_div(b, c);
1055
1056 c.full = dfixed_const(dmif_size);
1057 b.full = dfixed_div(c, b);
1058
1059 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1060
1061 b.full = dfixed_const(1000);
1062 c.full = dfixed_const(wm->disp_clk);
1063 b.full = dfixed_div(c, b);
1064 c.full = dfixed_const(wm->bytes_per_pixel);
1065 b.full = dfixed_mul(b, c);
1066
1067 lb_fill_bw = min(tmp, dfixed_trunc(b));
1068
1069 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1070 b.full = dfixed_const(1000);
1071 c.full = dfixed_const(lb_fill_bw);
1072 b.full = dfixed_div(c, b);
1073 a.full = dfixed_div(a, b);
1074 line_fill_time = dfixed_trunc(a);
1075
1076 if (line_fill_time < wm->active_time)
1077 return latency;
1078 else
1079 return latency + (line_fill_time - wm->active_time);
1080
1081}
1082
1083/**
1084 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1085 * average and available dram bandwidth
1086 *
1087 * @wm: watermark calculation data
1088 *
1089 * Check if the display average bandwidth fits in the display
1090 * dram bandwidth (CIK).
1091 * Used for display watermark bandwidth calculations
1092 * Returns true if the display fits, false if not.
1093 */
1094static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1095{
1096 if (dce_v8_0_average_bandwidth(wm) <=
1097 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1098 return true;
1099 else
1100 return false;
1101}
1102
1103/**
1104 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1105 * average and available bandwidth
1106 *
1107 * @wm: watermark calculation data
1108 *
1109 * Check if the display average bandwidth fits in the display
1110 * available bandwidth (CIK).
1111 * Used for display watermark bandwidth calculations
1112 * Returns true if the display fits, false if not.
1113 */
1114static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1115{
1116 if (dce_v8_0_average_bandwidth(wm) <=
1117 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1118 return true;
1119 else
1120 return false;
1121}
1122
1123/**
1124 * dce_v8_0_check_latency_hiding - check latency hiding
1125 *
1126 * @wm: watermark calculation data
1127 *
1128 * Check latency hiding (CIK).
1129 * Used for display watermark bandwidth calculations
1130 * Returns true if the display fits, false if not.
1131 */
1132static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1133{
1134 u32 lb_partitions = wm->lb_size / wm->src_width;
1135 u32 line_time = wm->active_time + wm->blank_time;
1136 u32 latency_tolerant_lines;
1137 u32 latency_hiding;
1138 fixed20_12 a;
1139
1140 a.full = dfixed_const(1);
1141 if (wm->vsc.full > a.full)
1142 latency_tolerant_lines = 1;
1143 else {
1144 if (lb_partitions <= (wm->vtaps + 1))
1145 latency_tolerant_lines = 1;
1146 else
1147 latency_tolerant_lines = 2;
1148 }
1149
1150 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1151
1152 if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1153 return true;
1154 else
1155 return false;
1156}
1157
1158/**
1159 * dce_v8_0_program_watermarks - program display watermarks
1160 *
1161 * @adev: amdgpu_device pointer
1162 * @amdgpu_crtc: the selected display controller
1163 * @lb_size: line buffer size
1164 * @num_heads: number of display controllers in use
1165 *
1166 * Calculate and program the display watermarks for the
1167 * selected display controller (CIK).
1168 */
1169static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1170 struct amdgpu_crtc *amdgpu_crtc,
1171 u32 lb_size, u32 num_heads)
1172{
1173 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1174 struct dce8_wm_params wm_low, wm_high;
1175 u32 pixel_period;
1176 u32 line_time = 0;
1177 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1178 u32 tmp, wm_mask;
1179
1180 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1181 pixel_period = 1000000 / (u32)mode->clock;
1182 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1183
1184 /* watermark for high clocks */
1185 if (adev->pm.dpm_enabled) {
1186 wm_high.yclk =
1187 amdgpu_dpm_get_mclk(adev, false) * 10;
1188 wm_high.sclk =
1189 amdgpu_dpm_get_sclk(adev, false) * 10;
1190 } else {
1191 wm_high.yclk = adev->pm.current_mclk * 10;
1192 wm_high.sclk = adev->pm.current_sclk * 10;
1193 }
1194
1195 wm_high.disp_clk = mode->clock;
1196 wm_high.src_width = mode->crtc_hdisplay;
1197 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1198 wm_high.blank_time = line_time - wm_high.active_time;
1199 wm_high.interlaced = false;
1200 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1201 wm_high.interlaced = true;
1202 wm_high.vsc = amdgpu_crtc->vsc;
1203 wm_high.vtaps = 1;
1204 if (amdgpu_crtc->rmx_type != RMX_OFF)
1205 wm_high.vtaps = 2;
1206 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1207 wm_high.lb_size = lb_size;
1208 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1209 wm_high.num_heads = num_heads;
1210
1211 /* set for high clocks */
1212 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1213
1214 /* possibly force display priority to high */
1215 /* should really do this at mode validation time... */
1216 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1217 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1218 !dce_v8_0_check_latency_hiding(&wm_high) ||
1219 (adev->mode_info.disp_priority == 2)) {
1220 DRM_DEBUG_KMS("force priority to high\n");
1221 }
1222
1223 /* watermark for low clocks */
1224 if (adev->pm.dpm_enabled) {
1225 wm_low.yclk =
1226 amdgpu_dpm_get_mclk(adev, true) * 10;
1227 wm_low.sclk =
1228 amdgpu_dpm_get_sclk(adev, true) * 10;
1229 } else {
1230 wm_low.yclk = adev->pm.current_mclk * 10;
1231 wm_low.sclk = adev->pm.current_sclk * 10;
1232 }
1233
1234 wm_low.disp_clk = mode->clock;
1235 wm_low.src_width = mode->crtc_hdisplay;
1236 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1237 wm_low.blank_time = line_time - wm_low.active_time;
1238 wm_low.interlaced = false;
1239 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1240 wm_low.interlaced = true;
1241 wm_low.vsc = amdgpu_crtc->vsc;
1242 wm_low.vtaps = 1;
1243 if (amdgpu_crtc->rmx_type != RMX_OFF)
1244 wm_low.vtaps = 2;
1245 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1246 wm_low.lb_size = lb_size;
1247 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1248 wm_low.num_heads = num_heads;
1249
1250 /* set for low clocks */
1251 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1252
1253 /* possibly force display priority to high */
1254 /* should really do this at mode validation time... */
1255 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1256 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1257 !dce_v8_0_check_latency_hiding(&wm_low) ||
1258 (adev->mode_info.disp_priority == 2)) {
1259 DRM_DEBUG_KMS("force priority to high\n");
1260 }
1261 }
1262
1263 /* select wm A */
1264 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1265 tmp = wm_mask;
1266 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1267 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1268 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1269 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1270 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1271 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1272 /* select wm B */
1273 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1274 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1275 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1276 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1277 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1278 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1279 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1280 /* restore original selection */
1281 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1282
1283 /* save values for DPM */
1284 amdgpu_crtc->line_time = line_time;
1285 amdgpu_crtc->wm_high = latency_watermark_a;
1286 amdgpu_crtc->wm_low = latency_watermark_b;
1287}
1288
1289/**
1290 * dce_v8_0_bandwidth_update - program display watermarks
1291 *
1292 * @adev: amdgpu_device pointer
1293 *
1294 * Calculate and program the display watermarks and line
1295 * buffer allocation (CIK).
1296 */
1297static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1298{
1299 struct drm_display_mode *mode = NULL;
1300 u32 num_heads = 0, lb_size;
1301 int i;
1302
1303 amdgpu_update_display_priority(adev);
1304
1305 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1306 if (adev->mode_info.crtcs[i]->base.enabled)
1307 num_heads++;
1308 }
1309 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1310 mode = &adev->mode_info.crtcs[i]->base.mode;
1311 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1312 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1313 lb_size, num_heads);
1314 }
1315}
1316
1317static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1318{
1319 int i;
1320 u32 offset, tmp;
1321
1322 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1323 offset = adev->mode_info.audio.pin[i].offset;
1324 tmp = RREG32_AUDIO_ENDPT(offset,
1325 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1326 if (((tmp &
1327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1328 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1329 adev->mode_info.audio.pin[i].connected = false;
1330 else
1331 adev->mode_info.audio.pin[i].connected = true;
1332 }
1333}
1334
1335static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1336{
1337 int i;
1338
1339 dce_v8_0_audio_get_connected_pins(adev);
1340
1341 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1342 if (adev->mode_info.audio.pin[i].connected)
1343 return &adev->mode_info.audio.pin[i];
1344 }
1345 DRM_ERROR("No connected audio pins found!\n");
1346 return NULL;
1347}
1348
1349static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1350{
1351 struct amdgpu_device *adev = encoder->dev->dev_private;
1352 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1353 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1354 u32 offset;
1355
1356 if (!dig || !dig->afmt || !dig->afmt->pin)
1357 return;
1358
1359 offset = dig->afmt->offset;
1360
1361 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1362 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1363}
1364
1365static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1366 struct drm_display_mode *mode)
1367{
1368 struct amdgpu_device *adev = encoder->dev->dev_private;
1369 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1370 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1371 struct drm_connector *connector;
1372 struct amdgpu_connector *amdgpu_connector = NULL;
1373 u32 tmp = 0, offset;
1374
1375 if (!dig || !dig->afmt || !dig->afmt->pin)
1376 return;
1377
1378 offset = dig->afmt->pin->offset;
1379
1380 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1381 if (connector->encoder == encoder) {
1382 amdgpu_connector = to_amdgpu_connector(connector);
1383 break;
1384 }
1385 }
1386
1387 if (!amdgpu_connector) {
1388 DRM_ERROR("Couldn't find encoder's connector\n");
1389 return;
1390 }
1391
1392 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1393 if (connector->latency_present[1])
1394 tmp =
1395 (connector->video_latency[1] <<
1396 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1397 (connector->audio_latency[1] <<
1398 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1399 else
1400 tmp =
1401 (0 <<
1402 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1403 (0 <<
1404 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1405 } else {
1406 if (connector->latency_present[0])
1407 tmp =
1408 (connector->video_latency[0] <<
1409 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1410 (connector->audio_latency[0] <<
1411 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1412 else
1413 tmp =
1414 (0 <<
1415 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1416 (0 <<
1417 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1418
1419 }
1420 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1421}
1422
1423static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1424{
1425 struct amdgpu_device *adev = encoder->dev->dev_private;
1426 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1427 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1428 struct drm_connector *connector;
1429 struct amdgpu_connector *amdgpu_connector = NULL;
1430 u32 offset, tmp;
1431 u8 *sadb = NULL;
1432 int sad_count;
1433
1434 if (!dig || !dig->afmt || !dig->afmt->pin)
1435 return;
1436
1437 offset = dig->afmt->pin->offset;
1438
1439 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1440 if (connector->encoder == encoder) {
1441 amdgpu_connector = to_amdgpu_connector(connector);
1442 break;
1443 }
1444 }
1445
1446 if (!amdgpu_connector) {
1447 DRM_ERROR("Couldn't find encoder's connector\n");
1448 return;
1449 }
1450
1451 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1452 if (sad_count < 0) {
1453 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1454 sad_count = 0;
1455 }
1456
1457 /* program the speaker allocation */
1458 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1459 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1460 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1461 /* set HDMI mode */
1462 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1463 if (sad_count)
1464 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1465 else
1466 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1467 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1468
1469 kfree(sadb);
1470}
1471
1472static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1473{
1474 struct amdgpu_device *adev = encoder->dev->dev_private;
1475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1476 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1477 u32 offset;
1478 struct drm_connector *connector;
1479 struct amdgpu_connector *amdgpu_connector = NULL;
1480 struct cea_sad *sads;
1481 int i, sad_count;
1482
1483 static const u16 eld_reg_to_type[][2] = {
1484 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1485 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1486 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1487 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1488 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1489 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1490 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1491 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1492 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1493 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1494 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1495 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1496 };
1497
1498 if (!dig || !dig->afmt || !dig->afmt->pin)
1499 return;
1500
1501 offset = dig->afmt->pin->offset;
1502
1503 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1504 if (connector->encoder == encoder) {
1505 amdgpu_connector = to_amdgpu_connector(connector);
1506 break;
1507 }
1508 }
1509
1510 if (!amdgpu_connector) {
1511 DRM_ERROR("Couldn't find encoder's connector\n");
1512 return;
1513 }
1514
1515 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1516 if (sad_count <= 0) {
1517 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1518 return;
1519 }
1520 BUG_ON(!sads);
1521
1522 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1523 u32 value = 0;
1524 u8 stereo_freqs = 0;
1525 int max_channels = -1;
1526 int j;
1527
1528 for (j = 0; j < sad_count; j++) {
1529 struct cea_sad *sad = &sads[j];
1530
1531 if (sad->format == eld_reg_to_type[i][1]) {
1532 if (sad->channels > max_channels) {
1533 value = (sad->channels <<
1534 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1535 (sad->byte2 <<
1536 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1537 (sad->freq <<
1538 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1539 max_channels = sad->channels;
1540 }
1541
1542 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1543 stereo_freqs |= sad->freq;
1544 else
1545 break;
1546 }
1547 }
1548
1549 value |= (stereo_freqs <<
1550 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1551
1552 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1553 }
1554
1555 kfree(sads);
1556}
1557
1558static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1559 struct amdgpu_audio_pin *pin,
1560 bool enable)
1561{
1562 if (!pin)
1563 return;
1564
1565 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1566 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1567}
1568
1569static const u32 pin_offsets[7] =
1570{
1571 (0x1780 - 0x1780),
1572 (0x1786 - 0x1780),
1573 (0x178c - 0x1780),
1574 (0x1792 - 0x1780),
1575 (0x1798 - 0x1780),
1576 (0x179d - 0x1780),
1577 (0x17a4 - 0x1780),
1578};
1579
1580static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1581{
1582 int i;
1583
1584 if (!amdgpu_audio)
1585 return 0;
1586
1587 adev->mode_info.audio.enabled = true;
1588
1589 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1590 adev->mode_info.audio.num_pins = 7;
1591 else if ((adev->asic_type == CHIP_KABINI) ||
1592 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1593 adev->mode_info.audio.num_pins = 3;
1594 else if ((adev->asic_type == CHIP_BONAIRE) ||
1595 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1596 adev->mode_info.audio.num_pins = 7;
1597 else
1598 adev->mode_info.audio.num_pins = 3;
1599
1600 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1601 adev->mode_info.audio.pin[i].channels = -1;
1602 adev->mode_info.audio.pin[i].rate = -1;
1603 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1604 adev->mode_info.audio.pin[i].status_bits = 0;
1605 adev->mode_info.audio.pin[i].category_code = 0;
1606 adev->mode_info.audio.pin[i].connected = false;
1607 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1608 adev->mode_info.audio.pin[i].id = i;
1609 /* disable audio. it will be set up later */
1610 /* XXX remove once we switch to ip funcs */
1611 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1612 }
1613
1614 return 0;
1615}
1616
1617static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1618{
1619 int i;
1620
1621 if (!adev->mode_info.audio.enabled)
1622 return;
1623
1624 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1625 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1626
1627 adev->mode_info.audio.enabled = false;
1628}
1629
1630/*
1631 * update the N and CTS parameters for a given pixel clock rate
1632 */
1633static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1634{
1635 struct drm_device *dev = encoder->dev;
1636 struct amdgpu_device *adev = dev->dev_private;
1637 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1638 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1639 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1640 uint32_t offset = dig->afmt->offset;
1641
1642 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1643 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1644
1645 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1646 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1647
1648 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1649 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1650}
1651
1652/*
1653 * build a HDMI Video Info Frame
1654 */
1655static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1656 void *buffer, size_t size)
1657{
1658 struct drm_device *dev = encoder->dev;
1659 struct amdgpu_device *adev = dev->dev_private;
1660 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1661 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1662 uint32_t offset = dig->afmt->offset;
1663 uint8_t *frame = buffer + 3;
1664 uint8_t *header = buffer;
1665
1666 WREG32(mmAFMT_AVI_INFO0 + offset,
1667 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1668 WREG32(mmAFMT_AVI_INFO1 + offset,
1669 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1670 WREG32(mmAFMT_AVI_INFO2 + offset,
1671 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1672 WREG32(mmAFMT_AVI_INFO3 + offset,
1673 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1674}
1675
1676static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1677{
1678 struct drm_device *dev = encoder->dev;
1679 struct amdgpu_device *adev = dev->dev_private;
1680 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1681 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1683 u32 dto_phase = 24 * 1000;
1684 u32 dto_modulo = clock;
1685
1686 if (!dig || !dig->afmt)
1687 return;
1688
1689 /* XXX two dtos; generally use dto0 for hdmi */
1690 /* Express [24MHz / target pixel clock] as an exact rational
1691 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1692 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1693 */
1694 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1695 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1696 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1697}
1698
1699/*
1700 * update the info frames with the data from the current display mode
1701 */
1702static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1703 struct drm_display_mode *mode)
1704{
1705 struct drm_device *dev = encoder->dev;
1706 struct amdgpu_device *adev = dev->dev_private;
1707 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1708 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1709 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1710 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1711 struct hdmi_avi_infoframe frame;
1712 uint32_t offset, val;
1713 ssize_t err;
1714 int bpc = 8;
1715
1716 if (!dig || !dig->afmt)
1717 return;
1718
1719 /* Silent, r600_hdmi_enable will raise WARN for us */
1720 if (!dig->afmt->enabled)
1721 return;
1722 offset = dig->afmt->offset;
1723
1724 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1725 if (encoder->crtc) {
1726 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1727 bpc = amdgpu_crtc->bpc;
1728 }
1729
1730 /* disable audio prior to setting up hw */
1731 dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1732 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1733
1734 dce_v8_0_audio_set_dto(encoder, mode->clock);
1735
1736 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1737 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1738
1739 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1740
1741 val = RREG32(mmHDMI_CONTROL + offset);
1742 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1743 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1744
1745 switch (bpc) {
1746 case 0:
1747 case 6:
1748 case 8:
1749 case 16:
1750 default:
1751 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1752 connector->name, bpc);
1753 break;
1754 case 10:
1755 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1756 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1757 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1758 connector->name);
1759 break;
1760 case 12:
1761 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1762 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1763 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1764 connector->name);
1765 break;
1766 }
1767
1768 WREG32(mmHDMI_CONTROL + offset, val);
1769
1770 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1771 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1772 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1773 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1774
1775 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1776 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1777 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1778
1779 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1780 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1781
1782 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1783 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1784
1785 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1786
1787 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1788 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1789 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1790
1791 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1792 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1793
1794 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1795
1796 if (bpc > 8)
1797 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1798 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1799 else
1800 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1801 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1802 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1803
1804 dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1805
1806 WREG32(mmAFMT_60958_0 + offset,
1807 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1808
1809 WREG32(mmAFMT_60958_1 + offset,
1810 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1811
1812 WREG32(mmAFMT_60958_2 + offset,
1813 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1814 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1815 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1816 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1817 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1818 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1819
1820 dce_v8_0_audio_write_speaker_allocation(encoder);
1821
1822
1823 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1824 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1825
1826 dce_v8_0_afmt_audio_select_pin(encoder);
1827 dce_v8_0_audio_write_sad_regs(encoder);
1828 dce_v8_0_audio_write_latency_fields(encoder, mode);
1829
1830 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1831 if (err < 0) {
1832 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1833 return;
1834 }
1835
1836 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1837 if (err < 0) {
1838 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1839 return;
1840 }
1841
1842 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1843
1844 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1845 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1846 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */
1847
1848 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1849 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1850 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1851
1852 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1853 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1854
1855 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1856 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1857 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1858 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1859 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1860
1861 /* enable audio after to setting up hw */
1862 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1863}
1864
1865static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1866{
1867 struct drm_device *dev = encoder->dev;
1868 struct amdgpu_device *adev = dev->dev_private;
1869 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1870 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1871
1872 if (!dig || !dig->afmt)
1873 return;
1874
1875 /* Silent, r600_hdmi_enable will raise WARN for us */
1876 if (enable && dig->afmt->enabled)
1877 return;
1878 if (!enable && !dig->afmt->enabled)
1879 return;
1880
1881 if (!enable && dig->afmt->pin) {
1882 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1883 dig->afmt->pin = NULL;
1884 }
1885
1886 dig->afmt->enabled = enable;
1887
1888 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1889 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1890}
1891
1892static void dce_v8_0_afmt_init(struct amdgpu_device *adev)
1893{
1894 int i;
1895
1896 for (i = 0; i < adev->mode_info.num_dig; i++)
1897 adev->mode_info.afmt[i] = NULL;
1898
1899 /* DCE8 has audio blocks tied to DIG encoders */
1900 for (i = 0; i < adev->mode_info.num_dig; i++) {
1901 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1902 if (adev->mode_info.afmt[i]) {
1903 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1904 adev->mode_info.afmt[i]->id = i;
1905 }
1906 }
1907}
1908
1909static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1910{
1911 int i;
1912
1913 for (i = 0; i < adev->mode_info.num_dig; i++) {
1914 kfree(adev->mode_info.afmt[i]);
1915 adev->mode_info.afmt[i] = NULL;
1916 }
1917}
1918
1919static const u32 vga_control_regs[6] =
1920{
1921 mmD1VGA_CONTROL,
1922 mmD2VGA_CONTROL,
1923 mmD3VGA_CONTROL,
1924 mmD4VGA_CONTROL,
1925 mmD5VGA_CONTROL,
1926 mmD6VGA_CONTROL,
1927};
1928
1929static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1930{
1931 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1932 struct drm_device *dev = crtc->dev;
1933 struct amdgpu_device *adev = dev->dev_private;
1934 u32 vga_control;
1935
1936 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1937 if (enable)
1938 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1939 else
1940 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1941}
1942
1943static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1944{
1945 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1946 struct drm_device *dev = crtc->dev;
1947 struct amdgpu_device *adev = dev->dev_private;
1948
1949 if (enable)
1950 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1951 else
1952 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1953}
1954
a2e73f56
AD		 1955static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1956 struct drm_framebuffer *fb,
1957 int x, int y, int atomic)
1958{
1959 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1960 struct drm_device *dev = crtc->dev;
1961 struct amdgpu_device *adev = dev->dev_private;
1962 struct amdgpu_framebuffer *amdgpu_fb;
1963 struct drm_framebuffer *target_fb;
1964 struct drm_gem_object *obj;
1965 struct amdgpu_bo *rbo;
1966 uint64_t fb_location, tiling_flags;
1967 uint32_t fb_format, fb_pitch_pixels;
a2e73f56 1968 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
fbd76d59 1969 u32 pipe_config;
a2e73f56
AD		 1970 u32 tmp, viewport_w, viewport_h;
1971 int r;
1972 bool bypass_lut = false;
1973
1974 /* no fb bound */
1975 if (!atomic && !crtc->primary->fb) {
1976 DRM_DEBUG_KMS("No FB bound\n");
1977 return 0;
1978 }
1979
1980 if (atomic) {
1981 amdgpu_fb = to_amdgpu_framebuffer(fb);
1982 target_fb = fb;
1983 }
1984 else {
1985 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1986 target_fb = crtc->primary->fb;
1987 }
1988
1989 /* If atomic, assume fb object is pinned & idle & fenced and
1990 * just update base pointers
1991 */
1992 obj = amdgpu_fb->obj;
1993 rbo = gem_to_amdgpu_bo(obj);
1994 r = amdgpu_bo_reserve(rbo, false);
1995 if (unlikely(r != 0))
1996 return r;
1997
1998 if (atomic)
1999 fb_location = amdgpu_bo_gpu_offset(rbo);
2000 else {
2001 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2002 if (unlikely(r != 0)) {
2003 amdgpu_bo_unreserve(rbo);
2004 return -EINVAL;
2005 }
2006 }
2007
2008 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2009 amdgpu_bo_unreserve(rbo);
2010
fbd76d59
MO		 2011 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2012
a2e73f56
AD		 2013 switch (target_fb->pixel_format) {
2014 case DRM_FORMAT_C8:
2015 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2016 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2017 break;
2018 case DRM_FORMAT_XRGB4444:
2019 case DRM_FORMAT_ARGB4444:
2020 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2021 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2022#ifdef __BIG_ENDIAN
2023 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2024#endif
2025 break;
2026 case DRM_FORMAT_XRGB1555:
2027 case DRM_FORMAT_ARGB1555:
2028 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2029 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2030#ifdef __BIG_ENDIAN
2031 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2032#endif
2033 break;
2034 case DRM_FORMAT_BGRX5551:
2035 case DRM_FORMAT_BGRA5551:
2036 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2037 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2038#ifdef __BIG_ENDIAN
2039 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2040#endif
2041 break;
2042 case DRM_FORMAT_RGB565:
2043 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2044 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2045#ifdef __BIG_ENDIAN
2046 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2047#endif
2048 break;
2049 case DRM_FORMAT_XRGB8888:
2050 case DRM_FORMAT_ARGB8888:
2051 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2052 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2053#ifdef __BIG_ENDIAN
2054 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2055#endif
2056 break;
2057 case DRM_FORMAT_XRGB2101010:
2058 case DRM_FORMAT_ARGB2101010:
2059 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2060 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2061#ifdef __BIG_ENDIAN
2062 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2063#endif
2064 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2065 bypass_lut = true;
2066 break;
2067 case DRM_FORMAT_BGRX1010102:
2068 case DRM_FORMAT_BGRA1010102:
2069 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2070 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2071#ifdef __BIG_ENDIAN
2072 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2073#endif
2074 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2075 bypass_lut = true;
2076 break;
2077 default:
2078 DRM_ERROR("Unsupported screen format %s\n",
2079 drm_get_format_name(target_fb->pixel_format));
2080 return -EINVAL;
2081 }
2082
fbd76d59
MO		 2083 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2084 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
a2e73f56 2085
fbd76d59
MO		 2086 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2087 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2088 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2089 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2090 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
a2e73f56 2091
a2e73f56
AD		 2092 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2093 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2094 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2095 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2096 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2097 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2098 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
fbd76d59 2099 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
a2e73f56
AD		 2100 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2101 }
2102
a2e73f56
AD		 2103 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2104
2105 dce_v8_0_vga_enable(crtc, false);
2106
2107 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2108 upper_32_bits(fb_location));
2109 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2110 upper_32_bits(fb_location));
2111 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2112 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2113 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2114 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2115 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2116 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2117
2118 /*
2119 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2120 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2121 * retain the full precision throughout the pipeline.
2122 */
2123 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2124 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2125 ~LUT_10BIT_BYPASS_EN);
2126
2127 if (bypass_lut)
2128 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2129
2130 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2131 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2132 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2133 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2134 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2135 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2136
2137 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2138 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2139
2140 dce_v8_0_grph_enable(crtc, true);
2141
2142 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2143 target_fb->height);
2144
2145 x &= ~3;
2146 y &= ~1;
2147 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2148 (x << 16) | y);
2149 viewport_w = crtc->mode.hdisplay;
2150 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2151 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2152 (viewport_w << 16) | viewport_h);
2153
2154 /* pageflip setup */
2155 /* make sure flip is at vb rather than hb */
2156 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2157 tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK;
2158 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2159
2160 /* set pageflip to happen only at start of vblank interval (front porch) */
2161 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2162
2163 if (!atomic && fb && fb != crtc->primary->fb) {
2164 amdgpu_fb = to_amdgpu_framebuffer(fb);
2165 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2166 r = amdgpu_bo_reserve(rbo, false);
2167 if (unlikely(r != 0))
2168 return r;
2169 amdgpu_bo_unpin(rbo);
2170 amdgpu_bo_unreserve(rbo);
2171 }
2172
2173 /* Bytes per pixel may have changed */
2174 dce_v8_0_bandwidth_update(adev);
2175
2176 return 0;
2177}
2178
2179static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2180 struct drm_display_mode *mode)
2181{
2182 struct drm_device *dev = crtc->dev;
2183 struct amdgpu_device *adev = dev->dev_private;
2184 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2185
2186 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2187 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2188 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2189 else
2190 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2191}
2192
2193static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2194{
2195 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2196 struct drm_device *dev = crtc->dev;
2197 struct amdgpu_device *adev = dev->dev_private;
2198 int i;
2199
2200 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2201
2202 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2203 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2204 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2205 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2206 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2207 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2208 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2209 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2210 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2211 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2212
2213 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2214
2215 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2216 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2217 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2218
2219 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2220 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2221 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2222
2223 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2224 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2225
2226 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2227 for (i = 0; i < 256; i++) {
2228 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2229 (amdgpu_crtc->lut_r[i] << 20) |
2230 (amdgpu_crtc->lut_g[i] << 10) |
2231 (amdgpu_crtc->lut_b[i] << 0));
2232 }
2233
2234 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2235 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2236 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2237 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2238 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2239 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2240 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2241 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2242 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2243 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2244 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2245 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2246 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2247 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2248 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2249 /* XXX this only needs to be programmed once per crtc at startup,
2250 * not sure where the best place for it is
2251 */
2252 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2253 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2254}
2255
2256static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2257{
2258 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2260
2261 switch (amdgpu_encoder->encoder_id) {
2262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2263 if (dig->linkb)
2264 return 1;
2265 else
2266 return 0;
2267 break;
2268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2269 if (dig->linkb)
2270 return 3;
2271 else
2272 return 2;
2273 break;
2274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2275 if (dig->linkb)
2276 return 5;
2277 else
2278 return 4;
2279 break;
2280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2281 return 6;
2282 break;
2283 default:
2284 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2285 return 0;
2286 }
2287}
2288
2289/**
2290 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2291 *
2292 * @crtc: drm crtc
2293 *
2294 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2295 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2296 * monitors a dedicated PPLL must be used. If a particular board has
2297 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2298 * as there is no need to program the PLL itself. If we are not able to
2299 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2300 * avoid messing up an existing monitor.
2301 *
2302 * Asic specific PLL information
2303 *
2304 * DCE 8.x
2305 * KB/KV
2306 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2307 * CI
2308 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2309 *
2310 */
2311static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2312{
2313 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2314 struct drm_device *dev = crtc->dev;
2315 struct amdgpu_device *adev = dev->dev_private;
2316 u32 pll_in_use;
2317 int pll;
2318
2319 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2320 if (adev->clock.dp_extclk)
2321 /* skip PPLL programming if using ext clock */
2322 return ATOM_PPLL_INVALID;
2323 else {
2324 /* use the same PPLL for all DP monitors */
2325 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2326 if (pll != ATOM_PPLL_INVALID)
2327 return pll;
2328 }
2329 } else {
2330 /* use the same PPLL for all monitors with the same clock */
2331 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2332 if (pll != ATOM_PPLL_INVALID)
2333 return pll;
2334 }
2335 /* otherwise, pick one of the plls */
2336 if ((adev->asic_type == CHIP_KABINI) ||
2337 (adev->asic_type == CHIP_MULLINS)) {
2338 /* KB/ML has PPLL1 and PPLL2 */
2339 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2340 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2341 return ATOM_PPLL2;
2342 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2343 return ATOM_PPLL1;
2344 DRM_ERROR("unable to allocate a PPLL\n");
2345 return ATOM_PPLL_INVALID;
2346 } else {
2347 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2348 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2349 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2350 return ATOM_PPLL2;
2351 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2352 return ATOM_PPLL1;
2353 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2354 return ATOM_PPLL0;
2355 DRM_ERROR("unable to allocate a PPLL\n");
2356 return ATOM_PPLL_INVALID;
2357 }
2358 return ATOM_PPLL_INVALID;
2359}
2360
2361static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2362{
2363 struct amdgpu_device *adev = crtc->dev->dev_private;
2364 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2365 uint32_t cur_lock;
2366
2367 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2368 if (lock)
2369 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2370 else
2371 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2372 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2373}
2374
2375static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2376{
2377 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2378 struct amdgpu_device *adev = crtc->dev->dev_private;
2379
2380 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2381 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2382 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2383}
2384
2385static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2386{
2387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2388 struct amdgpu_device *adev = crtc->dev->dev_private;
2389
a2df42da
AD		 2390 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2391 upper_32_bits(amdgpu_crtc->cursor_addr));
2392 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2393 lower_32_bits(amdgpu_crtc->cursor_addr));
2394
a2e73f56
AD		 2395 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2396 CUR_CONTROL__CURSOR_EN_MASK |
2397 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2398 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2399}
2400
77ed35b8
AD		 2401static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2402 int x, int y)
a2e73f56
AD		 2403{
2404 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405 struct amdgpu_device *adev = crtc->dev->dev_private;
2406 int xorigin = 0, yorigin = 0;
2407
2408 /* avivo cursor are offset into the total surface */
2409 x += crtc->x;
2410 y += crtc->y;
2411 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2412
2413 if (x < 0) {
2414 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2415 x = 0;
2416 }
2417 if (y < 0) {
2418 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2419 y = 0;
2420 }
2421
a2e73f56
AD		 2422 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2423 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2424 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2425 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
77ed35b8
AD		 2426
2427 amdgpu_crtc->cursor_x = x;
2428 amdgpu_crtc->cursor_y = y;
a2e73f56
AD		 2429
2430 return 0;
2431}
2432
77ed35b8
AD		 2433static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2434 int x, int y)
2435{
2436 int ret;
2437
2438 dce_v8_0_lock_cursor(crtc, true);
2439 ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2440 dce_v8_0_lock_cursor(crtc, false);
2441
2442 return ret;
2443}
2444
2445static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2446 struct drm_file *file_priv,
2447 uint32_t handle,
2448 uint32_t width,
2449 uint32_t height,
2450 int32_t hot_x,
2451 int32_t hot_y)
a2e73f56
AD		 2452{
2453 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2454 struct drm_gem_object *obj;
72b40067 2455 struct amdgpu_bo *aobj;
a2e73f56
AD		 2456 int ret;
2457
2458 if (!handle) {
2459 /* turn off cursor */
2460 dce_v8_0_hide_cursor(crtc);
2461 obj = NULL;
2462 goto unpin;
2463 }
2464
2465 if ((width > amdgpu_crtc->max_cursor_width) ||
2466 (height > amdgpu_crtc->max_cursor_height)) {
2467 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2468 return -EINVAL;
2469 }
2470
2471 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2472 if (!obj) {
2473 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2474 return -ENOENT;
2475 }
2476
72b40067
AD		 2477 aobj = gem_to_amdgpu_bo(obj);
2478 ret = amdgpu_bo_reserve(aobj, false);
2479 if (ret != 0) {
2480 drm_gem_object_unreference_unlocked(obj);
2481 return ret;
2482 }
2483
2484 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2485 amdgpu_bo_unreserve(aobj);
2486 if (ret) {
2487 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2488 drm_gem_object_unreference_unlocked(obj);
2489 return ret;
2490 }
2491
a2e73f56
AD		 2492 amdgpu_crtc->cursor_width = width;
2493 amdgpu_crtc->cursor_height = height;
2494
2495 dce_v8_0_lock_cursor(crtc, true);
c4e0dfad
AD		 2496
2497 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2498 hot_y != amdgpu_crtc->cursor_hot_y) {
2499 int x, y;
2500
2501 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2502 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2503
2504 dce_v8_0_cursor_move_locked(crtc, x, y);
2505
2506 amdgpu_crtc->cursor_hot_x = hot_x;
2507 amdgpu_crtc->cursor_hot_y = hot_y;
2508 }
2509
72b40067 2510 dce_v8_0_show_cursor(crtc);
a2e73f56
AD		 2511 dce_v8_0_lock_cursor(crtc, false);
2512
2513unpin:
2514 if (amdgpu_crtc->cursor_bo) {
fd70cf63
AD		 2515 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2516 ret = amdgpu_bo_reserve(aobj, false);
a2e73f56 2517 if (likely(ret == 0)) {
fd70cf63
AD		 2518 amdgpu_bo_unpin(aobj);
2519 amdgpu_bo_unreserve(aobj);
a2e73f56 2520 }
72b40067 2521 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
a2e73f56
AD		 2522 }
2523
2524 amdgpu_crtc->cursor_bo = obj;
2525 return 0;
fd70cf63 2526}
a2e73f56 2527
fd70cf63
AD		 2528static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2529{
2530 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
fd70cf63
AD		 2531
2532 if (amdgpu_crtc->cursor_bo) {
2533 dce_v8_0_lock_cursor(crtc, true);
2534
2535 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2536 amdgpu_crtc->cursor_y);
2537
72b40067 2538 dce_v8_0_show_cursor(crtc);
fd70cf63
AD		 2539
2540 dce_v8_0_lock_cursor(crtc, false);
2541 }
a2e73f56
AD		 2542}
2543
2544static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2545 u16 *blue, uint32_t start, uint32_t size)
2546{
2547 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2548 int end = (start + size > 256) ? 256 : start + size, i;
2549
2550 /* userspace palettes are always correct as is */
2551 for (i = start; i < end; i++) {
2552 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2553 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2554 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2555 }
2556 dce_v8_0_crtc_load_lut(crtc);
2557}
2558
2559static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2560{
2561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2562
2563 drm_crtc_cleanup(crtc);
2564 destroy_workqueue(amdgpu_crtc->pflip_queue);
2565 kfree(amdgpu_crtc);
2566}
2567
2568static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
77ed35b8 2569 .cursor_set2 = dce_v8_0_crtc_cursor_set2,
a2e73f56
AD		 2570 .cursor_move = dce_v8_0_crtc_cursor_move,
2571 .gamma_set = dce_v8_0_crtc_gamma_set,
2572 .set_config = amdgpu_crtc_set_config,
2573 .destroy = dce_v8_0_crtc_destroy,
2574 .page_flip = amdgpu_crtc_page_flip,
2575};
2576
2577static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2578{
2579 struct drm_device *dev = crtc->dev;
2580 struct amdgpu_device *adev = dev->dev_private;
2581 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1002d718 2582 unsigned type;
a2e73f56
AD		 2583
2584 switch (mode) {
2585 case DRM_MODE_DPMS_ON:
2586 amdgpu_crtc->enabled = true;
2587 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2588 dce_v8_0_vga_enable(crtc, true);
2589 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2590 dce_v8_0_vga_enable(crtc, false);
1002d718
MD		 2591 /* Make sure VBLANK interrupt is still enabled */
2592 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2593 amdgpu_irq_update(adev, &adev->crtc_irq, type);
a2e73f56
AD		 2594 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2595 dce_v8_0_crtc_load_lut(crtc);
2596 break;
2597 case DRM_MODE_DPMS_STANDBY:
2598 case DRM_MODE_DPMS_SUSPEND:
2599 case DRM_MODE_DPMS_OFF:
2600 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2601 if (amdgpu_crtc->enabled) {
2602 dce_v8_0_vga_enable(crtc, true);
2603 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2604 dce_v8_0_vga_enable(crtc, false);
2605 }
2606 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2607 amdgpu_crtc->enabled = false;
2608 break;
2609 }
2610 /* adjust pm to dpms */
2611 amdgpu_pm_compute_clocks(adev);
2612}
2613
2614static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2615{
2616 /* disable crtc pair power gating before programming */
2617 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2618 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2619 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2620}
2621
2622static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2623{
2624 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2625 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2626}
2627
2628static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2629{
2630 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2631 struct drm_device *dev = crtc->dev;
2632 struct amdgpu_device *adev = dev->dev_private;
2633 struct amdgpu_atom_ss ss;
2634 int i;
2635
2636 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2637 if (crtc->primary->fb) {
2638 int r;
2639 struct amdgpu_framebuffer *amdgpu_fb;
2640 struct amdgpu_bo *rbo;
2641
2642 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2643 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2644 r = amdgpu_bo_reserve(rbo, false);
2645 if (unlikely(r))
2646 DRM_ERROR("failed to reserve rbo before unpin\n");
2647 else {
2648 amdgpu_bo_unpin(rbo);
2649 amdgpu_bo_unreserve(rbo);
2650 }
2651 }
2652 /* disable the GRPH */
2653 dce_v8_0_grph_enable(crtc, false);
2654
2655 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2656
2657 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2658 if (adev->mode_info.crtcs[i] &&
2659 adev->mode_info.crtcs[i]->enabled &&
2660 i != amdgpu_crtc->crtc_id &&
2661 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2662 /* one other crtc is using this pll don't turn
2663 * off the pll
2664 */
2665 goto done;
2666 }
2667 }
2668
2669 switch (amdgpu_crtc->pll_id) {
2670 case ATOM_PPLL1:
2671 case ATOM_PPLL2:
2672 /* disable the ppll */
2673 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2674 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2675 break;
2676 case ATOM_PPLL0:
2677 /* disable the ppll */
2678 if ((adev->asic_type == CHIP_KAVERI) ||
2679 (adev->asic_type == CHIP_BONAIRE) ||
2680 (adev->asic_type == CHIP_HAWAII))
2681 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2682 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2683 break;
2684 default:
2685 break;
2686 }
2687done:
2688 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2689 amdgpu_crtc->adjusted_clock = 0;
2690 amdgpu_crtc->encoder = NULL;
2691 amdgpu_crtc->connector = NULL;
2692}
2693
2694static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2695 struct drm_display_mode *mode,
2696 struct drm_display_mode *adjusted_mode,
2697 int x, int y, struct drm_framebuffer *old_fb)
2698{
2699 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2700
2701 if (!amdgpu_crtc->adjusted_clock)
2702 return -EINVAL;
2703
2704 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2705 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2706 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2707 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2708 amdgpu_atombios_crtc_scaler_setup(crtc);
fd70cf63 2709 dce_v8_0_cursor_reset(crtc);
a2e73f56
AD		 2710 /* update the hw version fpr dpm */
2711 amdgpu_crtc->hw_mode = *adjusted_mode;
2712
2713 return 0;
2714}
2715
2716static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2717 const struct drm_display_mode *mode,
2718 struct drm_display_mode *adjusted_mode)
2719{
2720 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2721 struct drm_device *dev = crtc->dev;
2722 struct drm_encoder *encoder;
2723
2724 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2725 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2726 if (encoder->crtc == crtc) {
2727 amdgpu_crtc->encoder = encoder;
2728 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2729 break;
2730 }
2731 }
2732 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2733 amdgpu_crtc->encoder = NULL;
2734 amdgpu_crtc->connector = NULL;
2735 return false;
2736 }
2737 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2738 return false;
2739 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2740 return false;
2741 /* pick pll */
2742 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2743 /* if we can't get a PPLL for a non-DP encoder, fail */
2744 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2745 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2746 return false;
2747
2748 return true;
2749}
2750
2751static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2752 struct drm_framebuffer *old_fb)
2753{
2754 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2755}
2756
2757static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2758 struct drm_framebuffer *fb,
2759 int x, int y, enum mode_set_atomic state)
2760{
2761 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2762}
2763
2764static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2765 .dpms = dce_v8_0_crtc_dpms,
2766 .mode_fixup = dce_v8_0_crtc_mode_fixup,
2767 .mode_set = dce_v8_0_crtc_mode_set,
2768 .mode_set_base = dce_v8_0_crtc_set_base,
2769 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2770 .prepare = dce_v8_0_crtc_prepare,
2771 .commit = dce_v8_0_crtc_commit,
2772 .load_lut = dce_v8_0_crtc_load_lut,
2773 .disable = dce_v8_0_crtc_disable,
2774};
2775
2776static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2777{
2778 struct amdgpu_crtc *amdgpu_crtc;
2779 int i;
2780
2781 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2782 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2783 if (amdgpu_crtc == NULL)
2784 return -ENOMEM;
2785
2786 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2787
2788 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2789 amdgpu_crtc->crtc_id = index;
2790 amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2791 adev->mode_info.crtcs[index] = amdgpu_crtc;
2792
2793 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2794 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2795 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2796 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2797
2798 for (i = 0; i < 256; i++) {
2799 amdgpu_crtc->lut_r[i] = i << 2;
2800 amdgpu_crtc->lut_g[i] = i << 2;
2801 amdgpu_crtc->lut_b[i] = i << 2;
2802 }
2803
2804 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2805
2806 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2807 amdgpu_crtc->adjusted_clock = 0;
2808 amdgpu_crtc->encoder = NULL;
2809 amdgpu_crtc->connector = NULL;
2810 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2811
2812 return 0;
2813}
2814
5fc3aeeb 2815static int dce_v8_0_early_init(void *handle)
a2e73f56 2816{
5fc3aeeb 2817 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2818
a2e73f56
AD		 2819 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2820 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2821
2822 dce_v8_0_set_display_funcs(adev);
2823 dce_v8_0_set_irq_funcs(adev);
2824
2825 switch (adev->asic_type) {
2826 case CHIP_BONAIRE:
2827 case CHIP_HAWAII:
2828 adev->mode_info.num_crtc = 6;
2829 adev->mode_info.num_hpd = 6;
2830 adev->mode_info.num_dig = 6;
2831 break;
2832 case CHIP_KAVERI:
2833 adev->mode_info.num_crtc = 4;
2834 adev->mode_info.num_hpd = 6;
2835 adev->mode_info.num_dig = 7;
2836 break;
2837 case CHIP_KABINI:
2838 case CHIP_MULLINS:
2839 adev->mode_info.num_crtc = 2;
2840 adev->mode_info.num_hpd = 6;
2841 adev->mode_info.num_dig = 6; /* ? */
2842 break;
2843 default:
2844 /* FIXME: not supported yet */
2845 return -EINVAL;
2846 }
2847
2848 return 0;
2849}
2850
5fc3aeeb 2851static int dce_v8_0_sw_init(void *handle)
a2e73f56
AD		 2852{
2853 int r, i;
5fc3aeeb 2854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2855
2856 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2857 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2858 if (r)
2859 return r;
2860 }
2861
2862 for (i = 8; i < 20; i += 2) {
2863 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2864 if (r)
2865 return r;
2866 }
2867
2868 /* HPD hotplug */
2869 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2870 if (r)
2871 return r;
2872
2873 adev->mode_info.mode_config_initialized = true;
2874
2875 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2876
2877 adev->ddev->mode_config.max_width = 16384;
2878 adev->ddev->mode_config.max_height = 16384;
2879
2880 adev->ddev->mode_config.preferred_depth = 24;
2881 adev->ddev->mode_config.prefer_shadow = 1;
2882
2883 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2884
2885 r = amdgpu_modeset_create_props(adev);
2886 if (r)
2887 return r;
2888
2889 adev->ddev->mode_config.max_width = 16384;
2890 adev->ddev->mode_config.max_height = 16384;
2891
2892 /* allocate crtcs */
2893 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2894 r = dce_v8_0_crtc_init(adev, i);
2895 if (r)
2896 return r;
2897 }
2898
2899 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2900 amdgpu_print_display_setup(adev->ddev);
2901 else
2902 return -EINVAL;
2903
2904 /* setup afmt */
2905 dce_v8_0_afmt_init(adev);
2906
2907 r = dce_v8_0_audio_init(adev);
2908 if (r)
2909 return r;
2910
2911 drm_kms_helper_poll_init(adev->ddev);
2912
2913 return r;
2914}
2915
5fc3aeeb 2916static int dce_v8_0_sw_fini(void *handle)
a2e73f56 2917{
5fc3aeeb 2918 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2919
a2e73f56
AD		 2920 kfree(adev->mode_info.bios_hardcoded_edid);
2921
2922 drm_kms_helper_poll_fini(adev->ddev);
2923
2924 dce_v8_0_audio_fini(adev);
2925
2926 dce_v8_0_afmt_fini(adev);
2927
2928 drm_mode_config_cleanup(adev->ddev);
2929 adev->mode_info.mode_config_initialized = false;
2930
2931 return 0;
2932}
2933
5fc3aeeb 2934static int dce_v8_0_hw_init(void *handle)
a2e73f56
AD		 2935{
2936 int i;
5fc3aeeb 2937 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2938
2939 /* init dig PHYs, disp eng pll */
2940 amdgpu_atombios_encoder_init_dig(adev);
2941 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2942
2943 /* initialize hpd */
2944 dce_v8_0_hpd_init(adev);
2945
2946 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2947 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2948 }
2949
2950 return 0;
2951}
2952
5fc3aeeb 2953static int dce_v8_0_hw_fini(void *handle)
a2e73f56
AD		 2954{
2955 int i;
5fc3aeeb 2956 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 2957
2958 dce_v8_0_hpd_fini(adev);
2959
2960 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2961 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2962 }
2963
2964 return 0;
2965}
2966
5fc3aeeb 2967static int dce_v8_0_suspend(void *handle)
a2e73f56 2968{
5fc3aeeb 2969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 2970
a2e73f56
AD		 2971 amdgpu_atombios_scratch_regs_save(adev);
2972
f9fff064 2973 return dce_v8_0_hw_fini(handle);
a2e73f56
AD		 2974}
2975
5fc3aeeb 2976static int dce_v8_0_resume(void *handle)
a2e73f56 2977{
5fc3aeeb 2978 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064
AD		 2979 int ret;
2980
2981 ret = dce_v8_0_hw_init(handle);
a2e73f56
AD		 2982
2983 amdgpu_atombios_scratch_regs_restore(adev);
2984
a2e73f56
AD		 2985 /* turn on the BL */
2986 if (adev->mode_info.bl_encoder) {
2987 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2988 adev->mode_info.bl_encoder);
2989 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2990 bl_level);
2991 }
2992
f9fff064 2993 return ret;
a2e73f56
AD		 2994}
2995
5fc3aeeb 2996static bool dce_v8_0_is_idle(void *handle)
a2e73f56 2997{
a2e73f56
AD		 2998 return true;
2999}
3000
5fc3aeeb 3001static int dce_v8_0_wait_for_idle(void *handle)
a2e73f56 3002{
a2e73f56
AD		 3003 return 0;
3004}
3005
5fc3aeeb 3006static void dce_v8_0_print_status(void *handle)
a2e73f56 3007{
5fc3aeeb 3008 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3009
a2e73f56
AD		 3010 dev_info(adev->dev, "DCE 8.x registers\n");
3011 /* XXX todo */
3012}
3013
5fc3aeeb 3014static int dce_v8_0_soft_reset(void *handle)
a2e73f56
AD		 3015{
3016 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 3018
3019 if (dce_v8_0_is_display_hung(adev))
3020 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3021
3022 if (srbm_soft_reset) {
5fc3aeeb 3023 dce_v8_0_print_status((void *)adev);
a2e73f56
AD		 3024
3025 tmp = RREG32(mmSRBM_SOFT_RESET);
3026 tmp |= srbm_soft_reset;
3027 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3028 WREG32(mmSRBM_SOFT_RESET, tmp);
3029 tmp = RREG32(mmSRBM_SOFT_RESET);
3030
3031 udelay(50);
3032
3033 tmp &= ~srbm_soft_reset;
3034 WREG32(mmSRBM_SOFT_RESET, tmp);
3035 tmp = RREG32(mmSRBM_SOFT_RESET);
3036
3037 /* Wait a little for things to settle down */
3038 udelay(50);
5fc3aeeb 3039 dce_v8_0_print_status((void *)adev);
a2e73f56
AD		 3040 }
3041 return 0;
3042}
3043
3044static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3045 int crtc,
3046 enum amdgpu_interrupt_state state)
3047{
3048 u32 reg_block, lb_interrupt_mask;
3049
3050 if (crtc >= adev->mode_info.num_crtc) {
3051 DRM_DEBUG("invalid crtc %d\n", crtc);
3052 return;
3053 }
3054
3055 switch (crtc) {
3056 case 0:
3057 reg_block = CRTC0_REGISTER_OFFSET;
3058 break;
3059 case 1:
3060 reg_block = CRTC1_REGISTER_OFFSET;
3061 break;
3062 case 2:
3063 reg_block = CRTC2_REGISTER_OFFSET;
3064 break;
3065 case 3:
3066 reg_block = CRTC3_REGISTER_OFFSET;
3067 break;
3068 case 4:
3069 reg_block = CRTC4_REGISTER_OFFSET;
3070 break;
3071 case 5:
3072 reg_block = CRTC5_REGISTER_OFFSET;
3073 break;
3074 default:
3075 DRM_DEBUG("invalid crtc %d\n", crtc);
3076 return;
3077 }
3078
3079 switch (state) {
3080 case AMDGPU_IRQ_STATE_DISABLE:
3081 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3082 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3083 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3084 break;
3085 case AMDGPU_IRQ_STATE_ENABLE:
3086 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3087 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3088 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3089 break;
3090 default:
3091 break;
3092 }
3093}
3094
3095static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3096 int crtc,
3097 enum amdgpu_interrupt_state state)
3098{
3099 u32 reg_block, lb_interrupt_mask;
3100
3101 if (crtc >= adev->mode_info.num_crtc) {
3102 DRM_DEBUG("invalid crtc %d\n", crtc);
3103 return;
3104 }
3105
3106 switch (crtc) {
3107 case 0:
3108 reg_block = CRTC0_REGISTER_OFFSET;
3109 break;
3110 case 1:
3111 reg_block = CRTC1_REGISTER_OFFSET;
3112 break;
3113 case 2:
3114 reg_block = CRTC2_REGISTER_OFFSET;
3115 break;
3116 case 3:
3117 reg_block = CRTC3_REGISTER_OFFSET;
3118 break;
3119 case 4:
3120 reg_block = CRTC4_REGISTER_OFFSET;
3121 break;
3122 case 5:
3123 reg_block = CRTC5_REGISTER_OFFSET;
3124 break;
3125 default:
3126 DRM_DEBUG("invalid crtc %d\n", crtc);
3127 return;
3128 }
3129
3130 switch (state) {
3131 case AMDGPU_IRQ_STATE_DISABLE:
3132 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3133 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3134 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3135 break;
3136 case AMDGPU_IRQ_STATE_ENABLE:
3137 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3138 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3139 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3140 break;
3141 default:
3142 break;
3143 }
3144}
3145
3146static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3147 struct amdgpu_irq_src *src,
3148 unsigned type,
3149 enum amdgpu_interrupt_state state)
3150{
3151 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3152
3153 switch (type) {
3154 case AMDGPU_HPD_1:
3155 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3156 break;
3157 case AMDGPU_HPD_2:
3158 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3159 break;
3160 case AMDGPU_HPD_3:
3161 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3162 break;
3163 case AMDGPU_HPD_4:
3164 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3165 break;
3166 case AMDGPU_HPD_5:
3167 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3168 break;
3169 case AMDGPU_HPD_6:
3170 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3171 break;
3172 default:
3173 DRM_DEBUG("invalid hdp %d\n", type);
3174 return 0;
3175 }
3176
3177 switch (state) {
3178 case AMDGPU_IRQ_STATE_DISABLE:
3179 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3180 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3181 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3182 break;
3183 case AMDGPU_IRQ_STATE_ENABLE:
3184 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3185 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3186 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3187 break;
3188 default:
3189 break;
3190 }
3191
3192 return 0;
3193}
3194
3195static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3196 struct amdgpu_irq_src *src,
3197 unsigned type,
3198 enum amdgpu_interrupt_state state)
3199{
3200 switch (type) {
3201 case AMDGPU_CRTC_IRQ_VBLANK1:
3202 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3203 break;
3204 case AMDGPU_CRTC_IRQ_VBLANK2:
3205 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3206 break;
3207 case AMDGPU_CRTC_IRQ_VBLANK3:
3208 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3209 break;
3210 case AMDGPU_CRTC_IRQ_VBLANK4:
3211 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3212 break;
3213 case AMDGPU_CRTC_IRQ_VBLANK5:
3214 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3215 break;
3216 case AMDGPU_CRTC_IRQ_VBLANK6:
3217 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3218 break;
3219 case AMDGPU_CRTC_IRQ_VLINE1:
3220 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3221 break;
3222 case AMDGPU_CRTC_IRQ_VLINE2:
3223 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3224 break;
3225 case AMDGPU_CRTC_IRQ_VLINE3:
3226 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3227 break;
3228 case AMDGPU_CRTC_IRQ_VLINE4:
3229 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3230 break;
3231 case AMDGPU_CRTC_IRQ_VLINE5:
3232 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3233 break;
3234 case AMDGPU_CRTC_IRQ_VLINE6:
3235 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3236 break;
3237 default:
3238 break;
3239 }
3240 return 0;
3241}
3242
3243static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3244 struct amdgpu_irq_src *source,
3245 struct amdgpu_iv_entry *entry)
3246{
3247 unsigned crtc = entry->src_id - 1;
3248 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3249 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3250
3251 switch (entry->src_data) {
3252 case 0: /* vblank */
bd833144 3253 if (disp_int & interrupt_status_offsets[crtc].vblank)
a2e73f56 3254 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
bd833144
MK		 3255 else
3256 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3257
3258 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3259 drm_handle_vblank(adev->ddev, crtc);
a2e73f56 3260 }
bd833144
MK		 3261 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3262
a2e73f56
AD		 3263 break;
3264 case 1: /* vline */
bd833144 3265 if (disp_int & interrupt_status_offsets[crtc].vline)
a2e73f56 3266 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
bd833144
MK		 3267 else
3268 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3269
3270 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3271
a2e73f56
AD		 3272 break;
3273 default:
3274 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3275 break;
3276 }
3277
3278 return 0;
3279}
3280
3281static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3282 struct amdgpu_irq_src *src,
3283 unsigned type,
3284 enum amdgpu_interrupt_state state)
3285{
7dfac896
AD		 3286 u32 reg;
3287
3288 if (type >= adev->mode_info.num_crtc) {
3289 DRM_ERROR("invalid pageflip crtc %d\n", type);
3290 return -EINVAL;
a2e73f56
AD		 3291 }
3292
7dfac896 3293 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
a2e73f56 3294 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3295 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3296 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56 3297 else
7dfac896
AD		 3298 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3299 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
a2e73f56
AD		 3300
3301 return 0;
3302}
3303
3304static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3305 struct amdgpu_irq_src *source,
3306 struct amdgpu_iv_entry *entry)
3307{
a2e73f56
AD		 3308 unsigned long flags;
3309 unsigned crtc_id;
3310 struct amdgpu_crtc *amdgpu_crtc;
3311 struct amdgpu_flip_work *works;
3312
3313 crtc_id = (entry->src_id - 8) >> 1;
3314 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3315
7dfac896
AD		 3316 if (crtc_id >= adev->mode_info.num_crtc) {
3317 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3318 return -EINVAL;
a2e73f56
AD		 3319 }
3320
7dfac896
AD		 3321 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3322 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3323 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3324 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
a2e73f56
AD		 3325
3326 /* IRQ could occur when in initial stage */
3327 if (amdgpu_crtc == NULL)
3328 return 0;
3329
3330 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3331 works = amdgpu_crtc->pflip_works;
3332 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3333 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3334 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3335 amdgpu_crtc->pflip_status,
3336 AMDGPU_FLIP_SUBMITTED);
3337 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3338 return 0;
3339 }
3340
3341 /* page flip completed. clean up */
3342 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3343 amdgpu_crtc->pflip_works = NULL;
3344
3345 /* wakeup usersapce */
3346 if (works->event)
3347 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3348
3349 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3350
3351 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3352 amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
3353 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3354
3355 return 0;
3356}
3357
3358static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361{
3362 uint32_t disp_int, mask, int_control, tmp;
3363 unsigned hpd;
3364
e922cfb1 3365 if (entry->src_data >= adev->mode_info.num_hpd) {
a2e73f56
AD		 3366 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3367 return 0;
3368 }
3369
3370 hpd = entry->src_data;
3371 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3372 mask = interrupt_status_offsets[hpd].hpd;
3373 int_control = hpd_int_control_offsets[hpd];
3374
3375 if (disp_int & mask) {
3376 tmp = RREG32(int_control);
3377 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3378 WREG32(int_control, tmp);
3379 schedule_work(&adev->hotplug_work);
3380 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3381 }
3382
3383 return 0;
3384
3385}
3386
5fc3aeeb 3387static int dce_v8_0_set_clockgating_state(void *handle,
3388 enum amd_clockgating_state state)
a2e73f56
AD		 3389{
3390 return 0;
3391}
3392
5fc3aeeb 3393static int dce_v8_0_set_powergating_state(void *handle,
3394 enum amd_powergating_state state)
a2e73f56
AD		 3395{
3396 return 0;
3397}
3398
5fc3aeeb 3399const struct amd_ip_funcs dce_v8_0_ip_funcs = {
a2e73f56
AD		 3400 .early_init = dce_v8_0_early_init,
3401 .late_init = NULL,
3402 .sw_init = dce_v8_0_sw_init,
3403 .sw_fini = dce_v8_0_sw_fini,
3404 .hw_init = dce_v8_0_hw_init,
3405 .hw_fini = dce_v8_0_hw_fini,
3406 .suspend = dce_v8_0_suspend,
3407 .resume = dce_v8_0_resume,
3408 .is_idle = dce_v8_0_is_idle,
3409 .wait_for_idle = dce_v8_0_wait_for_idle,
3410 .soft_reset = dce_v8_0_soft_reset,
3411 .print_status = dce_v8_0_print_status,
3412 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3413 .set_powergating_state = dce_v8_0_set_powergating_state,
3414};
3415
3416static void
3417dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3418 struct drm_display_mode *mode,
3419 struct drm_display_mode *adjusted_mode)
3420{
3421 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3422
3423 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3424
3425 /* need to call this here rather than in prepare() since we need some crtc info */
3426 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3427
3428 /* set scaler clears this on some chips */
3429 dce_v8_0_set_interleave(encoder->crtc, mode);
3430
3431 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3432 dce_v8_0_afmt_enable(encoder, true);
3433 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3434 }
3435}
3436
3437static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3438{
3439 struct amdgpu_device *adev = encoder->dev->dev_private;
3440 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3441 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3442
3443 if ((amdgpu_encoder->active_device &
3444 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3445 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3446 ENCODER_OBJECT_ID_NONE)) {
3447 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3448 if (dig) {
3449 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3450 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3451 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3452 }
3453 }
3454
3455 amdgpu_atombios_scratch_regs_lock(adev, true);
3456
3457 if (connector) {
3458 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3459
3460 /* select the clock/data port if it uses a router */
3461 if (amdgpu_connector->router.cd_valid)
3462 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3463
3464 /* turn eDP panel on for mode set */
3465 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3466 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3467 ATOM_TRANSMITTER_ACTION_POWER_ON);
3468 }
3469
3470 /* this is needed for the pll/ss setup to work correctly in some cases */
3471 amdgpu_atombios_encoder_set_crtc_source(encoder);
3472 /* set up the FMT blocks */
3473 dce_v8_0_program_fmt(encoder);
3474}
3475
3476static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3477{
3478 struct drm_device *dev = encoder->dev;
3479 struct amdgpu_device *adev = dev->dev_private;
3480
3481 /* need to call this here as we need the crtc set up */
3482 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3483 amdgpu_atombios_scratch_regs_lock(adev, false);
3484}
3485
3486static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3487{
3488 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3489 struct amdgpu_encoder_atom_dig *dig;
3490
3491 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3492
3493 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3494 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3495 dce_v8_0_afmt_enable(encoder, false);
3496 dig = amdgpu_encoder->enc_priv;
3497 dig->dig_encoder = -1;
3498 }
3499 amdgpu_encoder->active_device = 0;
3500}
3501
3502/* these are handled by the primary encoders */
3503static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3504{
3505
3506}
3507
3508static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3509{
3510
3511}
3512
3513static void
3514dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3515 struct drm_display_mode *mode,
3516 struct drm_display_mode *adjusted_mode)
3517{
3518
3519}
3520
3521static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3522{
3523
3524}
3525
3526static void
3527dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3528{
3529
3530}
3531
3532static bool dce_v8_0_ext_mode_fixup(struct drm_encoder *encoder,
3533 const struct drm_display_mode *mode,
3534 struct drm_display_mode *adjusted_mode)
3535{
3536 return true;
3537}
3538
3539static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3540 .dpms = dce_v8_0_ext_dpms,
3541 .mode_fixup = dce_v8_0_ext_mode_fixup,
3542 .prepare = dce_v8_0_ext_prepare,
3543 .mode_set = dce_v8_0_ext_mode_set,
3544 .commit = dce_v8_0_ext_commit,
3545 .disable = dce_v8_0_ext_disable,
3546 /* no detect for TMDS/LVDS yet */
3547};
3548
3549static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3550 .dpms = amdgpu_atombios_encoder_dpms,
3551 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3552 .prepare = dce_v8_0_encoder_prepare,
3553 .mode_set = dce_v8_0_encoder_mode_set,
3554 .commit = dce_v8_0_encoder_commit,
3555 .disable = dce_v8_0_encoder_disable,
3556 .detect = amdgpu_atombios_encoder_dig_detect,
3557};
3558
3559static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3560 .dpms = amdgpu_atombios_encoder_dpms,
3561 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3562 .prepare = dce_v8_0_encoder_prepare,
3563 .mode_set = dce_v8_0_encoder_mode_set,
3564 .commit = dce_v8_0_encoder_commit,
3565 .detect = amdgpu_atombios_encoder_dac_detect,
3566};
3567
3568static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3569{
3570 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3571 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3572 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3573 kfree(amdgpu_encoder->enc_priv);
3574 drm_encoder_cleanup(encoder);
3575 kfree(amdgpu_encoder);
3576}
3577
3578static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3579 .destroy = dce_v8_0_encoder_destroy,
3580};
3581
3582static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3583 uint32_t encoder_enum,
3584 uint32_t supported_device,
3585 u16 caps)
3586{
3587 struct drm_device *dev = adev->ddev;
3588 struct drm_encoder *encoder;
3589 struct amdgpu_encoder *amdgpu_encoder;
3590
3591 /* see if we already added it */
3592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3593 amdgpu_encoder = to_amdgpu_encoder(encoder);
3594 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3595 amdgpu_encoder->devices |= supported_device;
3596 return;
3597 }
3598
3599 }
3600
3601 /* add a new one */
3602 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3603 if (!amdgpu_encoder)
3604 return;
3605
3606 encoder = &amdgpu_encoder->base;
3607 switch (adev->mode_info.num_crtc) {
3608 case 1:
3609 encoder->possible_crtcs = 0x1;
3610 break;
3611 case 2:
3612 default:
3613 encoder->possible_crtcs = 0x3;
3614 break;
3615 case 4:
3616 encoder->possible_crtcs = 0xf;
3617 break;
3618 case 6:
3619 encoder->possible_crtcs = 0x3f;
3620 break;
3621 }
3622
3623 amdgpu_encoder->enc_priv = NULL;
3624
3625 amdgpu_encoder->encoder_enum = encoder_enum;
3626 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3627 amdgpu_encoder->devices = supported_device;
3628 amdgpu_encoder->rmx_type = RMX_OFF;
3629 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3630 amdgpu_encoder->is_ext_encoder = false;
3631 amdgpu_encoder->caps = caps;
3632
3633 switch (amdgpu_encoder->encoder_id) {
3634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3635 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3636 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3637 DRM_MODE_ENCODER_DAC);
3638 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3639 break;
3640 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3641 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3642 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3643 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3644 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3645 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3646 amdgpu_encoder->rmx_type = RMX_FULL;
3647 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3648 DRM_MODE_ENCODER_LVDS);
3649 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3650 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3651 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3652 DRM_MODE_ENCODER_DAC);
3653 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3654 } else {
3655 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3656 DRM_MODE_ENCODER_TMDS);
3657 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3658 }
3659 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3660 break;
3661 case ENCODER_OBJECT_ID_SI170B:
3662 case ENCODER_OBJECT_ID_CH7303:
3663 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3664 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3665 case ENCODER_OBJECT_ID_TITFP513:
3666 case ENCODER_OBJECT_ID_VT1623:
3667 case ENCODER_OBJECT_ID_HDMI_SI1930:
3668 case ENCODER_OBJECT_ID_TRAVIS:
3669 case ENCODER_OBJECT_ID_NUTMEG:
3670 /* these are handled by the primary encoders */
3671 amdgpu_encoder->is_ext_encoder = true;
3672 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3673 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3674 DRM_MODE_ENCODER_LVDS);
3675 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3676 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3677 DRM_MODE_ENCODER_DAC);
3678 else
3679 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3680 DRM_MODE_ENCODER_TMDS);
3681 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3682 break;
3683 }
3684}
3685
3686static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3687 .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3688 .bandwidth_update = &dce_v8_0_bandwidth_update,
3689 .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3690 .vblank_wait = &dce_v8_0_vblank_wait,
3691 .is_display_hung = &dce_v8_0_is_display_hung,
3692 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3693 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3694 .hpd_sense = &dce_v8_0_hpd_sense,
3695 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3696 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3697 .page_flip = &dce_v8_0_page_flip,
3698 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3699 .add_encoder = &dce_v8_0_encoder_add,
3700 .add_connector = &amdgpu_connector_add,
3701 .stop_mc_access = &dce_v8_0_stop_mc_access,
3702 .resume_mc_access = &dce_v8_0_resume_mc_access,
3703};
3704
3705static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3706{
3707 if (adev->mode_info.funcs == NULL)
3708 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3709}
3710
3711static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3712 .set = dce_v8_0_set_crtc_interrupt_state,
3713 .process = dce_v8_0_crtc_irq,
3714};
3715
3716static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3717 .set = dce_v8_0_set_pageflip_interrupt_state,
3718 .process = dce_v8_0_pageflip_irq,
3719};
3720
3721static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3722 .set = dce_v8_0_set_hpd_interrupt_state,
3723 .process = dce_v8_0_hpd_irq,
3724};
3725
3726static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3727{
3728 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3729 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3730
3731 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3732 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3733
3734 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3735 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3736}
Linux 6.x block layer and io_uring tree(s)