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drm/amdgpu: add ELM/BAF DCE11 configs (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_11_0_d.h"
36#include "dce/dce_11_0_sh_mask.h"
37#include "dce/dce_11_0_enum.h"
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42
43static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
45
46static const u32 crtc_offsets[] =
47{
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55};
56
57static const u32 hpd_offsets[] =
58{
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65};
66
67static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET,
75 DIG7_REGISTER_OFFSET,
76 DIG8_REGISTER_OFFSET
77};
78
79static const struct {
80 uint32_t reg;
81 uint32_t vblank;
82 uint32_t vline;
83 uint32_t hpd;
84
85} interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
90}, {
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
95}, {
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
100}, {
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
105}, {
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
110}, {
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115} };
116
117static const u32 cz_golden_settings_a11[] =
118{
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
121};
122
5732a94f
AD		 123static const u32 cz_mgcg_cgcg_init[] =
124{
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
fa2f9bef
SL		 129static const u32 stoney_golden_settings_a11[] =
130{
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
133};
134
135
aaa36a97
AD		 136static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
137{
138 switch (adev->asic_type) {
139 case CHIP_CARRIZO:
5732a94f
AD		 140 amdgpu_program_register_sequence(adev,
141 cz_mgcg_cgcg_init,
142 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
aaa36a97
AD		 143 amdgpu_program_register_sequence(adev,
144 cz_golden_settings_a11,
145 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
146 break;
fa2f9bef
SL		 147 case CHIP_STONEY:
148 amdgpu_program_register_sequence(adev,
149 stoney_golden_settings_a11,
150 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
151 break;
aaa36a97
AD		 152 default:
153 break;
154 }
155}
156
157static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
158 u32 block_offset, u32 reg)
159{
160 unsigned long flags;
161 u32 r;
162
163 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
164 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
166 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
167
168 return r;
169}
170
171static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
172 u32 block_offset, u32 reg, u32 v)
173{
174 unsigned long flags;
175
176 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
177 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
178 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
179 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
180}
181
182static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
183{
184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
185 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
186 return true;
187 else
188 return false;
189}
190
191static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
192{
193 u32 pos1, pos2;
194
195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
197
198 if (pos1 != pos2)
199 return true;
200 else
201 return false;
202}
203
204/**
205 * dce_v11_0_vblank_wait - vblank wait asic callback.
206 *
207 * @adev: amdgpu_device pointer
208 * @crtc: crtc to wait for vblank on
209 *
210 * Wait for vblank on the requested crtc (evergreen+).
211 */
212static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
213{
9e4e1ae8 214 unsigned i = 100;
aaa36a97 215
15c3277f 216 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
aaa36a97
AD		 217 return;
218
219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
220 return;
221
222 /* depending on when we hit vblank, we may be close to active; if so,
223 * wait for another frame.
224 */
225 while (dce_v11_0_is_in_vblank(adev, crtc)) {
9e4e1ae8
TSD		 226 if (i++ == 100) {
227 i = 0;
aaa36a97
AD		 228 if (!dce_v11_0_is_counter_moving(adev, crtc))
229 break;
230 }
231 }
232
233 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
9e4e1ae8
TSD		 234 if (i++ == 100) {
235 i = 0;
aaa36a97
AD		 236 if (!dce_v11_0_is_counter_moving(adev, crtc))
237 break;
238 }
239 }
240}
241
242static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
243{
15c3277f 244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
aaa36a97
AD		 245 return 0;
246 else
247 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
248}
249
f6c7aba4
MD		 250static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
251{
252 unsigned i;
253
254 /* Enable pflip interrupts */
255 for (i = 0; i < adev->mode_info.num_crtc; i++)
256 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
257}
258
259static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
260{
261 unsigned i;
262
263 /* Disable pflip interrupts */
264 for (i = 0; i < adev->mode_info.num_crtc; i++)
265 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
266}
267
aaa36a97
AD		 268/**
269 * dce_v11_0_page_flip - pageflip callback.
270 *
271 * @adev: amdgpu_device pointer
272 * @crtc_id: crtc to cleanup pageflip on
273 * @crtc_base: new address of the crtc (GPU MC address)
274 *
ce055fe3
AD		 275 * Triggers the actual pageflip by updating the primary
276 * surface base address.
aaa36a97
AD		 277 */
278static void dce_v11_0_page_flip(struct amdgpu_device *adev,
279 int crtc_id, u64 crtc_base)
280{
281 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
aaa36a97
AD		 282
283 /* update the scanout addresses */
aaa36a97
AD		 284 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
285 upper_32_bits(crtc_base));
ce055fe3 286 /* writing to the low address triggers the update */
aaa36a97
AD		 287 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
288 lower_32_bits(crtc_base));
ce055fe3
AD		 289 /* post the write */
290 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
aaa36a97
AD		 291}
292
293static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
294 u32 *vbl, u32 *position)
295{
296 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
297 return -EINVAL;
298
299 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
300 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
301
302 return 0;
303}
304
305/**
306 * dce_v11_0_hpd_sense - hpd sense callback.
307 *
308 * @adev: amdgpu_device pointer
309 * @hpd: hpd (hotplug detect) pin
310 *
311 * Checks if a digital monitor is connected (evergreen+).
312 * Returns true if connected, false if not connected.
313 */
314static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
315 enum amdgpu_hpd_id hpd)
316{
317 int idx;
318 bool connected = false;
319
320 switch (hpd) {
321 case AMDGPU_HPD_1:
322 idx = 0;
323 break;
324 case AMDGPU_HPD_2:
325 idx = 1;
326 break;
327 case AMDGPU_HPD_3:
328 idx = 2;
329 break;
330 case AMDGPU_HPD_4:
331 idx = 3;
332 break;
333 case AMDGPU_HPD_5:
334 idx = 4;
335 break;
336 case AMDGPU_HPD_6:
337 idx = 5;
338 break;
339 default:
340 return connected;
341 }
342
343 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
344 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
345 connected = true;
346
347 return connected;
348}
349
350/**
351 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
352 *
353 * @adev: amdgpu_device pointer
354 * @hpd: hpd (hotplug detect) pin
355 *
356 * Set the polarity of the hpd pin (evergreen+).
357 */
358static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
359 enum amdgpu_hpd_id hpd)
360{
361 u32 tmp;
362 bool connected = dce_v11_0_hpd_sense(adev, hpd);
363 int idx;
364
365 switch (hpd) {
366 case AMDGPU_HPD_1:
367 idx = 0;
368 break;
369 case AMDGPU_HPD_2:
370 idx = 1;
371 break;
372 case AMDGPU_HPD_3:
373 idx = 2;
374 break;
375 case AMDGPU_HPD_4:
376 idx = 3;
377 break;
378 case AMDGPU_HPD_5:
379 idx = 4;
380 break;
381 case AMDGPU_HPD_6:
382 idx = 5;
383 break;
384 default:
385 return;
386 }
387
388 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
389 if (connected)
390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
391 else
392 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
393 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
394}
395
396/**
397 * dce_v11_0_hpd_init - hpd setup callback.
398 *
399 * @adev: amdgpu_device pointer
400 *
401 * Setup the hpd pins used by the card (evergreen+).
402 * Enable the pin, set the polarity, and enable the hpd interrupts.
403 */
404static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
405{
406 struct drm_device *dev = adev->ddev;
407 struct drm_connector *connector;
408 u32 tmp;
409 int idx;
410
411 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
412 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
413
414 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
415 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
416 /* don't try to enable hpd on eDP or LVDS avoid breaking the
417 * aux dp channel on imac and help (but not completely fix)
418 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
419 * also avoid interrupt storms during dpms.
420 */
421 continue;
422 }
423
424 switch (amdgpu_connector->hpd.hpd) {
425 case AMDGPU_HPD_1:
426 idx = 0;
427 break;
428 case AMDGPU_HPD_2:
429 idx = 1;
430 break;
431 case AMDGPU_HPD_3:
432 idx = 2;
433 break;
434 case AMDGPU_HPD_4:
435 idx = 3;
436 break;
437 case AMDGPU_HPD_5:
438 idx = 4;
439 break;
440 case AMDGPU_HPD_6:
441 idx = 5;
442 break;
443 default:
444 continue;
445 }
446
447 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
448 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
449 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
450
451 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
452 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
453 DC_HPD_CONNECT_INT_DELAY,
454 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
455 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
456 DC_HPD_DISCONNECT_INT_DELAY,
457 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
458 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
459
460 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
461 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
462 }
463}
464
465/**
466 * dce_v11_0_hpd_fini - hpd tear down callback.
467 *
468 * @adev: amdgpu_device pointer
469 *
470 * Tear down the hpd pins used by the card (evergreen+).
471 * Disable the hpd interrupts.
472 */
473static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
474{
475 struct drm_device *dev = adev->ddev;
476 struct drm_connector *connector;
477 u32 tmp;
478 int idx;
479
480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
481 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
482
483 switch (amdgpu_connector->hpd.hpd) {
484 case AMDGPU_HPD_1:
485 idx = 0;
486 break;
487 case AMDGPU_HPD_2:
488 idx = 1;
489 break;
490 case AMDGPU_HPD_3:
491 idx = 2;
492 break;
493 case AMDGPU_HPD_4:
494 idx = 3;
495 break;
496 case AMDGPU_HPD_5:
497 idx = 4;
498 break;
499 case AMDGPU_HPD_6:
500 idx = 5;
501 break;
502 default:
503 continue;
504 }
505
506 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
507 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
508 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
509
510 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
511 }
512}
513
514static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
515{
516 return mmDC_GPIO_HPD_A;
517}
518
519static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
520{
521 u32 crtc_hung = 0;
522 u32 crtc_status[6];
523 u32 i, j, tmp;
524
525 for (i = 0; i < adev->mode_info.num_crtc; i++) {
526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
527 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
528 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
529 crtc_hung |= (1 << i);
530 }
531 }
532
533 for (j = 0; j < 10; j++) {
534 for (i = 0; i < adev->mode_info.num_crtc; i++) {
535 if (crtc_hung & (1 << i)) {
536 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
537 if (tmp != crtc_status[i])
538 crtc_hung &= ~(1 << i);
539 }
540 }
541 if (crtc_hung == 0)
542 return false;
543 udelay(100);
544 }
545
546 return true;
547}
548
549static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
550 struct amdgpu_mode_mc_save *save)
551{
552 u32 crtc_enabled, tmp;
553 int i;
554
555 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
556 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
557
558 /* disable VGA render */
559 tmp = RREG32(mmVGA_RENDER_CONTROL);
560 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
561 WREG32(mmVGA_RENDER_CONTROL, tmp);
562
563 /* blank the display controllers */
564 for (i = 0; i < adev->mode_info.num_crtc; i++) {
565 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
566 CRTC_CONTROL, CRTC_MASTER_EN);
567 if (crtc_enabled) {
01c02a8b 568#if 1
aaa36a97
AD		 569 save->crtc_enabled[i] = true;
570 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
571 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
01c02a8b
VP		 572 /*it is correct only for RGB ; black is 0*/
573 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
aaa36a97
AD		 574 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
575 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
aaa36a97
AD		 576 }
577#else
578 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
579 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
580 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
581 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
582 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
583 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
584 save->crtc_enabled[i] = false;
585 /* ***** */
586#endif
587 } else {
588 save->crtc_enabled[i] = false;
589 }
590 }
591}
592
593static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
594 struct amdgpu_mode_mc_save *save)
595{
01c02a8b
VP		 596 u32 tmp;
597 int i;
aaa36a97
AD		 598
599 /* update crtc base addresses */
600 for (i = 0; i < adev->mode_info.num_crtc; i++) {
601 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
602 upper_32_bits(adev->mc.vram_start));
aaa36a97
AD		 603 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
604 (u32)adev->mc.vram_start);
aaa36a97
AD		 605
606 if (save->crtc_enabled[i]) {
aaa36a97
AD		 607 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
608 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
aaa36a97 609 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
aaa36a97
AD		 610 }
611 }
612
613 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
614 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
615
616 /* Unlock vga access */
617 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
618 mdelay(1);
619 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
620}
621
622static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
623 bool render)
624{
625 u32 tmp;
626
627 /* Lockout access through VGA aperture*/
628 tmp = RREG32(mmVGA_HDP_CONTROL);
629 if (render)
630 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
631 else
632 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
633 WREG32(mmVGA_HDP_CONTROL, tmp);
634
635 /* disable VGA render */
636 tmp = RREG32(mmVGA_RENDER_CONTROL);
637 if (render)
638 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
639 else
640 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
641 WREG32(mmVGA_RENDER_CONTROL, tmp);
642}
643
644static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
645{
646 struct drm_device *dev = encoder->dev;
647 struct amdgpu_device *adev = dev->dev_private;
648 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
649 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
650 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
651 int bpc = 0;
652 u32 tmp = 0;
653 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
654
655 if (connector) {
656 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
657 bpc = amdgpu_connector_get_monitor_bpc(connector);
658 dither = amdgpu_connector->dither;
659 }
660
661 /* LVDS/eDP FMT is set up by atom */
662 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
663 return;
664
665 /* not needed for analog */
666 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
667 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
668 return;
669
670 if (bpc == 0)
671 return;
672
673 switch (bpc) {
674 case 6:
675 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
676 /* XXX sort out optimal dither settings */
677 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
681 } else {
682 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
684 }
685 break;
686 case 8:
687 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
688 /* XXX sort out optimal dither settings */
689 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
694 } else {
695 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
697 }
698 break;
699 case 10:
700 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
701 /* XXX sort out optimal dither settings */
702 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
707 } else {
708 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
710 }
711 break;
712 default:
713 /* not needed */
714 break;
715 }
716
717 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
718}
719
720
721/* display watermark setup */
722/**
723 * dce_v11_0_line_buffer_adjust - Set up the line buffer
724 *
725 * @adev: amdgpu_device pointer
726 * @amdgpu_crtc: the selected display controller
727 * @mode: the current display mode on the selected display
728 * controller
729 *
730 * Setup up the line buffer allocation for
731 * the selected display controller (CIK).
732 * Returns the line buffer size in pixels.
733 */
734static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
735 struct amdgpu_crtc *amdgpu_crtc,
736 struct drm_display_mode *mode)
737{
738 u32 tmp, buffer_alloc, i, mem_cfg;
739 u32 pipe_offset = amdgpu_crtc->crtc_id;
740 /*
741 * Line Buffer Setup
742 * There are 6 line buffers, one for each display controllers.
743 * There are 3 partitions per LB. Select the number of partitions
744 * to enable based on the display width. For display widths larger
745 * than 4096, you need use to use 2 display controllers and combine
746 * them using the stereo blender.
747 */
748 if (amdgpu_crtc->base.enabled && mode) {
749 if (mode->crtc_hdisplay < 1920) {
750 mem_cfg = 1;
751 buffer_alloc = 2;
752 } else if (mode->crtc_hdisplay < 2560) {
753 mem_cfg = 2;
754 buffer_alloc = 2;
755 } else if (mode->crtc_hdisplay < 4096) {
756 mem_cfg = 0;
2f7d10b3 757 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 758 } else {
759 DRM_DEBUG_KMS("Mode too big for LB!\n");
760 mem_cfg = 0;
2f7d10b3 761 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 762 }
763 } else {
764 mem_cfg = 1;
765 buffer_alloc = 0;
766 }
767
768 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
769 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
770 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
771
772 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
773 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
774 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
775
776 for (i = 0; i < adev->usec_timeout; i++) {
777 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
778 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
779 break;
780 udelay(1);
781 }
782
783 if (amdgpu_crtc->base.enabled && mode) {
784 switch (mem_cfg) {
785 case 0:
786 default:
787 return 4096 * 2;
788 case 1:
789 return 1920 * 2;
790 case 2:
791 return 2560 * 2;
792 }
793 }
794
795 /* controller not enabled, so no lb used */
796 return 0;
797}
798
799/**
800 * cik_get_number_of_dram_channels - get the number of dram channels
801 *
802 * @adev: amdgpu_device pointer
803 *
804 * Look up the number of video ram channels (CIK).
805 * Used for display watermark bandwidth calculations
806 * Returns the number of dram channels
807 */
808static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
809{
810 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
811
812 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
813 case 0:
814 default:
815 return 1;
816 case 1:
817 return 2;
818 case 2:
819 return 4;
820 case 3:
821 return 8;
822 case 4:
823 return 3;
824 case 5:
825 return 6;
826 case 6:
827 return 10;
828 case 7:
829 return 12;
830 case 8:
831 return 16;
832 }
833}
834
835struct dce10_wm_params {
836 u32 dram_channels; /* number of dram channels */
837 u32 yclk; /* bandwidth per dram data pin in kHz */
838 u32 sclk; /* engine clock in kHz */
839 u32 disp_clk; /* display clock in kHz */
840 u32 src_width; /* viewport width */
841 u32 active_time; /* active display time in ns */
842 u32 blank_time; /* blank time in ns */
843 bool interlaced; /* mode is interlaced */
844 fixed20_12 vsc; /* vertical scale ratio */
845 u32 num_heads; /* number of active crtcs */
846 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
847 u32 lb_size; /* line buffer allocated to pipe */
848 u32 vtaps; /* vertical scaler taps */
849};
850
851/**
852 * dce_v11_0_dram_bandwidth - get the dram bandwidth
853 *
854 * @wm: watermark calculation data
855 *
856 * Calculate the raw dram bandwidth (CIK).
857 * Used for display watermark bandwidth calculations
858 * Returns the dram bandwidth in MBytes/s
859 */
860static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
861{
862 /* Calculate raw DRAM Bandwidth */
863 fixed20_12 dram_efficiency; /* 0.7 */
864 fixed20_12 yclk, dram_channels, bandwidth;
865 fixed20_12 a;
866
867 a.full = dfixed_const(1000);
868 yclk.full = dfixed_const(wm->yclk);
869 yclk.full = dfixed_div(yclk, a);
870 dram_channels.full = dfixed_const(wm->dram_channels * 4);
871 a.full = dfixed_const(10);
872 dram_efficiency.full = dfixed_const(7);
873 dram_efficiency.full = dfixed_div(dram_efficiency, a);
874 bandwidth.full = dfixed_mul(dram_channels, yclk);
875 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
876
877 return dfixed_trunc(bandwidth);
878}
879
880/**
881 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
882 *
883 * @wm: watermark calculation data
884 *
885 * Calculate the dram bandwidth used for display (CIK).
886 * Used for display watermark bandwidth calculations
887 * Returns the dram bandwidth for display in MBytes/s
888 */
889static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
890{
891 /* Calculate DRAM Bandwidth and the part allocated to display. */
892 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
893 fixed20_12 yclk, dram_channels, bandwidth;
894 fixed20_12 a;
895
896 a.full = dfixed_const(1000);
897 yclk.full = dfixed_const(wm->yclk);
898 yclk.full = dfixed_div(yclk, a);
899 dram_channels.full = dfixed_const(wm->dram_channels * 4);
900 a.full = dfixed_const(10);
901 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
902 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
903 bandwidth.full = dfixed_mul(dram_channels, yclk);
904 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
905
906 return dfixed_trunc(bandwidth);
907}
908
909/**
910 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
911 *
912 * @wm: watermark calculation data
913 *
914 * Calculate the data return bandwidth used for display (CIK).
915 * Used for display watermark bandwidth calculations
916 * Returns the data return bandwidth in MBytes/s
917 */
918static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
919{
920 /* Calculate the display Data return Bandwidth */
921 fixed20_12 return_efficiency; /* 0.8 */
922 fixed20_12 sclk, bandwidth;
923 fixed20_12 a;
924
925 a.full = dfixed_const(1000);
926 sclk.full = dfixed_const(wm->sclk);
927 sclk.full = dfixed_div(sclk, a);
928 a.full = dfixed_const(10);
929 return_efficiency.full = dfixed_const(8);
930 return_efficiency.full = dfixed_div(return_efficiency, a);
931 a.full = dfixed_const(32);
932 bandwidth.full = dfixed_mul(a, sclk);
933 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
934
935 return dfixed_trunc(bandwidth);
936}
937
938/**
939 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
940 *
941 * @wm: watermark calculation data
942 *
943 * Calculate the dmif bandwidth used for display (CIK).
944 * Used for display watermark bandwidth calculations
945 * Returns the dmif bandwidth in MBytes/s
946 */
947static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
948{
949 /* Calculate the DMIF Request Bandwidth */
950 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
951 fixed20_12 disp_clk, bandwidth;
952 fixed20_12 a, b;
953
954 a.full = dfixed_const(1000);
955 disp_clk.full = dfixed_const(wm->disp_clk);
956 disp_clk.full = dfixed_div(disp_clk, a);
957 a.full = dfixed_const(32);
958 b.full = dfixed_mul(a, disp_clk);
959
960 a.full = dfixed_const(10);
961 disp_clk_request_efficiency.full = dfixed_const(8);
962 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
963
964 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
965
966 return dfixed_trunc(bandwidth);
967}
968
969/**
970 * dce_v11_0_available_bandwidth - get the min available bandwidth
971 *
972 * @wm: watermark calculation data
973 *
974 * Calculate the min available bandwidth used for display (CIK).
975 * Used for display watermark bandwidth calculations
976 * Returns the min available bandwidth in MBytes/s
977 */
978static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
979{
980 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
981 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
982 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
983 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
984
985 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
986}
987
988/**
989 * dce_v11_0_average_bandwidth - get the average available bandwidth
990 *
991 * @wm: watermark calculation data
992 *
993 * Calculate the average available bandwidth used for display (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns the average available bandwidth in MBytes/s
996 */
997static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
998{
999 /* Calculate the display mode Average Bandwidth
1000 * DisplayMode should contain the source and destination dimensions,
1001 * timing, etc.
1002 */
1003 fixed20_12 bpp;
1004 fixed20_12 line_time;
1005 fixed20_12 src_width;
1006 fixed20_12 bandwidth;
1007 fixed20_12 a;
1008
1009 a.full = dfixed_const(1000);
1010 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1011 line_time.full = dfixed_div(line_time, a);
1012 bpp.full = dfixed_const(wm->bytes_per_pixel);
1013 src_width.full = dfixed_const(wm->src_width);
1014 bandwidth.full = dfixed_mul(src_width, bpp);
1015 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1016 bandwidth.full = dfixed_div(bandwidth, line_time);
1017
1018 return dfixed_trunc(bandwidth);
1019}
1020
1021/**
1022 * dce_v11_0_latency_watermark - get the latency watermark
1023 *
1024 * @wm: watermark calculation data
1025 *
1026 * Calculate the latency watermark (CIK).
1027 * Used for display watermark bandwidth calculations
1028 * Returns the latency watermark in ns
1029 */
1030static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1031{
1032 /* First calculate the latency in ns */
1033 u32 mc_latency = 2000; /* 2000 ns. */
1034 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1035 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1036 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1037 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1038 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1039 (wm->num_heads * cursor_line_pair_return_time);
1040 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1041 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1042 u32 tmp, dmif_size = 12288;
1043 fixed20_12 a, b, c;
1044
1045 if (wm->num_heads == 0)
1046 return 0;
1047
1048 a.full = dfixed_const(2);
1049 b.full = dfixed_const(1);
1050 if ((wm->vsc.full > a.full) ||
1051 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1052 (wm->vtaps >= 5) ||
1053 ((wm->vsc.full >= a.full) && wm->interlaced))
1054 max_src_lines_per_dst_line = 4;
1055 else
1056 max_src_lines_per_dst_line = 2;
1057
1058 a.full = dfixed_const(available_bandwidth);
1059 b.full = dfixed_const(wm->num_heads);
1060 a.full = dfixed_div(a, b);
1061
1062 b.full = dfixed_const(mc_latency + 512);
1063 c.full = dfixed_const(wm->disp_clk);
1064 b.full = dfixed_div(b, c);
1065
1066 c.full = dfixed_const(dmif_size);
1067 b.full = dfixed_div(c, b);
1068
1069 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1070
1071 b.full = dfixed_const(1000);
1072 c.full = dfixed_const(wm->disp_clk);
1073 b.full = dfixed_div(c, b);
1074 c.full = dfixed_const(wm->bytes_per_pixel);
1075 b.full = dfixed_mul(b, c);
1076
1077 lb_fill_bw = min(tmp, dfixed_trunc(b));
1078
1079 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1080 b.full = dfixed_const(1000);
1081 c.full = dfixed_const(lb_fill_bw);
1082 b.full = dfixed_div(c, b);
1083 a.full = dfixed_div(a, b);
1084 line_fill_time = dfixed_trunc(a);
1085
1086 if (line_fill_time < wm->active_time)
1087 return latency;
1088 else
1089 return latency + (line_fill_time - wm->active_time);
1090
1091}
1092
1093/**
1094 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1095 * average and available dram bandwidth
1096 *
1097 * @wm: watermark calculation data
1098 *
1099 * Check if the display average bandwidth fits in the display
1100 * dram bandwidth (CIK).
1101 * Used for display watermark bandwidth calculations
1102 * Returns true if the display fits, false if not.
1103 */
1104static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1105{
1106 if (dce_v11_0_average_bandwidth(wm) <=
1107 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1108 return true;
1109 else
1110 return false;
1111}
1112
1113/**
1114 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1115 * average and available bandwidth
1116 *
1117 * @wm: watermark calculation data
1118 *
1119 * Check if the display average bandwidth fits in the display
1120 * available bandwidth (CIK).
1121 * Used for display watermark bandwidth calculations
1122 * Returns true if the display fits, false if not.
1123 */
1124static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1125{
1126 if (dce_v11_0_average_bandwidth(wm) <=
1127 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1128 return true;
1129 else
1130 return false;
1131}
1132
1133/**
1134 * dce_v11_0_check_latency_hiding - check latency hiding
1135 *
1136 * @wm: watermark calculation data
1137 *
1138 * Check latency hiding (CIK).
1139 * Used for display watermark bandwidth calculations
1140 * Returns true if the display fits, false if not.
1141 */
1142static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1143{
1144 u32 lb_partitions = wm->lb_size / wm->src_width;
1145 u32 line_time = wm->active_time + wm->blank_time;
1146 u32 latency_tolerant_lines;
1147 u32 latency_hiding;
1148 fixed20_12 a;
1149
1150 a.full = dfixed_const(1);
1151 if (wm->vsc.full > a.full)
1152 latency_tolerant_lines = 1;
1153 else {
1154 if (lb_partitions <= (wm->vtaps + 1))
1155 latency_tolerant_lines = 1;
1156 else
1157 latency_tolerant_lines = 2;
1158 }
1159
1160 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1161
1162 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1163 return true;
1164 else
1165 return false;
1166}
1167
1168/**
1169 * dce_v11_0_program_watermarks - program display watermarks
1170 *
1171 * @adev: amdgpu_device pointer
1172 * @amdgpu_crtc: the selected display controller
1173 * @lb_size: line buffer size
1174 * @num_heads: number of display controllers in use
1175 *
1176 * Calculate and program the display watermarks for the
1177 * selected display controller (CIK).
1178 */
1179static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1180 struct amdgpu_crtc *amdgpu_crtc,
1181 u32 lb_size, u32 num_heads)
1182{
1183 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1184 struct dce10_wm_params wm_low, wm_high;
1185 u32 pixel_period;
1186 u32 line_time = 0;
1187 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1188 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
aaa36a97
AD		 1189
1190 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1191 pixel_period = 1000000 / (u32)mode->clock;
1192 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1193
1194 /* watermark for high clocks */
1195 if (adev->pm.dpm_enabled) {
1196 wm_high.yclk =
1197 amdgpu_dpm_get_mclk(adev, false) * 10;
1198 wm_high.sclk =
1199 amdgpu_dpm_get_sclk(adev, false) * 10;
1200 } else {
1201 wm_high.yclk = adev->pm.current_mclk * 10;
1202 wm_high.sclk = adev->pm.current_sclk * 10;
1203 }
1204
1205 wm_high.disp_clk = mode->clock;
1206 wm_high.src_width = mode->crtc_hdisplay;
1207 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1208 wm_high.blank_time = line_time - wm_high.active_time;
1209 wm_high.interlaced = false;
1210 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1211 wm_high.interlaced = true;
1212 wm_high.vsc = amdgpu_crtc->vsc;
1213 wm_high.vtaps = 1;
1214 if (amdgpu_crtc->rmx_type != RMX_OFF)
1215 wm_high.vtaps = 2;
1216 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1217 wm_high.lb_size = lb_size;
1218 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1219 wm_high.num_heads = num_heads;
1220
1221 /* set for high clocks */
1222 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1223
1224 /* possibly force display priority to high */
1225 /* should really do this at mode validation time... */
1226 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1227 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1228 !dce_v11_0_check_latency_hiding(&wm_high) ||
1229 (adev->mode_info.disp_priority == 2)) {
1230 DRM_DEBUG_KMS("force priority to high\n");
1231 }
1232
1233 /* watermark for low clocks */
1234 if (adev->pm.dpm_enabled) {
1235 wm_low.yclk =
1236 amdgpu_dpm_get_mclk(adev, true) * 10;
1237 wm_low.sclk =
1238 amdgpu_dpm_get_sclk(adev, true) * 10;
1239 } else {
1240 wm_low.yclk = adev->pm.current_mclk * 10;
1241 wm_low.sclk = adev->pm.current_sclk * 10;
1242 }
1243
1244 wm_low.disp_clk = mode->clock;
1245 wm_low.src_width = mode->crtc_hdisplay;
1246 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1247 wm_low.blank_time = line_time - wm_low.active_time;
1248 wm_low.interlaced = false;
1249 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1250 wm_low.interlaced = true;
1251 wm_low.vsc = amdgpu_crtc->vsc;
1252 wm_low.vtaps = 1;
1253 if (amdgpu_crtc->rmx_type != RMX_OFF)
1254 wm_low.vtaps = 2;
1255 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1256 wm_low.lb_size = lb_size;
1257 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1258 wm_low.num_heads = num_heads;
1259
1260 /* set for low clocks */
1261 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1262
1263 /* possibly force display priority to high */
1264 /* should really do this at mode validation time... */
1265 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1266 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1267 !dce_v11_0_check_latency_hiding(&wm_low) ||
1268 (adev->mode_info.disp_priority == 2)) {
1269 DRM_DEBUG_KMS("force priority to high\n");
1270 }
8e36f9d3 1271 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
aaa36a97
AD		 1272 }
1273
1274 /* select wm A */
1275 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1276 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1277 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1278 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1279 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1280 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1281 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1282 /* select wm B */
1283 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1284 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1285 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
99a09238 1286 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
aaa36a97
AD		 1287 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1288 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1289 /* restore original selection */
1290 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1291
1292 /* save values for DPM */
1293 amdgpu_crtc->line_time = line_time;
1294 amdgpu_crtc->wm_high = latency_watermark_a;
1295 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1296 /* Save number of lines the linebuffer leads before the scanout */
1297 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
aaa36a97
AD		 1298}
1299
1300/**
1301 * dce_v11_0_bandwidth_update - program display watermarks
1302 *
1303 * @adev: amdgpu_device pointer
1304 *
1305 * Calculate and program the display watermarks and line
1306 * buffer allocation (CIK).
1307 */
1308static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1309{
1310 struct drm_display_mode *mode = NULL;
1311 u32 num_heads = 0, lb_size;
1312 int i;
1313
1314 amdgpu_update_display_priority(adev);
1315
1316 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1317 if (adev->mode_info.crtcs[i]->base.enabled)
1318 num_heads++;
1319 }
1320 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1321 mode = &adev->mode_info.crtcs[i]->base.mode;
1322 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1323 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1324 lb_size, num_heads);
1325 }
1326}
1327
1328static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1329{
1330 int i;
1331 u32 offset, tmp;
1332
1333 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1334 offset = adev->mode_info.audio.pin[i].offset;
1335 tmp = RREG32_AUDIO_ENDPT(offset,
1336 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1337 if (((tmp &
1338 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1339 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1340 adev->mode_info.audio.pin[i].connected = false;
1341 else
1342 adev->mode_info.audio.pin[i].connected = true;
1343 }
1344}
1345
1346static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1347{
1348 int i;
1349
1350 dce_v11_0_audio_get_connected_pins(adev);
1351
1352 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1353 if (adev->mode_info.audio.pin[i].connected)
1354 return &adev->mode_info.audio.pin[i];
1355 }
1356 DRM_ERROR("No connected audio pins found!\n");
1357 return NULL;
1358}
1359
1360static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1361{
1362 struct amdgpu_device *adev = encoder->dev->dev_private;
1363 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1364 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1365 u32 tmp;
1366
1367 if (!dig || !dig->afmt || !dig->afmt->pin)
1368 return;
1369
1370 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1371 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1372 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1373}
1374
1375static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1376 struct drm_display_mode *mode)
1377{
1378 struct amdgpu_device *adev = encoder->dev->dev_private;
1379 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1380 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1381 struct drm_connector *connector;
1382 struct amdgpu_connector *amdgpu_connector = NULL;
1383 u32 tmp;
1384 int interlace = 0;
1385
1386 if (!dig || !dig->afmt || !dig->afmt->pin)
1387 return;
1388
1389 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1390 if (connector->encoder == encoder) {
1391 amdgpu_connector = to_amdgpu_connector(connector);
1392 break;
1393 }
1394 }
1395
1396 if (!amdgpu_connector) {
1397 DRM_ERROR("Couldn't find encoder's connector\n");
1398 return;
1399 }
1400
1401 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1402 interlace = 1;
1403 if (connector->latency_present[interlace]) {
1404 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1405 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1406 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1407 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1408 } else {
1409 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1410 VIDEO_LIPSYNC, 0);
1411 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1412 AUDIO_LIPSYNC, 0);
1413 }
1414 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1415 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1416}
1417
1418static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1419{
1420 struct amdgpu_device *adev = encoder->dev->dev_private;
1421 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1422 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1423 struct drm_connector *connector;
1424 struct amdgpu_connector *amdgpu_connector = NULL;
1425 u32 tmp;
1426 u8 *sadb = NULL;
1427 int sad_count;
1428
1429 if (!dig || !dig->afmt || !dig->afmt->pin)
1430 return;
1431
1432 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1433 if (connector->encoder == encoder) {
1434 amdgpu_connector = to_amdgpu_connector(connector);
1435 break;
1436 }
1437 }
1438
1439 if (!amdgpu_connector) {
1440 DRM_ERROR("Couldn't find encoder's connector\n");
1441 return;
1442 }
1443
1444 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1445 if (sad_count < 0) {
1446 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1447 sad_count = 0;
1448 }
1449
1450 /* program the speaker allocation */
1451 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1452 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1453 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1454 DP_CONNECTION, 0);
1455 /* set HDMI mode */
1456 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1457 HDMI_CONNECTION, 1);
1458 if (sad_count)
1459 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1460 SPEAKER_ALLOCATION, sadb[0]);
1461 else
1462 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1463 SPEAKER_ALLOCATION, 5); /* stereo */
1464 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1465 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1466
1467 kfree(sadb);
1468}
1469
1470static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1471{
1472 struct amdgpu_device *adev = encoder->dev->dev_private;
1473 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1474 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1475 struct drm_connector *connector;
1476 struct amdgpu_connector *amdgpu_connector = NULL;
1477 struct cea_sad *sads;
1478 int i, sad_count;
1479
1480 static const u16 eld_reg_to_type[][2] = {
1481 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1482 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1483 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1484 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1485 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1486 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1487 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1488 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1489 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1490 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1491 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1492 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1493 };
1494
1495 if (!dig || !dig->afmt || !dig->afmt->pin)
1496 return;
1497
1498 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1499 if (connector->encoder == encoder) {
1500 amdgpu_connector = to_amdgpu_connector(connector);
1501 break;
1502 }
1503 }
1504
1505 if (!amdgpu_connector) {
1506 DRM_ERROR("Couldn't find encoder's connector\n");
1507 return;
1508 }
1509
1510 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1511 if (sad_count <= 0) {
1512 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1513 return;
1514 }
1515 BUG_ON(!sads);
1516
1517 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1518 u32 tmp = 0;
1519 u8 stereo_freqs = 0;
1520 int max_channels = -1;
1521 int j;
1522
1523 for (j = 0; j < sad_count; j++) {
1524 struct cea_sad *sad = &sads[j];
1525
1526 if (sad->format == eld_reg_to_type[i][1]) {
1527 if (sad->channels > max_channels) {
1528 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1529 MAX_CHANNELS, sad->channels);
1530 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1531 DESCRIPTOR_BYTE_2, sad->byte2);
1532 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1533 SUPPORTED_FREQUENCIES, sad->freq);
1534 max_channels = sad->channels;
1535 }
1536
1537 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1538 stereo_freqs |= sad->freq;
1539 else
1540 break;
1541 }
1542 }
1543
1544 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1545 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1546 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1547 }
1548
1549 kfree(sads);
1550}
1551
1552static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1553 struct amdgpu_audio_pin *pin,
1554 bool enable)
1555{
1556 if (!pin)
1557 return;
1558
1559 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1560 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1561}
1562
1563static const u32 pin_offsets[] =
1564{
1565 AUD0_REGISTER_OFFSET,
1566 AUD1_REGISTER_OFFSET,
1567 AUD2_REGISTER_OFFSET,
1568 AUD3_REGISTER_OFFSET,
1569 AUD4_REGISTER_OFFSET,
1570 AUD5_REGISTER_OFFSET,
1571 AUD6_REGISTER_OFFSET,
1572};
1573
1574static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1575{
1576 int i;
1577
1578 if (!amdgpu_audio)
1579 return 0;
1580
1581 adev->mode_info.audio.enabled = true;
1582
d525eb8d
AD		 1583 switch (adev->asic_type) {
1584 case CHIP_CARRIZO:
1585 case CHIP_STONEY:
1586 adev->mode_info.audio.num_pins = 7;
1587 break;
1588 case CHIP_ELLESMERE:
1589 adev->mode_info.audio.num_pins = 8;
1590 break;
1591 case CHIP_BAFFIN:
1592 adev->mode_info.audio.num_pins = 6;
1593 break;
1594 default:
1595 return -EINVAL;
1596 }
aaa36a97
AD		 1597
1598 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1599 adev->mode_info.audio.pin[i].channels = -1;
1600 adev->mode_info.audio.pin[i].rate = -1;
1601 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1602 adev->mode_info.audio.pin[i].status_bits = 0;
1603 adev->mode_info.audio.pin[i].category_code = 0;
1604 adev->mode_info.audio.pin[i].connected = false;
1605 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1606 adev->mode_info.audio.pin[i].id = i;
1607 /* disable audio. it will be set up later */
1608 /* XXX remove once we switch to ip funcs */
1609 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1610 }
1611
1612 return 0;
1613}
1614
1615static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1616{
1617 int i;
1618
29f646df
TSD		 1619 if (!amdgpu_audio)
1620 return;
1621
aaa36a97
AD		 1622 if (!adev->mode_info.audio.enabled)
1623 return;
1624
1625 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1626 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1627
1628 adev->mode_info.audio.enabled = false;
1629}
1630
1631/*
1632 * update the N and CTS parameters for a given pixel clock rate
1633 */
1634static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1635{
1636 struct drm_device *dev = encoder->dev;
1637 struct amdgpu_device *adev = dev->dev_private;
1638 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1639 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1641 u32 tmp;
1642
1643 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1644 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1645 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1646 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1647 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1648 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1649
1650 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1651 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1652 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1653 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1654 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1655 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1656
1657 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1658 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1659 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1660 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1661 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1662 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1663
1664}
1665
1666/*
1667 * build a HDMI Video Info Frame
1668 */
1669static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1670 void *buffer, size_t size)
1671{
1672 struct drm_device *dev = encoder->dev;
1673 struct amdgpu_device *adev = dev->dev_private;
1674 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1675 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1676 uint8_t *frame = buffer + 3;
1677 uint8_t *header = buffer;
1678
1679 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1680 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1681 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1682 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1683 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1684 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1685 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1686 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1687}
1688
1689static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1690{
1691 struct drm_device *dev = encoder->dev;
1692 struct amdgpu_device *adev = dev->dev_private;
1693 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1694 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1695 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1696 u32 dto_phase = 24 * 1000;
1697 u32 dto_modulo = clock;
1698 u32 tmp;
1699
1700 if (!dig || !dig->afmt)
1701 return;
1702
1703 /* XXX two dtos; generally use dto0 for hdmi */
1704 /* Express [24MHz / target pixel clock] as an exact rational
1705 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1706 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1707 */
1708 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1709 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1710 amdgpu_crtc->crtc_id);
1711 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1712 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1713 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1714}
1715
1716/*
1717 * update the info frames with the data from the current display mode
1718 */
1719static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1720 struct drm_display_mode *mode)
1721{
1722 struct drm_device *dev = encoder->dev;
1723 struct amdgpu_device *adev = dev->dev_private;
1724 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1725 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1726 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1727 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1728 struct hdmi_avi_infoframe frame;
1729 ssize_t err;
1730 u32 tmp;
1731 int bpc = 8;
1732
1733 if (!dig || !dig->afmt)
1734 return;
1735
1736 /* Silent, r600_hdmi_enable will raise WARN for us */
1737 if (!dig->afmt->enabled)
1738 return;
1739
1740 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1741 if (encoder->crtc) {
1742 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1743 bpc = amdgpu_crtc->bpc;
1744 }
1745
1746 /* disable audio prior to setting up hw */
1747 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1748 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1749
1750 dce_v11_0_audio_set_dto(encoder, mode->clock);
1751
1752 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1753 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1754 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1755
1756 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1757
1758 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1759 switch (bpc) {
1760 case 0:
1761 case 6:
1762 case 8:
1763 case 16:
1764 default:
1765 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1766 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1767 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1768 connector->name, bpc);
1769 break;
1770 case 10:
1771 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1772 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1773 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1774 connector->name);
1775 break;
1776 case 12:
1777 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1778 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1779 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1780 connector->name);
1781 break;
1782 }
1783 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1784
1785 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1786 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1787 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1788 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1789 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1790
1791 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1792 /* enable audio info frames (frames won't be set until audio is enabled) */
1793 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1794 /* required for audio info values to be updated */
1795 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1796 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1797
1798 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1799 /* required for audio info values to be updated */
1800 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1801 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1802
1803 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1804 /* anything other than 0 */
1805 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1806 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1807
1808 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1809
1810 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1811 /* set the default audio delay */
1812 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1813 /* should be suffient for all audio modes and small enough for all hblanks */
1814 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1815 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1816
1817 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1818 /* allow 60958 channel status fields to be updated */
1819 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1820 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1821
1822 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1823 if (bpc > 8)
1824 /* clear SW CTS value */
1825 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1826 else
1827 /* select SW CTS value */
1828 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1829 /* allow hw to sent ACR packets when required */
1830 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1831 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1832
1833 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1834
1835 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1836 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1837 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1838
1839 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1840 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1841 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1842
1843 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1844 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1845 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1846 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1847 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1848 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1849 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1850 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1851
1852 dce_v11_0_audio_write_speaker_allocation(encoder);
1853
1854 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1855 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1856
1857 dce_v11_0_afmt_audio_select_pin(encoder);
1858 dce_v11_0_audio_write_sad_regs(encoder);
1859 dce_v11_0_audio_write_latency_fields(encoder, mode);
1860
1861 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1862 if (err < 0) {
1863 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1864 return;
1865 }
1866
1867 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1868 if (err < 0) {
1869 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1870 return;
1871 }
1872
1873 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1874
1875 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1876 /* enable AVI info frames */
1877 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1878 /* required for audio info values to be updated */
1879 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1880 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1881
1882 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1883 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1884 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1885
1886 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1887 /* send audio packets */
1888 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1889 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1890
1891 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1892 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1893 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1894 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1895
1896 /* enable audio after to setting up hw */
1897 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1898}
1899
1900static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1901{
1902 struct drm_device *dev = encoder->dev;
1903 struct amdgpu_device *adev = dev->dev_private;
1904 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1905 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1906
1907 if (!dig || !dig->afmt)
1908 return;
1909
1910 /* Silent, r600_hdmi_enable will raise WARN for us */
1911 if (enable && dig->afmt->enabled)
1912 return;
1913 if (!enable && !dig->afmt->enabled)
1914 return;
1915
1916 if (!enable && dig->afmt->pin) {
1917 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1918 dig->afmt->pin = NULL;
1919 }
1920
1921 dig->afmt->enabled = enable;
1922
1923 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1924 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1925}
1926
041ab0a4 1927static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
aaa36a97
AD		 1928{
1929 int i;
1930
1931 for (i = 0; i < adev->mode_info.num_dig; i++)
1932 adev->mode_info.afmt[i] = NULL;
1933
1934 /* DCE11 has audio blocks tied to DIG encoders */
1935 for (i = 0; i < adev->mode_info.num_dig; i++) {
1936 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1937 if (adev->mode_info.afmt[i]) {
1938 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1939 adev->mode_info.afmt[i]->id = i;
041ab0a4
TSD		 1940 } else {
1941 int j;
1942 for (j = 0; j < i; j++) {
1943 kfree(adev->mode_info.afmt[j]);
1944 adev->mode_info.afmt[j] = NULL;
1945 }
1946 return -ENOMEM;
aaa36a97
AD		 1947 }
1948 }
041ab0a4 1949 return 0;
aaa36a97
AD		 1950}
1951
1952static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1953{
1954 int i;
1955
1956 for (i = 0; i < adev->mode_info.num_dig; i++) {
1957 kfree(adev->mode_info.afmt[i]);
1958 adev->mode_info.afmt[i] = NULL;
1959 }
1960}
1961
1962static const u32 vga_control_regs[6] =
1963{
1964 mmD1VGA_CONTROL,
1965 mmD2VGA_CONTROL,
1966 mmD3VGA_CONTROL,
1967 mmD4VGA_CONTROL,
1968 mmD5VGA_CONTROL,
1969 mmD6VGA_CONTROL,
1970};
1971
1972static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1973{
1974 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1975 struct drm_device *dev = crtc->dev;
1976 struct amdgpu_device *adev = dev->dev_private;
1977 u32 vga_control;
1978
1979 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1980 if (enable)
1981 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1982 else
1983 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1984}
1985
1986static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1987{
1988 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1989 struct drm_device *dev = crtc->dev;
1990 struct amdgpu_device *adev = dev->dev_private;
1991
1992 if (enable)
1993 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1994 else
1995 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1996}
1997
aaa36a97
AD		 1998static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1999 struct drm_framebuffer *fb,
2000 int x, int y, int atomic)
2001{
2002 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2003 struct drm_device *dev = crtc->dev;
2004 struct amdgpu_device *adev = dev->dev_private;
2005 struct amdgpu_framebuffer *amdgpu_fb;
2006 struct drm_framebuffer *target_fb;
2007 struct drm_gem_object *obj;
2008 struct amdgpu_bo *rbo;
2009 uint64_t fb_location, tiling_flags;
2010 uint32_t fb_format, fb_pitch_pixels;
aaa36a97 2011 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
fbd76d59 2012 u32 pipe_config;
aaa36a97
AD		 2013 u32 tmp, viewport_w, viewport_h;
2014 int r;
2015 bool bypass_lut = false;
2016
2017 /* no fb bound */
2018 if (!atomic && !crtc->primary->fb) {
2019 DRM_DEBUG_KMS("No FB bound\n");
2020 return 0;
2021 }
2022
2023 if (atomic) {
2024 amdgpu_fb = to_amdgpu_framebuffer(fb);
2025 target_fb = fb;
e484f8d4 2026 } else {
aaa36a97
AD		 2027 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2028 target_fb = crtc->primary->fb;
2029 }
2030
2031 /* If atomic, assume fb object is pinned & idle & fenced and
2032 * just update base pointers
2033 */
2034 obj = amdgpu_fb->obj;
2035 rbo = gem_to_amdgpu_bo(obj);
2036 r = amdgpu_bo_reserve(rbo, false);
2037 if (unlikely(r != 0))
2038 return r;
2039
e484f8d4 2040 if (atomic) {
aaa36a97 2041 fb_location = amdgpu_bo_gpu_offset(rbo);
e484f8d4 2042 } else {
aaa36a97
AD		 2043 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2044 if (unlikely(r != 0)) {
2045 amdgpu_bo_unreserve(rbo);
2046 return -EINVAL;
2047 }
2048 }
2049
2050 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2051 amdgpu_bo_unreserve(rbo);
2052
fbd76d59
MO		 2053 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2054
aaa36a97
AD		 2055 switch (target_fb->pixel_format) {
2056 case DRM_FORMAT_C8:
2057 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2058 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2059 break;
2060 case DRM_FORMAT_XRGB4444:
2061 case DRM_FORMAT_ARGB4444:
2062 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2063 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2064#ifdef __BIG_ENDIAN
2065 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2066 ENDIAN_8IN16);
2067#endif
2068 break;
2069 case DRM_FORMAT_XRGB1555:
2070 case DRM_FORMAT_ARGB1555:
2071 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2072 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2073#ifdef __BIG_ENDIAN
2074 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2075 ENDIAN_8IN16);
2076#endif
2077 break;
2078 case DRM_FORMAT_BGRX5551:
2079 case DRM_FORMAT_BGRA5551:
2080 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2081 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2082#ifdef __BIG_ENDIAN
2083 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2084 ENDIAN_8IN16);
2085#endif
2086 break;
2087 case DRM_FORMAT_RGB565:
2088 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2089 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2090#ifdef __BIG_ENDIAN
2091 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2092 ENDIAN_8IN16);
2093#endif
2094 break;
2095 case DRM_FORMAT_XRGB8888:
2096 case DRM_FORMAT_ARGB8888:
2097 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2098 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2099#ifdef __BIG_ENDIAN
2100 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2101 ENDIAN_8IN32);
2102#endif
2103 break;
2104 case DRM_FORMAT_XRGB2101010:
2105 case DRM_FORMAT_ARGB2101010:
2106 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2107 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2108#ifdef __BIG_ENDIAN
2109 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2110 ENDIAN_8IN32);
2111#endif
2112 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2113 bypass_lut = true;
2114 break;
2115 case DRM_FORMAT_BGRX1010102:
2116 case DRM_FORMAT_BGRA1010102:
2117 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2118 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2119#ifdef __BIG_ENDIAN
2120 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2121 ENDIAN_8IN32);
2122#endif
2123 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2124 bypass_lut = true;
2125 break;
2126 default:
2127 DRM_ERROR("Unsupported screen format %s\n",
2128 drm_get_format_name(target_fb->pixel_format));
2129 return -EINVAL;
2130 }
2131
fbd76d59
MO		 2132 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2133 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
aaa36a97 2134
fbd76d59
MO		 2135 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2136 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2137 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2138 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2139 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
aaa36a97 2140
aaa36a97
AD		 2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2142 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2143 ARRAY_2D_TILED_THIN1);
2144 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2145 tile_split);
2146 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2147 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2148 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2149 mtaspect);
2150 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2151 ADDR_SURF_MICRO_TILING_DISPLAY);
fbd76d59 2152 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
aaa36a97
AD		 2153 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2154 ARRAY_1D_TILED_THIN1);
2155 }
2156
aaa36a97
AD		 2157 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2158 pipe_config);
2159
2160 dce_v11_0_vga_enable(crtc, false);
2161
2162 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2163 upper_32_bits(fb_location));
2164 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2165 upper_32_bits(fb_location));
2166 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2167 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2168 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2169 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2170 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2171 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2172
2173 /*
2174 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2175 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2176 * retain the full precision throughout the pipeline.
2177 */
2178 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2179 if (bypass_lut)
2180 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2181 else
2182 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2183 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2184
2185 if (bypass_lut)
2186 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2187
2188 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2189 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2190 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2191 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2192 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2193 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2194
2195 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2196 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2197
2198 dce_v11_0_grph_enable(crtc, true);
2199
2200 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2201 target_fb->height);
2202
2203 x &= ~3;
2204 y &= ~1;
2205 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2206 (x << 16) | y);
2207 viewport_w = crtc->mode.hdisplay;
2208 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2209 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2210 (viewport_w << 16) | viewport_h);
2211
2212 /* pageflip setup */
2213 /* make sure flip is at vb rather than hb */
2214 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2215 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2216 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2217 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2218
2219 /* set pageflip to happen only at start of vblank interval (front porch) */
2220 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2221
2222 if (!atomic && fb && fb != crtc->primary->fb) {
2223 amdgpu_fb = to_amdgpu_framebuffer(fb);
2224 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2225 r = amdgpu_bo_reserve(rbo, false);
2226 if (unlikely(r != 0))
2227 return r;
2228 amdgpu_bo_unpin(rbo);
2229 amdgpu_bo_unreserve(rbo);
2230 }
2231
2232 /* Bytes per pixel may have changed */
2233 dce_v11_0_bandwidth_update(adev);
2234
2235 return 0;
2236}
2237
2238static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2239 struct drm_display_mode *mode)
2240{
2241 struct drm_device *dev = crtc->dev;
2242 struct amdgpu_device *adev = dev->dev_private;
2243 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2244 u32 tmp;
2245
2246 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2247 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2248 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2249 else
2250 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2251 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2252}
2253
2254static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2255{
2256 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2257 struct drm_device *dev = crtc->dev;
2258 struct amdgpu_device *adev = dev->dev_private;
2259 int i;
2260 u32 tmp;
2261
2262 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2263
2264 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2265 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2266 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2267
2268 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2269 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2270 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2271
2272 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2273 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2274 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2275
2276 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2277
2278 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2279 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2280 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2281
2282 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2283 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2284 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2285
2286 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2287 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2288
2289 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2290 for (i = 0; i < 256; i++) {
2291 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2292 (amdgpu_crtc->lut_r[i] << 20) |
2293 (amdgpu_crtc->lut_g[i] << 10) |
2294 (amdgpu_crtc->lut_b[i] << 0));
2295 }
2296
2297 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2298 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2299 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2300 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2301 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2302
2303 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2304 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2305 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2306
2307 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2308 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2309 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2310
2311 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2312 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2313 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2314
2315 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2316 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2317 /* XXX this only needs to be programmed once per crtc at startup,
2318 * not sure where the best place for it is
2319 */
2320 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2321 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2322 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2323}
2324
2325static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2326{
2327 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2328 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2329
2330 switch (amdgpu_encoder->encoder_id) {
2331 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2332 if (dig->linkb)
2333 return 1;
2334 else
2335 return 0;
2336 break;
2337 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2338 if (dig->linkb)
2339 return 3;
2340 else
2341 return 2;
2342 break;
2343 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2344 if (dig->linkb)
2345 return 5;
2346 else
2347 return 4;
2348 break;
2349 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2350 return 6;
2351 break;
2352 default:
2353 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2354 return 0;
2355 }
2356}
2357
2358/**
2359 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2360 *
2361 * @crtc: drm crtc
2362 *
2363 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2364 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2365 * monitors a dedicated PPLL must be used. If a particular board has
2366 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2367 * as there is no need to program the PLL itself. If we are not able to
2368 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2369 * avoid messing up an existing monitor.
2370 *
2371 * Asic specific PLL information
2372 *
2373 * DCE 10.x
2374 * Tonga
2375 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2376 * CI
2377 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2378 *
2379 */
2380static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2381{
2382 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2383 struct drm_device *dev = crtc->dev;
2384 struct amdgpu_device *adev = dev->dev_private;
2385 u32 pll_in_use;
2386 int pll;
2387
2388 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2389 if (adev->clock.dp_extclk)
2390 /* skip PPLL programming if using ext clock */
2391 return ATOM_PPLL_INVALID;
2392 else {
2393 /* use the same PPLL for all DP monitors */
2394 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2395 if (pll != ATOM_PPLL_INVALID)
2396 return pll;
2397 }
2398 } else {
2399 /* use the same PPLL for all monitors with the same clock */
2400 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2401 if (pll != ATOM_PPLL_INVALID)
2402 return pll;
2403 }
2404
2405 /* XXX need to determine what plls are available on each DCE11 part */
2406 pll_in_use = amdgpu_pll_get_use_mask(crtc);
fa2f9bef 2407 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
aaa36a97
AD		 2408 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2409 return ATOM_PPLL1;
2410 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2411 return ATOM_PPLL0;
2412 DRM_ERROR("unable to allocate a PPLL\n");
2413 return ATOM_PPLL_INVALID;
2414 } else {
2415 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2416 return ATOM_PPLL2;
2417 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2418 return ATOM_PPLL1;
2419 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2420 return ATOM_PPLL0;
2421 DRM_ERROR("unable to allocate a PPLL\n");
2422 return ATOM_PPLL_INVALID;
2423 }
2424 return ATOM_PPLL_INVALID;
2425}
2426
2427static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2428{
2429 struct amdgpu_device *adev = crtc->dev->dev_private;
2430 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2431 uint32_t cur_lock;
2432
2433 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2434 if (lock)
2435 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2436 else
2437 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2438 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2439}
2440
2441static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2442{
2443 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2444 struct amdgpu_device *adev = crtc->dev->dev_private;
2445 u32 tmp;
2446
2447 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2448 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2449 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2450}
2451
2452static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2453{
2454 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2455 struct amdgpu_device *adev = crtc->dev->dev_private;
2456 u32 tmp;
2457
ec9353dc
AD		 2458 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2459 upper_32_bits(amdgpu_crtc->cursor_addr));
2460 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2461 lower_32_bits(amdgpu_crtc->cursor_addr));
2462
aaa36a97
AD		 2463 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2464 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2465 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2466 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2467}
2468
d8ee89c6
AD		 2469static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2470 int x, int y)
aaa36a97
AD		 2471{
2472 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2473 struct amdgpu_device *adev = crtc->dev->dev_private;
2474 int xorigin = 0, yorigin = 0;
2475
2476 /* avivo cursor are offset into the total surface */
2477 x += crtc->x;
2478 y += crtc->y;
2479 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2480
2481 if (x < 0) {
2482 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2483 x = 0;
2484 }
2485 if (y < 0) {
2486 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2487 y = 0;
2488 }
2489
aaa36a97
AD		 2490 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2491 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2492 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2493 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
d8ee89c6
AD		 2494
2495 amdgpu_crtc->cursor_x = x;
2496 amdgpu_crtc->cursor_y = y;
aaa36a97
AD		 2497
2498 return 0;
2499}
2500
d8ee89c6
AD		 2501static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2502 int x, int y)
2503{
2504 int ret;
2505
2506 dce_v11_0_lock_cursor(crtc, true);
2507 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2508 dce_v11_0_lock_cursor(crtc, false);
2509
2510 return ret;
2511}
2512
2513static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2514 struct drm_file *file_priv,
2515 uint32_t handle,
2516 uint32_t width,
2517 uint32_t height,
2518 int32_t hot_x,
2519 int32_t hot_y)
aaa36a97
AD		 2520{
2521 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2522 struct drm_gem_object *obj;
232cc652 2523 struct amdgpu_bo *aobj;
aaa36a97
AD		 2524 int ret;
2525
2526 if (!handle) {
2527 /* turn off cursor */
2528 dce_v11_0_hide_cursor(crtc);
2529 obj = NULL;
2530 goto unpin;
2531 }
2532
2533 if ((width > amdgpu_crtc->max_cursor_width) ||
2534 (height > amdgpu_crtc->max_cursor_height)) {
2535 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2536 return -EINVAL;
2537 }
2538
2539 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2540 if (!obj) {
2541 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2542 return -ENOENT;
2543 }
2544
232cc652
AD		 2545 aobj = gem_to_amdgpu_bo(obj);
2546 ret = amdgpu_bo_reserve(aobj, false);
2547 if (ret != 0) {
2548 drm_gem_object_unreference_unlocked(obj);
2549 return ret;
2550 }
2551
2552 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2553 amdgpu_bo_unreserve(aobj);
2554 if (ret) {
2555 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2556 drm_gem_object_unreference_unlocked(obj);
2557 return ret;
2558 }
aaa36a97
AD		 2559
2560 amdgpu_crtc->cursor_width = width;
2561 amdgpu_crtc->cursor_height = height;
2562
2563 dce_v11_0_lock_cursor(crtc, true);
1996ea09
AD		 2564
2565 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2566 hot_y != amdgpu_crtc->cursor_hot_y) {
2567 int x, y;
2568
2569 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2570 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2571
2572 dce_v11_0_cursor_move_locked(crtc, x, y);
2573
2574 amdgpu_crtc->cursor_hot_x = hot_x;
2575 amdgpu_crtc->cursor_hot_y = hot_y;
2576 }
2577
aaa36a97
AD		 2578 dce_v11_0_show_cursor(crtc);
2579 dce_v11_0_lock_cursor(crtc, false);
2580
2581unpin:
2582 if (amdgpu_crtc->cursor_bo) {
8ddef5a5
AD		 2583 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2584 ret = amdgpu_bo_reserve(aobj, false);
aaa36a97 2585 if (likely(ret == 0)) {
8ddef5a5
AD		 2586 amdgpu_bo_unpin(aobj);
2587 amdgpu_bo_unreserve(aobj);
aaa36a97
AD		 2588 }
2589 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2590 }
2591
2592 amdgpu_crtc->cursor_bo = obj;
2593 return 0;
8ddef5a5 2594}
aaa36a97 2595
8ddef5a5
AD		 2596static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2597{
2598 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
8ddef5a5
AD		 2599
2600 if (amdgpu_crtc->cursor_bo) {
2601 dce_v11_0_lock_cursor(crtc, true);
2602
2603 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2604 amdgpu_crtc->cursor_y);
2605
232cc652 2606 dce_v11_0_show_cursor(crtc);
8ddef5a5
AD		 2607
2608 dce_v11_0_lock_cursor(crtc, false);
2609 }
aaa36a97
AD		 2610}
2611
2612static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2613 u16 *blue, uint32_t start, uint32_t size)
2614{
2615 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2616 int end = (start + size > 256) ? 256 : start + size, i;
2617
2618 /* userspace palettes are always correct as is */
2619 for (i = start; i < end; i++) {
2620 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2621 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2622 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2623 }
2624 dce_v11_0_crtc_load_lut(crtc);
2625}
2626
2627static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2628{
2629 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2630
2631 drm_crtc_cleanup(crtc);
aaa36a97
AD		 2632 kfree(amdgpu_crtc);
2633}
2634
2635static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
d8ee89c6 2636 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
aaa36a97
AD		 2637 .cursor_move = dce_v11_0_crtc_cursor_move,
2638 .gamma_set = dce_v11_0_crtc_gamma_set,
2639 .set_config = amdgpu_crtc_set_config,
2640 .destroy = dce_v11_0_crtc_destroy,
2641 .page_flip = amdgpu_crtc_page_flip,
2642};
2643
2644static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2645{
2646 struct drm_device *dev = crtc->dev;
2647 struct amdgpu_device *adev = dev->dev_private;
2648 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
d84b272a 2649 unsigned type;
aaa36a97
AD		 2650
2651 switch (mode) {
2652 case DRM_MODE_DPMS_ON:
2653 amdgpu_crtc->enabled = true;
2654 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2655 dce_v11_0_vga_enable(crtc, true);
2656 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2657 dce_v11_0_vga_enable(crtc, false);
f6c7aba4 2658 /* Make sure VBLANK and PFLIP interrupts are still enabled */
d84b272a
MD		 2659 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2660 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2661 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
b6bae58d 2662 drm_vblank_on(dev, amdgpu_crtc->crtc_id);
aaa36a97
AD		 2663 dce_v11_0_crtc_load_lut(crtc);
2664 break;
2665 case DRM_MODE_DPMS_STANDBY:
2666 case DRM_MODE_DPMS_SUSPEND:
2667 case DRM_MODE_DPMS_OFF:
b6bae58d 2668 drm_vblank_off(dev, amdgpu_crtc->crtc_id);
aaa36a97
AD		 2669 if (amdgpu_crtc->enabled) {
2670 dce_v11_0_vga_enable(crtc, true);
2671 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2672 dce_v11_0_vga_enable(crtc, false);
2673 }
2674 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2675 amdgpu_crtc->enabled = false;
2676 break;
2677 }
2678 /* adjust pm to dpms */
2679 amdgpu_pm_compute_clocks(adev);
2680}
2681
2682static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2683{
2684 /* disable crtc pair power gating before programming */
2685 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2686 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2687 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2688}
2689
2690static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2691{
2692 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2693 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2694}
2695
2696static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2697{
2698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2699 struct drm_device *dev = crtc->dev;
2700 struct amdgpu_device *adev = dev->dev_private;
2701 struct amdgpu_atom_ss ss;
2702 int i;
2703
2704 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2705 if (crtc->primary->fb) {
2706 int r;
2707 struct amdgpu_framebuffer *amdgpu_fb;
2708 struct amdgpu_bo *rbo;
2709
2710 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2711 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2712 r = amdgpu_bo_reserve(rbo, false);
2713 if (unlikely(r))
2714 DRM_ERROR("failed to reserve rbo before unpin\n");
2715 else {
2716 amdgpu_bo_unpin(rbo);
2717 amdgpu_bo_unreserve(rbo);
2718 }
2719 }
2720 /* disable the GRPH */
2721 dce_v11_0_grph_enable(crtc, false);
2722
2723 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2724
2725 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2726 if (adev->mode_info.crtcs[i] &&
2727 adev->mode_info.crtcs[i]->enabled &&
2728 i != amdgpu_crtc->crtc_id &&
2729 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2730 /* one other crtc is using this pll don't turn
2731 * off the pll
2732 */
2733 goto done;
2734 }
2735 }
2736
2737 switch (amdgpu_crtc->pll_id) {
2738 case ATOM_PPLL0:
2739 case ATOM_PPLL1:
2740 case ATOM_PPLL2:
2741 /* disable the ppll */
2742 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2743 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2744 break;
2745 default:
2746 break;
2747 }
2748done:
2749 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2750 amdgpu_crtc->adjusted_clock = 0;
2751 amdgpu_crtc->encoder = NULL;
2752 amdgpu_crtc->connector = NULL;
2753}
2754
2755static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2756 struct drm_display_mode *mode,
2757 struct drm_display_mode *adjusted_mode,
2758 int x, int y, struct drm_framebuffer *old_fb)
2759{
2760 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2761
2762 if (!amdgpu_crtc->adjusted_clock)
2763 return -EINVAL;
2764
2765 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2766 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2767 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2768 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2769 amdgpu_atombios_crtc_scaler_setup(crtc);
8ddef5a5 2770 dce_v11_0_cursor_reset(crtc);
aaa36a97
AD		 2771 /* update the hw version fpr dpm */
2772 amdgpu_crtc->hw_mode = *adjusted_mode;
2773
2774 return 0;
2775}
2776
2777static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2778 const struct drm_display_mode *mode,
2779 struct drm_display_mode *adjusted_mode)
2780{
2781 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2782 struct drm_device *dev = crtc->dev;
2783 struct drm_encoder *encoder;
2784
2785 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2787 if (encoder->crtc == crtc) {
2788 amdgpu_crtc->encoder = encoder;
2789 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2790 break;
2791 }
2792 }
2793 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2794 amdgpu_crtc->encoder = NULL;
2795 amdgpu_crtc->connector = NULL;
2796 return false;
2797 }
2798 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2799 return false;
2800 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2801 return false;
2802 /* pick pll */
2803 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2804 /* if we can't get a PPLL for a non-DP encoder, fail */
2805 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2806 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2807 return false;
2808
2809 return true;
2810}
2811
2812static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2813 struct drm_framebuffer *old_fb)
2814{
2815 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2816}
2817
2818static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2819 struct drm_framebuffer *fb,
2820 int x, int y, enum mode_set_atomic state)
2821{
2822 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2823}
2824
2825static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2826 .dpms = dce_v11_0_crtc_dpms,
2827 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2828 .mode_set = dce_v11_0_crtc_mode_set,
2829 .mode_set_base = dce_v11_0_crtc_set_base,
2830 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2831 .prepare = dce_v11_0_crtc_prepare,
2832 .commit = dce_v11_0_crtc_commit,
2833 .load_lut = dce_v11_0_crtc_load_lut,
2834 .disable = dce_v11_0_crtc_disable,
2835};
2836
2837static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2838{
2839 struct amdgpu_crtc *amdgpu_crtc;
2840 int i;
2841
2842 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2843 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2844 if (amdgpu_crtc == NULL)
2845 return -ENOMEM;
2846
2847 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2848
2849 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2850 amdgpu_crtc->crtc_id = index;
aaa36a97
AD		 2851 adev->mode_info.crtcs[index] = amdgpu_crtc;
2852
2853 amdgpu_crtc->max_cursor_width = 128;
2854 amdgpu_crtc->max_cursor_height = 128;
2855 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2856 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2857
2858 for (i = 0; i < 256; i++) {
2859 amdgpu_crtc->lut_r[i] = i << 2;
2860 amdgpu_crtc->lut_g[i] = i << 2;
2861 amdgpu_crtc->lut_b[i] = i << 2;
2862 }
2863
2864 switch (amdgpu_crtc->crtc_id) {
2865 case 0:
2866 default:
2867 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2868 break;
2869 case 1:
2870 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2871 break;
2872 case 2:
2873 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2874 break;
2875 case 3:
2876 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2877 break;
2878 case 4:
2879 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2880 break;
2881 case 5:
2882 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2883 break;
2884 }
2885
2886 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2887 amdgpu_crtc->adjusted_clock = 0;
2888 amdgpu_crtc->encoder = NULL;
2889 amdgpu_crtc->connector = NULL;
2890 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2891
2892 return 0;
2893}
2894
5fc3aeeb 2895static int dce_v11_0_early_init(void *handle)
aaa36a97 2896{
5fc3aeeb 2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
aaa36a97
AD		 2899 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2900 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2901
2902 dce_v11_0_set_display_funcs(adev);
2903 dce_v11_0_set_irq_funcs(adev);
2904
2905 switch (adev->asic_type) {
2906 case CHIP_CARRIZO:
26d0c21d 2907 adev->mode_info.num_crtc = 3;
aaa36a97
AD		 2908 adev->mode_info.num_hpd = 6;
2909 adev->mode_info.num_dig = 9;
2910 break;
fa2f9bef
SL		 2911 case CHIP_STONEY:
2912 adev->mode_info.num_crtc = 2;
2913 adev->mode_info.num_hpd = 6;
2914 adev->mode_info.num_dig = 9;
2915 break;
d525eb8d
AD		 2916 case CHIP_ELLESMERE:
2917 adev->mode_info.num_crtc = 6;
2918 adev->mode_info.num_hpd = 6;
2919 adev->mode_info.num_dig = 6;
2920 break;
2921 case CHIP_BAFFIN:
2922 adev->mode_info.num_crtc = 5;
2923 adev->mode_info.num_hpd = 5;
2924 adev->mode_info.num_dig = 5;
2925 break;
aaa36a97
AD		 2926 default:
2927 /* FIXME: not supported yet */
2928 return -EINVAL;
2929 }
2930
2931 return 0;
2932}
2933
5fc3aeeb 2934static int dce_v11_0_sw_init(void *handle)
aaa36a97
AD		 2935{
2936 int r, i;
5fc3aeeb 2937 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 2938
2939 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2940 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2941 if (r)
bcc71beb 2942 return r;
aaa36a97
AD		 2943 }
2944
2945 for (i = 8; i < 20; i += 2) {
2946 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2947 if (r)
2948 return r;
2949 }
2950
2951 /* HPD hotplug */
2952 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2953 if (r)
bcc71beb 2954 return r;
aaa36a97 2955
aaa36a97
AD		 2956 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2957
2958 adev->ddev->mode_config.max_width = 16384;
2959 adev->ddev->mode_config.max_height = 16384;
2960
2961 adev->ddev->mode_config.preferred_depth = 24;
2962 adev->ddev->mode_config.prefer_shadow = 1;
2963
2964 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2965
2966 r = amdgpu_modeset_create_props(adev);
2967 if (r)
2968 return r;
2969
2970 adev->ddev->mode_config.max_width = 16384;
2971 adev->ddev->mode_config.max_height = 16384;
2972
c437b9d6 2973
aaa36a97
AD		 2974 /* allocate crtcs */
2975 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2976 r = dce_v11_0_crtc_init(adev, i);
2977 if (r)
2978 return r;
2979 }
2980
2981 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2982 amdgpu_print_display_setup(adev->ddev);
2983 else
2984 return -EINVAL;
2985
2986 /* setup afmt */
041ab0a4
TSD		 2987 r = dce_v11_0_afmt_init(adev);
2988 if (r)
2989 return r;
aaa36a97
AD		 2990
2991 r = dce_v11_0_audio_init(adev);
2992 if (r)
2993 return r;
2994
2995 drm_kms_helper_poll_init(adev->ddev);
2996
c437b9d6
TSD		 2997 adev->mode_info.mode_config_initialized = true;
2998 return 0;
aaa36a97
AD		 2999}
3000
5fc3aeeb 3001static int dce_v11_0_sw_fini(void *handle)
aaa36a97 3002{
5fc3aeeb 3003 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3004
aaa36a97
AD		 3005 kfree(adev->mode_info.bios_hardcoded_edid);
3006
3007 drm_kms_helper_poll_fini(adev->ddev);
3008
3009 dce_v11_0_audio_fini(adev);
3010
3011 dce_v11_0_afmt_fini(adev);
3012
3013 adev->mode_info.mode_config_initialized = false;
3014
3015 return 0;
3016}
3017
5fc3aeeb 3018static int dce_v11_0_hw_init(void *handle)
aaa36a97
AD		 3019{
3020 int i;
5fc3aeeb 3021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3022
3023 dce_v11_0_init_golden_registers(adev);
3024
3025 /* init dig PHYs, disp eng pll */
f9fff064 3026 amdgpu_atombios_crtc_powergate_init(adev);
aaa36a97
AD		 3027 amdgpu_atombios_encoder_init_dig(adev);
3028 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3029
3030 /* initialize hpd */
3031 dce_v11_0_hpd_init(adev);
3032
3033 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3034 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3035 }
3036
f6c7aba4
MD		 3037 dce_v11_0_pageflip_interrupt_init(adev);
3038
aaa36a97
AD		 3039 return 0;
3040}
3041
5fc3aeeb 3042static int dce_v11_0_hw_fini(void *handle)
aaa36a97
AD		 3043{
3044 int i;
5fc3aeeb 3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3046
3047 dce_v11_0_hpd_fini(adev);
3048
3049 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3050 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3051 }
3052
f6c7aba4
MD		 3053 dce_v11_0_pageflip_interrupt_fini(adev);
3054
aaa36a97
AD		 3055 return 0;
3056}
3057
5fc3aeeb 3058static int dce_v11_0_suspend(void *handle)
aaa36a97 3059{
5fc3aeeb 3060 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 3061
aaa36a97
AD		 3062 amdgpu_atombios_scratch_regs_save(adev);
3063
f9fff064 3064 return dce_v11_0_hw_fini(handle);
aaa36a97
AD		 3065}
3066
5fc3aeeb 3067static int dce_v11_0_resume(void *handle)
aaa36a97 3068{
5fc3aeeb 3069 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064 3070 int ret;
aaa36a97 3071
f9fff064 3072 ret = dce_v11_0_hw_init(handle);
aaa36a97
AD		 3073
3074 amdgpu_atombios_scratch_regs_restore(adev);
3075
aaa36a97
AD		 3076 /* turn on the BL */
3077 if (adev->mode_info.bl_encoder) {
3078 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3079 adev->mode_info.bl_encoder);
3080 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3081 bl_level);
3082 }
3083
f9fff064 3084 return ret;
aaa36a97
AD		 3085}
3086
5fc3aeeb 3087static bool dce_v11_0_is_idle(void *handle)
aaa36a97 3088{
aaa36a97
AD		 3089 return true;
3090}
3091
5fc3aeeb 3092static int dce_v11_0_wait_for_idle(void *handle)
aaa36a97 3093{
aaa36a97
AD		 3094 return 0;
3095}
3096
5fc3aeeb 3097static void dce_v11_0_print_status(void *handle)
aaa36a97 3098{
5fc3aeeb 3099 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3100
aaa36a97
AD		 3101 dev_info(adev->dev, "DCE 10.x registers\n");
3102 /* XXX todo */
3103}
3104
5fc3aeeb 3105static int dce_v11_0_soft_reset(void *handle)
aaa36a97
AD		 3106{
3107 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3108 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3109
3110 if (dce_v11_0_is_display_hung(adev))
3111 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3112
3113 if (srbm_soft_reset) {
5fc3aeeb 3114 dce_v11_0_print_status((void *)adev);
aaa36a97
AD		 3115
3116 tmp = RREG32(mmSRBM_SOFT_RESET);
3117 tmp |= srbm_soft_reset;
3118 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3119 WREG32(mmSRBM_SOFT_RESET, tmp);
3120 tmp = RREG32(mmSRBM_SOFT_RESET);
3121
3122 udelay(50);
3123
3124 tmp &= ~srbm_soft_reset;
3125 WREG32(mmSRBM_SOFT_RESET, tmp);
3126 tmp = RREG32(mmSRBM_SOFT_RESET);
3127
3128 /* Wait a little for things to settle down */
3129 udelay(50);
5fc3aeeb 3130 dce_v11_0_print_status((void *)adev);
aaa36a97
AD		 3131 }
3132 return 0;
3133}
3134
3135static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3136 int crtc,
3137 enum amdgpu_interrupt_state state)
3138{
3139 u32 lb_interrupt_mask;
3140
3141 if (crtc >= adev->mode_info.num_crtc) {
3142 DRM_DEBUG("invalid crtc %d\n", crtc);
3143 return;
3144 }
3145
3146 switch (state) {
3147 case AMDGPU_IRQ_STATE_DISABLE:
3148 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3149 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3150 VBLANK_INTERRUPT_MASK, 0);
3151 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3152 break;
3153 case AMDGPU_IRQ_STATE_ENABLE:
3154 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3155 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3156 VBLANK_INTERRUPT_MASK, 1);
3157 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3158 break;
3159 default:
3160 break;
3161 }
3162}
3163
3164static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3165 int crtc,
3166 enum amdgpu_interrupt_state state)
3167{
3168 u32 lb_interrupt_mask;
3169
3170 if (crtc >= adev->mode_info.num_crtc) {
3171 DRM_DEBUG("invalid crtc %d\n", crtc);
3172 return;
3173 }
3174
3175 switch (state) {
3176 case AMDGPU_IRQ_STATE_DISABLE:
3177 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3178 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3179 VLINE_INTERRUPT_MASK, 0);
3180 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3181 break;
3182 case AMDGPU_IRQ_STATE_ENABLE:
3183 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3184 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3185 VLINE_INTERRUPT_MASK, 1);
3186 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3187 break;
3188 default:
3189 break;
3190 }
3191}
3192
3193static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3194 struct amdgpu_irq_src *source,
3195 unsigned hpd,
3196 enum amdgpu_interrupt_state state)
3197{
3198 u32 tmp;
3199
3200 if (hpd >= adev->mode_info.num_hpd) {
3201 DRM_DEBUG("invalid hdp %d\n", hpd);
3202 return 0;
3203 }
3204
3205 switch (state) {
3206 case AMDGPU_IRQ_STATE_DISABLE:
3207 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3208 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3209 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3210 break;
3211 case AMDGPU_IRQ_STATE_ENABLE:
3212 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3213 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3214 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3215 break;
3216 default:
3217 break;
3218 }
3219
3220 return 0;
3221}
3222
3223static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3224 struct amdgpu_irq_src *source,
3225 unsigned type,
3226 enum amdgpu_interrupt_state state)
3227{
3228 switch (type) {
3229 case AMDGPU_CRTC_IRQ_VBLANK1:
3230 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3231 break;
3232 case AMDGPU_CRTC_IRQ_VBLANK2:
3233 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3234 break;
3235 case AMDGPU_CRTC_IRQ_VBLANK3:
3236 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3237 break;
3238 case AMDGPU_CRTC_IRQ_VBLANK4:
3239 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3240 break;
3241 case AMDGPU_CRTC_IRQ_VBLANK5:
3242 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3243 break;
3244 case AMDGPU_CRTC_IRQ_VBLANK6:
3245 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3246 break;
3247 case AMDGPU_CRTC_IRQ_VLINE1:
3248 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3249 break;
3250 case AMDGPU_CRTC_IRQ_VLINE2:
3251 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3252 break;
3253 case AMDGPU_CRTC_IRQ_VLINE3:
3254 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3255 break;
3256 case AMDGPU_CRTC_IRQ_VLINE4:
3257 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3258 break;
3259 case AMDGPU_CRTC_IRQ_VLINE5:
3260 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3261 break;
3262 case AMDGPU_CRTC_IRQ_VLINE6:
3263 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3264 break;
3265 default:
3266 break;
3267 }
3268 return 0;
3269}
3270
3271static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3272 struct amdgpu_irq_src *src,
3273 unsigned type,
3274 enum amdgpu_interrupt_state state)
3275{
7dfac896
AD		 3276 u32 reg;
3277
3278 if (type >= adev->mode_info.num_crtc) {
3279 DRM_ERROR("invalid pageflip crtc %d\n", type);
3280 return -EINVAL;
aaa36a97
AD		 3281 }
3282
7dfac896 3283 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
aaa36a97 3284 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3285 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3286 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97 3287 else
7dfac896
AD		 3288 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3289 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97
AD		 3290
3291 return 0;
3292}
3293
3294static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3295 struct amdgpu_irq_src *source,
3296 struct amdgpu_iv_entry *entry)
3297{
aaa36a97
AD		 3298 unsigned long flags;
3299 unsigned crtc_id;
3300 struct amdgpu_crtc *amdgpu_crtc;
3301 struct amdgpu_flip_work *works;
3302
3303 crtc_id = (entry->src_id - 8) >> 1;
3304 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3305
7dfac896
AD		 3306 if (crtc_id >= adev->mode_info.num_crtc) {
3307 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3308 return -EINVAL;
aaa36a97
AD		 3309 }
3310
7dfac896
AD		 3311 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3312 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3313 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3314 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
aaa36a97
AD		 3315
3316 /* IRQ could occur when in initial stage */
3317 if(amdgpu_crtc == NULL)
3318 return 0;
3319
3320 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3321 works = amdgpu_crtc->pflip_works;
3322 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3323 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3324 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3325 amdgpu_crtc->pflip_status,
3326 AMDGPU_FLIP_SUBMITTED);
3327 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3328 return 0;
3329 }
3330
3331 /* page flip completed. clean up */
3332 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3333 amdgpu_crtc->pflip_works = NULL;
3334
3335 /* wakeup usersapce */
3336 if(works->event)
3337 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3338
3339 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3340
3341 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
87d58c11 3342 schedule_work(&works->unpin_work);
aaa36a97
AD		 3343
3344 return 0;
3345}
3346
3347static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3348 int hpd)
3349{
3350 u32 tmp;
3351
3352 if (hpd >= adev->mode_info.num_hpd) {
3353 DRM_DEBUG("invalid hdp %d\n", hpd);
3354 return;
3355 }
3356
3357 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3358 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3359 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3360}
3361
3362static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3363 int crtc)
3364{
3365 u32 tmp;
3366
15c3277f 3367 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
aaa36a97
AD		 3368 DRM_DEBUG("invalid crtc %d\n", crtc);
3369 return;
3370 }
3371
3372 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3373 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3374 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3375}
3376
3377static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3378 int crtc)
3379{
3380 u32 tmp;
3381
15c3277f 3382 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
aaa36a97
AD		 3383 DRM_DEBUG("invalid crtc %d\n", crtc);
3384 return;
3385 }
3386
3387 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3388 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3389 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3390}
3391
3392static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3393 struct amdgpu_irq_src *source,
3394 struct amdgpu_iv_entry *entry)
3395{
3396 unsigned crtc = entry->src_id - 1;
3397 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3398 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3399
3400 switch (entry->src_data) {
3401 case 0: /* vblank */
bd833144 3402 if (disp_int & interrupt_status_offsets[crtc].vblank)
aaa36a97 3403 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
bd833144
MK		 3404 else
3405 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3406
3407 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3408 drm_handle_vblank(adev->ddev, crtc);
aaa36a97 3409 }
bd833144
MK		 3410 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3411
aaa36a97
AD		 3412 break;
3413 case 1: /* vline */
bd833144 3414 if (disp_int & interrupt_status_offsets[crtc].vline)
aaa36a97 3415 dce_v11_0_crtc_vline_int_ack(adev, crtc);
bd833144
MK		 3416 else
3417 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3418
3419 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3420
aaa36a97
AD		 3421 break;
3422 default:
3423 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3424 break;
3425 }
3426
3427 return 0;
3428}
3429
3430static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3431 struct amdgpu_irq_src *source,
3432 struct amdgpu_iv_entry *entry)
3433{
3434 uint32_t disp_int, mask;
3435 unsigned hpd;
3436
3437 if (entry->src_data >= adev->mode_info.num_hpd) {
3438 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3439 return 0;
3440 }
3441
3442 hpd = entry->src_data;
3443 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3444 mask = interrupt_status_offsets[hpd].hpd;
3445
3446 if (disp_int & mask) {
3447 dce_v11_0_hpd_int_ack(adev, hpd);
3448 schedule_work(&adev->hotplug_work);
3449 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3450 }
3451
3452 return 0;
3453}
3454
5fc3aeeb 3455static int dce_v11_0_set_clockgating_state(void *handle,
3456 enum amd_clockgating_state state)
aaa36a97
AD		 3457{
3458 return 0;
3459}
3460
5fc3aeeb 3461static int dce_v11_0_set_powergating_state(void *handle,
3462 enum amd_powergating_state state)
aaa36a97
AD		 3463{
3464 return 0;
3465}
3466
5fc3aeeb 3467const struct amd_ip_funcs dce_v11_0_ip_funcs = {
aaa36a97
AD		 3468 .early_init = dce_v11_0_early_init,
3469 .late_init = NULL,
3470 .sw_init = dce_v11_0_sw_init,
3471 .sw_fini = dce_v11_0_sw_fini,
3472 .hw_init = dce_v11_0_hw_init,
3473 .hw_fini = dce_v11_0_hw_fini,
3474 .suspend = dce_v11_0_suspend,
3475 .resume = dce_v11_0_resume,
3476 .is_idle = dce_v11_0_is_idle,
3477 .wait_for_idle = dce_v11_0_wait_for_idle,
3478 .soft_reset = dce_v11_0_soft_reset,
3479 .print_status = dce_v11_0_print_status,
3480 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3481 .set_powergating_state = dce_v11_0_set_powergating_state,
3482};
3483
3484static void
3485dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3486 struct drm_display_mode *mode,
3487 struct drm_display_mode *adjusted_mode)
3488{
3489 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3490
3491 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3492
3493 /* need to call this here rather than in prepare() since we need some crtc info */
3494 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3495
3496 /* set scaler clears this on some chips */
3497 dce_v11_0_set_interleave(encoder->crtc, mode);
3498
3499 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3500 dce_v11_0_afmt_enable(encoder, true);
3501 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3502 }
3503}
3504
3505static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3506{
3507 struct amdgpu_device *adev = encoder->dev->dev_private;
3508 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3509 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3510
3511 if ((amdgpu_encoder->active_device &
3512 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3513 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3514 ENCODER_OBJECT_ID_NONE)) {
3515 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3516 if (dig) {
3517 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3518 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3519 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3520 }
3521 }
3522
3523 amdgpu_atombios_scratch_regs_lock(adev, true);
3524
3525 if (connector) {
3526 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3527
3528 /* select the clock/data port if it uses a router */
3529 if (amdgpu_connector->router.cd_valid)
3530 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3531
3532 /* turn eDP panel on for mode set */
3533 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3534 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3535 ATOM_TRANSMITTER_ACTION_POWER_ON);
3536 }
3537
3538 /* this is needed for the pll/ss setup to work correctly in some cases */
3539 amdgpu_atombios_encoder_set_crtc_source(encoder);
3540 /* set up the FMT blocks */
3541 dce_v11_0_program_fmt(encoder);
3542}
3543
3544static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3545{
3546 struct drm_device *dev = encoder->dev;
3547 struct amdgpu_device *adev = dev->dev_private;
3548
3549 /* need to call this here as we need the crtc set up */
3550 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3551 amdgpu_atombios_scratch_regs_lock(adev, false);
3552}
3553
3554static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3555{
3556 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3557 struct amdgpu_encoder_atom_dig *dig;
3558
3559 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3560
3561 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3562 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3563 dce_v11_0_afmt_enable(encoder, false);
3564 dig = amdgpu_encoder->enc_priv;
3565 dig->dig_encoder = -1;
3566 }
3567 amdgpu_encoder->active_device = 0;
3568}
3569
3570/* these are handled by the primary encoders */
3571static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3572{
3573
3574}
3575
3576static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3577{
3578
3579}
3580
3581static void
3582dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3583 struct drm_display_mode *mode,
3584 struct drm_display_mode *adjusted_mode)
3585{
3586
3587}
3588
3589static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3590{
3591
3592}
3593
3594static void
3595dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3596{
3597
3598}
3599
aaa36a97
AD		 3600static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3601 .dpms = dce_v11_0_ext_dpms,
aaa36a97
AD		 3602 .prepare = dce_v11_0_ext_prepare,
3603 .mode_set = dce_v11_0_ext_mode_set,
3604 .commit = dce_v11_0_ext_commit,
3605 .disable = dce_v11_0_ext_disable,
3606 /* no detect for TMDS/LVDS yet */
3607};
3608
3609static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3610 .dpms = amdgpu_atombios_encoder_dpms,
3611 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3612 .prepare = dce_v11_0_encoder_prepare,
3613 .mode_set = dce_v11_0_encoder_mode_set,
3614 .commit = dce_v11_0_encoder_commit,
3615 .disable = dce_v11_0_encoder_disable,
3616 .detect = amdgpu_atombios_encoder_dig_detect,
3617};
3618
3619static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3620 .dpms = amdgpu_atombios_encoder_dpms,
3621 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3622 .prepare = dce_v11_0_encoder_prepare,
3623 .mode_set = dce_v11_0_encoder_mode_set,
3624 .commit = dce_v11_0_encoder_commit,
3625 .detect = amdgpu_atombios_encoder_dac_detect,
3626};
3627
3628static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3629{
3630 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3631 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3632 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3633 kfree(amdgpu_encoder->enc_priv);
3634 drm_encoder_cleanup(encoder);
3635 kfree(amdgpu_encoder);
3636}
3637
3638static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3639 .destroy = dce_v11_0_encoder_destroy,
3640};
3641
3642static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3643 uint32_t encoder_enum,
3644 uint32_t supported_device,
3645 u16 caps)
3646{
3647 struct drm_device *dev = adev->ddev;
3648 struct drm_encoder *encoder;
3649 struct amdgpu_encoder *amdgpu_encoder;
3650
3651 /* see if we already added it */
3652 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3653 amdgpu_encoder = to_amdgpu_encoder(encoder);
3654 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3655 amdgpu_encoder->devices |= supported_device;
3656 return;
3657 }
3658
3659 }
3660
3661 /* add a new one */
3662 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3663 if (!amdgpu_encoder)
3664 return;
3665
3666 encoder = &amdgpu_encoder->base;
3667 switch (adev->mode_info.num_crtc) {
3668 case 1:
3669 encoder->possible_crtcs = 0x1;
3670 break;
3671 case 2:
3672 default:
3673 encoder->possible_crtcs = 0x3;
3674 break;
3675 case 4:
3676 encoder->possible_crtcs = 0xf;
3677 break;
3678 case 6:
3679 encoder->possible_crtcs = 0x3f;
3680 break;
3681 }
3682
3683 amdgpu_encoder->enc_priv = NULL;
3684
3685 amdgpu_encoder->encoder_enum = encoder_enum;
3686 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3687 amdgpu_encoder->devices = supported_device;
3688 amdgpu_encoder->rmx_type = RMX_OFF;
3689 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3690 amdgpu_encoder->is_ext_encoder = false;
3691 amdgpu_encoder->caps = caps;
3692
3693 switch (amdgpu_encoder->encoder_id) {
3694 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3695 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3696 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3697 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3698 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3699 break;
3700 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3701 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3702 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3703 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3704 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3705 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3706 amdgpu_encoder->rmx_type = RMX_FULL;
3707 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3708 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3709 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3710 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3711 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3712 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3713 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3714 } else {
3715 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3716 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3717 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3718 }
3719 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3720 break;
3721 case ENCODER_OBJECT_ID_SI170B:
3722 case ENCODER_OBJECT_ID_CH7303:
3723 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3724 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3725 case ENCODER_OBJECT_ID_TITFP513:
3726 case ENCODER_OBJECT_ID_VT1623:
3727 case ENCODER_OBJECT_ID_HDMI_SI1930:
3728 case ENCODER_OBJECT_ID_TRAVIS:
3729 case ENCODER_OBJECT_ID_NUTMEG:
3730 /* these are handled by the primary encoders */
3731 amdgpu_encoder->is_ext_encoder = true;
3732 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3733 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3734 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3735 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3736 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3737 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3738 else
3739 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
13a3d91f 3740 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3741 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3742 break;
3743 }
3744}
3745
3746static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3747 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3748 .bandwidth_update = &dce_v11_0_bandwidth_update,
3749 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3750 .vblank_wait = &dce_v11_0_vblank_wait,
3751 .is_display_hung = &dce_v11_0_is_display_hung,
3752 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3753 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3754 .hpd_sense = &dce_v11_0_hpd_sense,
3755 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3756 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3757 .page_flip = &dce_v11_0_page_flip,
3758 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3759 .add_encoder = &dce_v11_0_encoder_add,
3760 .add_connector = &amdgpu_connector_add,
3761 .stop_mc_access = &dce_v11_0_stop_mc_access,
3762 .resume_mc_access = &dce_v11_0_resume_mc_access,
3763};
3764
3765static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3766{
3767 if (adev->mode_info.funcs == NULL)
3768 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3769}
3770
3771static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3772 .set = dce_v11_0_set_crtc_irq_state,
3773 .process = dce_v11_0_crtc_irq,
3774};
3775
3776static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3777 .set = dce_v11_0_set_pageflip_irq_state,
3778 .process = dce_v11_0_pageflip_irq,
3779};
3780
3781static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3782 .set = dce_v11_0_set_hpd_irq_state,
3783 .process = dce_v11_0_hpd_irq,
3784};
3785
3786static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3787{
3788 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3789 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3790
3791 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3792 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3793
3794 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3795 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3796}
Linux 6.x block layer and io_uring tree(s)