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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include "drmP.h" | |
24 | #include "amdgpu.h" | |
25 | #include "amdgpu_pm.h" | |
26 | #include "amdgpu_i2c.h" | |
27 | #include "vid.h" | |
28 | #include "atom.h" | |
29 | #include "amdgpu_atombios.h" | |
30 | #include "atombios_crtc.h" | |
31 | #include "atombios_encoders.h" | |
32 | #include "amdgpu_pll.h" | |
33 | #include "amdgpu_connectors.h" | |
34 | ||
35 | #include "dce/dce_10_0_d.h" | |
36 | #include "dce/dce_10_0_sh_mask.h" | |
37 | #include "dce/dce_10_0_enum.h" | |
38 | #include "oss/oss_3_0_d.h" | |
39 | #include "oss/oss_3_0_sh_mask.h" | |
40 | #include "gmc/gmc_8_1_d.h" | |
41 | #include "gmc/gmc_8_1_sh_mask.h" | |
42 | ||
43 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); | |
44 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); | |
45 | ||
46 | static const u32 crtc_offsets[] = | |
47 | { | |
48 | CRTC0_REGISTER_OFFSET, | |
49 | CRTC1_REGISTER_OFFSET, | |
50 | CRTC2_REGISTER_OFFSET, | |
51 | CRTC3_REGISTER_OFFSET, | |
52 | CRTC4_REGISTER_OFFSET, | |
53 | CRTC5_REGISTER_OFFSET, | |
54 | CRTC6_REGISTER_OFFSET | |
55 | }; | |
56 | ||
57 | static const u32 hpd_offsets[] = | |
58 | { | |
59 | HPD0_REGISTER_OFFSET, | |
60 | HPD1_REGISTER_OFFSET, | |
61 | HPD2_REGISTER_OFFSET, | |
62 | HPD3_REGISTER_OFFSET, | |
63 | HPD4_REGISTER_OFFSET, | |
64 | HPD5_REGISTER_OFFSET | |
65 | }; | |
66 | ||
67 | static const uint32_t dig_offsets[] = { | |
68 | DIG0_REGISTER_OFFSET, | |
69 | DIG1_REGISTER_OFFSET, | |
70 | DIG2_REGISTER_OFFSET, | |
71 | DIG3_REGISTER_OFFSET, | |
72 | DIG4_REGISTER_OFFSET, | |
73 | DIG5_REGISTER_OFFSET, | |
74 | DIG6_REGISTER_OFFSET | |
75 | }; | |
76 | ||
77 | static const struct { | |
78 | uint32_t reg; | |
79 | uint32_t vblank; | |
80 | uint32_t vline; | |
81 | uint32_t hpd; | |
82 | ||
83 | } interrupt_status_offsets[] = { { | |
84 | .reg = mmDISP_INTERRUPT_STATUS, | |
85 | .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, | |
86 | .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, | |
87 | .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK | |
88 | }, { | |
89 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, | |
90 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, | |
91 | .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, | |
92 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK | |
93 | }, { | |
94 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, | |
95 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, | |
96 | .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, | |
97 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK | |
98 | }, { | |
99 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, | |
100 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, | |
101 | .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, | |
102 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK | |
103 | }, { | |
104 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, | |
105 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, | |
106 | .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, | |
107 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK | |
108 | }, { | |
109 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, | |
110 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, | |
111 | .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, | |
112 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK | |
113 | } }; | |
114 | ||
115 | static const u32 golden_settings_tonga_a11[] = | |
116 | { | |
117 | mmDCI_CLK_CNTL, 0x00000080, 0x00000000, | |
118 | mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, | |
119 | mmFBC_MISC, 0x1f311fff, 0x12300000, | |
120 | mmHDMI_CONTROL, 0x31000111, 0x00000011, | |
121 | }; | |
122 | ||
5732a94f AD |
123 | static const u32 tonga_mgcg_cgcg_init[] = |
124 | { | |
125 | mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, | |
126 | mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, | |
127 | }; | |
128 | ||
84390860 DZ |
129 | static const u32 golden_settings_fiji_a10[] = |
130 | { | |
131 | mmDCI_CLK_CNTL, 0x00000080, 0x00000000, | |
132 | mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, | |
133 | mmFBC_MISC, 0x1f311fff, 0x12300000, | |
134 | mmHDMI_CONTROL, 0x31000111, 0x00000011, | |
135 | }; | |
136 | ||
137 | static const u32 fiji_mgcg_cgcg_init[] = | |
138 | { | |
139 | mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, | |
140 | mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, | |
141 | }; | |
142 | ||
aaa36a97 AD |
143 | static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) |
144 | { | |
145 | switch (adev->asic_type) { | |
84390860 DZ |
146 | case CHIP_FIJI: |
147 | amdgpu_program_register_sequence(adev, | |
148 | fiji_mgcg_cgcg_init, | |
149 | (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); | |
150 | amdgpu_program_register_sequence(adev, | |
151 | golden_settings_fiji_a10, | |
152 | (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); | |
153 | break; | |
aaa36a97 | 154 | case CHIP_TONGA: |
5732a94f AD |
155 | amdgpu_program_register_sequence(adev, |
156 | tonga_mgcg_cgcg_init, | |
157 | (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); | |
aaa36a97 AD |
158 | amdgpu_program_register_sequence(adev, |
159 | golden_settings_tonga_a11, | |
160 | (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); | |
161 | break; | |
162 | default: | |
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, | |
168 | u32 block_offset, u32 reg) | |
169 | { | |
170 | unsigned long flags; | |
171 | u32 r; | |
172 | ||
173 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); | |
174 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); | |
175 | r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); | |
176 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); | |
177 | ||
178 | return r; | |
179 | } | |
180 | ||
181 | static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, | |
182 | u32 block_offset, u32 reg, u32 v) | |
183 | { | |
184 | unsigned long flags; | |
185 | ||
186 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); | |
187 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); | |
188 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); | |
189 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); | |
190 | } | |
191 | ||
192 | static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) | |
193 | { | |
194 | if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & | |
195 | CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) | |
196 | return true; | |
197 | else | |
198 | return false; | |
199 | } | |
200 | ||
201 | static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) | |
202 | { | |
203 | u32 pos1, pos2; | |
204 | ||
205 | pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
206 | pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
207 | ||
208 | if (pos1 != pos2) | |
209 | return true; | |
210 | else | |
211 | return false; | |
212 | } | |
213 | ||
214 | /** | |
215 | * dce_v10_0_vblank_wait - vblank wait asic callback. | |
216 | * | |
217 | * @adev: amdgpu_device pointer | |
218 | * @crtc: crtc to wait for vblank on | |
219 | * | |
220 | * Wait for vblank on the requested crtc (evergreen+). | |
221 | */ | |
222 | static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) | |
223 | { | |
224 | unsigned i = 0; | |
225 | ||
226 | if (crtc >= adev->mode_info.num_crtc) | |
227 | return; | |
228 | ||
229 | if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) | |
230 | return; | |
231 | ||
232 | /* depending on when we hit vblank, we may be close to active; if so, | |
233 | * wait for another frame. | |
234 | */ | |
235 | while (dce_v10_0_is_in_vblank(adev, crtc)) { | |
236 | if (i++ % 100 == 0) { | |
237 | if (!dce_v10_0_is_counter_moving(adev, crtc)) | |
238 | break; | |
239 | } | |
240 | } | |
241 | ||
242 | while (!dce_v10_0_is_in_vblank(adev, crtc)) { | |
243 | if (i++ % 100 == 0) { | |
244 | if (!dce_v10_0_is_counter_moving(adev, crtc)) | |
245 | break; | |
246 | } | |
247 | } | |
248 | } | |
249 | ||
250 | static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
251 | { | |
252 | if (crtc >= adev->mode_info.num_crtc) | |
253 | return 0; | |
254 | else | |
255 | return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); | |
256 | } | |
257 | ||
258 | /** | |
259 | * dce_v10_0_page_flip - pageflip callback. | |
260 | * | |
261 | * @adev: amdgpu_device pointer | |
262 | * @crtc_id: crtc to cleanup pageflip on | |
263 | * @crtc_base: new address of the crtc (GPU MC address) | |
264 | * | |
265 | * Does the actual pageflip (evergreen+). | |
266 | * During vblank we take the crtc lock and wait for the update_pending | |
267 | * bit to go high, when it does, we release the lock, and allow the | |
268 | * double buffered update to take place. | |
269 | * Returns the current update pending status. | |
270 | */ | |
271 | static void dce_v10_0_page_flip(struct amdgpu_device *adev, | |
272 | int crtc_id, u64 crtc_base) | |
273 | { | |
274 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; | |
275 | u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); | |
276 | int i; | |
277 | ||
278 | /* Lock the graphics update lock */ | |
279 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); | |
280 | WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); | |
281 | ||
282 | /* update the scanout addresses */ | |
283 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
284 | upper_32_bits(crtc_base)); | |
285 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
286 | lower_32_bits(crtc_base)); | |
287 | ||
288 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
289 | upper_32_bits(crtc_base)); | |
290 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
291 | lower_32_bits(crtc_base)); | |
292 | ||
293 | /* Wait for update_pending to go high. */ | |
294 | for (i = 0; i < adev->usec_timeout; i++) { | |
295 | if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & | |
296 | GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) | |
297 | break; | |
298 | udelay(1); | |
299 | } | |
300 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); | |
301 | ||
302 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
303 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); | |
304 | WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); | |
305 | } | |
306 | ||
307 | static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
308 | u32 *vbl, u32 *position) | |
309 | { | |
310 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) | |
311 | return -EINVAL; | |
312 | ||
313 | *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); | |
314 | *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | /** | |
320 | * dce_v10_0_hpd_sense - hpd sense callback. | |
321 | * | |
322 | * @adev: amdgpu_device pointer | |
323 | * @hpd: hpd (hotplug detect) pin | |
324 | * | |
325 | * Checks if a digital monitor is connected (evergreen+). | |
326 | * Returns true if connected, false if not connected. | |
327 | */ | |
328 | static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, | |
329 | enum amdgpu_hpd_id hpd) | |
330 | { | |
331 | int idx; | |
332 | bool connected = false; | |
333 | ||
334 | switch (hpd) { | |
335 | case AMDGPU_HPD_1: | |
336 | idx = 0; | |
337 | break; | |
338 | case AMDGPU_HPD_2: | |
339 | idx = 1; | |
340 | break; | |
341 | case AMDGPU_HPD_3: | |
342 | idx = 2; | |
343 | break; | |
344 | case AMDGPU_HPD_4: | |
345 | idx = 3; | |
346 | break; | |
347 | case AMDGPU_HPD_5: | |
348 | idx = 4; | |
349 | break; | |
350 | case AMDGPU_HPD_6: | |
351 | idx = 5; | |
352 | break; | |
353 | default: | |
354 | return connected; | |
355 | } | |
356 | ||
357 | if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & | |
358 | DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) | |
359 | connected = true; | |
360 | ||
361 | return connected; | |
362 | } | |
363 | ||
364 | /** | |
365 | * dce_v10_0_hpd_set_polarity - hpd set polarity callback. | |
366 | * | |
367 | * @adev: amdgpu_device pointer | |
368 | * @hpd: hpd (hotplug detect) pin | |
369 | * | |
370 | * Set the polarity of the hpd pin (evergreen+). | |
371 | */ | |
372 | static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, | |
373 | enum amdgpu_hpd_id hpd) | |
374 | { | |
375 | u32 tmp; | |
376 | bool connected = dce_v10_0_hpd_sense(adev, hpd); | |
377 | int idx; | |
378 | ||
379 | switch (hpd) { | |
380 | case AMDGPU_HPD_1: | |
381 | idx = 0; | |
382 | break; | |
383 | case AMDGPU_HPD_2: | |
384 | idx = 1; | |
385 | break; | |
386 | case AMDGPU_HPD_3: | |
387 | idx = 2; | |
388 | break; | |
389 | case AMDGPU_HPD_4: | |
390 | idx = 3; | |
391 | break; | |
392 | case AMDGPU_HPD_5: | |
393 | idx = 4; | |
394 | break; | |
395 | case AMDGPU_HPD_6: | |
396 | idx = 5; | |
397 | break; | |
398 | default: | |
399 | return; | |
400 | } | |
401 | ||
402 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); | |
403 | if (connected) | |
404 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); | |
405 | else | |
406 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); | |
407 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); | |
408 | } | |
409 | ||
410 | /** | |
411 | * dce_v10_0_hpd_init - hpd setup callback. | |
412 | * | |
413 | * @adev: amdgpu_device pointer | |
414 | * | |
415 | * Setup the hpd pins used by the card (evergreen+). | |
416 | * Enable the pin, set the polarity, and enable the hpd interrupts. | |
417 | */ | |
418 | static void dce_v10_0_hpd_init(struct amdgpu_device *adev) | |
419 | { | |
420 | struct drm_device *dev = adev->ddev; | |
421 | struct drm_connector *connector; | |
422 | u32 tmp; | |
423 | int idx; | |
424 | ||
425 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
426 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
427 | ||
428 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || | |
429 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { | |
430 | /* don't try to enable hpd on eDP or LVDS avoid breaking the | |
431 | * aux dp channel on imac and help (but not completely fix) | |
432 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 | |
433 | * also avoid interrupt storms during dpms. | |
434 | */ | |
435 | continue; | |
436 | } | |
437 | ||
438 | switch (amdgpu_connector->hpd.hpd) { | |
439 | case AMDGPU_HPD_1: | |
440 | idx = 0; | |
441 | break; | |
442 | case AMDGPU_HPD_2: | |
443 | idx = 1; | |
444 | break; | |
445 | case AMDGPU_HPD_3: | |
446 | idx = 2; | |
447 | break; | |
448 | case AMDGPU_HPD_4: | |
449 | idx = 3; | |
450 | break; | |
451 | case AMDGPU_HPD_5: | |
452 | idx = 4; | |
453 | break; | |
454 | case AMDGPU_HPD_6: | |
455 | idx = 5; | |
456 | break; | |
457 | default: | |
458 | continue; | |
459 | } | |
460 | ||
461 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); | |
462 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); | |
463 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); | |
464 | ||
465 | tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); | |
466 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, | |
467 | DC_HPD_CONNECT_INT_DELAY, | |
468 | AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); | |
469 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, | |
470 | DC_HPD_DISCONNECT_INT_DELAY, | |
471 | AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); | |
472 | WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); | |
473 | ||
474 | dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); | |
475 | amdgpu_irq_get(adev, &adev->hpd_irq, | |
476 | amdgpu_connector->hpd.hpd); | |
477 | } | |
478 | } | |
479 | ||
480 | /** | |
481 | * dce_v10_0_hpd_fini - hpd tear down callback. | |
482 | * | |
483 | * @adev: amdgpu_device pointer | |
484 | * | |
485 | * Tear down the hpd pins used by the card (evergreen+). | |
486 | * Disable the hpd interrupts. | |
487 | */ | |
488 | static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) | |
489 | { | |
490 | struct drm_device *dev = adev->ddev; | |
491 | struct drm_connector *connector; | |
492 | u32 tmp; | |
493 | int idx; | |
494 | ||
495 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
496 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
497 | ||
498 | switch (amdgpu_connector->hpd.hpd) { | |
499 | case AMDGPU_HPD_1: | |
500 | idx = 0; | |
501 | break; | |
502 | case AMDGPU_HPD_2: | |
503 | idx = 1; | |
504 | break; | |
505 | case AMDGPU_HPD_3: | |
506 | idx = 2; | |
507 | break; | |
508 | case AMDGPU_HPD_4: | |
509 | idx = 3; | |
510 | break; | |
511 | case AMDGPU_HPD_5: | |
512 | idx = 4; | |
513 | break; | |
514 | case AMDGPU_HPD_6: | |
515 | idx = 5; | |
516 | break; | |
517 | default: | |
518 | continue; | |
519 | } | |
520 | ||
521 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); | |
522 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); | |
523 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); | |
524 | ||
525 | amdgpu_irq_put(adev, &adev->hpd_irq, | |
526 | amdgpu_connector->hpd.hpd); | |
527 | } | |
528 | } | |
529 | ||
530 | static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) | |
531 | { | |
532 | return mmDC_GPIO_HPD_A; | |
533 | } | |
534 | ||
535 | static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) | |
536 | { | |
537 | u32 crtc_hung = 0; | |
538 | u32 crtc_status[6]; | |
539 | u32 i, j, tmp; | |
540 | ||
541 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
542 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); | |
543 | if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { | |
544 | crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
545 | crtc_hung |= (1 << i); | |
546 | } | |
547 | } | |
548 | ||
549 | for (j = 0; j < 10; j++) { | |
550 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
551 | if (crtc_hung & (1 << i)) { | |
552 | tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
553 | if (tmp != crtc_status[i]) | |
554 | crtc_hung &= ~(1 << i); | |
555 | } | |
556 | } | |
557 | if (crtc_hung == 0) | |
558 | return false; | |
559 | udelay(100); | |
560 | } | |
561 | ||
562 | return true; | |
563 | } | |
564 | ||
565 | static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, | |
566 | struct amdgpu_mode_mc_save *save) | |
567 | { | |
568 | u32 crtc_enabled, tmp; | |
569 | int i; | |
570 | ||
571 | save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); | |
572 | save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); | |
573 | ||
574 | /* disable VGA render */ | |
575 | tmp = RREG32(mmVGA_RENDER_CONTROL); | |
576 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); | |
577 | WREG32(mmVGA_RENDER_CONTROL, tmp); | |
578 | ||
579 | /* blank the display controllers */ | |
580 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
581 | crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), | |
582 | CRTC_CONTROL, CRTC_MASTER_EN); | |
583 | if (crtc_enabled) { | |
584 | #if 0 | |
585 | u32 frame_count; | |
586 | int j; | |
587 | ||
588 | save->crtc_enabled[i] = true; | |
589 | tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); | |
590 | if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { | |
591 | amdgpu_display_vblank_wait(adev, i); | |
592 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
593 | tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); | |
594 | WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); | |
595 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
596 | } | |
597 | /* wait for the next frame */ | |
598 | frame_count = amdgpu_display_vblank_get_counter(adev, i); | |
599 | for (j = 0; j < adev->usec_timeout; j++) { | |
600 | if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) | |
601 | break; | |
602 | udelay(1); | |
603 | } | |
604 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); | |
605 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { | |
606 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); | |
607 | WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); | |
608 | } | |
609 | tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); | |
610 | if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { | |
611 | tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); | |
612 | WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); | |
613 | } | |
614 | #else | |
615 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ | |
616 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
617 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); | |
618 | tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); | |
619 | WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); | |
620 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
621 | save->crtc_enabled[i] = false; | |
622 | /* ***** */ | |
623 | #endif | |
624 | } else { | |
625 | save->crtc_enabled[i] = false; | |
626 | } | |
627 | } | |
628 | } | |
629 | ||
630 | static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, | |
631 | struct amdgpu_mode_mc_save *save) | |
632 | { | |
633 | u32 tmp, frame_count; | |
634 | int i, j; | |
635 | ||
636 | /* update crtc base addresses */ | |
637 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
638 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], | |
639 | upper_32_bits(adev->mc.vram_start)); | |
640 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], | |
641 | upper_32_bits(adev->mc.vram_start)); | |
642 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], | |
643 | (u32)adev->mc.vram_start); | |
644 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], | |
645 | (u32)adev->mc.vram_start); | |
646 | ||
647 | if (save->crtc_enabled[i]) { | |
648 | tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); | |
649 | if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { | |
650 | tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); | |
651 | WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); | |
652 | } | |
653 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); | |
654 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { | |
655 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); | |
656 | WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); | |
657 | } | |
658 | tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); | |
659 | if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { | |
660 | tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); | |
661 | WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); | |
662 | } | |
663 | for (j = 0; j < adev->usec_timeout; j++) { | |
664 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); | |
665 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) | |
666 | break; | |
667 | udelay(1); | |
668 | } | |
669 | tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); | |
670 | tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); | |
671 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); | |
672 | WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); | |
673 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); | |
674 | /* wait for the next frame */ | |
675 | frame_count = amdgpu_display_vblank_get_counter(adev, i); | |
676 | for (j = 0; j < adev->usec_timeout; j++) { | |
677 | if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) | |
678 | break; | |
679 | udelay(1); | |
680 | } | |
681 | } | |
682 | } | |
683 | ||
684 | WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); | |
685 | WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); | |
686 | ||
687 | /* Unlock vga access */ | |
688 | WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); | |
689 | mdelay(1); | |
690 | WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); | |
691 | } | |
692 | ||
693 | static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, | |
694 | bool render) | |
695 | { | |
696 | u32 tmp; | |
697 | ||
698 | /* Lockout access through VGA aperture*/ | |
699 | tmp = RREG32(mmVGA_HDP_CONTROL); | |
700 | if (render) | |
701 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); | |
702 | else | |
703 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); | |
704 | WREG32(mmVGA_HDP_CONTROL, tmp); | |
705 | ||
706 | /* disable VGA render */ | |
707 | tmp = RREG32(mmVGA_RENDER_CONTROL); | |
708 | if (render) | |
709 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); | |
710 | else | |
711 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); | |
712 | WREG32(mmVGA_RENDER_CONTROL, tmp); | |
713 | } | |
714 | ||
715 | static void dce_v10_0_program_fmt(struct drm_encoder *encoder) | |
716 | { | |
717 | struct drm_device *dev = encoder->dev; | |
718 | struct amdgpu_device *adev = dev->dev_private; | |
719 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
720 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); | |
721 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); | |
722 | int bpc = 0; | |
723 | u32 tmp = 0; | |
724 | enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; | |
725 | ||
726 | if (connector) { | |
727 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
728 | bpc = amdgpu_connector_get_monitor_bpc(connector); | |
729 | dither = amdgpu_connector->dither; | |
730 | } | |
731 | ||
732 | /* LVDS/eDP FMT is set up by atom */ | |
733 | if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
734 | return; | |
735 | ||
736 | /* not needed for analog */ | |
737 | if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || | |
738 | (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) | |
739 | return; | |
740 | ||
741 | if (bpc == 0) | |
742 | return; | |
743 | ||
744 | switch (bpc) { | |
745 | case 6: | |
746 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { | |
747 | /* XXX sort out optimal dither settings */ | |
748 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); | |
749 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); | |
750 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); | |
751 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); | |
752 | } else { | |
753 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); | |
754 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); | |
755 | } | |
756 | break; | |
757 | case 8: | |
758 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { | |
759 | /* XXX sort out optimal dither settings */ | |
760 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); | |
761 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); | |
762 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); | |
763 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); | |
764 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); | |
765 | } else { | |
766 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); | |
767 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); | |
768 | } | |
769 | break; | |
770 | case 10: | |
771 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { | |
772 | /* XXX sort out optimal dither settings */ | |
773 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); | |
774 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); | |
775 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); | |
776 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); | |
777 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); | |
778 | } else { | |
779 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); | |
780 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); | |
781 | } | |
782 | break; | |
783 | default: | |
784 | /* not needed */ | |
785 | break; | |
786 | } | |
787 | ||
788 | WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
789 | } | |
790 | ||
791 | ||
792 | /* display watermark setup */ | |
793 | /** | |
794 | * dce_v10_0_line_buffer_adjust - Set up the line buffer | |
795 | * | |
796 | * @adev: amdgpu_device pointer | |
797 | * @amdgpu_crtc: the selected display controller | |
798 | * @mode: the current display mode on the selected display | |
799 | * controller | |
800 | * | |
801 | * Setup up the line buffer allocation for | |
802 | * the selected display controller (CIK). | |
803 | * Returns the line buffer size in pixels. | |
804 | */ | |
805 | static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, | |
806 | struct amdgpu_crtc *amdgpu_crtc, | |
807 | struct drm_display_mode *mode) | |
808 | { | |
809 | u32 tmp, buffer_alloc, i, mem_cfg; | |
810 | u32 pipe_offset = amdgpu_crtc->crtc_id; | |
811 | /* | |
812 | * Line Buffer Setup | |
813 | * There are 6 line buffers, one for each display controllers. | |
814 | * There are 3 partitions per LB. Select the number of partitions | |
815 | * to enable based on the display width. For display widths larger | |
816 | * than 4096, you need use to use 2 display controllers and combine | |
817 | * them using the stereo blender. | |
818 | */ | |
819 | if (amdgpu_crtc->base.enabled && mode) { | |
820 | if (mode->crtc_hdisplay < 1920) { | |
821 | mem_cfg = 1; | |
822 | buffer_alloc = 2; | |
823 | } else if (mode->crtc_hdisplay < 2560) { | |
824 | mem_cfg = 2; | |
825 | buffer_alloc = 2; | |
826 | } else if (mode->crtc_hdisplay < 4096) { | |
827 | mem_cfg = 0; | |
2f7d10b3 | 828 | buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; |
aaa36a97 AD |
829 | } else { |
830 | DRM_DEBUG_KMS("Mode too big for LB!\n"); | |
831 | mem_cfg = 0; | |
2f7d10b3 | 832 | buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; |
aaa36a97 AD |
833 | } |
834 | } else { | |
835 | mem_cfg = 1; | |
836 | buffer_alloc = 0; | |
837 | } | |
838 | ||
839 | tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); | |
840 | tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); | |
841 | WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); | |
842 | ||
843 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); | |
844 | tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); | |
845 | WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); | |
846 | ||
847 | for (i = 0; i < adev->usec_timeout; i++) { | |
848 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); | |
849 | if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) | |
850 | break; | |
851 | udelay(1); | |
852 | } | |
853 | ||
854 | if (amdgpu_crtc->base.enabled && mode) { | |
855 | switch (mem_cfg) { | |
856 | case 0: | |
857 | default: | |
858 | return 4096 * 2; | |
859 | case 1: | |
860 | return 1920 * 2; | |
861 | case 2: | |
862 | return 2560 * 2; | |
863 | } | |
864 | } | |
865 | ||
866 | /* controller not enabled, so no lb used */ | |
867 | return 0; | |
868 | } | |
869 | ||
870 | /** | |
871 | * cik_get_number_of_dram_channels - get the number of dram channels | |
872 | * | |
873 | * @adev: amdgpu_device pointer | |
874 | * | |
875 | * Look up the number of video ram channels (CIK). | |
876 | * Used for display watermark bandwidth calculations | |
877 | * Returns the number of dram channels | |
878 | */ | |
879 | static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) | |
880 | { | |
881 | u32 tmp = RREG32(mmMC_SHARED_CHMAP); | |
882 | ||
883 | switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { | |
884 | case 0: | |
885 | default: | |
886 | return 1; | |
887 | case 1: | |
888 | return 2; | |
889 | case 2: | |
890 | return 4; | |
891 | case 3: | |
892 | return 8; | |
893 | case 4: | |
894 | return 3; | |
895 | case 5: | |
896 | return 6; | |
897 | case 6: | |
898 | return 10; | |
899 | case 7: | |
900 | return 12; | |
901 | case 8: | |
902 | return 16; | |
903 | } | |
904 | } | |
905 | ||
906 | struct dce10_wm_params { | |
907 | u32 dram_channels; /* number of dram channels */ | |
908 | u32 yclk; /* bandwidth per dram data pin in kHz */ | |
909 | u32 sclk; /* engine clock in kHz */ | |
910 | u32 disp_clk; /* display clock in kHz */ | |
911 | u32 src_width; /* viewport width */ | |
912 | u32 active_time; /* active display time in ns */ | |
913 | u32 blank_time; /* blank time in ns */ | |
914 | bool interlaced; /* mode is interlaced */ | |
915 | fixed20_12 vsc; /* vertical scale ratio */ | |
916 | u32 num_heads; /* number of active crtcs */ | |
917 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ | |
918 | u32 lb_size; /* line buffer allocated to pipe */ | |
919 | u32 vtaps; /* vertical scaler taps */ | |
920 | }; | |
921 | ||
922 | /** | |
923 | * dce_v10_0_dram_bandwidth - get the dram bandwidth | |
924 | * | |
925 | * @wm: watermark calculation data | |
926 | * | |
927 | * Calculate the raw dram bandwidth (CIK). | |
928 | * Used for display watermark bandwidth calculations | |
929 | * Returns the dram bandwidth in MBytes/s | |
930 | */ | |
931 | static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) | |
932 | { | |
933 | /* Calculate raw DRAM Bandwidth */ | |
934 | fixed20_12 dram_efficiency; /* 0.7 */ | |
935 | fixed20_12 yclk, dram_channels, bandwidth; | |
936 | fixed20_12 a; | |
937 | ||
938 | a.full = dfixed_const(1000); | |
939 | yclk.full = dfixed_const(wm->yclk); | |
940 | yclk.full = dfixed_div(yclk, a); | |
941 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
942 | a.full = dfixed_const(10); | |
943 | dram_efficiency.full = dfixed_const(7); | |
944 | dram_efficiency.full = dfixed_div(dram_efficiency, a); | |
945 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
946 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); | |
947 | ||
948 | return dfixed_trunc(bandwidth); | |
949 | } | |
950 | ||
951 | /** | |
952 | * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display | |
953 | * | |
954 | * @wm: watermark calculation data | |
955 | * | |
956 | * Calculate the dram bandwidth used for display (CIK). | |
957 | * Used for display watermark bandwidth calculations | |
958 | * Returns the dram bandwidth for display in MBytes/s | |
959 | */ | |
960 | static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) | |
961 | { | |
962 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
963 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ | |
964 | fixed20_12 yclk, dram_channels, bandwidth; | |
965 | fixed20_12 a; | |
966 | ||
967 | a.full = dfixed_const(1000); | |
968 | yclk.full = dfixed_const(wm->yclk); | |
969 | yclk.full = dfixed_div(yclk, a); | |
970 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
971 | a.full = dfixed_const(10); | |
972 | disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ | |
973 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); | |
974 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
975 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); | |
976 | ||
977 | return dfixed_trunc(bandwidth); | |
978 | } | |
979 | ||
980 | /** | |
981 | * dce_v10_0_data_return_bandwidth - get the data return bandwidth | |
982 | * | |
983 | * @wm: watermark calculation data | |
984 | * | |
985 | * Calculate the data return bandwidth used for display (CIK). | |
986 | * Used for display watermark bandwidth calculations | |
987 | * Returns the data return bandwidth in MBytes/s | |
988 | */ | |
989 | static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) | |
990 | { | |
991 | /* Calculate the display Data return Bandwidth */ | |
992 | fixed20_12 return_efficiency; /* 0.8 */ | |
993 | fixed20_12 sclk, bandwidth; | |
994 | fixed20_12 a; | |
995 | ||
996 | a.full = dfixed_const(1000); | |
997 | sclk.full = dfixed_const(wm->sclk); | |
998 | sclk.full = dfixed_div(sclk, a); | |
999 | a.full = dfixed_const(10); | |
1000 | return_efficiency.full = dfixed_const(8); | |
1001 | return_efficiency.full = dfixed_div(return_efficiency, a); | |
1002 | a.full = dfixed_const(32); | |
1003 | bandwidth.full = dfixed_mul(a, sclk); | |
1004 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency); | |
1005 | ||
1006 | return dfixed_trunc(bandwidth); | |
1007 | } | |
1008 | ||
1009 | /** | |
1010 | * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth | |
1011 | * | |
1012 | * @wm: watermark calculation data | |
1013 | * | |
1014 | * Calculate the dmif bandwidth used for display (CIK). | |
1015 | * Used for display watermark bandwidth calculations | |
1016 | * Returns the dmif bandwidth in MBytes/s | |
1017 | */ | |
1018 | static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) | |
1019 | { | |
1020 | /* Calculate the DMIF Request Bandwidth */ | |
1021 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ | |
1022 | fixed20_12 disp_clk, bandwidth; | |
1023 | fixed20_12 a, b; | |
1024 | ||
1025 | a.full = dfixed_const(1000); | |
1026 | disp_clk.full = dfixed_const(wm->disp_clk); | |
1027 | disp_clk.full = dfixed_div(disp_clk, a); | |
1028 | a.full = dfixed_const(32); | |
1029 | b.full = dfixed_mul(a, disp_clk); | |
1030 | ||
1031 | a.full = dfixed_const(10); | |
1032 | disp_clk_request_efficiency.full = dfixed_const(8); | |
1033 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); | |
1034 | ||
1035 | bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); | |
1036 | ||
1037 | return dfixed_trunc(bandwidth); | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * dce_v10_0_available_bandwidth - get the min available bandwidth | |
1042 | * | |
1043 | * @wm: watermark calculation data | |
1044 | * | |
1045 | * Calculate the min available bandwidth used for display (CIK). | |
1046 | * Used for display watermark bandwidth calculations | |
1047 | * Returns the min available bandwidth in MBytes/s | |
1048 | */ | |
1049 | static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) | |
1050 | { | |
1051 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ | |
1052 | u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); | |
1053 | u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); | |
1054 | u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); | |
1055 | ||
1056 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); | |
1057 | } | |
1058 | ||
1059 | /** | |
1060 | * dce_v10_0_average_bandwidth - get the average available bandwidth | |
1061 | * | |
1062 | * @wm: watermark calculation data | |
1063 | * | |
1064 | * Calculate the average available bandwidth used for display (CIK). | |
1065 | * Used for display watermark bandwidth calculations | |
1066 | * Returns the average available bandwidth in MBytes/s | |
1067 | */ | |
1068 | static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) | |
1069 | { | |
1070 | /* Calculate the display mode Average Bandwidth | |
1071 | * DisplayMode should contain the source and destination dimensions, | |
1072 | * timing, etc. | |
1073 | */ | |
1074 | fixed20_12 bpp; | |
1075 | fixed20_12 line_time; | |
1076 | fixed20_12 src_width; | |
1077 | fixed20_12 bandwidth; | |
1078 | fixed20_12 a; | |
1079 | ||
1080 | a.full = dfixed_const(1000); | |
1081 | line_time.full = dfixed_const(wm->active_time + wm->blank_time); | |
1082 | line_time.full = dfixed_div(line_time, a); | |
1083 | bpp.full = dfixed_const(wm->bytes_per_pixel); | |
1084 | src_width.full = dfixed_const(wm->src_width); | |
1085 | bandwidth.full = dfixed_mul(src_width, bpp); | |
1086 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc); | |
1087 | bandwidth.full = dfixed_div(bandwidth, line_time); | |
1088 | ||
1089 | return dfixed_trunc(bandwidth); | |
1090 | } | |
1091 | ||
1092 | /** | |
1093 | * dce_v10_0_latency_watermark - get the latency watermark | |
1094 | * | |
1095 | * @wm: watermark calculation data | |
1096 | * | |
1097 | * Calculate the latency watermark (CIK). | |
1098 | * Used for display watermark bandwidth calculations | |
1099 | * Returns the latency watermark in ns | |
1100 | */ | |
1101 | static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) | |
1102 | { | |
1103 | /* First calculate the latency in ns */ | |
1104 | u32 mc_latency = 2000; /* 2000 ns. */ | |
1105 | u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); | |
1106 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; | |
1107 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; | |
1108 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ | |
1109 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + | |
1110 | (wm->num_heads * cursor_line_pair_return_time); | |
1111 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; | |
1112 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; | |
1113 | u32 tmp, dmif_size = 12288; | |
1114 | fixed20_12 a, b, c; | |
1115 | ||
1116 | if (wm->num_heads == 0) | |
1117 | return 0; | |
1118 | ||
1119 | a.full = dfixed_const(2); | |
1120 | b.full = dfixed_const(1); | |
1121 | if ((wm->vsc.full > a.full) || | |
1122 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || | |
1123 | (wm->vtaps >= 5) || | |
1124 | ((wm->vsc.full >= a.full) && wm->interlaced)) | |
1125 | max_src_lines_per_dst_line = 4; | |
1126 | else | |
1127 | max_src_lines_per_dst_line = 2; | |
1128 | ||
1129 | a.full = dfixed_const(available_bandwidth); | |
1130 | b.full = dfixed_const(wm->num_heads); | |
1131 | a.full = dfixed_div(a, b); | |
1132 | ||
1133 | b.full = dfixed_const(mc_latency + 512); | |
1134 | c.full = dfixed_const(wm->disp_clk); | |
1135 | b.full = dfixed_div(b, c); | |
1136 | ||
1137 | c.full = dfixed_const(dmif_size); | |
1138 | b.full = dfixed_div(c, b); | |
1139 | ||
1140 | tmp = min(dfixed_trunc(a), dfixed_trunc(b)); | |
1141 | ||
1142 | b.full = dfixed_const(1000); | |
1143 | c.full = dfixed_const(wm->disp_clk); | |
1144 | b.full = dfixed_div(c, b); | |
1145 | c.full = dfixed_const(wm->bytes_per_pixel); | |
1146 | b.full = dfixed_mul(b, c); | |
1147 | ||
1148 | lb_fill_bw = min(tmp, dfixed_trunc(b)); | |
1149 | ||
1150 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | |
1151 | b.full = dfixed_const(1000); | |
1152 | c.full = dfixed_const(lb_fill_bw); | |
1153 | b.full = dfixed_div(c, b); | |
1154 | a.full = dfixed_div(a, b); | |
1155 | line_fill_time = dfixed_trunc(a); | |
1156 | ||
1157 | if (line_fill_time < wm->active_time) | |
1158 | return latency; | |
1159 | else | |
1160 | return latency + (line_fill_time - wm->active_time); | |
1161 | ||
1162 | } | |
1163 | ||
1164 | /** | |
1165 | * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check | |
1166 | * average and available dram bandwidth | |
1167 | * | |
1168 | * @wm: watermark calculation data | |
1169 | * | |
1170 | * Check if the display average bandwidth fits in the display | |
1171 | * dram bandwidth (CIK). | |
1172 | * Used for display watermark bandwidth calculations | |
1173 | * Returns true if the display fits, false if not. | |
1174 | */ | |
1175 | static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) | |
1176 | { | |
1177 | if (dce_v10_0_average_bandwidth(wm) <= | |
1178 | (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) | |
1179 | return true; | |
1180 | else | |
1181 | return false; | |
1182 | } | |
1183 | ||
1184 | /** | |
1185 | * dce_v10_0_average_bandwidth_vs_available_bandwidth - check | |
1186 | * average and available bandwidth | |
1187 | * | |
1188 | * @wm: watermark calculation data | |
1189 | * | |
1190 | * Check if the display average bandwidth fits in the display | |
1191 | * available bandwidth (CIK). | |
1192 | * Used for display watermark bandwidth calculations | |
1193 | * Returns true if the display fits, false if not. | |
1194 | */ | |
1195 | static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) | |
1196 | { | |
1197 | if (dce_v10_0_average_bandwidth(wm) <= | |
1198 | (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) | |
1199 | return true; | |
1200 | else | |
1201 | return false; | |
1202 | } | |
1203 | ||
1204 | /** | |
1205 | * dce_v10_0_check_latency_hiding - check latency hiding | |
1206 | * | |
1207 | * @wm: watermark calculation data | |
1208 | * | |
1209 | * Check latency hiding (CIK). | |
1210 | * Used for display watermark bandwidth calculations | |
1211 | * Returns true if the display fits, false if not. | |
1212 | */ | |
1213 | static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) | |
1214 | { | |
1215 | u32 lb_partitions = wm->lb_size / wm->src_width; | |
1216 | u32 line_time = wm->active_time + wm->blank_time; | |
1217 | u32 latency_tolerant_lines; | |
1218 | u32 latency_hiding; | |
1219 | fixed20_12 a; | |
1220 | ||
1221 | a.full = dfixed_const(1); | |
1222 | if (wm->vsc.full > a.full) | |
1223 | latency_tolerant_lines = 1; | |
1224 | else { | |
1225 | if (lb_partitions <= (wm->vtaps + 1)) | |
1226 | latency_tolerant_lines = 1; | |
1227 | else | |
1228 | latency_tolerant_lines = 2; | |
1229 | } | |
1230 | ||
1231 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); | |
1232 | ||
1233 | if (dce_v10_0_latency_watermark(wm) <= latency_hiding) | |
1234 | return true; | |
1235 | else | |
1236 | return false; | |
1237 | } | |
1238 | ||
1239 | /** | |
1240 | * dce_v10_0_program_watermarks - program display watermarks | |
1241 | * | |
1242 | * @adev: amdgpu_device pointer | |
1243 | * @amdgpu_crtc: the selected display controller | |
1244 | * @lb_size: line buffer size | |
1245 | * @num_heads: number of display controllers in use | |
1246 | * | |
1247 | * Calculate and program the display watermarks for the | |
1248 | * selected display controller (CIK). | |
1249 | */ | |
1250 | static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, | |
1251 | struct amdgpu_crtc *amdgpu_crtc, | |
1252 | u32 lb_size, u32 num_heads) | |
1253 | { | |
1254 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; | |
1255 | struct dce10_wm_params wm_low, wm_high; | |
1256 | u32 pixel_period; | |
1257 | u32 line_time = 0; | |
1258 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | |
1259 | u32 tmp, wm_mask; | |
1260 | ||
1261 | if (amdgpu_crtc->base.enabled && num_heads && mode) { | |
1262 | pixel_period = 1000000 / (u32)mode->clock; | |
1263 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | |
1264 | ||
1265 | /* watermark for high clocks */ | |
1266 | if (adev->pm.dpm_enabled) { | |
1267 | wm_high.yclk = | |
1268 | amdgpu_dpm_get_mclk(adev, false) * 10; | |
1269 | wm_high.sclk = | |
1270 | amdgpu_dpm_get_sclk(adev, false) * 10; | |
1271 | } else { | |
1272 | wm_high.yclk = adev->pm.current_mclk * 10; | |
1273 | wm_high.sclk = adev->pm.current_sclk * 10; | |
1274 | } | |
1275 | ||
1276 | wm_high.disp_clk = mode->clock; | |
1277 | wm_high.src_width = mode->crtc_hdisplay; | |
1278 | wm_high.active_time = mode->crtc_hdisplay * pixel_period; | |
1279 | wm_high.blank_time = line_time - wm_high.active_time; | |
1280 | wm_high.interlaced = false; | |
1281 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1282 | wm_high.interlaced = true; | |
1283 | wm_high.vsc = amdgpu_crtc->vsc; | |
1284 | wm_high.vtaps = 1; | |
1285 | if (amdgpu_crtc->rmx_type != RMX_OFF) | |
1286 | wm_high.vtaps = 2; | |
1287 | wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
1288 | wm_high.lb_size = lb_size; | |
1289 | wm_high.dram_channels = cik_get_number_of_dram_channels(adev); | |
1290 | wm_high.num_heads = num_heads; | |
1291 | ||
1292 | /* set for high clocks */ | |
1293 | latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); | |
1294 | ||
1295 | /* possibly force display priority to high */ | |
1296 | /* should really do this at mode validation time... */ | |
1297 | if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || | |
1298 | !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || | |
1299 | !dce_v10_0_check_latency_hiding(&wm_high) || | |
1300 | (adev->mode_info.disp_priority == 2)) { | |
1301 | DRM_DEBUG_KMS("force priority to high\n"); | |
1302 | } | |
1303 | ||
1304 | /* watermark for low clocks */ | |
1305 | if (adev->pm.dpm_enabled) { | |
1306 | wm_low.yclk = | |
1307 | amdgpu_dpm_get_mclk(adev, true) * 10; | |
1308 | wm_low.sclk = | |
1309 | amdgpu_dpm_get_sclk(adev, true) * 10; | |
1310 | } else { | |
1311 | wm_low.yclk = adev->pm.current_mclk * 10; | |
1312 | wm_low.sclk = adev->pm.current_sclk * 10; | |
1313 | } | |
1314 | ||
1315 | wm_low.disp_clk = mode->clock; | |
1316 | wm_low.src_width = mode->crtc_hdisplay; | |
1317 | wm_low.active_time = mode->crtc_hdisplay * pixel_period; | |
1318 | wm_low.blank_time = line_time - wm_low.active_time; | |
1319 | wm_low.interlaced = false; | |
1320 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1321 | wm_low.interlaced = true; | |
1322 | wm_low.vsc = amdgpu_crtc->vsc; | |
1323 | wm_low.vtaps = 1; | |
1324 | if (amdgpu_crtc->rmx_type != RMX_OFF) | |
1325 | wm_low.vtaps = 2; | |
1326 | wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
1327 | wm_low.lb_size = lb_size; | |
1328 | wm_low.dram_channels = cik_get_number_of_dram_channels(adev); | |
1329 | wm_low.num_heads = num_heads; | |
1330 | ||
1331 | /* set for low clocks */ | |
1332 | latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); | |
1333 | ||
1334 | /* possibly force display priority to high */ | |
1335 | /* should really do this at mode validation time... */ | |
1336 | if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || | |
1337 | !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || | |
1338 | !dce_v10_0_check_latency_hiding(&wm_low) || | |
1339 | (adev->mode_info.disp_priority == 2)) { | |
1340 | DRM_DEBUG_KMS("force priority to high\n"); | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | /* select wm A */ | |
1345 | wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); | |
1346 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); | |
1347 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1348 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); | |
1349 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); | |
1350 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); | |
1351 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1352 | /* select wm B */ | |
1353 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); | |
1354 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1355 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); | |
be9fd2e9 | 1356 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); |
aaa36a97 AD |
1357 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); |
1358 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
1359 | /* restore original selection */ | |
1360 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); | |
1361 | ||
1362 | /* save values for DPM */ | |
1363 | amdgpu_crtc->line_time = line_time; | |
1364 | amdgpu_crtc->wm_high = latency_watermark_a; | |
1365 | amdgpu_crtc->wm_low = latency_watermark_b; | |
1366 | } | |
1367 | ||
1368 | /** | |
1369 | * dce_v10_0_bandwidth_update - program display watermarks | |
1370 | * | |
1371 | * @adev: amdgpu_device pointer | |
1372 | * | |
1373 | * Calculate and program the display watermarks and line | |
1374 | * buffer allocation (CIK). | |
1375 | */ | |
1376 | static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) | |
1377 | { | |
1378 | struct drm_display_mode *mode = NULL; | |
1379 | u32 num_heads = 0, lb_size; | |
1380 | int i; | |
1381 | ||
1382 | amdgpu_update_display_priority(adev); | |
1383 | ||
1384 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
1385 | if (adev->mode_info.crtcs[i]->base.enabled) | |
1386 | num_heads++; | |
1387 | } | |
1388 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
1389 | mode = &adev->mode_info.crtcs[i]->base.mode; | |
1390 | lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); | |
1391 | dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], | |
1392 | lb_size, num_heads); | |
1393 | } | |
1394 | } | |
1395 | ||
1396 | static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) | |
1397 | { | |
1398 | int i; | |
1399 | u32 offset, tmp; | |
1400 | ||
1401 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1402 | offset = adev->mode_info.audio.pin[i].offset; | |
1403 | tmp = RREG32_AUDIO_ENDPT(offset, | |
1404 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); | |
1405 | if (((tmp & | |
1406 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> | |
1407 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) | |
1408 | adev->mode_info.audio.pin[i].connected = false; | |
1409 | else | |
1410 | adev->mode_info.audio.pin[i].connected = true; | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) | |
1415 | { | |
1416 | int i; | |
1417 | ||
1418 | dce_v10_0_audio_get_connected_pins(adev); | |
1419 | ||
1420 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1421 | if (adev->mode_info.audio.pin[i].connected) | |
1422 | return &adev->mode_info.audio.pin[i]; | |
1423 | } | |
1424 | DRM_ERROR("No connected audio pins found!\n"); | |
1425 | return NULL; | |
1426 | } | |
1427 | ||
1428 | static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) | |
1429 | { | |
1430 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1431 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1432 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1433 | u32 tmp; | |
1434 | ||
1435 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1436 | return; | |
1437 | ||
1438 | tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); | |
1439 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); | |
1440 | WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); | |
1441 | } | |
1442 | ||
1443 | static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, | |
1444 | struct drm_display_mode *mode) | |
1445 | { | |
1446 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1447 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1448 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1449 | struct drm_connector *connector; | |
1450 | struct amdgpu_connector *amdgpu_connector = NULL; | |
1451 | u32 tmp; | |
1452 | int interlace = 0; | |
1453 | ||
1454 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1455 | return; | |
1456 | ||
1457 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
1458 | if (connector->encoder == encoder) { | |
1459 | amdgpu_connector = to_amdgpu_connector(connector); | |
1460 | break; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | if (!amdgpu_connector) { | |
1465 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
1466 | return; | |
1467 | } | |
1468 | ||
1469 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1470 | interlace = 1; | |
1471 | if (connector->latency_present[interlace]) { | |
1472 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1473 | VIDEO_LIPSYNC, connector->video_latency[interlace]); | |
1474 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1475 | AUDIO_LIPSYNC, connector->audio_latency[interlace]); | |
1476 | } else { | |
1477 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1478 | VIDEO_LIPSYNC, 0); | |
1479 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, | |
1480 | AUDIO_LIPSYNC, 0); | |
1481 | } | |
1482 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, | |
1483 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); | |
1484 | } | |
1485 | ||
1486 | static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) | |
1487 | { | |
1488 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1489 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1490 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1491 | struct drm_connector *connector; | |
1492 | struct amdgpu_connector *amdgpu_connector = NULL; | |
1493 | u32 tmp; | |
1494 | u8 *sadb = NULL; | |
1495 | int sad_count; | |
1496 | ||
1497 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1498 | return; | |
1499 | ||
1500 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
1501 | if (connector->encoder == encoder) { | |
1502 | amdgpu_connector = to_amdgpu_connector(connector); | |
1503 | break; | |
1504 | } | |
1505 | } | |
1506 | ||
1507 | if (!amdgpu_connector) { | |
1508 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
1509 | return; | |
1510 | } | |
1511 | ||
1512 | sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); | |
1513 | if (sad_count < 0) { | |
1514 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); | |
1515 | sad_count = 0; | |
1516 | } | |
1517 | ||
1518 | /* program the speaker allocation */ | |
1519 | tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, | |
1520 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); | |
1521 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1522 | DP_CONNECTION, 0); | |
1523 | /* set HDMI mode */ | |
1524 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1525 | HDMI_CONNECTION, 1); | |
1526 | if (sad_count) | |
1527 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1528 | SPEAKER_ALLOCATION, sadb[0]); | |
1529 | else | |
1530 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, | |
1531 | SPEAKER_ALLOCATION, 5); /* stereo */ | |
1532 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, | |
1533 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); | |
1534 | ||
1535 | kfree(sadb); | |
1536 | } | |
1537 | ||
1538 | static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) | |
1539 | { | |
1540 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
1541 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1542 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1543 | struct drm_connector *connector; | |
1544 | struct amdgpu_connector *amdgpu_connector = NULL; | |
1545 | struct cea_sad *sads; | |
1546 | int i, sad_count; | |
1547 | ||
1548 | static const u16 eld_reg_to_type[][2] = { | |
1549 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
1550 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
1551 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
1552 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
1553 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
1554 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
1555 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
1556 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
1557 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
1558 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
1559 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
1560 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
1561 | }; | |
1562 | ||
1563 | if (!dig || !dig->afmt || !dig->afmt->pin) | |
1564 | return; | |
1565 | ||
1566 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
1567 | if (connector->encoder == encoder) { | |
1568 | amdgpu_connector = to_amdgpu_connector(connector); | |
1569 | break; | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | if (!amdgpu_connector) { | |
1574 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
1575 | return; | |
1576 | } | |
1577 | ||
1578 | sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); | |
1579 | if (sad_count <= 0) { | |
1580 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); | |
1581 | return; | |
1582 | } | |
1583 | BUG_ON(!sads); | |
1584 | ||
1585 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { | |
1586 | u32 tmp = 0; | |
1587 | u8 stereo_freqs = 0; | |
1588 | int max_channels = -1; | |
1589 | int j; | |
1590 | ||
1591 | for (j = 0; j < sad_count; j++) { | |
1592 | struct cea_sad *sad = &sads[j]; | |
1593 | ||
1594 | if (sad->format == eld_reg_to_type[i][1]) { | |
1595 | if (sad->channels > max_channels) { | |
1596 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1597 | MAX_CHANNELS, sad->channels); | |
1598 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1599 | DESCRIPTOR_BYTE_2, sad->byte2); | |
1600 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1601 | SUPPORTED_FREQUENCIES, sad->freq); | |
1602 | max_channels = sad->channels; | |
1603 | } | |
1604 | ||
1605 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) | |
1606 | stereo_freqs |= sad->freq; | |
1607 | else | |
1608 | break; | |
1609 | } | |
1610 | } | |
1611 | ||
1612 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, | |
1613 | SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); | |
1614 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); | |
1615 | } | |
1616 | ||
1617 | kfree(sads); | |
1618 | } | |
1619 | ||
1620 | static void dce_v10_0_audio_enable(struct amdgpu_device *adev, | |
1621 | struct amdgpu_audio_pin *pin, | |
1622 | bool enable) | |
1623 | { | |
1624 | if (!pin) | |
1625 | return; | |
1626 | ||
1627 | WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | |
1628 | enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); | |
1629 | } | |
1630 | ||
1631 | static const u32 pin_offsets[] = | |
1632 | { | |
1633 | AUD0_REGISTER_OFFSET, | |
1634 | AUD1_REGISTER_OFFSET, | |
1635 | AUD2_REGISTER_OFFSET, | |
1636 | AUD3_REGISTER_OFFSET, | |
1637 | AUD4_REGISTER_OFFSET, | |
1638 | AUD5_REGISTER_OFFSET, | |
1639 | AUD6_REGISTER_OFFSET, | |
1640 | }; | |
1641 | ||
1642 | static int dce_v10_0_audio_init(struct amdgpu_device *adev) | |
1643 | { | |
1644 | int i; | |
1645 | ||
1646 | if (!amdgpu_audio) | |
1647 | return 0; | |
1648 | ||
1649 | adev->mode_info.audio.enabled = true; | |
1650 | ||
1651 | adev->mode_info.audio.num_pins = 7; | |
1652 | ||
1653 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
1654 | adev->mode_info.audio.pin[i].channels = -1; | |
1655 | adev->mode_info.audio.pin[i].rate = -1; | |
1656 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
1657 | adev->mode_info.audio.pin[i].status_bits = 0; | |
1658 | adev->mode_info.audio.pin[i].category_code = 0; | |
1659 | adev->mode_info.audio.pin[i].connected = false; | |
1660 | adev->mode_info.audio.pin[i].offset = pin_offsets[i]; | |
1661 | adev->mode_info.audio.pin[i].id = i; | |
1662 | /* disable audio. it will be set up later */ | |
1663 | /* XXX remove once we switch to ip funcs */ | |
1664 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
1665 | } | |
1666 | ||
1667 | return 0; | |
1668 | } | |
1669 | ||
1670 | static void dce_v10_0_audio_fini(struct amdgpu_device *adev) | |
1671 | { | |
1672 | int i; | |
1673 | ||
1674 | if (!adev->mode_info.audio.enabled) | |
1675 | return; | |
1676 | ||
1677 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) | |
1678 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
1679 | ||
1680 | adev->mode_info.audio.enabled = false; | |
1681 | } | |
1682 | ||
1683 | /* | |
1684 | * update the N and CTS parameters for a given pixel clock rate | |
1685 | */ | |
1686 | static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
1687 | { | |
1688 | struct drm_device *dev = encoder->dev; | |
1689 | struct amdgpu_device *adev = dev->dev_private; | |
1690 | struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); | |
1691 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1692 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1693 | u32 tmp; | |
1694 | ||
1695 | tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); | |
1696 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); | |
1697 | WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); | |
1698 | tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); | |
1699 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); | |
1700 | WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); | |
1701 | ||
1702 | tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); | |
1703 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); | |
1704 | WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); | |
1705 | tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); | |
1706 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); | |
1707 | WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); | |
1708 | ||
1709 | tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); | |
1710 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); | |
1711 | WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); | |
1712 | tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); | |
1713 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); | |
1714 | WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); | |
1715 | ||
1716 | } | |
1717 | ||
1718 | /* | |
1719 | * build a HDMI Video Info Frame | |
1720 | */ | |
1721 | static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, | |
1722 | void *buffer, size_t size) | |
1723 | { | |
1724 | struct drm_device *dev = encoder->dev; | |
1725 | struct amdgpu_device *adev = dev->dev_private; | |
1726 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1727 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1728 | uint8_t *frame = buffer + 3; | |
1729 | uint8_t *header = buffer; | |
1730 | ||
1731 | WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, | |
1732 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); | |
1733 | WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, | |
1734 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); | |
1735 | WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, | |
1736 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); | |
1737 | WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, | |
1738 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); | |
1739 | } | |
1740 | ||
1741 | static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |
1742 | { | |
1743 | struct drm_device *dev = encoder->dev; | |
1744 | struct amdgpu_device *adev = dev->dev_private; | |
1745 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1746 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1747 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); | |
1748 | u32 dto_phase = 24 * 1000; | |
1749 | u32 dto_modulo = clock; | |
1750 | u32 tmp; | |
1751 | ||
1752 | if (!dig || !dig->afmt) | |
1753 | return; | |
1754 | ||
1755 | /* XXX two dtos; generally use dto0 for hdmi */ | |
1756 | /* Express [24MHz / target pixel clock] as an exact rational | |
1757 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
1758 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
1759 | */ | |
1760 | tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); | |
1761 | tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, | |
1762 | amdgpu_crtc->crtc_id); | |
1763 | WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); | |
1764 | WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); | |
1765 | WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); | |
1766 | } | |
1767 | ||
1768 | /* | |
1769 | * update the info frames with the data from the current display mode | |
1770 | */ | |
1771 | static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, | |
1772 | struct drm_display_mode *mode) | |
1773 | { | |
1774 | struct drm_device *dev = encoder->dev; | |
1775 | struct amdgpu_device *adev = dev->dev_private; | |
1776 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1777 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1778 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); | |
1779 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; | |
1780 | struct hdmi_avi_infoframe frame; | |
1781 | ssize_t err; | |
1782 | u32 tmp; | |
1783 | int bpc = 8; | |
1784 | ||
1785 | if (!dig || !dig->afmt) | |
1786 | return; | |
1787 | ||
1788 | /* Silent, r600_hdmi_enable will raise WARN for us */ | |
1789 | if (!dig->afmt->enabled) | |
1790 | return; | |
1791 | ||
1792 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ | |
1793 | if (encoder->crtc) { | |
1794 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); | |
1795 | bpc = amdgpu_crtc->bpc; | |
1796 | } | |
1797 | ||
1798 | /* disable audio prior to setting up hw */ | |
1799 | dig->afmt->pin = dce_v10_0_audio_get_pin(adev); | |
1800 | dce_v10_0_audio_enable(adev, dig->afmt->pin, false); | |
1801 | ||
1802 | dce_v10_0_audio_set_dto(encoder, mode->clock); | |
1803 | ||
1804 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); | |
1805 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); | |
1806 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ | |
1807 | ||
1808 | WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); | |
1809 | ||
1810 | tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); | |
1811 | switch (bpc) { | |
1812 | case 0: | |
1813 | case 6: | |
1814 | case 8: | |
1815 | case 16: | |
1816 | default: | |
1817 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); | |
1818 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); | |
1819 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", | |
1820 | connector->name, bpc); | |
1821 | break; | |
1822 | case 10: | |
1823 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); | |
1824 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); | |
1825 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", | |
1826 | connector->name); | |
1827 | break; | |
1828 | case 12: | |
1829 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); | |
1830 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); | |
1831 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", | |
1832 | connector->name); | |
1833 | break; | |
1834 | } | |
1835 | WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); | |
1836 | ||
1837 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); | |
1838 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ | |
1839 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ | |
1840 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ | |
1841 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1842 | ||
1843 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); | |
1844 | /* enable audio info frames (frames won't be set until audio is enabled) */ | |
1845 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); | |
1846 | /* required for audio info values to be updated */ | |
1847 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); | |
1848 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); | |
1849 | ||
1850 | tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); | |
1851 | /* required for audio info values to be updated */ | |
1852 | tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); | |
1853 | WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); | |
1854 | ||
1855 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); | |
1856 | /* anything other than 0 */ | |
1857 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); | |
1858 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); | |
1859 | ||
1860 | WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ | |
1861 | ||
1862 | tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); | |
1863 | /* set the default audio delay */ | |
1864 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); | |
1865 | /* should be suffient for all audio modes and small enough for all hblanks */ | |
1866 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); | |
1867 | WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1868 | ||
1869 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); | |
1870 | /* allow 60958 channel status fields to be updated */ | |
1871 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); | |
1872 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1873 | ||
1874 | tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); | |
1875 | if (bpc > 8) | |
1876 | /* clear SW CTS value */ | |
1877 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); | |
1878 | else | |
1879 | /* select SW CTS value */ | |
1880 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); | |
1881 | /* allow hw to sent ACR packets when required */ | |
1882 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); | |
1883 | WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1884 | ||
1885 | dce_v10_0_afmt_update_ACR(encoder, mode->clock); | |
1886 | ||
1887 | tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); | |
1888 | tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); | |
1889 | WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); | |
1890 | ||
1891 | tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); | |
1892 | tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); | |
1893 | WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); | |
1894 | ||
1895 | tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); | |
1896 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); | |
1897 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); | |
1898 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); | |
1899 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); | |
1900 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); | |
1901 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); | |
1902 | WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); | |
1903 | ||
1904 | dce_v10_0_audio_write_speaker_allocation(encoder); | |
1905 | ||
1906 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, | |
1907 | (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); | |
1908 | ||
1909 | dce_v10_0_afmt_audio_select_pin(encoder); | |
1910 | dce_v10_0_audio_write_sad_regs(encoder); | |
1911 | dce_v10_0_audio_write_latency_fields(encoder, mode); | |
1912 | ||
1913 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); | |
1914 | if (err < 0) { | |
1915 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
1916 | return; | |
1917 | } | |
1918 | ||
1919 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
1920 | if (err < 0) { | |
1921 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
1922 | return; | |
1923 | } | |
1924 | ||
1925 | dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); | |
1926 | ||
1927 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); | |
1928 | /* enable AVI info frames */ | |
1929 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); | |
1930 | /* required for audio info values to be updated */ | |
1931 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); | |
1932 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); | |
1933 | ||
1934 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); | |
1935 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); | |
1936 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); | |
1937 | ||
1938 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); | |
1939 | /* send audio packets */ | |
1940 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); | |
1941 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); | |
1942 | ||
1943 | WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); | |
1944 | WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); | |
1945 | WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); | |
1946 | WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); | |
1947 | ||
1948 | /* enable audio after to setting up hw */ | |
1949 | dce_v10_0_audio_enable(adev, dig->afmt->pin, true); | |
1950 | } | |
1951 | ||
1952 | static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) | |
1953 | { | |
1954 | struct drm_device *dev = encoder->dev; | |
1955 | struct amdgpu_device *adev = dev->dev_private; | |
1956 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
1957 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
1958 | ||
1959 | if (!dig || !dig->afmt) | |
1960 | return; | |
1961 | ||
1962 | /* Silent, r600_hdmi_enable will raise WARN for us */ | |
1963 | if (enable && dig->afmt->enabled) | |
1964 | return; | |
1965 | if (!enable && !dig->afmt->enabled) | |
1966 | return; | |
1967 | ||
1968 | if (!enable && dig->afmt->pin) { | |
1969 | dce_v10_0_audio_enable(adev, dig->afmt->pin, false); | |
1970 | dig->afmt->pin = NULL; | |
1971 | } | |
1972 | ||
1973 | dig->afmt->enabled = enable; | |
1974 | ||
1975 | DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", | |
1976 | enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); | |
1977 | } | |
1978 | ||
1979 | static void dce_v10_0_afmt_init(struct amdgpu_device *adev) | |
1980 | { | |
1981 | int i; | |
1982 | ||
1983 | for (i = 0; i < adev->mode_info.num_dig; i++) | |
1984 | adev->mode_info.afmt[i] = NULL; | |
1985 | ||
1986 | /* DCE10 has audio blocks tied to DIG encoders */ | |
1987 | for (i = 0; i < adev->mode_info.num_dig; i++) { | |
1988 | adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); | |
1989 | if (adev->mode_info.afmt[i]) { | |
1990 | adev->mode_info.afmt[i]->offset = dig_offsets[i]; | |
1991 | adev->mode_info.afmt[i]->id = i; | |
1992 | } | |
1993 | } | |
1994 | } | |
1995 | ||
1996 | static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) | |
1997 | { | |
1998 | int i; | |
1999 | ||
2000 | for (i = 0; i < adev->mode_info.num_dig; i++) { | |
2001 | kfree(adev->mode_info.afmt[i]); | |
2002 | adev->mode_info.afmt[i] = NULL; | |
2003 | } | |
2004 | } | |
2005 | ||
2006 | static const u32 vga_control_regs[6] = | |
2007 | { | |
2008 | mmD1VGA_CONTROL, | |
2009 | mmD2VGA_CONTROL, | |
2010 | mmD3VGA_CONTROL, | |
2011 | mmD4VGA_CONTROL, | |
2012 | mmD5VGA_CONTROL, | |
2013 | mmD6VGA_CONTROL, | |
2014 | }; | |
2015 | ||
2016 | static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) | |
2017 | { | |
2018 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2019 | struct drm_device *dev = crtc->dev; | |
2020 | struct amdgpu_device *adev = dev->dev_private; | |
2021 | u32 vga_control; | |
2022 | ||
2023 | vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; | |
2024 | if (enable) | |
2025 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); | |
2026 | else | |
2027 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); | |
2028 | } | |
2029 | ||
2030 | static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) | |
2031 | { | |
2032 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2033 | struct drm_device *dev = crtc->dev; | |
2034 | struct amdgpu_device *adev = dev->dev_private; | |
2035 | ||
2036 | if (enable) | |
2037 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); | |
2038 | else | |
2039 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); | |
2040 | } | |
2041 | ||
aaa36a97 AD |
2042 | static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, |
2043 | struct drm_framebuffer *fb, | |
2044 | int x, int y, int atomic) | |
2045 | { | |
2046 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2047 | struct drm_device *dev = crtc->dev; | |
2048 | struct amdgpu_device *adev = dev->dev_private; | |
2049 | struct amdgpu_framebuffer *amdgpu_fb; | |
2050 | struct drm_framebuffer *target_fb; | |
2051 | struct drm_gem_object *obj; | |
2052 | struct amdgpu_bo *rbo; | |
2053 | uint64_t fb_location, tiling_flags; | |
2054 | uint32_t fb_format, fb_pitch_pixels; | |
aaa36a97 | 2055 | u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); |
fbd76d59 | 2056 | u32 pipe_config; |
aaa36a97 AD |
2057 | u32 tmp, viewport_w, viewport_h; |
2058 | int r; | |
2059 | bool bypass_lut = false; | |
2060 | ||
2061 | /* no fb bound */ | |
2062 | if (!atomic && !crtc->primary->fb) { | |
2063 | DRM_DEBUG_KMS("No FB bound\n"); | |
2064 | return 0; | |
2065 | } | |
2066 | ||
2067 | if (atomic) { | |
2068 | amdgpu_fb = to_amdgpu_framebuffer(fb); | |
2069 | target_fb = fb; | |
2070 | } | |
2071 | else { | |
2072 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
2073 | target_fb = crtc->primary->fb; | |
2074 | } | |
2075 | ||
2076 | /* If atomic, assume fb object is pinned & idle & fenced and | |
2077 | * just update base pointers | |
2078 | */ | |
2079 | obj = amdgpu_fb->obj; | |
2080 | rbo = gem_to_amdgpu_bo(obj); | |
2081 | r = amdgpu_bo_reserve(rbo, false); | |
2082 | if (unlikely(r != 0)) | |
2083 | return r; | |
2084 | ||
2085 | if (atomic) | |
2086 | fb_location = amdgpu_bo_gpu_offset(rbo); | |
2087 | else { | |
2088 | r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); | |
2089 | if (unlikely(r != 0)) { | |
2090 | amdgpu_bo_unreserve(rbo); | |
2091 | return -EINVAL; | |
2092 | } | |
2093 | } | |
2094 | ||
2095 | amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); | |
2096 | amdgpu_bo_unreserve(rbo); | |
2097 | ||
fbd76d59 MO |
2098 | pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); |
2099 | ||
aaa36a97 AD |
2100 | switch (target_fb->pixel_format) { |
2101 | case DRM_FORMAT_C8: | |
2102 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); | |
2103 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); | |
2104 | break; | |
2105 | case DRM_FORMAT_XRGB4444: | |
2106 | case DRM_FORMAT_ARGB4444: | |
2107 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2108 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); | |
2109 | #ifdef __BIG_ENDIAN | |
2110 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2111 | ENDIAN_8IN16); | |
2112 | #endif | |
2113 | break; | |
2114 | case DRM_FORMAT_XRGB1555: | |
2115 | case DRM_FORMAT_ARGB1555: | |
2116 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2117 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); | |
2118 | #ifdef __BIG_ENDIAN | |
2119 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2120 | ENDIAN_8IN16); | |
2121 | #endif | |
2122 | break; | |
2123 | case DRM_FORMAT_BGRX5551: | |
2124 | case DRM_FORMAT_BGRA5551: | |
2125 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2126 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); | |
2127 | #ifdef __BIG_ENDIAN | |
2128 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2129 | ENDIAN_8IN16); | |
2130 | #endif | |
2131 | break; | |
2132 | case DRM_FORMAT_RGB565: | |
2133 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); | |
2134 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); | |
2135 | #ifdef __BIG_ENDIAN | |
2136 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2137 | ENDIAN_8IN16); | |
2138 | #endif | |
2139 | break; | |
2140 | case DRM_FORMAT_XRGB8888: | |
2141 | case DRM_FORMAT_ARGB8888: | |
2142 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); | |
2143 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); | |
2144 | #ifdef __BIG_ENDIAN | |
2145 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2146 | ENDIAN_8IN32); | |
2147 | #endif | |
2148 | break; | |
2149 | case DRM_FORMAT_XRGB2101010: | |
2150 | case DRM_FORMAT_ARGB2101010: | |
2151 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); | |
2152 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); | |
2153 | #ifdef __BIG_ENDIAN | |
2154 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2155 | ENDIAN_8IN32); | |
2156 | #endif | |
2157 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | |
2158 | bypass_lut = true; | |
2159 | break; | |
2160 | case DRM_FORMAT_BGRX1010102: | |
2161 | case DRM_FORMAT_BGRA1010102: | |
2162 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); | |
2163 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); | |
2164 | #ifdef __BIG_ENDIAN | |
2165 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, | |
2166 | ENDIAN_8IN32); | |
2167 | #endif | |
2168 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ | |
2169 | bypass_lut = true; | |
2170 | break; | |
2171 | default: | |
2172 | DRM_ERROR("Unsupported screen format %s\n", | |
2173 | drm_get_format_name(target_fb->pixel_format)); | |
2174 | return -EINVAL; | |
2175 | } | |
2176 | ||
fbd76d59 MO |
2177 | if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { |
2178 | unsigned bankw, bankh, mtaspect, tile_split, num_banks; | |
aaa36a97 | 2179 | |
fbd76d59 MO |
2180 | bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); |
2181 | bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); | |
2182 | mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); | |
2183 | tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); | |
2184 | num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); | |
aaa36a97 | 2185 | |
aaa36a97 AD |
2186 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); |
2187 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, | |
2188 | ARRAY_2D_TILED_THIN1); | |
2189 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, | |
2190 | tile_split); | |
2191 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); | |
2192 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); | |
2193 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, | |
2194 | mtaspect); | |
2195 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, | |
2196 | ADDR_SURF_MICRO_TILING_DISPLAY); | |
fbd76d59 | 2197 | } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { |
aaa36a97 AD |
2198 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, |
2199 | ARRAY_1D_TILED_THIN1); | |
2200 | } | |
2201 | ||
aaa36a97 AD |
2202 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, |
2203 | pipe_config); | |
2204 | ||
2205 | dce_v10_0_vga_enable(crtc, false); | |
2206 | ||
2207 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
2208 | upper_32_bits(fb_location)); | |
2209 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
2210 | upper_32_bits(fb_location)); | |
2211 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
2212 | (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); | |
2213 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
2214 | (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); | |
2215 | WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); | |
2216 | WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); | |
2217 | ||
2218 | /* | |
2219 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT | |
2220 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to | |
2221 | * retain the full precision throughout the pipeline. | |
2222 | */ | |
2223 | tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); | |
2224 | if (bypass_lut) | |
2225 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); | |
2226 | else | |
2227 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); | |
2228 | WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); | |
2229 | ||
2230 | if (bypass_lut) | |
2231 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); | |
2232 | ||
2233 | WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); | |
2234 | WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); | |
2235 | WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); | |
2236 | WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); | |
2237 | WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); | |
2238 | WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); | |
2239 | ||
2240 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); | |
2241 | WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); | |
2242 | ||
2243 | dce_v10_0_grph_enable(crtc, true); | |
2244 | ||
2245 | WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, | |
2246 | target_fb->height); | |
2247 | ||
2248 | x &= ~3; | |
2249 | y &= ~1; | |
2250 | WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, | |
2251 | (x << 16) | y); | |
2252 | viewport_w = crtc->mode.hdisplay; | |
2253 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | |
2254 | WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, | |
2255 | (viewport_w << 16) | viewport_h); | |
2256 | ||
2257 | /* pageflip setup */ | |
2258 | /* make sure flip is at vb rather than hb */ | |
2259 | tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); | |
2260 | tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, | |
2261 | GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); | |
2262 | WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2263 | ||
2264 | /* set pageflip to happen only at start of vblank interval (front porch) */ | |
2265 | WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); | |
2266 | ||
2267 | if (!atomic && fb && fb != crtc->primary->fb) { | |
2268 | amdgpu_fb = to_amdgpu_framebuffer(fb); | |
2269 | rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); | |
2270 | r = amdgpu_bo_reserve(rbo, false); | |
2271 | if (unlikely(r != 0)) | |
2272 | return r; | |
2273 | amdgpu_bo_unpin(rbo); | |
2274 | amdgpu_bo_unreserve(rbo); | |
2275 | } | |
2276 | ||
2277 | /* Bytes per pixel may have changed */ | |
2278 | dce_v10_0_bandwidth_update(adev); | |
2279 | ||
2280 | return 0; | |
2281 | } | |
2282 | ||
2283 | static void dce_v10_0_set_interleave(struct drm_crtc *crtc, | |
2284 | struct drm_display_mode *mode) | |
2285 | { | |
2286 | struct drm_device *dev = crtc->dev; | |
2287 | struct amdgpu_device *adev = dev->dev_private; | |
2288 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2289 | u32 tmp; | |
2290 | ||
2291 | tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); | |
2292 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2293 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); | |
2294 | else | |
2295 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); | |
2296 | WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); | |
2297 | } | |
2298 | ||
2299 | static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) | |
2300 | { | |
2301 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2302 | struct drm_device *dev = crtc->dev; | |
2303 | struct amdgpu_device *adev = dev->dev_private; | |
2304 | int i; | |
2305 | u32 tmp; | |
2306 | ||
2307 | DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); | |
2308 | ||
2309 | tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); | |
2310 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); | |
2311 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); | |
2312 | WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2313 | ||
2314 | tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); | |
2315 | tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); | |
2316 | WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2317 | ||
2318 | tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); | |
2319 | tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); | |
2320 | WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2321 | ||
2322 | tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); | |
2323 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); | |
2324 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); | |
2325 | WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2326 | ||
2327 | WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); | |
2328 | ||
2329 | WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); | |
2330 | WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); | |
2331 | WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); | |
2332 | ||
2333 | WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); | |
2334 | WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); | |
2335 | WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); | |
2336 | ||
2337 | WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); | |
2338 | WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); | |
2339 | ||
2340 | WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); | |
2341 | for (i = 0; i < 256; i++) { | |
2342 | WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, | |
2343 | (amdgpu_crtc->lut_r[i] << 20) | | |
2344 | (amdgpu_crtc->lut_g[i] << 10) | | |
2345 | (amdgpu_crtc->lut_b[i] << 0)); | |
2346 | } | |
2347 | ||
2348 | tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); | |
2349 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); | |
2350 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); | |
2351 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); | |
2352 | WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2353 | ||
2354 | tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); | |
2355 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); | |
2356 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); | |
2357 | WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2358 | ||
2359 | tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); | |
2360 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); | |
2361 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); | |
2362 | WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2363 | ||
2364 | tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); | |
2365 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); | |
2366 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); | |
2367 | WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2368 | ||
2369 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ | |
2370 | WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); | |
2371 | /* XXX this only needs to be programmed once per crtc at startup, | |
2372 | * not sure where the best place for it is | |
2373 | */ | |
2374 | tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); | |
2375 | tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); | |
2376 | WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2377 | } | |
2378 | ||
2379 | static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) | |
2380 | { | |
2381 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
2382 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
2383 | ||
2384 | switch (amdgpu_encoder->encoder_id) { | |
2385 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2386 | if (dig->linkb) | |
2387 | return 1; | |
2388 | else | |
2389 | return 0; | |
2390 | break; | |
2391 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2392 | if (dig->linkb) | |
2393 | return 3; | |
2394 | else | |
2395 | return 2; | |
2396 | break; | |
2397 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
2398 | if (dig->linkb) | |
2399 | return 5; | |
2400 | else | |
2401 | return 4; | |
2402 | break; | |
2403 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: | |
2404 | return 6; | |
2405 | break; | |
2406 | default: | |
2407 | DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); | |
2408 | return 0; | |
2409 | } | |
2410 | } | |
2411 | ||
2412 | /** | |
2413 | * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. | |
2414 | * | |
2415 | * @crtc: drm crtc | |
2416 | * | |
2417 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors | |
2418 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP | |
2419 | * monitors a dedicated PPLL must be used. If a particular board has | |
2420 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming | |
2421 | * as there is no need to program the PLL itself. If we are not able to | |
2422 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to | |
2423 | * avoid messing up an existing monitor. | |
2424 | * | |
2425 | * Asic specific PLL information | |
2426 | * | |
2427 | * DCE 10.x | |
2428 | * Tonga | |
2429 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) | |
2430 | * CI | |
2431 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
2432 | * | |
2433 | */ | |
2434 | static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) | |
2435 | { | |
2436 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2437 | struct drm_device *dev = crtc->dev; | |
2438 | struct amdgpu_device *adev = dev->dev_private; | |
2439 | u32 pll_in_use; | |
2440 | int pll; | |
2441 | ||
2442 | if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { | |
2443 | if (adev->clock.dp_extclk) | |
2444 | /* skip PPLL programming if using ext clock */ | |
2445 | return ATOM_PPLL_INVALID; | |
2446 | else { | |
2447 | /* use the same PPLL for all DP monitors */ | |
2448 | pll = amdgpu_pll_get_shared_dp_ppll(crtc); | |
2449 | if (pll != ATOM_PPLL_INVALID) | |
2450 | return pll; | |
2451 | } | |
2452 | } else { | |
2453 | /* use the same PPLL for all monitors with the same clock */ | |
2454 | pll = amdgpu_pll_get_shared_nondp_ppll(crtc); | |
2455 | if (pll != ATOM_PPLL_INVALID) | |
2456 | return pll; | |
2457 | } | |
2458 | ||
2459 | /* DCE10 has PPLL0, PPLL1, and PPLL2 */ | |
2460 | pll_in_use = amdgpu_pll_get_use_mask(crtc); | |
2461 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | |
2462 | return ATOM_PPLL2; | |
2463 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | |
2464 | return ATOM_PPLL1; | |
2465 | if (!(pll_in_use & (1 << ATOM_PPLL0))) | |
2466 | return ATOM_PPLL0; | |
2467 | DRM_ERROR("unable to allocate a PPLL\n"); | |
2468 | return ATOM_PPLL_INVALID; | |
2469 | } | |
2470 | ||
2471 | static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) | |
2472 | { | |
2473 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2474 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2475 | uint32_t cur_lock; | |
2476 | ||
2477 | cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); | |
2478 | if (lock) | |
2479 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); | |
2480 | else | |
2481 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); | |
2482 | WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); | |
2483 | } | |
2484 | ||
2485 | static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) | |
2486 | { | |
2487 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2488 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2489 | u32 tmp; | |
2490 | ||
2491 | tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); | |
2492 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); | |
2493 | WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2494 | } | |
2495 | ||
2496 | static void dce_v10_0_show_cursor(struct drm_crtc *crtc) | |
2497 | { | |
2498 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2499 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2500 | u32 tmp; | |
2501 | ||
2502 | tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); | |
2503 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); | |
2504 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); | |
2505 | WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); | |
2506 | } | |
2507 | ||
29275a9b AD |
2508 | static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, |
2509 | int x, int y) | |
aaa36a97 AD |
2510 | { |
2511 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2512 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2513 | int xorigin = 0, yorigin = 0; | |
2514 | ||
2515 | /* avivo cursor are offset into the total surface */ | |
2516 | x += crtc->x; | |
2517 | y += crtc->y; | |
2518 | DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); | |
2519 | ||
2520 | if (x < 0) { | |
2521 | xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); | |
2522 | x = 0; | |
2523 | } | |
2524 | if (y < 0) { | |
2525 | yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); | |
2526 | y = 0; | |
2527 | } | |
2528 | ||
aaa36a97 AD |
2529 | WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); |
2530 | WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); | |
2531 | WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, | |
2532 | ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); | |
29275a9b AD |
2533 | |
2534 | amdgpu_crtc->cursor_x = x; | |
2535 | amdgpu_crtc->cursor_y = y; | |
aaa36a97 AD |
2536 | |
2537 | return 0; | |
2538 | } | |
2539 | ||
ef67e38c | 2540 | static int dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj) |
29275a9b AD |
2541 | { |
2542 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2543 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
dd0b5d2f AD |
2544 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(obj); |
2545 | uint64_t gpu_addr; | |
2546 | int ret; | |
2547 | ||
2548 | ret = amdgpu_bo_reserve(aobj, false); | |
2549 | if (unlikely(ret != 0)) | |
2550 | goto fail; | |
2551 | ||
2552 | ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); | |
2553 | amdgpu_bo_unreserve(aobj); | |
2554 | if (ret) | |
2555 | goto fail; | |
29275a9b AD |
2556 | |
2557 | WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, | |
2558 | upper_32_bits(gpu_addr)); | |
2559 | WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, | |
2560 | lower_32_bits(gpu_addr)); | |
2561 | ||
dd0b5d2f AD |
2562 | return 0; |
2563 | ||
2564 | fail: | |
2565 | drm_gem_object_unreference_unlocked(obj); | |
2566 | ||
2567 | return ret; | |
29275a9b AD |
2568 | } |
2569 | ||
2570 | static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, | |
2571 | int x, int y) | |
2572 | { | |
2573 | int ret; | |
2574 | ||
2575 | dce_v10_0_lock_cursor(crtc, true); | |
2576 | ret = dce_v10_0_cursor_move_locked(crtc, x, y); | |
2577 | dce_v10_0_lock_cursor(crtc, false); | |
2578 | ||
2579 | return ret; | |
2580 | } | |
2581 | ||
2582 | static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, | |
2583 | struct drm_file *file_priv, | |
2584 | uint32_t handle, | |
2585 | uint32_t width, | |
2586 | uint32_t height, | |
2587 | int32_t hot_x, | |
2588 | int32_t hot_y) | |
aaa36a97 AD |
2589 | { |
2590 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2591 | struct drm_gem_object *obj; | |
aaa36a97 AD |
2592 | int ret; |
2593 | ||
2594 | if (!handle) { | |
2595 | /* turn off cursor */ | |
2596 | dce_v10_0_hide_cursor(crtc); | |
2597 | obj = NULL; | |
2598 | goto unpin; | |
2599 | } | |
2600 | ||
2601 | if ((width > amdgpu_crtc->max_cursor_width) || | |
2602 | (height > amdgpu_crtc->max_cursor_height)) { | |
2603 | DRM_ERROR("bad cursor width or height %d x %d\n", width, height); | |
2604 | return -EINVAL; | |
2605 | } | |
2606 | ||
2607 | obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); | |
2608 | if (!obj) { | |
2609 | DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); | |
2610 | return -ENOENT; | |
2611 | } | |
2612 | ||
aaa36a97 AD |
2613 | amdgpu_crtc->cursor_width = width; |
2614 | amdgpu_crtc->cursor_height = height; | |
2615 | ||
2616 | dce_v10_0_lock_cursor(crtc, true); | |
ef67e38c AD |
2617 | |
2618 | if (hot_x != amdgpu_crtc->cursor_hot_x || | |
2619 | hot_y != amdgpu_crtc->cursor_hot_y) { | |
2620 | int x, y; | |
2621 | ||
2622 | x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; | |
2623 | y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; | |
2624 | ||
2625 | dce_v10_0_cursor_move_locked(crtc, x, y); | |
2626 | ||
2627 | amdgpu_crtc->cursor_hot_x = hot_x; | |
2628 | amdgpu_crtc->cursor_hot_y = hot_y; | |
2629 | } | |
2630 | ||
2631 | ret = dce_v10_0_set_cursor(crtc, obj); | |
dd0b5d2f AD |
2632 | if (ret) |
2633 | DRM_ERROR("dce_v10_0_set_cursor returned %d, not changing cursor\n", | |
2634 | ret); | |
2635 | else | |
2636 | dce_v10_0_show_cursor(crtc); | |
aaa36a97 AD |
2637 | dce_v10_0_lock_cursor(crtc, false); |
2638 | ||
2639 | unpin: | |
2640 | if (amdgpu_crtc->cursor_bo) { | |
dd0b5d2f AD |
2641 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
2642 | ret = amdgpu_bo_reserve(aobj, false); | |
aaa36a97 | 2643 | if (likely(ret == 0)) { |
dd0b5d2f AD |
2644 | amdgpu_bo_unpin(aobj); |
2645 | amdgpu_bo_unreserve(aobj); | |
aaa36a97 | 2646 | } |
dd0b5d2f AD |
2647 | if (amdgpu_crtc->cursor_bo != obj) |
2648 | drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); | |
aaa36a97 AD |
2649 | } |
2650 | ||
2651 | amdgpu_crtc->cursor_bo = obj; | |
2652 | return 0; | |
dd0b5d2f | 2653 | } |
aaa36a97 | 2654 | |
dd0b5d2f AD |
2655 | static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) |
2656 | { | |
2657 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2658 | int ret; | |
2659 | ||
2660 | if (amdgpu_crtc->cursor_bo) { | |
2661 | dce_v10_0_lock_cursor(crtc, true); | |
2662 | ||
2663 | dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, | |
2664 | amdgpu_crtc->cursor_y); | |
2665 | ||
ef67e38c | 2666 | ret = dce_v10_0_set_cursor(crtc, amdgpu_crtc->cursor_bo); |
dd0b5d2f AD |
2667 | if (ret) |
2668 | DRM_ERROR("dce_v10_0_set_cursor returned %d, not showing " | |
2669 | "cursor\n", ret); | |
2670 | else | |
2671 | dce_v10_0_show_cursor(crtc); | |
2672 | ||
2673 | dce_v10_0_lock_cursor(crtc, false); | |
2674 | } | |
aaa36a97 AD |
2675 | } |
2676 | ||
2677 | static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
2678 | u16 *blue, uint32_t start, uint32_t size) | |
2679 | { | |
2680 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2681 | int end = (start + size > 256) ? 256 : start + size, i; | |
2682 | ||
2683 | /* userspace palettes are always correct as is */ | |
2684 | for (i = start; i < end; i++) { | |
2685 | amdgpu_crtc->lut_r[i] = red[i] >> 6; | |
2686 | amdgpu_crtc->lut_g[i] = green[i] >> 6; | |
2687 | amdgpu_crtc->lut_b[i] = blue[i] >> 6; | |
2688 | } | |
2689 | dce_v10_0_crtc_load_lut(crtc); | |
2690 | } | |
2691 | ||
2692 | static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) | |
2693 | { | |
2694 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2695 | ||
2696 | drm_crtc_cleanup(crtc); | |
2697 | destroy_workqueue(amdgpu_crtc->pflip_queue); | |
2698 | kfree(amdgpu_crtc); | |
2699 | } | |
2700 | ||
2701 | static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { | |
29275a9b | 2702 | .cursor_set2 = dce_v10_0_crtc_cursor_set2, |
aaa36a97 AD |
2703 | .cursor_move = dce_v10_0_crtc_cursor_move, |
2704 | .gamma_set = dce_v10_0_crtc_gamma_set, | |
2705 | .set_config = amdgpu_crtc_set_config, | |
2706 | .destroy = dce_v10_0_crtc_destroy, | |
2707 | .page_flip = amdgpu_crtc_page_flip, | |
2708 | }; | |
2709 | ||
2710 | static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2711 | { | |
2712 | struct drm_device *dev = crtc->dev; | |
2713 | struct amdgpu_device *adev = dev->dev_private; | |
2714 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
5e6775ab | 2715 | unsigned type; |
aaa36a97 AD |
2716 | |
2717 | switch (mode) { | |
2718 | case DRM_MODE_DPMS_ON: | |
2719 | amdgpu_crtc->enabled = true; | |
2720 | amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); | |
2721 | dce_v10_0_vga_enable(crtc, true); | |
2722 | amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); | |
2723 | dce_v10_0_vga_enable(crtc, false); | |
5e6775ab MD |
2724 | /* Make sure VBLANK interrupt is still enabled */ |
2725 | type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); | |
2726 | amdgpu_irq_update(adev, &adev->crtc_irq, type); | |
aaa36a97 AD |
2727 | drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); |
2728 | dce_v10_0_crtc_load_lut(crtc); | |
2729 | break; | |
2730 | case DRM_MODE_DPMS_STANDBY: | |
2731 | case DRM_MODE_DPMS_SUSPEND: | |
2732 | case DRM_MODE_DPMS_OFF: | |
2733 | drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); | |
2734 | if (amdgpu_crtc->enabled) { | |
2735 | dce_v10_0_vga_enable(crtc, true); | |
2736 | amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); | |
2737 | dce_v10_0_vga_enable(crtc, false); | |
2738 | } | |
2739 | amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); | |
2740 | amdgpu_crtc->enabled = false; | |
2741 | break; | |
2742 | } | |
2743 | /* adjust pm to dpms */ | |
2744 | amdgpu_pm_compute_clocks(adev); | |
2745 | } | |
2746 | ||
2747 | static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) | |
2748 | { | |
2749 | /* disable crtc pair power gating before programming */ | |
2750 | amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); | |
2751 | amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); | |
2752 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
2753 | } | |
2754 | ||
2755 | static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) | |
2756 | { | |
2757 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); | |
2758 | amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); | |
2759 | } | |
2760 | ||
2761 | static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) | |
2762 | { | |
2763 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2764 | struct drm_device *dev = crtc->dev; | |
2765 | struct amdgpu_device *adev = dev->dev_private; | |
2766 | struct amdgpu_atom_ss ss; | |
2767 | int i; | |
2768 | ||
2769 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
2770 | if (crtc->primary->fb) { | |
2771 | int r; | |
2772 | struct amdgpu_framebuffer *amdgpu_fb; | |
2773 | struct amdgpu_bo *rbo; | |
2774 | ||
2775 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
2776 | rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); | |
2777 | r = amdgpu_bo_reserve(rbo, false); | |
2778 | if (unlikely(r)) | |
2779 | DRM_ERROR("failed to reserve rbo before unpin\n"); | |
2780 | else { | |
2781 | amdgpu_bo_unpin(rbo); | |
2782 | amdgpu_bo_unreserve(rbo); | |
2783 | } | |
2784 | } | |
2785 | /* disable the GRPH */ | |
2786 | dce_v10_0_grph_enable(crtc, false); | |
2787 | ||
2788 | amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); | |
2789 | ||
2790 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
2791 | if (adev->mode_info.crtcs[i] && | |
2792 | adev->mode_info.crtcs[i]->enabled && | |
2793 | i != amdgpu_crtc->crtc_id && | |
2794 | amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { | |
2795 | /* one other crtc is using this pll don't turn | |
2796 | * off the pll | |
2797 | */ | |
2798 | goto done; | |
2799 | } | |
2800 | } | |
2801 | ||
2802 | switch (amdgpu_crtc->pll_id) { | |
2803 | case ATOM_PPLL0: | |
2804 | case ATOM_PPLL1: | |
2805 | case ATOM_PPLL2: | |
2806 | /* disable the ppll */ | |
2807 | amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, | |
2808 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); | |
2809 | break; | |
2810 | default: | |
2811 | break; | |
2812 | } | |
2813 | done: | |
2814 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; | |
2815 | amdgpu_crtc->adjusted_clock = 0; | |
2816 | amdgpu_crtc->encoder = NULL; | |
2817 | amdgpu_crtc->connector = NULL; | |
2818 | } | |
2819 | ||
2820 | static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, | |
2821 | struct drm_display_mode *mode, | |
2822 | struct drm_display_mode *adjusted_mode, | |
2823 | int x, int y, struct drm_framebuffer *old_fb) | |
2824 | { | |
2825 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2826 | ||
2827 | if (!amdgpu_crtc->adjusted_clock) | |
2828 | return -EINVAL; | |
2829 | ||
2830 | amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); | |
2831 | amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); | |
2832 | dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
2833 | amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); | |
2834 | amdgpu_atombios_crtc_scaler_setup(crtc); | |
dd0b5d2f | 2835 | dce_v10_0_cursor_reset(crtc); |
aaa36a97 AD |
2836 | /* update the hw version fpr dpm */ |
2837 | amdgpu_crtc->hw_mode = *adjusted_mode; | |
2838 | ||
2839 | return 0; | |
2840 | } | |
2841 | ||
2842 | static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, | |
2843 | const struct drm_display_mode *mode, | |
2844 | struct drm_display_mode *adjusted_mode) | |
2845 | { | |
2846 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2847 | struct drm_device *dev = crtc->dev; | |
2848 | struct drm_encoder *encoder; | |
2849 | ||
2850 | /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ | |
2851 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2852 | if (encoder->crtc == crtc) { | |
2853 | amdgpu_crtc->encoder = encoder; | |
2854 | amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); | |
2855 | break; | |
2856 | } | |
2857 | } | |
2858 | if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { | |
2859 | amdgpu_crtc->encoder = NULL; | |
2860 | amdgpu_crtc->connector = NULL; | |
2861 | return false; | |
2862 | } | |
2863 | if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) | |
2864 | return false; | |
2865 | if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) | |
2866 | return false; | |
2867 | /* pick pll */ | |
2868 | amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); | |
2869 | /* if we can't get a PPLL for a non-DP encoder, fail */ | |
2870 | if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && | |
2871 | !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) | |
2872 | return false; | |
2873 | ||
2874 | return true; | |
2875 | } | |
2876 | ||
2877 | static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, | |
2878 | struct drm_framebuffer *old_fb) | |
2879 | { | |
2880 | return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
2881 | } | |
2882 | ||
2883 | static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, | |
2884 | struct drm_framebuffer *fb, | |
2885 | int x, int y, enum mode_set_atomic state) | |
2886 | { | |
2887 | return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); | |
2888 | } | |
2889 | ||
2890 | static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { | |
2891 | .dpms = dce_v10_0_crtc_dpms, | |
2892 | .mode_fixup = dce_v10_0_crtc_mode_fixup, | |
2893 | .mode_set = dce_v10_0_crtc_mode_set, | |
2894 | .mode_set_base = dce_v10_0_crtc_set_base, | |
2895 | .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, | |
2896 | .prepare = dce_v10_0_crtc_prepare, | |
2897 | .commit = dce_v10_0_crtc_commit, | |
2898 | .load_lut = dce_v10_0_crtc_load_lut, | |
2899 | .disable = dce_v10_0_crtc_disable, | |
2900 | }; | |
2901 | ||
2902 | static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) | |
2903 | { | |
2904 | struct amdgpu_crtc *amdgpu_crtc; | |
2905 | int i; | |
2906 | ||
2907 | amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + | |
2908 | (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
2909 | if (amdgpu_crtc == NULL) | |
2910 | return -ENOMEM; | |
2911 | ||
2912 | drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); | |
2913 | ||
2914 | drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); | |
2915 | amdgpu_crtc->crtc_id = index; | |
2916 | amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); | |
2917 | adev->mode_info.crtcs[index] = amdgpu_crtc; | |
2918 | ||
2919 | amdgpu_crtc->max_cursor_width = 128; | |
2920 | amdgpu_crtc->max_cursor_height = 128; | |
2921 | adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; | |
2922 | adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; | |
2923 | ||
2924 | for (i = 0; i < 256; i++) { | |
2925 | amdgpu_crtc->lut_r[i] = i << 2; | |
2926 | amdgpu_crtc->lut_g[i] = i << 2; | |
2927 | amdgpu_crtc->lut_b[i] = i << 2; | |
2928 | } | |
2929 | ||
2930 | switch (amdgpu_crtc->crtc_id) { | |
2931 | case 0: | |
2932 | default: | |
2933 | amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; | |
2934 | break; | |
2935 | case 1: | |
2936 | amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; | |
2937 | break; | |
2938 | case 2: | |
2939 | amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; | |
2940 | break; | |
2941 | case 3: | |
2942 | amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; | |
2943 | break; | |
2944 | case 4: | |
2945 | amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; | |
2946 | break; | |
2947 | case 5: | |
2948 | amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; | |
2949 | break; | |
2950 | } | |
2951 | ||
2952 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; | |
2953 | amdgpu_crtc->adjusted_clock = 0; | |
2954 | amdgpu_crtc->encoder = NULL; | |
2955 | amdgpu_crtc->connector = NULL; | |
2956 | drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); | |
2957 | ||
2958 | return 0; | |
2959 | } | |
2960 | ||
5fc3aeeb | 2961 | static int dce_v10_0_early_init(void *handle) |
aaa36a97 | 2962 | { |
5fc3aeeb | 2963 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2964 | ||
aaa36a97 AD |
2965 | adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; |
2966 | adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; | |
2967 | ||
2968 | dce_v10_0_set_display_funcs(adev); | |
2969 | dce_v10_0_set_irq_funcs(adev); | |
2970 | ||
2971 | switch (adev->asic_type) { | |
84390860 | 2972 | case CHIP_FIJI: |
aaa36a97 AD |
2973 | case CHIP_TONGA: |
2974 | adev->mode_info.num_crtc = 6; /* XXX 7??? */ | |
2975 | adev->mode_info.num_hpd = 6; | |
2976 | adev->mode_info.num_dig = 7; | |
2977 | break; | |
2978 | default: | |
2979 | /* FIXME: not supported yet */ | |
2980 | return -EINVAL; | |
2981 | } | |
2982 | ||
2983 | return 0; | |
2984 | } | |
2985 | ||
5fc3aeeb | 2986 | static int dce_v10_0_sw_init(void *handle) |
aaa36a97 AD |
2987 | { |
2988 | int r, i; | |
5fc3aeeb | 2989 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
2990 | |
2991 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
2992 | r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); | |
2993 | if (r) | |
2994 | return r; | |
2995 | } | |
2996 | ||
2997 | for (i = 8; i < 20; i += 2) { | |
2998 | r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); | |
2999 | if (r) | |
3000 | return r; | |
3001 | } | |
3002 | ||
3003 | /* HPD hotplug */ | |
3004 | r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); | |
3005 | if (r) | |
3006 | return r; | |
3007 | ||
3008 | adev->mode_info.mode_config_initialized = true; | |
3009 | ||
3010 | adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; | |
3011 | ||
3012 | adev->ddev->mode_config.max_width = 16384; | |
3013 | adev->ddev->mode_config.max_height = 16384; | |
3014 | ||
3015 | adev->ddev->mode_config.preferred_depth = 24; | |
3016 | adev->ddev->mode_config.prefer_shadow = 1; | |
3017 | ||
3018 | adev->ddev->mode_config.fb_base = adev->mc.aper_base; | |
3019 | ||
3020 | r = amdgpu_modeset_create_props(adev); | |
3021 | if (r) | |
3022 | return r; | |
3023 | ||
3024 | adev->ddev->mode_config.max_width = 16384; | |
3025 | adev->ddev->mode_config.max_height = 16384; | |
3026 | ||
3027 | /* allocate crtcs */ | |
3028 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
3029 | r = dce_v10_0_crtc_init(adev, i); | |
3030 | if (r) | |
3031 | return r; | |
3032 | } | |
3033 | ||
3034 | if (amdgpu_atombios_get_connector_info_from_object_table(adev)) | |
3035 | amdgpu_print_display_setup(adev->ddev); | |
3036 | else | |
3037 | return -EINVAL; | |
3038 | ||
3039 | /* setup afmt */ | |
3040 | dce_v10_0_afmt_init(adev); | |
3041 | ||
3042 | r = dce_v10_0_audio_init(adev); | |
3043 | if (r) | |
3044 | return r; | |
3045 | ||
3046 | drm_kms_helper_poll_init(adev->ddev); | |
3047 | ||
3048 | return r; | |
3049 | } | |
3050 | ||
5fc3aeeb | 3051 | static int dce_v10_0_sw_fini(void *handle) |
aaa36a97 | 3052 | { |
5fc3aeeb | 3053 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3054 | ||
aaa36a97 AD |
3055 | kfree(adev->mode_info.bios_hardcoded_edid); |
3056 | ||
3057 | drm_kms_helper_poll_fini(adev->ddev); | |
3058 | ||
3059 | dce_v10_0_audio_fini(adev); | |
3060 | ||
3061 | dce_v10_0_afmt_fini(adev); | |
3062 | ||
3063 | drm_mode_config_cleanup(adev->ddev); | |
3064 | adev->mode_info.mode_config_initialized = false; | |
3065 | ||
3066 | return 0; | |
3067 | } | |
3068 | ||
5fc3aeeb | 3069 | static int dce_v10_0_hw_init(void *handle) |
aaa36a97 AD |
3070 | { |
3071 | int i; | |
5fc3aeeb | 3072 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3073 | |
3074 | dce_v10_0_init_golden_registers(adev); | |
3075 | ||
3076 | /* init dig PHYs, disp eng pll */ | |
3077 | amdgpu_atombios_encoder_init_dig(adev); | |
3078 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); | |
3079 | ||
3080 | /* initialize hpd */ | |
3081 | dce_v10_0_hpd_init(adev); | |
3082 | ||
3083 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
3084 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
3085 | } | |
3086 | ||
3087 | return 0; | |
3088 | } | |
3089 | ||
5fc3aeeb | 3090 | static int dce_v10_0_hw_fini(void *handle) |
aaa36a97 AD |
3091 | { |
3092 | int i; | |
5fc3aeeb | 3093 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3094 | |
3095 | dce_v10_0_hpd_fini(adev); | |
3096 | ||
3097 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
3098 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); | |
3099 | } | |
3100 | ||
3101 | return 0; | |
3102 | } | |
3103 | ||
5fc3aeeb | 3104 | static int dce_v10_0_suspend(void *handle) |
aaa36a97 | 3105 | { |
5fc3aeeb | 3106 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 | 3107 | |
aaa36a97 AD |
3108 | amdgpu_atombios_scratch_regs_save(adev); |
3109 | ||
3110 | dce_v10_0_hpd_fini(adev); | |
3111 | ||
3112 | return 0; | |
3113 | } | |
3114 | ||
5fc3aeeb | 3115 | static int dce_v10_0_resume(void *handle) |
aaa36a97 | 3116 | { |
5fc3aeeb | 3117 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3118 | |
3119 | dce_v10_0_init_golden_registers(adev); | |
3120 | ||
3121 | amdgpu_atombios_scratch_regs_restore(adev); | |
3122 | ||
3123 | /* init dig PHYs, disp eng pll */ | |
3124 | amdgpu_atombios_encoder_init_dig(adev); | |
3125 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); | |
3126 | /* turn on the BL */ | |
3127 | if (adev->mode_info.bl_encoder) { | |
3128 | u8 bl_level = amdgpu_display_backlight_get_level(adev, | |
3129 | adev->mode_info.bl_encoder); | |
3130 | amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, | |
3131 | bl_level); | |
3132 | } | |
3133 | ||
3134 | /* initialize hpd */ | |
3135 | dce_v10_0_hpd_init(adev); | |
3136 | ||
aaa36a97 AD |
3137 | return 0; |
3138 | } | |
3139 | ||
5fc3aeeb | 3140 | static bool dce_v10_0_is_idle(void *handle) |
aaa36a97 | 3141 | { |
aaa36a97 AD |
3142 | return true; |
3143 | } | |
3144 | ||
5fc3aeeb | 3145 | static int dce_v10_0_wait_for_idle(void *handle) |
aaa36a97 | 3146 | { |
aaa36a97 AD |
3147 | return 0; |
3148 | } | |
3149 | ||
5fc3aeeb | 3150 | static void dce_v10_0_print_status(void *handle) |
aaa36a97 | 3151 | { |
5fc3aeeb | 3152 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
3153 | ||
aaa36a97 AD |
3154 | dev_info(adev->dev, "DCE 10.x registers\n"); |
3155 | /* XXX todo */ | |
3156 | } | |
3157 | ||
5fc3aeeb | 3158 | static int dce_v10_0_soft_reset(void *handle) |
aaa36a97 AD |
3159 | { |
3160 | u32 srbm_soft_reset = 0, tmp; | |
5fc3aeeb | 3161 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
3162 | |
3163 | if (dce_v10_0_is_display_hung(adev)) | |
3164 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; | |
3165 | ||
3166 | if (srbm_soft_reset) { | |
5fc3aeeb | 3167 | dce_v10_0_print_status((void *)adev); |
aaa36a97 AD |
3168 | |
3169 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
3170 | tmp |= srbm_soft_reset; | |
3171 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
3172 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
3173 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
3174 | ||
3175 | udelay(50); | |
3176 | ||
3177 | tmp &= ~srbm_soft_reset; | |
3178 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
3179 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
3180 | ||
3181 | /* Wait a little for things to settle down */ | |
3182 | udelay(50); | |
5fc3aeeb | 3183 | dce_v10_0_print_status((void *)adev); |
aaa36a97 AD |
3184 | } |
3185 | return 0; | |
3186 | } | |
3187 | ||
3188 | static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, | |
3189 | int crtc, | |
3190 | enum amdgpu_interrupt_state state) | |
3191 | { | |
3192 | u32 lb_interrupt_mask; | |
3193 | ||
3194 | if (crtc >= adev->mode_info.num_crtc) { | |
3195 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3196 | return; | |
3197 | } | |
3198 | ||
3199 | switch (state) { | |
3200 | case AMDGPU_IRQ_STATE_DISABLE: | |
3201 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3202 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3203 | VBLANK_INTERRUPT_MASK, 0); | |
3204 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3205 | break; | |
3206 | case AMDGPU_IRQ_STATE_ENABLE: | |
3207 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3208 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3209 | VBLANK_INTERRUPT_MASK, 1); | |
3210 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3211 | break; | |
3212 | default: | |
3213 | break; | |
3214 | } | |
3215 | } | |
3216 | ||
3217 | static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, | |
3218 | int crtc, | |
3219 | enum amdgpu_interrupt_state state) | |
3220 | { | |
3221 | u32 lb_interrupt_mask; | |
3222 | ||
3223 | if (crtc >= adev->mode_info.num_crtc) { | |
3224 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3225 | return; | |
3226 | } | |
3227 | ||
3228 | switch (state) { | |
3229 | case AMDGPU_IRQ_STATE_DISABLE: | |
3230 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3231 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3232 | VLINE_INTERRUPT_MASK, 0); | |
3233 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3234 | break; | |
3235 | case AMDGPU_IRQ_STATE_ENABLE: | |
3236 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); | |
3237 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, | |
3238 | VLINE_INTERRUPT_MASK, 1); | |
3239 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); | |
3240 | break; | |
3241 | default: | |
3242 | break; | |
3243 | } | |
3244 | } | |
3245 | ||
3246 | static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, | |
3247 | struct amdgpu_irq_src *source, | |
3248 | unsigned hpd, | |
3249 | enum amdgpu_interrupt_state state) | |
3250 | { | |
3251 | u32 tmp; | |
3252 | ||
3253 | if (hpd >= adev->mode_info.num_hpd) { | |
3254 | DRM_DEBUG("invalid hdp %d\n", hpd); | |
3255 | return 0; | |
3256 | } | |
3257 | ||
3258 | switch (state) { | |
3259 | case AMDGPU_IRQ_STATE_DISABLE: | |
3260 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); | |
3261 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); | |
3262 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); | |
3263 | break; | |
3264 | case AMDGPU_IRQ_STATE_ENABLE: | |
3265 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); | |
3266 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); | |
3267 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); | |
3268 | break; | |
3269 | default: | |
3270 | break; | |
3271 | } | |
3272 | ||
3273 | return 0; | |
3274 | } | |
3275 | ||
3276 | static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, | |
3277 | struct amdgpu_irq_src *source, | |
3278 | unsigned type, | |
3279 | enum amdgpu_interrupt_state state) | |
3280 | { | |
3281 | switch (type) { | |
3282 | case AMDGPU_CRTC_IRQ_VBLANK1: | |
3283 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); | |
3284 | break; | |
3285 | case AMDGPU_CRTC_IRQ_VBLANK2: | |
3286 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); | |
3287 | break; | |
3288 | case AMDGPU_CRTC_IRQ_VBLANK3: | |
3289 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); | |
3290 | break; | |
3291 | case AMDGPU_CRTC_IRQ_VBLANK4: | |
3292 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); | |
3293 | break; | |
3294 | case AMDGPU_CRTC_IRQ_VBLANK5: | |
3295 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); | |
3296 | break; | |
3297 | case AMDGPU_CRTC_IRQ_VBLANK6: | |
3298 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); | |
3299 | break; | |
3300 | case AMDGPU_CRTC_IRQ_VLINE1: | |
3301 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); | |
3302 | break; | |
3303 | case AMDGPU_CRTC_IRQ_VLINE2: | |
3304 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); | |
3305 | break; | |
3306 | case AMDGPU_CRTC_IRQ_VLINE3: | |
3307 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); | |
3308 | break; | |
3309 | case AMDGPU_CRTC_IRQ_VLINE4: | |
3310 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); | |
3311 | break; | |
3312 | case AMDGPU_CRTC_IRQ_VLINE5: | |
3313 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); | |
3314 | break; | |
3315 | case AMDGPU_CRTC_IRQ_VLINE6: | |
3316 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); | |
3317 | break; | |
3318 | default: | |
3319 | break; | |
3320 | } | |
3321 | return 0; | |
3322 | } | |
3323 | ||
3324 | static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, | |
3325 | struct amdgpu_irq_src *src, | |
3326 | unsigned type, | |
3327 | enum amdgpu_interrupt_state state) | |
3328 | { | |
3329 | u32 reg, reg_block; | |
3330 | /* now deal with page flip IRQ */ | |
3331 | switch (type) { | |
3332 | case AMDGPU_PAGEFLIP_IRQ_D1: | |
3333 | reg_block = CRTC0_REGISTER_OFFSET; | |
3334 | break; | |
3335 | case AMDGPU_PAGEFLIP_IRQ_D2: | |
3336 | reg_block = CRTC1_REGISTER_OFFSET; | |
3337 | break; | |
3338 | case AMDGPU_PAGEFLIP_IRQ_D3: | |
3339 | reg_block = CRTC2_REGISTER_OFFSET; | |
3340 | break; | |
3341 | case AMDGPU_PAGEFLIP_IRQ_D4: | |
3342 | reg_block = CRTC3_REGISTER_OFFSET; | |
3343 | break; | |
3344 | case AMDGPU_PAGEFLIP_IRQ_D5: | |
3345 | reg_block = CRTC4_REGISTER_OFFSET; | |
3346 | break; | |
3347 | case AMDGPU_PAGEFLIP_IRQ_D6: | |
3348 | reg_block = CRTC5_REGISTER_OFFSET; | |
3349 | break; | |
3350 | default: | |
3351 | DRM_ERROR("invalid pageflip crtc %d\n", type); | |
3352 | return -EINVAL; | |
3353 | } | |
3354 | ||
3355 | reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); | |
3356 | if (state == AMDGPU_IRQ_STATE_DISABLE) | |
3357 | WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); | |
3358 | else | |
3359 | WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); | |
3360 | ||
3361 | return 0; | |
3362 | } | |
3363 | ||
3364 | static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, | |
3365 | struct amdgpu_irq_src *source, | |
3366 | struct amdgpu_iv_entry *entry) | |
3367 | { | |
3368 | int reg_block; | |
3369 | unsigned long flags; | |
3370 | unsigned crtc_id; | |
3371 | struct amdgpu_crtc *amdgpu_crtc; | |
3372 | struct amdgpu_flip_work *works; | |
3373 | ||
3374 | crtc_id = (entry->src_id - 8) >> 1; | |
3375 | amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; | |
3376 | ||
3377 | /* ack the interrupt */ | |
3378 | switch(crtc_id){ | |
3379 | case AMDGPU_PAGEFLIP_IRQ_D1: | |
3380 | reg_block = CRTC0_REGISTER_OFFSET; | |
3381 | break; | |
3382 | case AMDGPU_PAGEFLIP_IRQ_D2: | |
3383 | reg_block = CRTC1_REGISTER_OFFSET; | |
3384 | break; | |
3385 | case AMDGPU_PAGEFLIP_IRQ_D3: | |
3386 | reg_block = CRTC2_REGISTER_OFFSET; | |
3387 | break; | |
3388 | case AMDGPU_PAGEFLIP_IRQ_D4: | |
3389 | reg_block = CRTC3_REGISTER_OFFSET; | |
3390 | break; | |
3391 | case AMDGPU_PAGEFLIP_IRQ_D5: | |
3392 | reg_block = CRTC4_REGISTER_OFFSET; | |
3393 | break; | |
3394 | case AMDGPU_PAGEFLIP_IRQ_D6: | |
3395 | reg_block = CRTC5_REGISTER_OFFSET; | |
3396 | break; | |
3397 | default: | |
3398 | DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); | |
3399 | return -EINVAL; | |
3400 | } | |
3401 | ||
3402 | if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) | |
3403 | WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); | |
3404 | ||
3405 | /* IRQ could occur when in initial stage */ | |
3406 | if (amdgpu_crtc == NULL) | |
3407 | return 0; | |
3408 | ||
3409 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
3410 | works = amdgpu_crtc->pflip_works; | |
3411 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { | |
3412 | DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " | |
3413 | "AMDGPU_FLIP_SUBMITTED(%d)\n", | |
3414 | amdgpu_crtc->pflip_status, | |
3415 | AMDGPU_FLIP_SUBMITTED); | |
3416 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
3417 | return 0; | |
3418 | } | |
3419 | ||
3420 | /* page flip completed. clean up */ | |
3421 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; | |
3422 | amdgpu_crtc->pflip_works = NULL; | |
3423 | ||
3424 | /* wakeup usersapce */ | |
3425 | if (works->event) | |
3426 | drm_send_vblank_event(adev->ddev, crtc_id, works->event); | |
3427 | ||
3428 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
3429 | ||
3430 | drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); | |
3431 | amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); | |
3432 | queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); | |
3433 | ||
3434 | return 0; | |
3435 | } | |
3436 | ||
3437 | static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, | |
3438 | int hpd) | |
3439 | { | |
3440 | u32 tmp; | |
3441 | ||
3442 | if (hpd >= adev->mode_info.num_hpd) { | |
3443 | DRM_DEBUG("invalid hdp %d\n", hpd); | |
3444 | return; | |
3445 | } | |
3446 | ||
3447 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); | |
3448 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); | |
3449 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); | |
3450 | } | |
3451 | ||
3452 | static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, | |
3453 | int crtc) | |
3454 | { | |
3455 | u32 tmp; | |
3456 | ||
3457 | if (crtc >= adev->mode_info.num_crtc) { | |
3458 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3459 | return; | |
3460 | } | |
3461 | ||
3462 | tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); | |
3463 | tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); | |
3464 | WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); | |
3465 | } | |
3466 | ||
3467 | static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, | |
3468 | int crtc) | |
3469 | { | |
3470 | u32 tmp; | |
3471 | ||
3472 | if (crtc >= adev->mode_info.num_crtc) { | |
3473 | DRM_DEBUG("invalid crtc %d\n", crtc); | |
3474 | return; | |
3475 | } | |
3476 | ||
3477 | tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); | |
3478 | tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); | |
3479 | WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); | |
3480 | } | |
3481 | ||
3482 | static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, | |
3483 | struct amdgpu_irq_src *source, | |
3484 | struct amdgpu_iv_entry *entry) | |
3485 | { | |
3486 | unsigned crtc = entry->src_id - 1; | |
3487 | uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); | |
3488 | unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); | |
3489 | ||
3490 | switch (entry->src_data) { | |
3491 | case 0: /* vblank */ | |
bd833144 | 3492 | if (disp_int & interrupt_status_offsets[crtc].vblank) |
aaa36a97 | 3493 | dce_v10_0_crtc_vblank_int_ack(adev, crtc); |
bd833144 MK |
3494 | else |
3495 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); | |
3496 | ||
3497 | if (amdgpu_irq_enabled(adev, source, irq_type)) { | |
3498 | drm_handle_vblank(adev->ddev, crtc); | |
aaa36a97 | 3499 | } |
bd833144 MK |
3500 | DRM_DEBUG("IH: D%d vblank\n", crtc + 1); |
3501 | ||
aaa36a97 AD |
3502 | break; |
3503 | case 1: /* vline */ | |
bd833144 | 3504 | if (disp_int & interrupt_status_offsets[crtc].vline) |
aaa36a97 | 3505 | dce_v10_0_crtc_vline_int_ack(adev, crtc); |
bd833144 MK |
3506 | else |
3507 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); | |
3508 | ||
3509 | DRM_DEBUG("IH: D%d vline\n", crtc + 1); | |
3510 | ||
aaa36a97 AD |
3511 | break; |
3512 | default: | |
3513 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); | |
3514 | break; | |
3515 | } | |
3516 | ||
3517 | return 0; | |
3518 | } | |
3519 | ||
3520 | static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, | |
3521 | struct amdgpu_irq_src *source, | |
3522 | struct amdgpu_iv_entry *entry) | |
3523 | { | |
3524 | uint32_t disp_int, mask; | |
3525 | unsigned hpd; | |
3526 | ||
3527 | if (entry->src_data >= adev->mode_info.num_hpd) { | |
3528 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); | |
3529 | return 0; | |
3530 | } | |
3531 | ||
3532 | hpd = entry->src_data; | |
3533 | disp_int = RREG32(interrupt_status_offsets[hpd].reg); | |
3534 | mask = interrupt_status_offsets[hpd].hpd; | |
3535 | ||
3536 | if (disp_int & mask) { | |
3537 | dce_v10_0_hpd_int_ack(adev, hpd); | |
3538 | schedule_work(&adev->hotplug_work); | |
3539 | DRM_DEBUG("IH: HPD%d\n", hpd + 1); | |
3540 | } | |
3541 | ||
3542 | return 0; | |
3543 | } | |
3544 | ||
5fc3aeeb | 3545 | static int dce_v10_0_set_clockgating_state(void *handle, |
3546 | enum amd_clockgating_state state) | |
aaa36a97 AD |
3547 | { |
3548 | return 0; | |
3549 | } | |
3550 | ||
5fc3aeeb | 3551 | static int dce_v10_0_set_powergating_state(void *handle, |
3552 | enum amd_powergating_state state) | |
aaa36a97 AD |
3553 | { |
3554 | return 0; | |
3555 | } | |
3556 | ||
5fc3aeeb | 3557 | const struct amd_ip_funcs dce_v10_0_ip_funcs = { |
aaa36a97 AD |
3558 | .early_init = dce_v10_0_early_init, |
3559 | .late_init = NULL, | |
3560 | .sw_init = dce_v10_0_sw_init, | |
3561 | .sw_fini = dce_v10_0_sw_fini, | |
3562 | .hw_init = dce_v10_0_hw_init, | |
3563 | .hw_fini = dce_v10_0_hw_fini, | |
3564 | .suspend = dce_v10_0_suspend, | |
3565 | .resume = dce_v10_0_resume, | |
3566 | .is_idle = dce_v10_0_is_idle, | |
3567 | .wait_for_idle = dce_v10_0_wait_for_idle, | |
3568 | .soft_reset = dce_v10_0_soft_reset, | |
3569 | .print_status = dce_v10_0_print_status, | |
3570 | .set_clockgating_state = dce_v10_0_set_clockgating_state, | |
3571 | .set_powergating_state = dce_v10_0_set_powergating_state, | |
3572 | }; | |
3573 | ||
3574 | static void | |
3575 | dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, | |
3576 | struct drm_display_mode *mode, | |
3577 | struct drm_display_mode *adjusted_mode) | |
3578 | { | |
3579 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3580 | ||
3581 | amdgpu_encoder->pixel_clock = adjusted_mode->clock; | |
3582 | ||
3583 | /* need to call this here rather than in prepare() since we need some crtc info */ | |
3584 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
3585 | ||
3586 | /* set scaler clears this on some chips */ | |
3587 | dce_v10_0_set_interleave(encoder->crtc, mode); | |
3588 | ||
3589 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { | |
3590 | dce_v10_0_afmt_enable(encoder, true); | |
3591 | dce_v10_0_afmt_setmode(encoder, adjusted_mode); | |
3592 | } | |
3593 | } | |
3594 | ||
3595 | static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) | |
3596 | { | |
3597 | struct amdgpu_device *adev = encoder->dev->dev_private; | |
3598 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3599 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); | |
3600 | ||
3601 | if ((amdgpu_encoder->active_device & | |
3602 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || | |
3603 | (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != | |
3604 | ENCODER_OBJECT_ID_NONE)) { | |
3605 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; | |
3606 | if (dig) { | |
3607 | dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); | |
3608 | if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) | |
3609 | dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; | |
3610 | } | |
3611 | } | |
3612 | ||
3613 | amdgpu_atombios_scratch_regs_lock(adev, true); | |
3614 | ||
3615 | if (connector) { | |
3616 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); | |
3617 | ||
3618 | /* select the clock/data port if it uses a router */ | |
3619 | if (amdgpu_connector->router.cd_valid) | |
3620 | amdgpu_i2c_router_select_cd_port(amdgpu_connector); | |
3621 | ||
3622 | /* turn eDP panel on for mode set */ | |
3623 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
3624 | amdgpu_atombios_encoder_set_edp_panel_power(connector, | |
3625 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
3626 | } | |
3627 | ||
3628 | /* this is needed for the pll/ss setup to work correctly in some cases */ | |
3629 | amdgpu_atombios_encoder_set_crtc_source(encoder); | |
3630 | /* set up the FMT blocks */ | |
3631 | dce_v10_0_program_fmt(encoder); | |
3632 | } | |
3633 | ||
3634 | static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) | |
3635 | { | |
3636 | struct drm_device *dev = encoder->dev; | |
3637 | struct amdgpu_device *adev = dev->dev_private; | |
3638 | ||
3639 | /* need to call this here as we need the crtc set up */ | |
3640 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | |
3641 | amdgpu_atombios_scratch_regs_lock(adev, false); | |
3642 | } | |
3643 | ||
3644 | static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) | |
3645 | { | |
3646 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3647 | struct amdgpu_encoder_atom_dig *dig; | |
3648 | ||
3649 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
3650 | ||
3651 | if (amdgpu_atombios_encoder_is_digital(encoder)) { | |
3652 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) | |
3653 | dce_v10_0_afmt_enable(encoder, false); | |
3654 | dig = amdgpu_encoder->enc_priv; | |
3655 | dig->dig_encoder = -1; | |
3656 | } | |
3657 | amdgpu_encoder->active_device = 0; | |
3658 | } | |
3659 | ||
3660 | /* these are handled by the primary encoders */ | |
3661 | static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) | |
3662 | { | |
3663 | ||
3664 | } | |
3665 | ||
3666 | static void dce_v10_0_ext_commit(struct drm_encoder *encoder) | |
3667 | { | |
3668 | ||
3669 | } | |
3670 | ||
3671 | static void | |
3672 | dce_v10_0_ext_mode_set(struct drm_encoder *encoder, | |
3673 | struct drm_display_mode *mode, | |
3674 | struct drm_display_mode *adjusted_mode) | |
3675 | { | |
3676 | ||
3677 | } | |
3678 | ||
3679 | static void dce_v10_0_ext_disable(struct drm_encoder *encoder) | |
3680 | { | |
3681 | ||
3682 | } | |
3683 | ||
3684 | static void | |
3685 | dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) | |
3686 | { | |
3687 | ||
3688 | } | |
3689 | ||
3690 | static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder, | |
3691 | const struct drm_display_mode *mode, | |
3692 | struct drm_display_mode *adjusted_mode) | |
3693 | { | |
3694 | return true; | |
3695 | } | |
3696 | ||
3697 | static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { | |
3698 | .dpms = dce_v10_0_ext_dpms, | |
3699 | .mode_fixup = dce_v10_0_ext_mode_fixup, | |
3700 | .prepare = dce_v10_0_ext_prepare, | |
3701 | .mode_set = dce_v10_0_ext_mode_set, | |
3702 | .commit = dce_v10_0_ext_commit, | |
3703 | .disable = dce_v10_0_ext_disable, | |
3704 | /* no detect for TMDS/LVDS yet */ | |
3705 | }; | |
3706 | ||
3707 | static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { | |
3708 | .dpms = amdgpu_atombios_encoder_dpms, | |
3709 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, | |
3710 | .prepare = dce_v10_0_encoder_prepare, | |
3711 | .mode_set = dce_v10_0_encoder_mode_set, | |
3712 | .commit = dce_v10_0_encoder_commit, | |
3713 | .disable = dce_v10_0_encoder_disable, | |
3714 | .detect = amdgpu_atombios_encoder_dig_detect, | |
3715 | }; | |
3716 | ||
3717 | static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { | |
3718 | .dpms = amdgpu_atombios_encoder_dpms, | |
3719 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, | |
3720 | .prepare = dce_v10_0_encoder_prepare, | |
3721 | .mode_set = dce_v10_0_encoder_mode_set, | |
3722 | .commit = dce_v10_0_encoder_commit, | |
3723 | .detect = amdgpu_atombios_encoder_dac_detect, | |
3724 | }; | |
3725 | ||
3726 | static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) | |
3727 | { | |
3728 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3729 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
3730 | amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); | |
3731 | kfree(amdgpu_encoder->enc_priv); | |
3732 | drm_encoder_cleanup(encoder); | |
3733 | kfree(amdgpu_encoder); | |
3734 | } | |
3735 | ||
3736 | static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { | |
3737 | .destroy = dce_v10_0_encoder_destroy, | |
3738 | }; | |
3739 | ||
3740 | static void dce_v10_0_encoder_add(struct amdgpu_device *adev, | |
3741 | uint32_t encoder_enum, | |
3742 | uint32_t supported_device, | |
3743 | u16 caps) | |
3744 | { | |
3745 | struct drm_device *dev = adev->ddev; | |
3746 | struct drm_encoder *encoder; | |
3747 | struct amdgpu_encoder *amdgpu_encoder; | |
3748 | ||
3749 | /* see if we already added it */ | |
3750 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3751 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3752 | if (amdgpu_encoder->encoder_enum == encoder_enum) { | |
3753 | amdgpu_encoder->devices |= supported_device; | |
3754 | return; | |
3755 | } | |
3756 | ||
3757 | } | |
3758 | ||
3759 | /* add a new one */ | |
3760 | amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); | |
3761 | if (!amdgpu_encoder) | |
3762 | return; | |
3763 | ||
3764 | encoder = &amdgpu_encoder->base; | |
3765 | switch (adev->mode_info.num_crtc) { | |
3766 | case 1: | |
3767 | encoder->possible_crtcs = 0x1; | |
3768 | break; | |
3769 | case 2: | |
3770 | default: | |
3771 | encoder->possible_crtcs = 0x3; | |
3772 | break; | |
3773 | case 4: | |
3774 | encoder->possible_crtcs = 0xf; | |
3775 | break; | |
3776 | case 6: | |
3777 | encoder->possible_crtcs = 0x3f; | |
3778 | break; | |
3779 | } | |
3780 | ||
3781 | amdgpu_encoder->enc_priv = NULL; | |
3782 | ||
3783 | amdgpu_encoder->encoder_enum = encoder_enum; | |
3784 | amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
3785 | amdgpu_encoder->devices = supported_device; | |
3786 | amdgpu_encoder->rmx_type = RMX_OFF; | |
3787 | amdgpu_encoder->underscan_type = UNDERSCAN_OFF; | |
3788 | amdgpu_encoder->is_ext_encoder = false; | |
3789 | amdgpu_encoder->caps = caps; | |
3790 | ||
3791 | switch (amdgpu_encoder->encoder_id) { | |
3792 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
3793 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
3794 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3795 | DRM_MODE_ENCODER_DAC); | |
3796 | drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); | |
3797 | break; | |
3798 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
3799 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
3800 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
3801 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
3802 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: | |
3803 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
3804 | amdgpu_encoder->rmx_type = RMX_FULL; | |
3805 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3806 | DRM_MODE_ENCODER_LVDS); | |
3807 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); | |
3808 | } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { | |
3809 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3810 | DRM_MODE_ENCODER_DAC); | |
3811 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); | |
3812 | } else { | |
3813 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3814 | DRM_MODE_ENCODER_TMDS); | |
3815 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); | |
3816 | } | |
3817 | drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); | |
3818 | break; | |
3819 | case ENCODER_OBJECT_ID_SI170B: | |
3820 | case ENCODER_OBJECT_ID_CH7303: | |
3821 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: | |
3822 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: | |
3823 | case ENCODER_OBJECT_ID_TITFP513: | |
3824 | case ENCODER_OBJECT_ID_VT1623: | |
3825 | case ENCODER_OBJECT_ID_HDMI_SI1930: | |
3826 | case ENCODER_OBJECT_ID_TRAVIS: | |
3827 | case ENCODER_OBJECT_ID_NUTMEG: | |
3828 | /* these are handled by the primary encoders */ | |
3829 | amdgpu_encoder->is_ext_encoder = true; | |
3830 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
3831 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3832 | DRM_MODE_ENCODER_LVDS); | |
3833 | else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) | |
3834 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3835 | DRM_MODE_ENCODER_DAC); | |
3836 | else | |
3837 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, | |
3838 | DRM_MODE_ENCODER_TMDS); | |
3839 | drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); | |
3840 | break; | |
3841 | } | |
3842 | } | |
3843 | ||
3844 | static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { | |
3845 | .set_vga_render_state = &dce_v10_0_set_vga_render_state, | |
3846 | .bandwidth_update = &dce_v10_0_bandwidth_update, | |
3847 | .vblank_get_counter = &dce_v10_0_vblank_get_counter, | |
3848 | .vblank_wait = &dce_v10_0_vblank_wait, | |
3849 | .is_display_hung = &dce_v10_0_is_display_hung, | |
3850 | .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, | |
3851 | .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, | |
3852 | .hpd_sense = &dce_v10_0_hpd_sense, | |
3853 | .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, | |
3854 | .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, | |
3855 | .page_flip = &dce_v10_0_page_flip, | |
3856 | .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, | |
3857 | .add_encoder = &dce_v10_0_encoder_add, | |
3858 | .add_connector = &amdgpu_connector_add, | |
3859 | .stop_mc_access = &dce_v10_0_stop_mc_access, | |
3860 | .resume_mc_access = &dce_v10_0_resume_mc_access, | |
3861 | }; | |
3862 | ||
3863 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) | |
3864 | { | |
3865 | if (adev->mode_info.funcs == NULL) | |
3866 | adev->mode_info.funcs = &dce_v10_0_display_funcs; | |
3867 | } | |
3868 | ||
3869 | static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { | |
3870 | .set = dce_v10_0_set_crtc_irq_state, | |
3871 | .process = dce_v10_0_crtc_irq, | |
3872 | }; | |
3873 | ||
3874 | static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { | |
3875 | .set = dce_v10_0_set_pageflip_irq_state, | |
3876 | .process = dce_v10_0_pageflip_irq, | |
3877 | }; | |
3878 | ||
3879 | static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { | |
3880 | .set = dce_v10_0_set_hpd_irq_state, | |
3881 | .process = dce_v10_0_hpd_irq, | |
3882 | }; | |
3883 | ||
3884 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) | |
3885 | { | |
3886 | adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; | |
3887 | adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; | |
3888 | ||
3889 | adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; | |
3890 | adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; | |
3891 | ||
3892 | adev->hpd_irq.num_types = AMDGPU_HPD_LAST; | |
3893 | adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; | |
3894 | } |