[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / cz_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/pci.h>

#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_3_0_1_d.h"
#include "oss/oss_3_0_1_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * cz_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_cntl = RREG32(mmIH_CNTL);
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	WREG32(mmIH_CNTL, ih_cntl);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * cz_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	u32 ih_cntl = RREG32(mmIH_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	WREG32(mmIH_CNTL, ih_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * cz_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int cz_ih_irq_init(struct amdgpu_device *adev)
{
	struct amdgpu_ih_ring *ih = &adev->irq.ih;
	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
	int rb_bufsz;

	/* disable irqs */
	cz_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

	/* set the writeback address whether it's enabled or not */
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	/* Default settings for IH_CNTL (disabled at first) */
	ih_cntl = RREG32(mmIH_CNTL);
	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

	if (adev->irq.msi_enabled)
		ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
	WREG32(mmIH_CNTL, ih_cntl);

	pci_set_master(adev->pdev);

	/* enable interrupts */
	cz_ih_enable_interrupts(adev);

	return 0;
}

/**
 * cz_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void cz_ih_irq_disable(struct amdgpu_device *adev)
{
	cz_ih_disable_interrupts(adev);

	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * cz_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to fetch wptr
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
			  struct amdgpu_ih_ring *ih)
{
	u32 wptr, tmp;

	wptr = le32_to_cpu(*ih->wptr_cpu);

	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
		goto out;

	/* Double check that the overflow wasn't already cleared. */
	wptr = RREG32(mmIH_RB_WPTR);

	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
		goto out;

	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

	/* When a ring buffer overflow happen start parsing interrupt
	 * from the last not overwritten vector (wptr + 16). Hopefully
	 * this should allow us to catchup.
	 */
	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
	ih->rptr = (wptr + 16) & ih->ptr_mask;
	tmp = RREG32(mmIH_RB_CNTL);
	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	WREG32(mmIH_RB_CNTL, tmp);

	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
	 * can be detected.
	 */
	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
	WREG32(mmIH_RB_CNTL, tmp);

out:
	return (wptr & ih->ptr_mask);
}

/**
 * cz_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to decode
 * @entry: IV entry to place decoded information into
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void cz_ih_decode_iv(struct amdgpu_device *adev,
			    struct amdgpu_ih_ring *ih,
			    struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = ih->rptr >> 2;
	uint32_t dw[4];

	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);

	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
	entry->src_id = dw[0] & 0xff;
	entry->src_data[0] = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vmid = (dw[2] >> 8) & 0xff;
	entry->pasid = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	ih->rptr += 16;
}

/**
 * cz_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to set rptr
 *
 * Set the IH ring buffer rptr.
 */
static void cz_ih_set_rptr(struct amdgpu_device *adev,
			   struct amdgpu_ih_ring *ih)
{
	WREG32(mmIH_RB_RPTR, ih->rptr);
}

static int cz_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	ret = amdgpu_irq_add_domain(adev);
	if (ret)
		return ret;

	cz_ih_set_interrupt_funcs(adev);

	return 0;
}

static int cz_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
	if (r)
		return r;

	r = amdgpu_irq_init(adev);

	return r;
}

static int cz_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini_sw(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}

static int cz_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = cz_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int cz_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	cz_ih_irq_disable(adev);

	return 0;
}

static int cz_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return cz_ih_hw_fini(adev);
}

static int cz_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return cz_ih_hw_init(adev);
}

static bool cz_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
		return false;

	return true;
}

static int cz_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS);
		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static int cz_ih_soft_reset(void *handle)
{
	u32 srbm_soft_reset = 0;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
						SOFT_RESET_IH, 1);

	if (srbm_soft_reset) {
		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);
	}

	return 0;
}

static int cz_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	// TODO
	return 0;
}

static int cz_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	// TODO
	return 0;
}

static const struct amd_ip_funcs cz_ih_ip_funcs = {
	.name = "cz_ih",
	.early_init = cz_ih_early_init,
	.late_init = NULL,
	.sw_init = cz_ih_sw_init,
	.sw_fini = cz_ih_sw_fini,
	.hw_init = cz_ih_hw_init,
	.hw_fini = cz_ih_hw_fini,
	.suspend = cz_ih_suspend,
	.resume = cz_ih_resume,
	.is_idle = cz_ih_is_idle,
	.wait_for_idle = cz_ih_wait_for_idle,
	.soft_reset = cz_ih_soft_reset,
	.set_clockgating_state = cz_ih_set_clockgating_state,
	.set_powergating_state = cz_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs cz_ih_funcs = {
	.get_wptr = cz_ih_get_wptr,
	.decode_iv = cz_ih_decode_iv,
	.set_rptr = cz_ih_set_rptr
};

static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	adev->irq.ih_funcs = &cz_ih_funcs;
}

const struct amdgpu_ip_block_version cz_ih_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_IH,
	.major = 3,
	.minor = 0,
	.rev = 0,
	.funcs = &cz_ih_ip_funcs,
};
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
47b757fb SR	23
	24	#include <linux/pci.h>
	25
aaa36a97 AD	26	#include "amdgpu.h"
	27	#include "amdgpu_ih.h"
	28	#include "vid.h"
	29
	30	#include "oss/oss_3_0_1_d.h"
	31	#include "oss/oss_3_0_1_sh_mask.h"
	32
	33	#include "bif/bif_5_1_d.h"
	34	#include "bif/bif_5_1_sh_mask.h"
	35
	36	/*
	37	* Interrupts
	38	* Starting with r6xx, interrupts are handled via a ring buffer.
	39	* Ring buffers are areas of GPU accessible memory that the GPU
	40	* writes interrupt vectors into and the host reads vectors out of.
	41	* There is a rptr (read pointer) that determines where the
	42	* host is currently reading, and a wptr (write pointer)
	43	* which determines where the GPU has written. When the
	44	* pointers are equal, the ring is idle. When the GPU
	45	* writes vectors to the ring buffer, it increments the
	46	* wptr. When there is an interrupt, the host then starts
	47	* fetching commands and processing them until the pointers are
	48	* equal again at which point it updates the rptr.
	49	*/
	50
	51	static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	52
	53	/**
	54	* cz_ih_enable_interrupts - Enable the interrupt ring buffer
	55	*
	56	* @adev: amdgpu_device pointer
	57	*
	58	* Enable the interrupt ring buffer (VI).
	59	*/
	60	static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
	61	{
	62	u32 ih_cntl = RREG32(mmIH_CNTL);
	63	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	64
	65	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
	66	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	67	WREG32(mmIH_CNTL, ih_cntl);
	68	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	69	adev->irq.ih.enabled = true;
	70	}
	71
	72	/**
	73	* cz_ih_disable_interrupts - Disable the interrupt ring buffer
	74	*
	75	* @adev: amdgpu_device pointer
	76	*
	77	* Disable the interrupt ring buffer (VI).
	78	*/
	79	static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
	80	{
	81	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	82	u32 ih_cntl = RREG32(mmIH_CNTL);
	83
	84	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	85	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
	86	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	87	WREG32(mmIH_CNTL, ih_cntl);
	88	/* set rptr, wptr to 0 */
	89	WREG32(mmIH_RB_RPTR, 0);
90	WREG32(mmIH_RB_WPTR, 0);
91	adev->irq.ih.enabled = false;
92	adev->irq.ih.rptr = 0;
93	}
94
95	/**
96	* cz_ih_irq_init - init and enable the interrupt ring
97	*
98	* @adev: amdgpu_device pointer
99	*
100	* Allocate a ring buffer for the interrupt controller,
101	* enable the RLC, disable interrupts, enable the IH
102	* ring buffer and enable it (VI).
103	* Called at device load and reume.
104	* Returns 0 for success, errors for failure.
105	*/
106	static int cz_ih_irq_init(struct amdgpu_device *adev)
107	{
d81f78b4	108	struct amdgpu_ih_ring *ih = &adev->irq.ih;
aaa36a97	109	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
d81f78b4	110	int rb_bufsz;
aaa36a97 AD	111
	112	/* disable irqs */
	113	cz_ih_disable_interrupts(adev);
	114
	115	/* setup interrupt control */
92e71b06	116	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
aaa36a97 AD	117	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	118	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	119	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	120	*/
	121	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	122	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	123	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	124	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
	125
	126	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	127	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
	128
	129	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	130	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
	131	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	132	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	133
	134	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	135	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	136
	137	/* set the writeback address whether it's enabled or not */
d81f78b4 CK	138	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
d81f78b4 CK	139	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
aaa36a97 AD	140
	141	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	142
	143	/* set rptr, wptr to 0 */
	144	WREG32(mmIH_RB_RPTR, 0);
	145	WREG32(mmIH_RB_WPTR, 0);
	146
	147	/* Default settings for IH_CNTL (disabled at first) */
	148	ih_cntl = RREG32(mmIH_CNTL);
	149	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
	150
	151	if (adev->irq.msi_enabled)
	152	ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
	153	WREG32(mmIH_CNTL, ih_cntl);
	154
	155	pci_set_master(adev->pdev);
	156
	157	/* enable interrupts */
	158	cz_ih_enable_interrupts(adev);
	159
0e2b854e	160	return 0;
aaa36a97 AD	161	}
	162
	163	/**
	164	* cz_ih_irq_disable - disable interrupts
	165	*
	166	* @adev: amdgpu_device pointer
	167	*
	168	* Disable interrupts on the hw (VI).
	169	*/
	170	static void cz_ih_irq_disable(struct amdgpu_device *adev)
	171	{
	172	cz_ih_disable_interrupts(adev);
	173
	174	/* Wait and acknowledge irq */
	175	mdelay(1);
	176	}
	177
	178	/**
	179	* cz_ih_get_wptr - get the IH ring buffer wptr
	180	*
	181	* @adev: amdgpu_device pointer
a549a9da	182	* @ih: IH ring buffer to fetch wptr
aaa36a97 AD	183	*
	184	* Get the IH ring buffer wptr from either the register
	185	* or the writeback memory buffer (VI). Also check for
	186	* ring buffer overflow and deal with it.
	187	* Used by cz_irq_process(VI).
	188	* Returns the value of the wptr.
	189	*/
8bb9eb48 CK	190	static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
8bb9eb48 CK	191	struct amdgpu_ih_ring *ih)
aaa36a97 AD	192	{
	193	u32 wptr, tmp;
	194
d81f78b4	195	wptr = le32_to_cpu(*ih->wptr_cpu);
aaa36a97	196
e4180c42 DB	197	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
	198	goto out;
	199
	200	/* Double check that the overflow wasn't already cleared. */
	201	wptr = RREG32(mmIH_RB_WPTR);
	202
	203	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
	204	goto out;
	205
	206	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
	207
	208	/* When a ring buffer overflow happen start parsing interrupt
	209	* from the last not overwritten vector (wptr + 16). Hopefully
	210	* this should allow us to catchup.
	211	*/
	212	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
	213	wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
	214	ih->rptr = (wptr + 16) & ih->ptr_mask;
	215	tmp = RREG32(mmIH_RB_CNTL);
	216	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	217	WREG32(mmIH_RB_CNTL, tmp);
	218
9217b91c FV	219	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
	220	* can be detected.
	221	*/
	222	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
	223	WREG32(mmIH_RB_CNTL, tmp);
e4180c42 DB	224
e4180c42 DB	225	out:
8bb9eb48	226	return (wptr & ih->ptr_mask);
aaa36a97 AD	227	}
	228
	229	/**
	230	* cz_ih_decode_iv - decode an interrupt vector
	231	*
	232	* @adev: amdgpu_device pointer
a549a9da LJ	233	* @ih: IH ring buffer to decode
a549a9da LJ	234	* @entry: IV entry to place decoded information into
aaa36a97 AD	235	*
	236	* Decodes the interrupt vector at the current rptr
	237	* position and also advance the position.
	238	*/
	239	static void cz_ih_decode_iv(struct amdgpu_device *adev,
8bb9eb48 CK	240	struct amdgpu_ih_ring *ih,
8bb9eb48 CK	241	struct amdgpu_iv_entry *entry)
aaa36a97 AD	242	{
aaa36a97 AD	243	/* wptr/rptr are in bytes! */
8bb9eb48	244	u32 ring_index = ih->rptr >> 2;
aaa36a97	245	uint32_t dw[4];
edf600da	246
8bb9eb48 CK	247	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
	248	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
	249	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
	250	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
aaa36a97	251
1ffdeca6	252	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
aaa36a97	253	entry->src_id = dw[0] & 0xff;
7ccf5aa8	254	entry->src_data[0] = dw[1] & 0xfffffff;
aaa36a97	255	entry->ring_id = dw[2] & 0xff;
c4f46f22	256	entry->vmid = (dw[2] >> 8) & 0xff;
3816e42f	257	entry->pasid = (dw[2] >> 16) & 0xffff;
aaa36a97 AD	258
aaa36a97 AD	259	/* wptr/rptr are in bytes! */
8bb9eb48	260	ih->rptr += 16;
aaa36a97 AD	261	}
	262
	263	/**
	264	* cz_ih_set_rptr - set the IH ring buffer rptr
	265	*
	266	* @adev: amdgpu_device pointer
a549a9da	267	* @ih: IH ring buffer to set rptr
aaa36a97 AD	268	*
	269	* Set the IH ring buffer rptr.
	270	*/
8bb9eb48 CK	271	static void cz_ih_set_rptr(struct amdgpu_device *adev,
8bb9eb48 CK	272	struct amdgpu_ih_ring *ih)
aaa36a97	273	{
8bb9eb48	274	WREG32(mmIH_RB_RPTR, ih->rptr);
aaa36a97 AD	275	}
aaa36a97 AD	276
5fc3aeeb	277	static int cz_ih_early_init(void *handle)
aaa36a97	278	{
5fc3aeeb	279	struct amdgpu_device adev = (struct amdgpu_device )handle;
5f232365 AD	280	int ret;
	281
	282	ret = amdgpu_irq_add_domain(adev);
	283	if (ret)
	284	return ret;
5fc3aeeb	285
aaa36a97	286	cz_ih_set_interrupt_funcs(adev);
5f232365	287
aaa36a97 AD	288	return 0;
	289	}
	290
5fc3aeeb	291	static int cz_ih_sw_init(void *handle)
aaa36a97 AD	292	{
aaa36a97 AD	293	int r;
5fc3aeeb	294	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97	295
425c3143	296	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
aaa36a97 AD	297	if (r)
	298	return r;
	299
	300	r = amdgpu_irq_init(adev);
	301
	302	return r;
	303	}
	304
5fc3aeeb	305	static int cz_ih_sw_fini(void *handle)
aaa36a97	306	{
5fc3aeeb	307	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	308
72c8c97b	309	amdgpu_irq_fini_sw(adev);
5f232365	310	amdgpu_irq_remove_domain(adev);
aaa36a97 AD	311
	312	return 0;
	313	}
	314
5fc3aeeb	315	static int cz_ih_hw_init(void *handle)
aaa36a97 AD	316	{
aaa36a97 AD	317	int r;
5fc3aeeb	318	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	319
	320	r = cz_ih_irq_init(adev);
	321	if (r)
	322	return r;
	323
	324	return 0;
	325	}
	326
5fc3aeeb	327	static int cz_ih_hw_fini(void *handle)
aaa36a97	328	{
5fc3aeeb	329	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	330
aaa36a97 AD	331	cz_ih_irq_disable(adev);
	332
	333	return 0;
	334	}
	335
5fc3aeeb	336	static int cz_ih_suspend(void *handle)
aaa36a97	337	{
5fc3aeeb	338	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	339
aaa36a97 AD	340	return cz_ih_hw_fini(adev);
	341	}
	342
5fc3aeeb	343	static int cz_ih_resume(void *handle)
aaa36a97	344	{
5fc3aeeb	345	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	346
aaa36a97 AD	347	return cz_ih_hw_init(adev);
	348	}
	349
5fc3aeeb	350	static bool cz_ih_is_idle(void *handle)
aaa36a97	351	{
5fc3aeeb	352	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	353	u32 tmp = RREG32(mmSRBM_STATUS);
	354
	355	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	356	return false;
	357
	358	return true;
	359	}
	360
5fc3aeeb	361	static int cz_ih_wait_for_idle(void *handle)
aaa36a97 AD	362	{
	363	unsigned i;
	364	u32 tmp;
5fc3aeeb	365	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	366
	367	for (i = 0; i < adev->usec_timeout; i++) {
	368	/* read MC_STATUS */
	369	tmp = RREG32(mmSRBM_STATUS);
	370	if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	371	return 0;
	372	udelay(1);
	373	}
	374	return -ETIMEDOUT;
	375	}
	376
5fc3aeeb	377	static int cz_ih_soft_reset(void *handle)
aaa36a97 AD	378	{
aaa36a97 AD	379	u32 srbm_soft_reset = 0;
5fc3aeeb	380	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	381	u32 tmp = RREG32(mmSRBM_STATUS);
	382
	383	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	384	srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
	385	SOFT_RESET_IH, 1);
	386
	387	if (srbm_soft_reset) {
aaa36a97 AD	388	tmp = RREG32(mmSRBM_SOFT_RESET);
	389	tmp \|= srbm_soft_reset;
	390	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	391	WREG32(mmSRBM_SOFT_RESET, tmp);
	392	tmp = RREG32(mmSRBM_SOFT_RESET);
	393
	394	udelay(50);
	395
	396	tmp &= ~srbm_soft_reset;
	397	WREG32(mmSRBM_SOFT_RESET, tmp);
	398	tmp = RREG32(mmSRBM_SOFT_RESET);
	399
	400	/* Wait a little for things to settle down */
	401	udelay(50);
aaa36a97 AD	402	}
	403
	404	return 0;
	405	}
	406
5fc3aeeb	407	static int cz_ih_set_clockgating_state(void *handle,
5fc3aeeb	408	enum amd_clockgating_state state)
aaa36a97 AD	409	{
	410	// TODO
	411	return 0;
	412	}
	413
5fc3aeeb	414	static int cz_ih_set_powergating_state(void *handle,
5fc3aeeb	415	enum amd_powergating_state state)
aaa36a97 AD	416	{
	417	// TODO
	418	return 0;
	419	}
	420
a1255107	421	static const struct amd_ip_funcs cz_ih_ip_funcs = {
88a907d6	422	.name = "cz_ih",
aaa36a97 AD	423	.early_init = cz_ih_early_init,
	424	.late_init = NULL,
	425	.sw_init = cz_ih_sw_init,
	426	.sw_fini = cz_ih_sw_fini,
	427	.hw_init = cz_ih_hw_init,
	428	.hw_fini = cz_ih_hw_fini,
	429	.suspend = cz_ih_suspend,
	430	.resume = cz_ih_resume,
	431	.is_idle = cz_ih_is_idle,
	432	.wait_for_idle = cz_ih_wait_for_idle,
	433	.soft_reset = cz_ih_soft_reset,
aaa36a97 AD	434	.set_clockgating_state = cz_ih_set_clockgating_state,
	435	.set_powergating_state = cz_ih_set_powergating_state,
	436	};
	437
	438	static const struct amdgpu_ih_funcs cz_ih_funcs = {
	439	.get_wptr = cz_ih_get_wptr,
	440	.decode_iv = cz_ih_decode_iv,
	441	.set_rptr = cz_ih_set_rptr
	442	};
	443
	444	static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	445	{
f54b30d7	446	adev->irq.ih_funcs = &cz_ih_funcs;
aaa36a97 AD	447	}
aaa36a97 AD	448
a1255107 AD	449	const struct amdgpu_ip_block_version cz_ih_ip_block =
	450	{
	451	.type = AMD_IP_BLOCK_TYPE_IH,
	452	.major = 3,
	453	.minor = 0,
	454	.rev = 0,
	455	.funcs = &cz_ih_ip_funcs,
	456	};