[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / cik_ih.c

/*
 * Copyright 2012 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "drmP.h"
#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "cikd.h"

#include "bif/bif_4_1_d.h"
#include "bif/bif_4_1_sh_mask.h"

#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * cik_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (CIK).
 */
static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_cntl = RREG32(mmIH_CNTL);
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_cntl |= IH_CNTL__ENABLE_INTR_MASK;
	ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK;
	WREG32(mmIH_CNTL, ih_cntl);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * cik_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (CIK).
 */
static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	u32 ih_cntl = RREG32(mmIH_CNTL);

	ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
	ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	WREG32(mmIH_CNTL, ih_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * cik_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (CIK).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int cik_ih_irq_init(struct amdgpu_device *adev)
{
	int ret = 0;
	int rb_bufsz;
	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
	u64 wptr_off;

	/* disable irqs */
	cik_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);

	ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK |
		      IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK |
		      (rb_bufsz << 1));

	ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;

	/* set the writeback address whether it's enabled or not */
	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	/* Default settings for IH_CNTL (disabled at first) */
	ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) |
		(0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) |
		(0 << IH_CNTL__MC_VMID__SHIFT);
	/* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
	if (adev->irq.msi_enabled)
		ih_cntl |= IH_CNTL__RPTR_REARM_MASK;
	WREG32(mmIH_CNTL, ih_cntl);

	pci_set_master(adev->pdev);

	/* enable irqs */
	cik_ih_enable_interrupts(adev);

	return ret;
}

/**
 * cik_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (CIK).
 */
static void cik_ih_irq_disable(struct amdgpu_device *adev)
{
	cik_ih_disable_interrupts(adev);
	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * cik_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (CIK).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cik_irq_process().
 * Returns the value of the wptr.
 */
static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
{
	u32 wptr, tmp;

	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);

	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
		wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
		/* When a ring buffer overflow happen start parsing interrupt
		 * from the last not overwritten vector (wptr + 16). Hopefully
		 * this should allow us to catchup.
		 */
		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
		tmp = RREG32(mmIH_RB_CNTL);
		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
		WREG32(mmIH_RB_CNTL, tmp);
	}
	return (wptr & adev->irq.ih.ptr_mask);
}

/*        CIK IV Ring
 * Each IV ring entry is 128 bits:
 * [7:0]    - interrupt source id
 * [31:8]   - reserved
 * [59:32]  - interrupt source data
 * [63:60]  - reserved
 * [71:64]  - RINGID
 *            CP:
 *            ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
 *            QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
 *                     - for gfx, hw shader state (0=PS...5=LS, 6=CS)
 *            ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
 *            PIPE_ID - ME0 0=3D
 *                    - ME1&2 compute dispatcher (4 pipes each)
 *            SDMA:
 *            INSTANCE_ID [1:0], QUEUE_ID[1:0]
 *            INSTANCE_ID - 0 = sdma0, 1 = sdma1
 *            QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
 * [79:72]  - VMID
 * [95:80]  - PASID
 * [127:96] - reserved
 */

 /**
 * cik_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void cik_ih_decode_iv(struct amdgpu_device *adev,
			     struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = adev->irq.ih.rptr >> 2;
	uint32_t dw[4];
	
	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);

	entry->src_id = dw[0] & 0xff;
	entry->src_data = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vm_id = (dw[2] >> 8) & 0xff;
	entry->pas_id = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	adev->irq.ih.rptr += 16;
}

/**
 * cik_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 *
 * Set the IH ring buffer rptr.
 */
static void cik_ih_set_rptr(struct amdgpu_device *adev)
{
	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}

static int cik_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	ret = amdgpu_irq_add_domain(adev);
	if (ret)
		return ret;

	cik_ih_set_interrupt_funcs(adev);

	return 0;
}

static int cik_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
	if (r)
		return r;

	r = amdgpu_irq_init(adev);

	return r;
}

static int cik_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini(adev);
	amdgpu_ih_ring_fini(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}

static int cik_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = cik_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int cik_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	cik_ih_irq_disable(adev);

	return 0;
}

static int cik_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return cik_ih_hw_fini(adev);
}

static int cik_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return cik_ih_hw_init(adev);
}

static bool cik_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		return false;

	return true;
}

static int cik_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
		if (!tmp)
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static void cik_ih_print_status(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	dev_info(adev->dev, "CIK IH registers\n");
	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
		RREG32(mmSRBM_STATUS));
	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
		RREG32(mmSRBM_STATUS2));
	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",
		 RREG32(mmINTERRUPT_CNTL));
	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",
		 RREG32(mmINTERRUPT_CNTL2));
	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",
		 RREG32(mmIH_CNTL));
	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",
		 RREG32(mmIH_RB_CNTL));
	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",
		 RREG32(mmIH_RB_BASE));
	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",
		 RREG32(mmIH_RB_WPTR_ADDR_LO));
	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",
		 RREG32(mmIH_RB_WPTR_ADDR_HI));
	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",
		 RREG32(mmIH_RB_RPTR));
	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",
		 RREG32(mmIH_RB_WPTR));
}

static int cik_ih_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	u32 srbm_soft_reset = 0;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;

	if (srbm_soft_reset) {
		cik_ih_print_status((void *)adev);

		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);

		cik_ih_print_status((void *)adev);
	}

	return 0;
}

static int cik_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int cik_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

const struct amd_ip_funcs cik_ih_ip_funcs = {
	.early_init = cik_ih_early_init,
	.late_init = NULL,
	.sw_init = cik_ih_sw_init,
	.sw_fini = cik_ih_sw_fini,
	.hw_init = cik_ih_hw_init,
	.hw_fini = cik_ih_hw_fini,
	.suspend = cik_ih_suspend,
	.resume = cik_ih_resume,
	.is_idle = cik_ih_is_idle,
	.wait_for_idle = cik_ih_wait_for_idle,
	.soft_reset = cik_ih_soft_reset,
	.print_status = cik_ih_print_status,
	.set_clockgating_state = cik_ih_set_clockgating_state,
	.set_powergating_state = cik_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs cik_ih_funcs = {
	.get_wptr = cik_ih_get_wptr,
	.decode_iv = cik_ih_decode_iv,
	.set_rptr = cik_ih_set_rptr
};

static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	if (adev->irq.ih_funcs == NULL)
		adev->irq.ih_funcs = &cik_ih_funcs;
}
Commit	Line	Data
a2e73f56 AD	1	/*
	2	* Copyright 2012 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "drmP.h"
	24	#include "amdgpu.h"
	25	#include "amdgpu_ih.h"
	26	#include "cikd.h"
	27
	28	#include "bif/bif_4_1_d.h"
	29	#include "bif/bif_4_1_sh_mask.h"
	30
	31	#include "oss/oss_2_0_d.h"
	32	#include "oss/oss_2_0_sh_mask.h"
	33
	34	/*
	35	* Interrupts
	36	* Starting with r6xx, interrupts are handled via a ring buffer.
	37	* Ring buffers are areas of GPU accessible memory that the GPU
	38	* writes interrupt vectors into and the host reads vectors out of.
	39	* There is a rptr (read pointer) that determines where the
	40	* host is currently reading, and a wptr (write pointer)
	41	* which determines where the GPU has written. When the
	42	* pointers are equal, the ring is idle. When the GPU
	43	* writes vectors to the ring buffer, it increments the
	44	* wptr. When there is an interrupt, the host then starts
	45	* fetching commands and processing them until the pointers are
	46	* equal again at which point it updates the rptr.
	47	*/
	48
	49	static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	50
	51	/**
	52	* cik_ih_enable_interrupts - Enable the interrupt ring buffer
	53	*
	54	* @adev: amdgpu_device pointer
	55	*
	56	* Enable the interrupt ring buffer (CIK).
	57	*/
	58	static void cik_ih_enable_interrupts(struct amdgpu_device *adev)
	59	{
	60	u32 ih_cntl = RREG32(mmIH_CNTL);
	61	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	62
	63	ih_cntl \|= IH_CNTL__ENABLE_INTR_MASK;
	64	ih_rb_cntl \|= IH_RB_CNTL__RB_ENABLE_MASK;
65	WREG32(mmIH_CNTL, ih_cntl);
66	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
67	adev->irq.ih.enabled = true;
68	}
69
70	/**
71	* cik_ih_disable_interrupts - Disable the interrupt ring buffer
72	*
73	* @adev: amdgpu_device pointer
74	*
75	* Disable the interrupt ring buffer (CIK).
76	*/
77	static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
78	{
79	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
80	u32 ih_cntl = RREG32(mmIH_CNTL);
81
82	ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK;
83	ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK;
84	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
85	WREG32(mmIH_CNTL, ih_cntl);
86	/* set rptr, wptr to 0 */
87	WREG32(mmIH_RB_RPTR, 0);
88	WREG32(mmIH_RB_WPTR, 0);
89	adev->irq.ih.enabled = false;
90	adev->irq.ih.rptr = 0;
91	}
92
93	/**
94	* cik_ih_irq_init - init and enable the interrupt ring
95	*
96	* @adev: amdgpu_device pointer
97	*
98	* Allocate a ring buffer for the interrupt controller,
99	* enable the RLC, disable interrupts, enable the IH
100	* ring buffer and enable it (CIK).
101	* Called at device load and reume.
102	* Returns 0 for success, errors for failure.
103	*/
104	static int cik_ih_irq_init(struct amdgpu_device *adev)
105	{
106	int ret = 0;
107	int rb_bufsz;
108	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
109	u64 wptr_off;
110
111	/* disable irqs */
112	cik_ih_disable_interrupts(adev);
113
114	/* setup interrupt control */
115	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
116	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
117	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
118	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
119	*/
120	interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK;
121	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
122	interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK;
123	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
124
125	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
126	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
127
128	ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK \|
129	IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK \|
130	(rb_bufsz << 1));
131
132	ih_rb_cntl \|= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
133
134	/* set the writeback address whether it's enabled or not */
135	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
136	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
137	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
138
139	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
140
141	/* set rptr, wptr to 0 */
142	WREG32(mmIH_RB_RPTR, 0);
143	WREG32(mmIH_RB_WPTR, 0);
144
145	/* Default settings for IH_CNTL (disabled at first) */
146	ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) \|
147	(0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) \|
148	(0 << IH_CNTL__MC_VMID__SHIFT);
149	/* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
150	if (adev->irq.msi_enabled)
151	ih_cntl \|= IH_CNTL__RPTR_REARM_MASK;
152	WREG32(mmIH_CNTL, ih_cntl);
153
154	pci_set_master(adev->pdev);
155
156	/* enable irqs */
157	cik_ih_enable_interrupts(adev);
158
159	return ret;
160	}
161
162	/**
163	* cik_ih_irq_disable - disable interrupts
164	*
165	* @adev: amdgpu_device pointer
166	*
167	* Disable interrupts on the hw (CIK).
168	*/
169	static void cik_ih_irq_disable(struct amdgpu_device *adev)
170	{
171	cik_ih_disable_interrupts(adev);
172	/* Wait and acknowledge irq */
173	mdelay(1);
174	}
175
176	/**
177	* cik_ih_get_wptr - get the IH ring buffer wptr
178	*
179	* @adev: amdgpu_device pointer
180	*
181	* Get the IH ring buffer wptr from either the register
182	* or the writeback memory buffer (CIK). Also check for
183	* ring buffer overflow and deal with it.
184	* Used by cik_irq_process().
185	* Returns the value of the wptr.
186	*/
187	static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
188	{
189	u32 wptr, tmp;
190
191	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
192
193	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
194	wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
195	/* When a ring buffer overflow happen start parsing interrupt
196	* from the last not overwritten vector (wptr + 16). Hopefully
197	* this should allow us to catchup.
198	*/
199	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
200	wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
201	adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
202	tmp = RREG32(mmIH_RB_CNTL);
203	tmp \|= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
204	WREG32(mmIH_RB_CNTL, tmp);
205	}
206	return (wptr & adev->irq.ih.ptr_mask);
207	}
208
209	/* CIK IV Ring
210	* Each IV ring entry is 128 bits:
211	* [7:0] - interrupt source id
212	* [31:8] - reserved
213	* [59:32] - interrupt source data
214	* [63:60] - reserved
215	* [71:64] - RINGID
216	* CP:
217	* ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
218	* QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
219	* - for gfx, hw shader state (0=PS...5=LS, 6=CS)
220	* ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
221	* PIPE_ID - ME0 0=3D
222	* - ME1&2 compute dispatcher (4 pipes each)
223	* SDMA:
224	* INSTANCE_ID [1:0], QUEUE_ID[1:0]
225	* INSTANCE_ID - 0 = sdma0, 1 = sdma1
226	* QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
227	* [79:72] - VMID
228	* [95:80] - PASID
229	* [127:96] - reserved
230	*/
231
232	/**
233	* cik_ih_decode_iv - decode an interrupt vector
234	*
235	* @adev: amdgpu_device pointer
236	*
237	* Decodes the interrupt vector at the current rptr
238	* position and also advance the position.
239	*/
240	static void cik_ih_decode_iv(struct amdgpu_device *adev,
241	struct amdgpu_iv_entry *entry)
242	{
243	/* wptr/rptr are in bytes! */
244	u32 ring_index = adev->irq.ih.rptr >> 2;
245	uint32_t dw[4];
246
247	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
248	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
249	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
250	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
251
252	entry->src_id = dw[0] & 0xff;
253	entry->src_data = dw[1] & 0xfffffff;
254	entry->ring_id = dw[2] & 0xff;
255	entry->vm_id = (dw[2] >> 8) & 0xff;
256	entry->pas_id = (dw[2] >> 16) & 0xffff;
257
258	/* wptr/rptr are in bytes! */
259	adev->irq.ih.rptr += 16;
260	}
261
262	/**
263	* cik_ih_set_rptr - set the IH ring buffer rptr
264	*
265	* @adev: amdgpu_device pointer
266	*
267	* Set the IH ring buffer rptr.
268	*/
269	static void cik_ih_set_rptr(struct amdgpu_device *adev)
270	{
271	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
272	}
273
5fc3aeeb	274	static int cik_ih_early_init(void *handle)
a2e73f56	275	{
5fc3aeeb	276	struct amdgpu_device adev = (struct amdgpu_device )handle;
5f232365 AD	277	int ret;
	278
	279	ret = amdgpu_irq_add_domain(adev);
	280	if (ret)
	281	return ret;
5fc3aeeb	282
a2e73f56 AD	283	cik_ih_set_interrupt_funcs(adev);
	284
	285	return 0;
	286	}
	287
5fc3aeeb	288	static int cik_ih_sw_init(void *handle)
a2e73f56 AD	289	{
a2e73f56 AD	290	int r;
5fc3aeeb	291	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	292
	293	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
	294	if (r)
	295	return r;
	296
	297	r = amdgpu_irq_init(adev);
	298
	299	return r;
	300	}
	301
5fc3aeeb	302	static int cik_ih_sw_fini(void *handle)
a2e73f56	303	{
5fc3aeeb	304	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	305
a2e73f56 AD	306	amdgpu_irq_fini(adev);
a2e73f56 AD	307	amdgpu_ih_ring_fini(adev);
5f232365	308	amdgpu_irq_remove_domain(adev);
a2e73f56 AD	309
	310	return 0;
	311	}
	312
5fc3aeeb	313	static int cik_ih_hw_init(void *handle)
a2e73f56 AD	314	{
a2e73f56 AD	315	int r;
5fc3aeeb	316	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	317
	318	r = cik_ih_irq_init(adev);
	319	if (r)
	320	return r;
	321
	322	return 0;
	323	}
	324
5fc3aeeb	325	static int cik_ih_hw_fini(void *handle)
a2e73f56	326	{
5fc3aeeb	327	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	328
a2e73f56 AD	329	cik_ih_irq_disable(adev);
	330
	331	return 0;
	332	}
	333
5fc3aeeb	334	static int cik_ih_suspend(void *handle)
a2e73f56	335	{
5fc3aeeb	336	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	337
a2e73f56 AD	338	return cik_ih_hw_fini(adev);
	339	}
	340
5fc3aeeb	341	static int cik_ih_resume(void *handle)
a2e73f56	342	{
5fc3aeeb	343	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	344
a2e73f56 AD	345	return cik_ih_hw_init(adev);
	346	}
	347
5fc3aeeb	348	static bool cik_ih_is_idle(void *handle)
a2e73f56	349	{
5fc3aeeb	350	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	351	u32 tmp = RREG32(mmSRBM_STATUS);
	352
	353	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	354	return false;
	355
	356	return true;
	357	}
	358
5fc3aeeb	359	static int cik_ih_wait_for_idle(void *handle)
a2e73f56 AD	360	{
	361	unsigned i;
	362	u32 tmp;
5fc3aeeb	363	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	364
	365	for (i = 0; i < adev->usec_timeout; i++) {
	366	/* read MC_STATUS */
	367	tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
	368	if (!tmp)
	369	return 0;
	370	udelay(1);
	371	}
	372	return -ETIMEDOUT;
	373	}
	374
5fc3aeeb	375	static void cik_ih_print_status(void *handle)
a2e73f56	376	{
5fc3aeeb	377	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	378
a2e73f56 AD	379	dev_info(adev->dev, "CIK IH registers\n");
	380	dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
	381	RREG32(mmSRBM_STATUS));
	382	dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
	383	RREG32(mmSRBM_STATUS2));
	384	dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
	385	RREG32(mmINTERRUPT_CNTL));
	386	dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
	387	RREG32(mmINTERRUPT_CNTL2));
	388	dev_info(adev->dev, " IH_CNTL=0x%08X\n",
	389	RREG32(mmIH_CNTL));
	390	dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
	391	RREG32(mmIH_RB_CNTL));
	392	dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
	393	RREG32(mmIH_RB_BASE));
	394	dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
	395	RREG32(mmIH_RB_WPTR_ADDR_LO));
	396	dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
	397	RREG32(mmIH_RB_WPTR_ADDR_HI));
	398	dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
	399	RREG32(mmIH_RB_RPTR));
	400	dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
	401	RREG32(mmIH_RB_WPTR));
	402	}
	403
5fc3aeeb	404	static int cik_ih_soft_reset(void *handle)
a2e73f56	405	{
5fc3aeeb	406	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	407
a2e73f56 AD	408	u32 srbm_soft_reset = 0;
	409	u32 tmp = RREG32(mmSRBM_STATUS);
	410
	411	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	412	srbm_soft_reset \|= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
	413
	414	if (srbm_soft_reset) {
5fc3aeeb	415	cik_ih_print_status((void *)adev);
a2e73f56 AD	416
	417	tmp = RREG32(mmSRBM_SOFT_RESET);
	418	tmp \|= srbm_soft_reset;
	419	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	420	WREG32(mmSRBM_SOFT_RESET, tmp);
	421	tmp = RREG32(mmSRBM_SOFT_RESET);
	422
	423	udelay(50);
	424
	425	tmp &= ~srbm_soft_reset;
	426	WREG32(mmSRBM_SOFT_RESET, tmp);
	427	tmp = RREG32(mmSRBM_SOFT_RESET);
	428
	429	/* Wait a little for things to settle down */
	430	udelay(50);
	431
5fc3aeeb	432	cik_ih_print_status((void *)adev);
a2e73f56 AD	433	}
	434
	435	return 0;
	436	}
	437
5fc3aeeb	438	static int cik_ih_set_clockgating_state(void *handle,
5fc3aeeb	439	enum amd_clockgating_state state)
a2e73f56 AD	440	{
	441	return 0;
	442	}
	443
5fc3aeeb	444	static int cik_ih_set_powergating_state(void *handle,
5fc3aeeb	445	enum amd_powergating_state state)
a2e73f56 AD	446	{
	447	return 0;
	448	}
	449
5fc3aeeb	450	const struct amd_ip_funcs cik_ih_ip_funcs = {
a2e73f56 AD	451	.early_init = cik_ih_early_init,
	452	.late_init = NULL,
	453	.sw_init = cik_ih_sw_init,
	454	.sw_fini = cik_ih_sw_fini,
	455	.hw_init = cik_ih_hw_init,
	456	.hw_fini = cik_ih_hw_fini,
	457	.suspend = cik_ih_suspend,
	458	.resume = cik_ih_resume,
	459	.is_idle = cik_ih_is_idle,
	460	.wait_for_idle = cik_ih_wait_for_idle,
	461	.soft_reset = cik_ih_soft_reset,
	462	.print_status = cik_ih_print_status,
	463	.set_clockgating_state = cik_ih_set_clockgating_state,
	464	.set_powergating_state = cik_ih_set_powergating_state,
	465	};
	466
	467	static const struct amdgpu_ih_funcs cik_ih_funcs = {
	468	.get_wptr = cik_ih_get_wptr,
	469	.decode_iv = cik_ih_decode_iv,
	470	.set_rptr = cik_ih_set_rptr
	471	};
	472
	473	static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	474	{
	475	if (adev->irq.ih_funcs == NULL)
	476	adev->irq.ih_funcs = &cik_ih_funcs;
	477	}