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Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / atombios_dp.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#include <drm/drmP.h>
28#include <drm/amdgpu_drm.h>
29#include "amdgpu.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include "atombios_encoders.h"
34#include "atombios_dp.h"
35#include "amdgpu_connectors.h"
36#include "amdgpu_atombios.h"
37#include <drm/drm_dp_helper.h>
38
39/* move these to drm_dp_helper.c/h */
40#define DP_LINK_CONFIGURATION_SIZE 9
41#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
42
43static char *voltage_names[] = {
44 "0.4V", "0.6V", "0.8V", "1.2V"
45};
46static char *pre_emph_names[] = {
47 "0dB", "3.5dB", "6dB", "9.5dB"
48};
49
50/***** amdgpu AUX functions *****/
51
52union aux_channel_transaction {
53 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
54 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
55};
56
57static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
58 u8 *send, int send_bytes,
59 u8 *recv, int recv_size,
60 u8 delay, u8 *ack)
61{
62 struct drm_device *dev = chan->dev;
63 struct amdgpu_device *adev = dev->dev_private;
64 union aux_channel_transaction args;
65 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
66 unsigned char *base;
67 int recv_bytes;
68 int r = 0;
69
70 memset(&args, 0, sizeof(args));
71
72 mutex_lock(&chan->mutex);
73
74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
75
76 amdgpu_atombios_copy_swap(base, send, send_bytes, true);
77
78 args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
79 args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
80 args.v2.ucDataOutLen = 0;
81 args.v2.ucChannelID = chan->rec.i2c_id;
82 args.v2.ucDelay = delay / 10;
83 args.v2.ucHPD_ID = chan->rec.hpd;
84
85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
86
87 *ack = args.v2.ucReplyStatus;
88
89 /* timeout */
90 if (args.v2.ucReplyStatus == 1) {
91 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
92 r = -ETIMEDOUT;
93 goto done;
94 }
95
96 /* flags not zero */
97 if (args.v2.ucReplyStatus == 2) {
98 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
99 r = -EIO;
100 goto done;
101 }
102
103 /* error */
104 if (args.v2.ucReplyStatus == 3) {
105 DRM_DEBUG_KMS("dp_aux_ch error\n");
106 r = -EIO;
107 goto done;
108 }
109
110 recv_bytes = args.v1.ucDataOutLen;
111 if (recv_bytes > recv_size)
112 recv_bytes = recv_size;
113
114 if (recv && recv_size)
115 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
116
117 r = recv_bytes;
118done:
119 mutex_unlock(&chan->mutex);
120
121 return r;
122}
123
124#define BARE_ADDRESS_SIZE 3
125#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
126
127static ssize_t
128amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
129{
130 struct amdgpu_i2c_chan *chan =
131 container_of(aux, struct amdgpu_i2c_chan, aux);
132 int ret;
133 u8 tx_buf[20];
134 size_t tx_size;
135 u8 ack, delay = 0;
136
137 if (WARN_ON(msg->size > 16))
138 return -E2BIG;
139
140 tx_buf[0] = msg->address & 0xff;
141 tx_buf[1] = msg->address >> 8;
e39daf2c
AD		 142 tx_buf[2] = (msg->request << 4) |
143 ((msg->address >> 16) & 0xf);
d38ceaf9
AD		 144 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
145
146 switch (msg->request & ~DP_AUX_I2C_MOT) {
147 case DP_AUX_NATIVE_WRITE:
148 case DP_AUX_I2C_WRITE:
149 /* tx_size needs to be 4 even for bare address packets since the atom
150 * table needs the info in tx_buf[3].
151 */
152 tx_size = HEADER_SIZE + msg->size;
153 if (msg->size == 0)
154 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
155 else
156 tx_buf[3] |= tx_size << 4;
157 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
158 ret = amdgpu_atombios_dp_process_aux_ch(chan,
159 tx_buf, tx_size, NULL, 0, delay, &ack);
160 if (ret >= 0)
161 /* Return payload size. */
162 ret = msg->size;
163 break;
164 case DP_AUX_NATIVE_READ:
165 case DP_AUX_I2C_READ:
166 /* tx_size needs to be 4 even for bare address packets since the atom
167 * table needs the info in tx_buf[3].
168 */
169 tx_size = HEADER_SIZE;
170 if (msg->size == 0)
171 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
172 else
173 tx_buf[3] |= tx_size << 4;
174 ret = amdgpu_atombios_dp_process_aux_ch(chan,
175 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
176 break;
177 default:
178 ret = -EINVAL;
179 break;
180 }
181
182 if (ret >= 0)
183 msg->reply = ack >> 4;
184
185 return ret;
186}
187
188void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
189{
190 int ret;
191
192 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
193 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
194 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
195 ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
196 if (!ret)
197 amdgpu_connector->ddc_bus->has_aux = true;
198
199 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
200}
201
202/***** general DP utility functions *****/
203
204#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
205#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
206
dc5f428d
AD		 207static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
208 int lane_count,
209 u8 train_set[4])
d38ceaf9
AD		 210{
211 u8 v = 0;
212 u8 p = 0;
213 int lane;
214
215 for (lane = 0; lane < lane_count; lane++) {
216 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
217 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
218
219 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
220 lane,
221 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
222 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
223
224 if (this_v > v)
225 v = this_v;
226 if (this_p > p)
227 p = this_p;
228 }
229
230 if (v >= DP_VOLTAGE_MAX)
231 v |= DP_TRAIN_MAX_SWING_REACHED;
232
233 if (p >= DP_PRE_EMPHASIS_MAX)
234 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
235
236 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
237 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
238 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
239
240 for (lane = 0; lane < 4; lane++)
241 train_set[lane] = v | p;
242}
243
244/* convert bits per color to bits per pixel */
245/* get bpc from the EDID */
41869c1c 246static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
d38ceaf9
AD		 247{
248 if (bpc == 0)
249 return 24;
250 else
251 return bpc * 3;
252}
253
d38ceaf9
AD		 254/***** amdgpu specific DP functions *****/
255
41869c1c 256static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
dc5f428d 257 const u8 dpcd[DP_DPCD_SIZE],
41869c1c
AD		 258 unsigned pix_clock,
259 unsigned *dp_lanes, unsigned *dp_rate)
d38ceaf9 260{
41869c1c
AD		 261 unsigned bpp =
262 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
263 static const unsigned link_rates[3] = { 162000, 270000, 540000 };
264 unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
265 unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
266 unsigned lane_num, i, max_pix_clock;
267
02d27234
AD		 268 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
269 ENCODER_OBJECT_ID_NUTMEG) {
270 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
271 max_pix_clock = (lane_num * 270000 * 8) / bpp;
41869c1c
AD		 272 if (max_pix_clock >= pix_clock) {
273 *dp_lanes = lane_num;
02d27234 274 *dp_rate = 270000;
41869c1c
AD		 275 return 0;
276 }
277 }
02d27234 278 } else {
c47b9e09
AD		 279 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
280 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
02d27234
AD		 281 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
282 if (max_pix_clock >= pix_clock) {
283 *dp_lanes = lane_num;
284 *dp_rate = link_rates[i];
285 return 0;
286 }
287 }
288 }
d38ceaf9
AD		 289 }
290
41869c1c 291 return -EINVAL;
d38ceaf9
AD		 292}
293
294static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
295 int action, int dp_clock,
296 u8 ucconfig, u8 lane_num)
297{
298 DP_ENCODER_SERVICE_PARAMETERS args;
299 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
300
301 memset(&args, 0, sizeof(args));
302 args.ucLinkClock = dp_clock / 10;
303 args.ucConfig = ucconfig;
304 args.ucAction = action;
305 args.ucLaneNum = lane_num;
306 args.ucStatus = 0;
307
308 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
309 return args.ucStatus;
310}
311
312u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
313{
314 struct drm_device *dev = amdgpu_connector->base.dev;
315 struct amdgpu_device *adev = dev->dev_private;
316
317 return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
318 amdgpu_connector->ddc_bus->rec.i2c_id, 0);
319}
320
321static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
322{
323 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
324 u8 buf[3];
325
326 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
327 return;
328
329 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
330 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
331 buf[0], buf[1], buf[2]);
332
333 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
334 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
335 buf[0], buf[1], buf[2]);
336}
337
338int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
339{
340 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
341 u8 msg[DP_DPCD_SIZE];
67ed0092 342 int ret, i;
d38ceaf9 343
67ed0092
AD		 344 for (i = 0; i < 7; i++) {
345 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg,
346 DP_DPCD_SIZE);
347 if (ret == DP_DPCD_SIZE) {
348 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
7af93b50 349
67ed0092
AD		 350 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
351 dig_connector->dpcd);
d38ceaf9 352
67ed0092 353 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
d38ceaf9 354
67ed0092
AD		 355 return 0;
356 }
d38ceaf9
AD		 357 }
358 dig_connector->dpcd[0] = 0;
359 return -EINVAL;
360}
361
362int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
363 struct drm_connector *connector)
364{
365 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
366 struct amdgpu_connector_atom_dig *dig_connector;
367 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
368 u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
369 u8 tmp;
370
371 if (!amdgpu_connector->con_priv)
372 return panel_mode;
373
374 dig_connector = amdgpu_connector->con_priv;
375
376 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
377 /* DP bridge chips */
378 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
379 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
380 if (tmp & 1)
381 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
382 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
383 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
384 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
385 else
386 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
387 }
388 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
389 /* eDP */
390 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
391 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
392 if (tmp & 1)
393 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
394 }
395 }
396
397 return panel_mode;
398}
399
400void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
401 const struct drm_display_mode *mode)
402{
403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
404 struct amdgpu_connector_atom_dig *dig_connector;
41869c1c 405 int ret;
d38ceaf9
AD		 406
407 if (!amdgpu_connector->con_priv)
408 return;
409 dig_connector = amdgpu_connector->con_priv;
410
411 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
412 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
41869c1c
AD		 413 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
414 mode->clock,
415 &dig_connector->dp_lane_count,
416 &dig_connector->dp_clock);
417 if (ret) {
418 dig_connector->dp_clock = 0;
419 dig_connector->dp_lane_count = 0;
420 }
d38ceaf9
AD		 421 }
422}
423
424int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
425 struct drm_display_mode *mode)
426{
427 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
428 struct amdgpu_connector_atom_dig *dig_connector;
41869c1c
AD		 429 unsigned dp_lanes, dp_clock;
430 int ret;
d38ceaf9
AD		 431
432 if (!amdgpu_connector->con_priv)
433 return MODE_CLOCK_HIGH;
434 dig_connector = amdgpu_connector->con_priv;
435
41869c1c
AD		 436 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
437 mode->clock, &dp_lanes, &dp_clock);
438 if (ret)
439 return MODE_CLOCK_HIGH;
d38ceaf9
AD		 440
441 if ((dp_clock == 540000) &&
442 (!amdgpu_connector_is_dp12_capable(connector)))
443 return MODE_CLOCK_HIGH;
444
445 return MODE_OK;
446}
447
448bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
449{
450 u8 link_status[DP_LINK_STATUS_SIZE];
451 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
452
453 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
454 <= 0)
455 return false;
456 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
457 return false;
458 return true;
459}
460
461void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
462 u8 power_state)
463{
464 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
465 struct amdgpu_connector_atom_dig *dig_connector;
466
467 if (!amdgpu_connector->con_priv)
468 return;
469
470 dig_connector = amdgpu_connector->con_priv;
471
472 /* power up/down the sink */
473 if (dig_connector->dpcd[0] >= 0x11) {
474 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
475 DP_SET_POWER, power_state);
476 usleep_range(1000, 2000);
477 }
478}
479
480struct amdgpu_atombios_dp_link_train_info {
481 struct amdgpu_device *adev;
482 struct drm_encoder *encoder;
483 struct drm_connector *connector;
484 int dp_clock;
485 int dp_lane_count;
486 bool tp3_supported;
487 u8 dpcd[DP_RECEIVER_CAP_SIZE];
488 u8 train_set[4];
489 u8 link_status[DP_LINK_STATUS_SIZE];
490 u8 tries;
491 struct drm_dp_aux *aux;
492};
493
494static void
495amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
496{
497 /* set the initial vs/emph on the source */
498 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
499 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
500 0, dp_info->train_set[0]); /* sets all lanes at once */
501
502 /* set the vs/emph on the sink */
503 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
504 dp_info->train_set, dp_info->dp_lane_count);
505}
506
507static void
508amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
509{
510 int rtp = 0;
511
512 /* set training pattern on the source */
513 switch (tp) {
514 case DP_TRAINING_PATTERN_1:
515 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
516 break;
517 case DP_TRAINING_PATTERN_2:
518 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
519 break;
520 case DP_TRAINING_PATTERN_3:
521 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
522 break;
523 }
524 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
525
526 /* enable training pattern on the sink */
527 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
528}
529
530static int
531amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
532{
533 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
534 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
535 u8 tmp;
536
537 /* power up the sink */
538 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
539
540 /* possibly enable downspread on the sink */
541 if (dp_info->dpcd[3] & 0x1)
542 drm_dp_dpcd_writeb(dp_info->aux,
543 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
544 else
545 drm_dp_dpcd_writeb(dp_info->aux,
546 DP_DOWNSPREAD_CTRL, 0);
547
548 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
549 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
550
551 /* set the lane count on the sink */
552 tmp = dp_info->dp_lane_count;
553 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
554 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
555 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
556
557 /* set the link rate on the sink */
558 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
559 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
560
561 /* start training on the source */
562 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
563 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
564
565 /* disable the training pattern on the sink */
566 drm_dp_dpcd_writeb(dp_info->aux,
567 DP_TRAINING_PATTERN_SET,
568 DP_TRAINING_PATTERN_DISABLE);
569
570 return 0;
571}
572
573static int
574amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
575{
576 udelay(400);
577
578 /* disable the training pattern on the sink */
579 drm_dp_dpcd_writeb(dp_info->aux,
580 DP_TRAINING_PATTERN_SET,
581 DP_TRAINING_PATTERN_DISABLE);
582
583 /* disable the training pattern on the source */
584 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
585 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
586
587 return 0;
588}
589
590static int
591amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
592{
593 bool clock_recovery;
594 u8 voltage;
595 int i;
596
597 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
598 memset(dp_info->train_set, 0, 4);
599 amdgpu_atombios_dp_update_vs_emph(dp_info);
600
601 udelay(400);
602
603 /* clock recovery loop */
604 clock_recovery = false;
605 dp_info->tries = 0;
606 voltage = 0xff;
607 while (1) {
608 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
609
610 if (drm_dp_dpcd_read_link_status(dp_info->aux,
611 dp_info->link_status) <= 0) {
612 DRM_ERROR("displayport link status failed\n");
613 break;
614 }
615
616 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
617 clock_recovery = true;
618 break;
619 }
620
621 for (i = 0; i < dp_info->dp_lane_count; i++) {
622 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
623 break;
624 }
625 if (i == dp_info->dp_lane_count) {
626 DRM_ERROR("clock recovery reached max voltage\n");
627 break;
628 }
629
630 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
631 ++dp_info->tries;
632 if (dp_info->tries == 5) {
633 DRM_ERROR("clock recovery tried 5 times\n");
634 break;
635 }
636 } else
637 dp_info->tries = 0;
638
639 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
640
641 /* Compute new train_set as requested by sink */
642 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
643 dp_info->train_set);
644
645 amdgpu_atombios_dp_update_vs_emph(dp_info);
646 }
647 if (!clock_recovery) {
648 DRM_ERROR("clock recovery failed\n");
649 return -1;
650 } else {
651 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
652 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
653 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
654 DP_TRAIN_PRE_EMPHASIS_SHIFT);
655 return 0;
656 }
657}
658
659static int
660amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
661{
662 bool channel_eq;
663
664 if (dp_info->tp3_supported)
665 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
666 else
667 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
668
669 /* channel equalization loop */
670 dp_info->tries = 0;
671 channel_eq = false;
672 while (1) {
673 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
674
675 if (drm_dp_dpcd_read_link_status(dp_info->aux,
676 dp_info->link_status) <= 0) {
677 DRM_ERROR("displayport link status failed\n");
678 break;
679 }
680
681 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
682 channel_eq = true;
683 break;
684 }
685
686 /* Try 5 times */
687 if (dp_info->tries > 5) {
688 DRM_ERROR("channel eq failed: 5 tries\n");
689 break;
690 }
691
692 /* Compute new train_set as requested by sink */
693 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
694 dp_info->train_set);
695
696 amdgpu_atombios_dp_update_vs_emph(dp_info);
697 dp_info->tries++;
698 }
699
700 if (!channel_eq) {
701 DRM_ERROR("channel eq failed\n");
702 return -1;
703 } else {
704 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
705 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
706 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
707 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
708 return 0;
709 }
710}
711
712void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
713 struct drm_connector *connector)
714{
715 struct drm_device *dev = encoder->dev;
716 struct amdgpu_device *adev = dev->dev_private;
717 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
718 struct amdgpu_encoder_atom_dig *dig;
719 struct amdgpu_connector *amdgpu_connector;
720 struct amdgpu_connector_atom_dig *dig_connector;
721 struct amdgpu_atombios_dp_link_train_info dp_info;
722 u8 tmp;
723
724 if (!amdgpu_encoder->enc_priv)
725 return;
726 dig = amdgpu_encoder->enc_priv;
727
728 amdgpu_connector = to_amdgpu_connector(connector);
729 if (!amdgpu_connector->con_priv)
730 return;
731 dig_connector = amdgpu_connector->con_priv;
732
733 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
734 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
735 return;
736
737 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
738 == 1) {
739 if (tmp & DP_TPS3_SUPPORTED)
740 dp_info.tp3_supported = true;
741 else
742 dp_info.tp3_supported = false;
743 } else {
744 dp_info.tp3_supported = false;
745 }
746
747 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
748 dp_info.adev = adev;
749 dp_info.encoder = encoder;
750 dp_info.connector = connector;
751 dp_info.dp_lane_count = dig_connector->dp_lane_count;
752 dp_info.dp_clock = dig_connector->dp_clock;
753 dp_info.aux = &amdgpu_connector->ddc_bus->aux;
754
755 if (amdgpu_atombios_dp_link_train_init(&dp_info))
756 goto done;
757 if (amdgpu_atombios_dp_link_train_cr(&dp_info))
758 goto done;
759 if (amdgpu_atombios_dp_link_train_ce(&dp_info))
760 goto done;
761done:
762 if (amdgpu_atombios_dp_link_train_finish(&dp_info))
763 return;
764}
Linux 6.x block layer and io_uring tree(s)