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45d76eeb LG |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include "amdgpu.h" | |
25 | #include "athub_v2_1.h" | |
26 | ||
27 | #include "athub/athub_2_1_0_offset.h" | |
28 | #include "athub/athub_2_1_0_sh_mask.h" | |
45d76eeb LG |
29 | |
30 | #include "soc15_common.h" | |
31 | ||
32 | static void | |
33 | athub_v2_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, | |
34 | bool enable) | |
35 | { | |
36 | uint32_t def, data; | |
37 | ||
38 | def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); | |
39 | ||
40 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) | |
41 | data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; | |
42 | else | |
43 | data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; | |
44 | ||
45 | if (def != data) | |
46 | WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); | |
47 | } | |
48 | ||
49 | static void | |
50 | athub_v2_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, | |
51 | bool enable) | |
52 | { | |
53 | uint32_t def, data; | |
54 | ||
55 | def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); | |
56 | ||
57 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && | |
58 | (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) | |
59 | data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; | |
60 | else | |
61 | data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; | |
62 | ||
63 | if(def != data) | |
64 | WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); | |
65 | } | |
66 | ||
67 | int athub_v2_1_set_clockgating(struct amdgpu_device *adev, | |
68 | enum amd_clockgating_state state) | |
69 | { | |
70 | if (amdgpu_sriov_vf(adev)) | |
71 | return 0; | |
72 | ||
4e8303cf | 73 | switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { |
258fa17d AD |
74 | case IP_VERSION(2, 1, 0): |
75 | case IP_VERSION(2, 1, 1): | |
76 | case IP_VERSION(2, 1, 2): | |
f06d9e4e | 77 | case IP_VERSION(2, 4, 0): |
6c65a582 JC |
78 | athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); |
79 | athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE); | |
45d76eeb LG |
80 | break; |
81 | default: | |
82 | break; | |
83 | } | |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
25faeddc | 88 | void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags) |
45d76eeb LG |
89 | { |
90 | int data; | |
91 | ||
92 | /* AMD_CG_SUPPORT_ATHUB_MGCG */ | |
93 | data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); | |
94 | if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) | |
95 | *flags |= AMD_CG_SUPPORT_ATHUB_MGCG; | |
96 | ||
97 | /* AMD_CG_SUPPORT_ATHUB_LS */ | |
98 | if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK) | |
99 | *flags |= AMD_CG_SUPPORT_ATHUB_LS; | |
100 | } |