[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgv_sriovmsg.h

/*
 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#ifndef AMDGV_SRIOV_MSG__H_
#define AMDGV_SRIOV_MSG__H_

/* unit in kilobytes */
#define AMD_SRIOV_MSG_VBIOS_OFFSET	     0
#define AMD_SRIOV_MSG_VBIOS_SIZE_KB	     64
#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB   4

/*
 * layout
 * 0           64KB        65KB        66KB
 * |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | ...
 * |   64KB    |   1KB     |   1KB     |
 */
#define AMD_SRIOV_MSG_SIZE_KB                   1
#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB           AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB           (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB        (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)

/*
 * PF2VF history log:
 * v1 defined in amdgim
 * v2 current
 *
 * VF2PF history log:
 * v1 defined in amdgim
 * v2 defined in amdgim
 * v3 current
 */
#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3

#define AMD_SRIOV_MSG_RESERVE_UCODE 24

#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4

enum amd_sriov_ucode_engine_id {
	AMD_SRIOV_UCODE_ID_VCE = 0,
	AMD_SRIOV_UCODE_ID_UVD,
	AMD_SRIOV_UCODE_ID_MC,
	AMD_SRIOV_UCODE_ID_ME,
	AMD_SRIOV_UCODE_ID_PFP,
	AMD_SRIOV_UCODE_ID_CE,
	AMD_SRIOV_UCODE_ID_RLC,
	AMD_SRIOV_UCODE_ID_RLC_SRLC,
	AMD_SRIOV_UCODE_ID_RLC_SRLG,
	AMD_SRIOV_UCODE_ID_RLC_SRLS,
	AMD_SRIOV_UCODE_ID_MEC,
	AMD_SRIOV_UCODE_ID_MEC2,
	AMD_SRIOV_UCODE_ID_SOS,
	AMD_SRIOV_UCODE_ID_ASD,
	AMD_SRIOV_UCODE_ID_TA_RAS,
	AMD_SRIOV_UCODE_ID_TA_XGMI,
	AMD_SRIOV_UCODE_ID_SMC,
	AMD_SRIOV_UCODE_ID_SDMA,
	AMD_SRIOV_UCODE_ID_SDMA2,
	AMD_SRIOV_UCODE_ID_VCN,
	AMD_SRIOV_UCODE_ID_DMCU,
	AMD_SRIOV_UCODE_ID__MAX
};

#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed

union amd_sriov_msg_feature_flags {
	struct {
		uint32_t error_log_collect : 1;
		uint32_t host_load_ucodes  : 1;
		uint32_t host_flr_vramlost : 1;
		uint32_t mm_bw_management  : 1;
		uint32_t pp_one_vf_mode    : 1;
		uint32_t reg_indirect_acc  : 1;
		uint32_t av1_support       : 1;
		uint32_t vcn_rb_decouple   : 1;
		uint32_t mes_info_enable   : 1;
		uint32_t reserved          : 23;
	} flags;
	uint32_t all;
};

union amd_sriov_reg_access_flags {
	struct {
		uint32_t vf_reg_access_ih 	 : 1;
		uint32_t vf_reg_access_mmhub : 1;
		uint32_t vf_reg_access_gc 	 : 1;
		uint32_t reserved	         : 29;
	} flags;
	uint32_t all;
};

union amd_sriov_msg_os_info {
	struct {
		uint32_t windows  : 1;
		uint32_t reserved : 31;
	} info;
	uint32_t all;
};

struct amd_sriov_msg_uuid_info {
	union {
		struct {
			uint32_t did	: 16;
			uint32_t fcn	: 8;
			uint32_t asic_7 : 8;
		};
		uint32_t time_low;
	};

	struct {
		uint32_t time_mid  : 16;
		uint32_t time_high : 12;
		uint32_t version   : 4;
	};

	struct {
		struct {
			uint8_t clk_seq_hi : 6;
			uint8_t variant    : 2;
		};
		union {
			uint8_t clk_seq_low;
			uint8_t asic_6;
		};
		uint16_t asic_4;
	};

	uint32_t asic_0;
};

struct amd_sriov_msg_pf2vf_info_header {
	/* the total structure size in byte */
	uint32_t size;
	/* version of this structure, written by the HOST */
	uint32_t version;
	/* reserved */
	uint32_t reserved[2];
};

#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (49)
struct amd_sriov_msg_pf2vf_info {
	/* header contains size and version */
	struct amd_sriov_msg_pf2vf_info_header header;
	/* use private key from mailbox 2 to create checksum */
	uint32_t checksum;
	/* The features flags of the HOST driver supports */
	union amd_sriov_msg_feature_flags feature_flags;
	/* (max_width * max_height * fps) / (16 * 16) */
	uint32_t hevc_enc_max_mb_per_second;
	/* (max_width * max_height) / (16 * 16) */
	uint32_t hevc_enc_max_mb_per_frame;
	/* (max_width * max_height * fps) / (16 * 16) */
	uint32_t avc_enc_max_mb_per_second;
	/* (max_width * max_height) / (16 * 16) */
	uint32_t avc_enc_max_mb_per_frame;
	/* MEC FW position in BYTE from the start of VF visible frame buffer */
	uint64_t mecfw_offset;
	/* MEC FW size in BYTE */
	uint32_t mecfw_size;
	/* UVD FW position in BYTE from the start of VF visible frame buffer */
	uint64_t uvdfw_offset;
	/* UVD FW size in BYTE */
	uint32_t uvdfw_size;
	/* VCE FW position in BYTE from the start of VF visible frame buffer */
	uint64_t vcefw_offset;
	/* VCE FW size in BYTE */
	uint32_t vcefw_size;
	/* Bad pages block position in BYTE */
	uint32_t bp_block_offset_low;
	uint32_t bp_block_offset_high;
	/* Bad pages block size in BYTE */
	uint32_t bp_block_size;
	/* frequency for VF to update the VF2PF area in msec, 0 = manual */
	uint32_t vf2pf_update_interval_ms;
	/* identification in ROCm SMI */
	uint64_t uuid;
	uint32_t fcn_idx;
	/* flags to indicate which register access method VF should use */
	union amd_sriov_reg_access_flags reg_access_flags;
	/* MM BW management */
	struct {
		uint32_t decode_max_dimension_pixels;
		uint32_t decode_max_frame_pixels;
		uint32_t encode_max_dimension_pixels;
		uint32_t encode_max_frame_pixels;
	} mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
	/* UUID info */
	struct amd_sriov_msg_uuid_info uuid_info;
	/* PCIE atomic ops support flag */
	uint32_t pcie_atomic_ops_support_flags;
	/* Portion of GPU memory occupied by VF.  MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */
	uint32_t gpu_capacity;
	/* reserved */
	uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
} __packed;

struct amd_sriov_msg_vf2pf_info_header {
	/* the total structure size in byte */
	uint32_t size;
	/* version of this structure, written by the guest */
	uint32_t version;
	/* reserved */
	uint32_t reserved[2];
};

#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73)
struct amd_sriov_msg_vf2pf_info {
	/* header contains size and version */
	struct amd_sriov_msg_vf2pf_info_header header;
	uint32_t checksum;
	/* driver version */
	uint8_t driver_version[64];
	/* driver certification, 1=WHQL, 0=None */
	uint32_t driver_cert;
	/* guest OS type and version */
	union amd_sriov_msg_os_info os_info;
	/* guest fb information in the unit of MB */
	uint32_t fb_usage;
	/* guest gfx engine usage percentage */
	uint32_t gfx_usage;
	/* guest gfx engine health percentage */
	uint32_t gfx_health;
	/* guest compute engine usage percentage */
	uint32_t compute_usage;
	/* guest compute engine health percentage */
	uint32_t compute_health;
	/* guest avc engine usage percentage. 0xffff means N/A */
	uint32_t avc_enc_usage;
	/* guest avc engine health percentage. 0xffff means N/A */
	uint32_t avc_enc_health;
	/* guest hevc engine usage percentage. 0xffff means N/A */
	uint32_t hevc_enc_usage;
	/* guest hevc engine usage percentage. 0xffff means N/A */
	uint32_t hevc_enc_health;
	/* combined encode/decode usage */
	uint32_t encode_usage;
	uint32_t decode_usage;
	/* Version of PF2VF that VF understands */
	uint32_t pf2vf_version_required;
	/* additional FB usage */
	uint32_t fb_vis_usage;
	uint32_t fb_vis_size;
	uint32_t fb_size;
	/* guest ucode data, each one is 1.25 Dword */
	struct {
		uint8_t id;
		uint32_t version;
	} ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
	uint64_t dummy_page_addr;
	/* FB allocated for guest MES to record UQ info */
	uint64_t mes_info_addr;
	uint32_t mes_info_size;
	/* reserved */
	uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
} __packed;

/* mailbox message send from guest to host  */
enum amd_sriov_mailbox_request_message {
	MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
	MB_REQ_MSG_REL_GPU_INIT_ACCESS,
	MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
	MB_REQ_MSG_REL_GPU_FINI_ACCESS,
	MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
	MB_REQ_MSG_REQ_GPU_INIT_DATA,

	MB_REQ_MSG_LOG_VF_ERROR = 200,
};

/* mailbox message send from host to guest  */
enum amd_sriov_mailbox_response_message {
	MB_RES_MSG_CLR_MSG_BUF = 0,
	MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
	MB_RES_MSG_FLR_NOTIFICATION,
	MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
	MB_RES_MSG_SUCCESS,
	MB_RES_MSG_FAIL,
	MB_RES_MSG_QUERY_ALIVE,
	MB_RES_MSG_GPU_INIT_DATA_READY,

	MB_RES_MSG_TEXT_MESSAGE = 255
};

/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
enum amd_sriov_gpu_init_data_version {
	GPU_INIT_DATA_READY_V1 = 1,
};

#pragma pack(pop) // Restore previous packing option

/* checksum function between host and guest */
unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
				    unsigned int checksum);

/* assertion at compile time */
#ifdef __linux__
#define stringification(s)  _stringification(s)
#define _stringification(s) #s

_Static_assert(
	sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
	"amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");

_Static_assert(
	sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
	"amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");

_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
	       "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");

_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
	       "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");

#undef _stringification
#undef stringification
#endif

#endif /* AMDGV_SRIOV_MSG__H_ */
Commit	Line	Data
1721bc1b	1	/*
c649287a	2	* Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved.
1721bc1b	3	*
c649287a BZ	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
1721bc1b BZ	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
c649287a BZ	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
1721bc1b BZ	21	*/
	22
	23	#ifndef AMDGV_SRIOV_MSG__H_
	24	#define AMDGV_SRIOV_MSG__H_
	25
	26	/* unit in kilobytes */
451913e9 BZ	27	#define AMD_SRIOV_MSG_VBIOS_OFFSET 0
	28	#define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
	29	#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
	30	#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4
1721bc1b BZ	31
	32	/*
	33	* layout
	34	* 0 64KB 65KB 66KB
	35	* \| VBIOS \| PF2VF \| VF2PF \| Bad Page \| ...
	36	* \| 64KB \| 1KB \| 1KB \|
	37	*/
	38	#define AMD_SRIOV_MSG_SIZE_KB 1
	39	#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
	40	#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
	41	#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
	42
	43	/*
	44	* PF2VF history log:
	45	* v1 defined in amdgim
	46	* v2 current
	47	*
	48	* VF2PF history log:
	49	* v1 defined in amdgim
	50	* v2 defined in amdgim
	51	* v3 current
	52	*/
451913e9 BZ	53	#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
451913e9 BZ	54	#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
1721bc1b	55
451913e9	56	#define AMD_SRIOV_MSG_RESERVE_UCODE 24
1721bc1b	57
ed9d2053 BZ	58	#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
ed9d2053 BZ	59
1721bc1b BZ	60	enum amd_sriov_ucode_engine_id {
	61	AMD_SRIOV_UCODE_ID_VCE = 0,
	62	AMD_SRIOV_UCODE_ID_UVD,
	63	AMD_SRIOV_UCODE_ID_MC,
	64	AMD_SRIOV_UCODE_ID_ME,
	65	AMD_SRIOV_UCODE_ID_PFP,
	66	AMD_SRIOV_UCODE_ID_CE,
	67	AMD_SRIOV_UCODE_ID_RLC,
	68	AMD_SRIOV_UCODE_ID_RLC_SRLC,
	69	AMD_SRIOV_UCODE_ID_RLC_SRLG,
	70	AMD_SRIOV_UCODE_ID_RLC_SRLS,
	71	AMD_SRIOV_UCODE_ID_MEC,
	72	AMD_SRIOV_UCODE_ID_MEC2,
	73	AMD_SRIOV_UCODE_ID_SOS,
	74	AMD_SRIOV_UCODE_ID_ASD,
	75	AMD_SRIOV_UCODE_ID_TA_RAS,
	76	AMD_SRIOV_UCODE_ID_TA_XGMI,
	77	AMD_SRIOV_UCODE_ID_SMC,
	78	AMD_SRIOV_UCODE_ID_SDMA,
	79	AMD_SRIOV_UCODE_ID_SDMA2,
	80	AMD_SRIOV_UCODE_ID_VCN,
	81	AMD_SRIOV_UCODE_ID_DMCU,
	82	AMD_SRIOV_UCODE_ID__MAX
	83	};
	84
451913e9	85	#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
1721bc1b BZ	86
	87	union amd_sriov_msg_feature_flags {
	88	struct {
451913e9 BZ	89	uint32_t error_log_collect : 1;
	90	uint32_t host_load_ucodes : 1;
	91	uint32_t host_flr_vramlost : 1;
	92	uint32_t mm_bw_management : 1;
97b28216	93	uint32_t pp_one_vf_mode : 1;
451913e9	94	uint32_t reg_indirect_acc : 1;
dcaf5000	95	uint32_t av1_support : 1;
97b28216	96	uint32_t vcn_rb_decouple : 1;
f6ac0842	97	uint32_t mes_info_enable : 1;
f6ac0842	98	uint32_t reserved : 23;
1721bc1b	99	} flags;
451913e9	100	uint32_t all;
1721bc1b BZ	101	};
1721bc1b BZ	102
4d675e1e RK	103	union amd_sriov_reg_access_flags {
4d675e1e RK	104	struct {
ed9d2053 BZ	105	uint32_t vf_reg_access_ih : 1;
	106	uint32_t vf_reg_access_mmhub : 1;
	107	uint32_t vf_reg_access_gc : 1;
	108	uint32_t reserved : 29;
4d675e1e RK	109	} flags;
	110	uint32_t all;
	111	};
	112
1721bc1b BZ	113	union amd_sriov_msg_os_info {
1721bc1b BZ	114	struct {
451913e9 BZ	115	uint32_t windows : 1;
451913e9 BZ	116	uint32_t reserved : 31;
1721bc1b	117	} info;
451913e9	118	uint32_t all;
1721bc1b BZ	119	};
1721bc1b BZ	120
ed9d2053 BZ	121	struct amd_sriov_msg_uuid_info {
	122	union {
	123	struct {
	124	uint32_t did : 16;
	125	uint32_t fcn : 8;
	126	uint32_t asic_7 : 8;
	127	};
	128	uint32_t time_low;
	129	};
	130
	131	struct {
	132	uint32_t time_mid : 16;
	133	uint32_t time_high : 12;
	134	uint32_t version : 4;
	135	};
	136
	137	struct {
	138	struct {
	139	uint8_t clk_seq_hi : 6;
	140	uint8_t variant : 2;
	141	};
	142	union {
	143	uint8_t clk_seq_low;
	144	uint8_t asic_6;
	145	};
	146	uint16_t asic_4;
	147	};
	148
	149	uint32_t asic_0;
	150	};
	151
1721bc1b BZ	152	struct amd_sriov_msg_pf2vf_info_header {
	153	/* the total structure size in byte */
	154	uint32_t size;
	155	/* version of this structure, written by the HOST */
	156	uint32_t version;
	157	/* reserved */
	158	uint32_t reserved[2];
	159	};
	160
6b0d7803	161	#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (49)
1721bc1b BZ	162	struct amd_sriov_msg_pf2vf_info {
	163	/* header contains size and version */
	164	struct amd_sriov_msg_pf2vf_info_header header;
	165	/* use private key from mailbox 2 to create checksum */
	166	uint32_t checksum;
	167	/* The features flags of the HOST driver supports */
	168	union amd_sriov_msg_feature_flags feature_flags;
	169	/* (max_width * max_height * fps) / (16 * 16) */
	170	uint32_t hevc_enc_max_mb_per_second;
	171	/* (max_width * max_height) / (16 * 16) */
	172	uint32_t hevc_enc_max_mb_per_frame;
	173	/* (max_width * max_height * fps) / (16 * 16) */
	174	uint32_t avc_enc_max_mb_per_second;
	175	/* (max_width * max_height) / (16 * 16) */
	176	uint32_t avc_enc_max_mb_per_frame;
	177	/* MEC FW position in BYTE from the start of VF visible frame buffer */
	178	uint64_t mecfw_offset;
	179	/* MEC FW size in BYTE */
	180	uint32_t mecfw_size;
	181	/* UVD FW position in BYTE from the start of VF visible frame buffer */
	182	uint64_t uvdfw_offset;
	183	/* UVD FW size in BYTE */
	184	uint32_t uvdfw_size;
	185	/* VCE FW position in BYTE from the start of VF visible frame buffer */
	186	uint64_t vcefw_offset;
	187	/* VCE FW size in BYTE */
	188	uint32_t vcefw_size;
	189	/* Bad pages block position in BYTE */
	190	uint32_t bp_block_offset_low;
	191	uint32_t bp_block_offset_high;
	192	/* Bad pages block size in BYTE */
	193	uint32_t bp_block_size;
	194	/* frequency for VF to update the VF2PF area in msec, 0 = manual */
	195	uint32_t vf2pf_update_interval_ms;
	196	/* identification in ROCm SMI */
	197	uint64_t uuid;
	198	uint32_t fcn_idx;
ed9d2053	199	/* flags to indicate which register access method VF should use */
4d675e1e	200	union amd_sriov_reg_access_flags reg_access_flags;
ed9d2053 BZ	201	/* MM BW management */
	202	struct {
	203	uint32_t decode_max_dimension_pixels;
	204	uint32_t decode_max_frame_pixels;
	205	uint32_t encode_max_dimension_pixels;
	206	uint32_t encode_max_frame_pixels;
	207	} mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
	208	/* UUID info */
	209	struct amd_sriov_msg_uuid_info uuid_info;
e15c9d06 BZ	210	/* PCIE atomic ops support flag */
e15c9d06 BZ	211	uint32_t pcie_atomic_ops_support_flags;
6b0d7803 LI	212	/* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */
6b0d7803 LI	213	uint32_t gpu_capacity;
1721bc1b	214	/* reserved */
e15c9d06	215	uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
0cee47cd	216	} __packed;
1721bc1b BZ	217
	218	struct amd_sriov_msg_vf2pf_info_header {
	219	/* the total structure size in byte */
	220	uint32_t size;
	221	/* version of this structure, written by the guest */
	222	uint32_t version;
	223	/* reserved */
	224	uint32_t reserved[2];
	225	};
	226
f6ac0842	227	#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73)
1721bc1b BZ	228	struct amd_sriov_msg_vf2pf_info {
	229	/* header contains size and version */
	230	struct amd_sriov_msg_vf2pf_info_header header;
	231	uint32_t checksum;
	232	/* driver version */
451913e9	233	uint8_t driver_version[64];
1721bc1b BZ	234	/* driver certification, 1=WHQL, 0=None */
	235	uint32_t driver_cert;
	236	/* guest OS type and version */
	237	union amd_sriov_msg_os_info os_info;
	238	/* guest fb information in the unit of MB */
	239	uint32_t fb_usage;
	240	/* guest gfx engine usage percentage */
	241	uint32_t gfx_usage;
	242	/* guest gfx engine health percentage */
	243	uint32_t gfx_health;
	244	/* guest compute engine usage percentage */
	245	uint32_t compute_usage;
	246	/* guest compute engine health percentage */
	247	uint32_t compute_health;
	248	/* guest avc engine usage percentage. 0xffff means N/A */
	249	uint32_t avc_enc_usage;
	250	/* guest avc engine health percentage. 0xffff means N/A */
	251	uint32_t avc_enc_health;
	252	/* guest hevc engine usage percentage. 0xffff means N/A */
	253	uint32_t hevc_enc_usage;
	254	/* guest hevc engine usage percentage. 0xffff means N/A */
	255	uint32_t hevc_enc_health;
	256	/* combined encode/decode usage */
	257	uint32_t encode_usage;
	258	uint32_t decode_usage;
	259	/* Version of PF2VF that VF understands */
	260	uint32_t pf2vf_version_required;
	261	/* additional FB usage */
	262	uint32_t fb_vis_usage;
	263	uint32_t fb_vis_size;
	264	uint32_t fb_size;
	265	/* guest ucode data, each one is 1.25 Dword */
	266	struct {
451913e9	267	uint8_t id;
1721bc1b BZ	268	uint32_t version;
1721bc1b BZ	269	} ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
e77f0f5c	270	uint64_t dummy_page_addr;
f6ac0842	271	/* FB allocated for guest MES to record UQ info */
	272	uint64_t mes_info_addr;
	273	uint32_t mes_info_size;
1721bc1b	274	/* reserved */
e15c9d06	275	uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
0cee47cd	276	} __packed;
1721bc1b BZ	277
	278	/* mailbox message send from guest to host */
	279	enum amd_sriov_mailbox_request_message {
	280	MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
	281	MB_REQ_MSG_REL_GPU_INIT_ACCESS,
	282	MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
	283	MB_REQ_MSG_REL_GPU_FINI_ACCESS,
	284	MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
	285	MB_REQ_MSG_REQ_GPU_INIT_DATA,
	286
451913e9	287	MB_REQ_MSG_LOG_VF_ERROR = 200,
1721bc1b BZ	288	};
	289
	290	/* mailbox message send from host to guest */
	291	enum amd_sriov_mailbox_response_message {
	292	MB_RES_MSG_CLR_MSG_BUF = 0,
	293	MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
	294	MB_RES_MSG_FLR_NOTIFICATION,
	295	MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
	296	MB_RES_MSG_SUCCESS,
	297	MB_RES_MSG_FAIL,
	298	MB_RES_MSG_QUERY_ALIVE,
	299	MB_RES_MSG_GPU_INIT_DATA_READY,
	300
	301	MB_RES_MSG_TEXT_MESSAGE = 255
	302	};
	303
	304	/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
	305	enum amd_sriov_gpu_init_data_version {
	306	GPU_INIT_DATA_READY_V1 = 1,
	307	};
	308
451913e9	309	#pragma pack(pop) // Restore previous packing option
1721bc1b BZ	310
1721bc1b BZ	311	/* checksum function between host and guest */
451913e9 BZ	312	unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
451913e9 BZ	313	unsigned int checksum);
1721bc1b BZ	314
	315	/* assertion at compile time */
	316	#ifdef __linux__
451913e9	317	#define stringification(s) _stringification(s)
1721bc1b BZ	318	#define _stringification(s) #s
	319
	320	_Static_assert(
	321	sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
	322	"amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
	323
	324	_Static_assert(
	325	sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
	326	"amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
	327
451913e9 BZ	328	_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
451913e9 BZ	329	"AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
1721bc1b	330
451913e9 BZ	331	_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
451913e9 BZ	332	"AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
1721bc1b BZ	333
	334	#undef _stringification
	335	#undef stringification
	336	#endif
	337
	338	#endif /* AMDGV_SRIOV_MSG__H_ */