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fb30fc59 SL |
1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/list.h> | |
25 | #include "amdgpu.h" | |
5183411b | 26 | #include "amdgpu_xgmi.h" |
029fbd43 | 27 | #include "amdgpu_ras.h" |
18f36157 | 28 | #include "soc15.h" |
24f9aacf | 29 | #include "df/df_3_6_offset.h" |
18f36157 HZ |
30 | #include "xgmi/xgmi_4_0_0_smn.h" |
31 | #include "xgmi/xgmi_4_0_0_sh_mask.h" | |
32 | #include "wafl/wafl2_4_0_0_smn.h" | |
33 | #include "wafl/wafl2_4_0_0_sh_mask.h" | |
fb30fc59 SL |
34 | |
35 | static DEFINE_MUTEX(xgmi_mutex); | |
36 | ||
fb30fc59 SL |
37 | #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 |
38 | ||
d95e8e97 | 39 | static LIST_HEAD(xgmi_hive_list); |
fb30fc59 | 40 | |
18f36157 HZ |
41 | static const int xgmi_pcs_err_status_reg_vg20[] = { |
42 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, | |
43 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, | |
44 | }; | |
45 | ||
46 | static const int wafl_pcs_err_status_reg_vg20[] = { | |
47 | smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, | |
48 | smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, | |
49 | }; | |
50 | ||
a61f41b1 HZ |
51 | static const int xgmi_pcs_err_status_reg_arct[] = { |
52 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, | |
53 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, | |
54 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, | |
55 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, | |
56 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, | |
57 | smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, | |
58 | }; | |
59 | ||
60 | /* same as vg20*/ | |
61 | static const int wafl_pcs_err_status_reg_arct[] = { | |
62 | smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, | |
63 | smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, | |
64 | }; | |
65 | ||
18f36157 HZ |
66 | static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { |
67 | {"XGMI PCS DataLossErr", | |
68 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, | |
69 | {"XGMI PCS TrainingErr", | |
70 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, | |
71 | {"XGMI PCS CRCErr", | |
72 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, | |
73 | {"XGMI PCS BERExceededErr", | |
74 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, | |
75 | {"XGMI PCS TxMetaDataErr", | |
76 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, | |
77 | {"XGMI PCS ReplayBufParityErr", | |
78 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, | |
79 | {"XGMI PCS DataParityErr", | |
80 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, | |
81 | {"XGMI PCS ReplayFifoOverflowErr", | |
82 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, | |
83 | {"XGMI PCS ReplayFifoUnderflowErr", | |
84 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, | |
85 | {"XGMI PCS ElasticFifoOverflowErr", | |
86 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, | |
87 | {"XGMI PCS DeskewErr", | |
88 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, | |
89 | {"XGMI PCS DataStartupLimitErr", | |
90 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, | |
91 | {"XGMI PCS FCInitTimeoutErr", | |
92 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, | |
93 | {"XGMI PCS RecoveryTimeoutErr", | |
94 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, | |
95 | {"XGMI PCS ReadySerialTimeoutErr", | |
96 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, | |
97 | {"XGMI PCS ReadySerialAttemptErr", | |
98 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, | |
99 | {"XGMI PCS RecoveryAttemptErr", | |
100 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, | |
101 | {"XGMI PCS RecoveryRelockAttemptErr", | |
102 | SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, | |
103 | }; | |
104 | ||
105 | static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { | |
106 | {"WAFL PCS DataLossErr", | |
107 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, | |
108 | {"WAFL PCS TrainingErr", | |
109 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, | |
110 | {"WAFL PCS CRCErr", | |
111 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, | |
112 | {"WAFL PCS BERExceededErr", | |
113 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, | |
114 | {"WAFL PCS TxMetaDataErr", | |
115 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, | |
116 | {"WAFL PCS ReplayBufParityErr", | |
117 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, | |
118 | {"WAFL PCS DataParityErr", | |
119 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, | |
120 | {"WAFL PCS ReplayFifoOverflowErr", | |
121 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, | |
122 | {"WAFL PCS ReplayFifoUnderflowErr", | |
123 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, | |
124 | {"WAFL PCS ElasticFifoOverflowErr", | |
125 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, | |
126 | {"WAFL PCS DeskewErr", | |
127 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, | |
128 | {"WAFL PCS DataStartupLimitErr", | |
129 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, | |
130 | {"WAFL PCS FCInitTimeoutErr", | |
131 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, | |
132 | {"WAFL PCS RecoveryTimeoutErr", | |
133 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, | |
134 | {"WAFL PCS ReadySerialTimeoutErr", | |
135 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, | |
136 | {"WAFL PCS ReadySerialAttemptErr", | |
137 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, | |
138 | {"WAFL PCS RecoveryAttemptErr", | |
139 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, | |
140 | {"WAFL PCS RecoveryRelockAttemptErr", | |
141 | SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, | |
142 | }; | |
143 | ||
1c1e53f7 TSD |
144 | /** |
145 | * DOC: AMDGPU XGMI Support | |
146 | * | |
147 | * XGMI is a high speed interconnect that joins multiple GPU cards | |
148 | * into a homogeneous memory space that is organized by a collective | |
149 | * hive ID and individual node IDs, both of which are 64-bit numbers. | |
150 | * | |
151 | * The file xgmi_device_id contains the unique per GPU device ID and | |
152 | * is stored in the /sys/class/drm/card${cardno}/device/ directory. | |
153 | * | |
154 | * Inside the device directory a sub-directory 'xgmi_hive_info' is | |
155 | * created which contains the hive ID and the list of nodes. | |
156 | * | |
157 | * The hive ID is stored in: | |
158 | * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id | |
159 | * | |
160 | * The node information is stored in numbered directories: | |
161 | * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id | |
162 | * | |
163 | * Each device has their own xgmi_hive_info direction with a mirror | |
164 | * set of node sub-directories. | |
165 | * | |
166 | * The XGMI memory space is built by contiguously adding the power of | |
167 | * two padded VRAM space from each node to each other. | |
168 | * | |
169 | */ | |
170 | ||
d95e8e97 DL |
171 | static struct attribute amdgpu_xgmi_hive_id = { |
172 | .name = "xgmi_hive_id", | |
173 | .mode = S_IRUGO | |
174 | }; | |
1c1e53f7 | 175 | |
d95e8e97 DL |
176 | static struct attribute *amdgpu_xgmi_hive_attrs[] = { |
177 | &amdgpu_xgmi_hive_id, | |
178 | NULL | |
179 | }; | |
b1fa8c89 | 180 | |
d95e8e97 DL |
181 | static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, |
182 | struct attribute *attr, char *buf) | |
b1fa8c89 | 183 | { |
d95e8e97 DL |
184 | struct amdgpu_hive_info *hive = container_of( |
185 | kobj, struct amdgpu_hive_info, kobj); | |
b1fa8c89 | 186 | |
d95e8e97 DL |
187 | if (attr == &amdgpu_xgmi_hive_id) |
188 | return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); | |
b1fa8c89 | 189 | |
d95e8e97 | 190 | return 0; |
b1fa8c89 AG |
191 | } |
192 | ||
d95e8e97 | 193 | static void amdgpu_xgmi_hive_release(struct kobject *kobj) |
b1fa8c89 | 194 | { |
d95e8e97 DL |
195 | struct amdgpu_hive_info *hive = container_of( |
196 | kobj, struct amdgpu_hive_info, kobj); | |
197 | ||
198 | mutex_destroy(&hive->hive_lock); | |
199 | kfree(hive); | |
b1fa8c89 AG |
200 | } |
201 | ||
d95e8e97 DL |
202 | static const struct sysfs_ops amdgpu_xgmi_hive_ops = { |
203 | .show = amdgpu_xgmi_show_attrs, | |
204 | }; | |
205 | ||
206 | struct kobj_type amdgpu_xgmi_hive_type = { | |
207 | .release = amdgpu_xgmi_hive_release, | |
208 | .sysfs_ops = &amdgpu_xgmi_hive_ops, | |
209 | .default_attrs = amdgpu_xgmi_hive_attrs, | |
210 | }; | |
211 | ||
b1fa8c89 AG |
212 | static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, |
213 | struct device_attribute *attr, | |
214 | char *buf) | |
215 | { | |
216 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 217 | struct amdgpu_device *adev = drm_to_adev(ddev); |
b1fa8c89 | 218 | |
36000c7a | 219 | return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); |
b1fa8c89 AG |
220 | |
221 | } | |
222 | ||
24f9aacf JK |
223 | #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) |
224 | static ssize_t amdgpu_xgmi_show_error(struct device *dev, | |
225 | struct device_attribute *attr, | |
226 | char *buf) | |
227 | { | |
228 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 229 | struct amdgpu_device *adev = drm_to_adev(ddev); |
24f9aacf JK |
230 | uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; |
231 | uint64_t fica_out; | |
232 | unsigned int error_count = 0; | |
233 | ||
234 | ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); | |
235 | ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); | |
b1fa8c89 | 236 | |
bdf84a80 | 237 | fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); |
24f9aacf JK |
238 | if (fica_out != 0x1f) |
239 | pr_err("xGMI error counters not enabled!\n"); | |
240 | ||
bdf84a80 | 241 | fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); |
24f9aacf JK |
242 | |
243 | if ((fica_out & 0xffff) == 2) | |
244 | error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); | |
b1fa8c89 | 245 | |
bdf84a80 | 246 | adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); |
24f9aacf | 247 | |
36000c7a | 248 | return sysfs_emit(buf, "%u\n", error_count); |
24f9aacf JK |
249 | } |
250 | ||
251 | ||
252 | static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); | |
253 | static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); | |
b1fa8c89 AG |
254 | |
255 | static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, | |
256 | struct amdgpu_hive_info *hive) | |
257 | { | |
258 | int ret = 0; | |
259 | char node[10] = { 0 }; | |
260 | ||
261 | /* Create xgmi device id file */ | |
262 | ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); | |
263 | if (ret) { | |
264 | dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); | |
265 | return ret; | |
266 | } | |
267 | ||
24f9aacf JK |
268 | /* Create xgmi error file */ |
269 | ret = device_create_file(adev->dev, &dev_attr_xgmi_error); | |
270 | if (ret) | |
271 | pr_err("failed to create xgmi_error\n"); | |
272 | ||
273 | ||
b1fa8c89 | 274 | /* Create sysfs link to hive info folder on the first device */ |
d95e8e97 DL |
275 | if (hive->kobj.parent != (&adev->dev->kobj)) { |
276 | ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, | |
b1fa8c89 AG |
277 | "xgmi_hive_info"); |
278 | if (ret) { | |
279 | dev_err(adev->dev, "XGMI: Failed to create link to hive info"); | |
280 | goto remove_file; | |
281 | } | |
282 | } | |
283 | ||
d95e8e97 | 284 | sprintf(node, "node%d", atomic_read(&hive->number_devices)); |
b1fa8c89 | 285 | /* Create sysfs link form the hive folder to yourself */ |
d95e8e97 | 286 | ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); |
b1fa8c89 AG |
287 | if (ret) { |
288 | dev_err(adev->dev, "XGMI: Failed to create link from hive info"); | |
289 | goto remove_link; | |
290 | } | |
291 | ||
292 | goto success; | |
293 | ||
294 | ||
295 | remove_link: | |
4a580877 | 296 | sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); |
b1fa8c89 AG |
297 | |
298 | remove_file: | |
299 | device_remove_file(adev->dev, &dev_attr_xgmi_device_id); | |
300 | ||
301 | success: | |
302 | return ret; | |
303 | } | |
304 | ||
305 | static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, | |
306 | struct amdgpu_hive_info *hive) | |
307 | { | |
a89b5dae JZ |
308 | char node[10]; |
309 | memset(node, 0, sizeof(node)); | |
310 | ||
b1fa8c89 | 311 | device_remove_file(adev->dev, &dev_attr_xgmi_device_id); |
a89b5dae JZ |
312 | device_remove_file(adev->dev, &dev_attr_xgmi_error); |
313 | ||
d95e8e97 | 314 | if (hive->kobj.parent != (&adev->dev->kobj)) |
a89b5dae JZ |
315 | sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); |
316 | ||
d95e8e97 DL |
317 | sprintf(node, "node%d", atomic_read(&hive->number_devices)); |
318 | sysfs_remove_link(&hive->kobj, node); | |
a89b5dae | 319 | |
b1fa8c89 AG |
320 | } |
321 | ||
322 | ||
323 | ||
d95e8e97 | 324 | struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) |
fb30fc59 | 325 | { |
be8901c2 | 326 | struct amdgpu_hive_info *hive = NULL; |
d95e8e97 | 327 | int ret; |
fb30fc59 SL |
328 | |
329 | if (!adev->gmc.xgmi.hive_id) | |
330 | return NULL; | |
22d6575b | 331 | |
d95e8e97 DL |
332 | if (adev->hive) { |
333 | kobject_get(&adev->hive->kobj); | |
334 | return adev->hive; | |
335 | } | |
336 | ||
22d6575b TSD |
337 | mutex_lock(&xgmi_mutex); |
338 | ||
be8901c2 KW |
339 | list_for_each_entry(hive, &xgmi_hive_list, node) { |
340 | if (hive->hive_id == adev->gmc.xgmi.hive_id) | |
341 | goto pro_end; | |
fb30fc59 | 342 | } |
d95e8e97 DL |
343 | |
344 | hive = kzalloc(sizeof(*hive), GFP_KERNEL); | |
345 | if (!hive) { | |
346 | dev_err(adev->dev, "XGMI: allocation failed\n"); | |
347 | hive = NULL; | |
348 | goto pro_end; | |
22d6575b | 349 | } |
fb30fc59 SL |
350 | |
351 | /* initialize new hive if not exist */ | |
d95e8e97 DL |
352 | ret = kobject_init_and_add(&hive->kobj, |
353 | &amdgpu_xgmi_hive_type, | |
354 | &adev->dev->kobj, | |
355 | "%s", "xgmi_hive_info"); | |
356 | if (ret) { | |
357 | dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); | |
358 | kfree(hive); | |
359 | hive = NULL; | |
360 | goto pro_end; | |
b1fa8c89 AG |
361 | } |
362 | ||
d95e8e97 DL |
363 | hive->hive_id = adev->gmc.xgmi.hive_id; |
364 | INIT_LIST_HEAD(&hive->device_list); | |
365 | INIT_LIST_HEAD(&hive->node); | |
366 | mutex_init(&hive->hive_lock); | |
367 | atomic_set(&hive->in_reset, 0); | |
368 | atomic_set(&hive->number_devices, 0); | |
369 | task_barrier_init(&hive->tb); | |
370 | hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; | |
371 | hive->hi_req_gpu = NULL; | |
d84a430d JK |
372 | /* |
373 | * hive pstate on boot is high in vega20 so we have to go to low | |
374 | * pstate on after boot. | |
375 | */ | |
d95e8e97 DL |
376 | hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; |
377 | list_add_tail(&hive->node, &xgmi_hive_list); | |
378 | ||
379 | pro_end: | |
380 | if (hive) | |
381 | kobject_get(&hive->kobj); | |
22d6575b | 382 | mutex_unlock(&xgmi_mutex); |
d95e8e97 DL |
383 | return hive; |
384 | } | |
ed2bf522 | 385 | |
d95e8e97 DL |
386 | void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) |
387 | { | |
388 | if (hive) | |
389 | kobject_put(&hive->kobj); | |
fb30fc59 SL |
390 | } |
391 | ||
df399b06 | 392 | int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) |
393 | { | |
394 | int ret = 0; | |
a9f5f98f HZ |
395 | struct amdgpu_hive_info *hive; |
396 | struct amdgpu_device *request_adev; | |
d84a430d | 397 | bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; |
a9f5f98f | 398 | bool init_low; |
df399b06 | 399 | |
a9f5f98f HZ |
400 | hive = amdgpu_get_xgmi_hive(adev); |
401 | if (!hive) | |
402 | return 0; | |
403 | ||
404 | request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; | |
405 | init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; | |
d95e8e97 | 406 | amdgpu_put_xgmi_hive(hive); |
d84a430d | 407 | /* fw bug so temporarily disable pstate switching */ |
dfe31f25 JK |
408 | return 0; |
409 | ||
410 | if (!hive || adev->asic_type != CHIP_VEGA20) | |
df399b06 | 411 | return 0; |
412 | ||
f1403342 | 413 | mutex_lock(&hive->hive_lock); |
5c5b2ba0 | 414 | |
d84a430d JK |
415 | if (is_hi_req) |
416 | hive->hi_req_count++; | |
417 | else | |
418 | hive->hi_req_count--; | |
419 | ||
420 | /* | |
421 | * Vega20 only needs single peer to request pstate high for the hive to | |
422 | * go high but all peers must request pstate low for the hive to go low | |
423 | */ | |
424 | if (hive->pstate == pstate || | |
425 | (!is_hi_req && hive->hi_req_count && !init_low)) | |
cb5932f8 | 426 | goto out; |
93abb05f | 427 | |
d84a430d | 428 | dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); |
93abb05f | 429 | |
d84a430d | 430 | ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); |
5c5b2ba0 | 431 | if (ret) { |
d84a430d | 432 | dev_err(request_adev->dev, |
93abb05f | 433 | "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", |
d84a430d JK |
434 | request_adev->gmc.xgmi.node_id, |
435 | request_adev->gmc.xgmi.hive_id, ret); | |
5c5b2ba0 EQ |
436 | goto out; |
437 | } | |
438 | ||
d84a430d JK |
439 | if (init_low) |
440 | hive->pstate = hive->hi_req_count ? | |
441 | hive->pstate : AMDGPU_XGMI_PSTATE_MIN; | |
442 | else { | |
5c5b2ba0 | 443 | hive->pstate = pstate; |
d84a430d JK |
444 | hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? |
445 | adev : NULL; | |
446 | } | |
5c5b2ba0 | 447 | out: |
f1403342 | 448 | mutex_unlock(&hive->hive_lock); |
df399b06 | 449 | return ret; |
450 | } | |
451 | ||
5183411b AG |
452 | int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) |
453 | { | |
29c1ec24 | 454 | int ret; |
5183411b AG |
455 | |
456 | /* Each psp need to set the latest topology */ | |
457 | ret = psp_xgmi_set_topology_info(&adev->psp, | |
d95e8e97 | 458 | atomic_read(&hive->number_devices), |
da361dd1 | 459 | &adev->psp.xgmi_context.top_info); |
5183411b AG |
460 | if (ret) |
461 | dev_err(adev->dev, | |
462 | "XGMI: Set topology failure on device %llx, hive %llx, ret %d", | |
463 | adev->gmc.xgmi.node_id, | |
464 | adev->gmc.xgmi.hive_id, ret); | |
5183411b AG |
465 | |
466 | return ret; | |
467 | } | |
468 | ||
da361dd1 | 469 | |
4ac5617c JK |
470 | /* |
471 | * NOTE psp_xgmi_node_info.num_hops layout is as follows: | |
472 | * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) | |
473 | * num_hops[5:3] = reserved | |
474 | * num_hops[2:0] = number of hops | |
475 | */ | |
da361dd1 | 476 | int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, |
477 | struct amdgpu_device *peer_adev) | |
478 | { | |
479 | struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; | |
4ac5617c | 480 | uint8_t num_hops_mask = 0x7; |
da361dd1 | 481 | int i; |
482 | ||
483 | for (i = 0 ; i < top->num_nodes; ++i) | |
484 | if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) | |
4ac5617c | 485 | return top->nodes[i].num_hops & num_hops_mask; |
da361dd1 | 486 | return -EINVAL; |
487 | } | |
488 | ||
3f46c4e9 JK |
489 | int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, |
490 | struct amdgpu_device *peer_adev) | |
491 | { | |
492 | struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; | |
493 | int i; | |
494 | ||
495 | for (i = 0 ; i < top->num_nodes; ++i) | |
496 | if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) | |
497 | return top->nodes[i].num_links; | |
498 | return -EINVAL; | |
499 | } | |
500 | ||
fb30fc59 SL |
501 | int amdgpu_xgmi_add_device(struct amdgpu_device *adev) |
502 | { | |
da361dd1 | 503 | struct psp_xgmi_topology_info *top_info; |
fb30fc59 SL |
504 | struct amdgpu_hive_info *hive; |
505 | struct amdgpu_xgmi *entry; | |
5183411b | 506 | struct amdgpu_device *tmp_adev = NULL; |
fb30fc59 | 507 | |
75b2fce2 | 508 | int count = 0, ret = 0; |
fb30fc59 | 509 | |
47622ba0 | 510 | if (!adev->gmc.xgmi.supported) |
fb30fc59 | 511 | return 0; |
47622ba0 | 512 | |
e3c1b071 | 513 | if (!adev->gmc.xgmi.pending_reset && |
514 | amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { | |
0b9d3760 HZ |
515 | ret = psp_xgmi_initialize(&adev->psp); |
516 | if (ret) { | |
517 | dev_err(adev->dev, | |
518 | "XGMI: Failed to initialize xgmi session\n"); | |
519 | return ret; | |
520 | } | |
521 | ||
2f2eab3a OZ |
522 | ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); |
523 | if (ret) { | |
524 | dev_err(adev->dev, | |
525 | "XGMI: Failed to get hive id\n"); | |
526 | return ret; | |
527 | } | |
379c237e | 528 | |
2f2eab3a OZ |
529 | ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); |
530 | if (ret) { | |
531 | dev_err(adev->dev, | |
532 | "XGMI: Failed to get node id\n"); | |
533 | return ret; | |
534 | } | |
535 | } else { | |
536 | adev->gmc.xgmi.hive_id = 16; | |
537 | adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; | |
379c237e | 538 | } |
fb30fc59 | 539 | |
d95e8e97 | 540 | hive = amdgpu_get_xgmi_hive(adev); |
36ca09a0 | 541 | if (!hive) { |
542 | ret = -EINVAL; | |
543 | dev_err(adev->dev, | |
c1219b94 | 544 | "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", |
36ca09a0 | 545 | adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); |
fb30fc59 | 546 | goto exit; |
36ca09a0 | 547 | } |
d95e8e97 | 548 | mutex_lock(&hive->hive_lock); |
fb30fc59 | 549 | |
da361dd1 | 550 | top_info = &adev->psp.xgmi_context.top_info; |
5183411b | 551 | |
fb30fc59 SL |
552 | list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); |
553 | list_for_each_entry(entry, &hive->device_list, head) | |
da361dd1 | 554 | top_info->nodes[count++].node_id = entry->node_id; |
e008299e | 555 | top_info->num_nodes = count; |
d95e8e97 | 556 | atomic_set(&hive->number_devices, count); |
fb30fc59 | 557 | |
f33a8770 AG |
558 | task_barrier_add_task(&hive->tb); |
559 | ||
e3c1b071 | 560 | if (!adev->gmc.xgmi.pending_reset && |
561 | amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { | |
75b2fce2 LM |
562 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { |
563 | /* update node list for other device in the hive */ | |
564 | if (tmp_adev != adev) { | |
565 | top_info = &tmp_adev->psp.xgmi_context.top_info; | |
566 | top_info->nodes[count - 1].node_id = | |
567 | adev->gmc.xgmi.node_id; | |
568 | top_info->num_nodes = count; | |
569 | } | |
570 | ret = amdgpu_xgmi_update_topology(hive, tmp_adev); | |
571 | if (ret) | |
94561899 | 572 | goto exit_unlock; |
e008299e | 573 | } |
e008299e | 574 | |
75b2fce2 LM |
575 | /* get latest topology info for each device from psp */ |
576 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
577 | ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, | |
578 | &tmp_adev->psp.xgmi_context.top_info); | |
579 | if (ret) { | |
580 | dev_err(tmp_adev->dev, | |
581 | "XGMI: Get topology failure on device %llx, hive %llx, ret %d", | |
582 | tmp_adev->gmc.xgmi.node_id, | |
583 | tmp_adev->gmc.xgmi.hive_id, ret); | |
584 | /* To do : continue with some node failed or disable the whole hive */ | |
94561899 | 585 | goto exit_unlock; |
75b2fce2 | 586 | } |
a82c1566 | 587 | } |
fb30fc59 | 588 | } |
a82c1566 | 589 | |
e3c1b071 | 590 | if (!ret && !adev->gmc.xgmi.pending_reset) |
b1fa8c89 AG |
591 | ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); |
592 | ||
94561899 | 593 | exit_unlock: |
e008299e | 594 | mutex_unlock(&hive->hive_lock); |
595 | exit: | |
d95e8e97 DL |
596 | if (!ret) { |
597 | adev->hive = hive; | |
b1fa8c89 AG |
598 | dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", |
599 | adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); | |
d95e8e97 DL |
600 | } else { |
601 | amdgpu_put_xgmi_hive(hive); | |
b1fa8c89 AG |
602 | dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", |
603 | adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, | |
604 | ret); | |
d95e8e97 | 605 | } |
b1fa8c89 | 606 | |
fb30fc59 SL |
607 | return ret; |
608 | } | |
a82400b5 | 609 | |
0b9d3760 | 610 | int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) |
a82400b5 | 611 | { |
d95e8e97 | 612 | struct amdgpu_hive_info *hive = adev->hive; |
a82400b5 AG |
613 | |
614 | if (!adev->gmc.xgmi.supported) | |
0b9d3760 | 615 | return -EINVAL; |
a82400b5 | 616 | |
a82400b5 | 617 | if (!hive) |
0b9d3760 | 618 | return -EINVAL; |
a82400b5 | 619 | |
d95e8e97 | 620 | mutex_lock(&hive->hive_lock); |
a89b5dae JZ |
621 | task_barrier_rem_task(&hive->tb); |
622 | amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); | |
d95e8e97 DL |
623 | if (hive->hi_req_gpu == adev) |
624 | hive->hi_req_gpu = NULL; | |
625 | list_del(&adev->gmc.xgmi.head); | |
a89b5dae JZ |
626 | mutex_unlock(&hive->hive_lock); |
627 | ||
d95e8e97 DL |
628 | amdgpu_put_xgmi_hive(hive); |
629 | adev->hive = NULL; | |
630 | ||
631 | if (atomic_dec_return(&hive->number_devices) == 0) { | |
632 | /* Remove the hive from global hive list */ | |
633 | mutex_lock(&xgmi_mutex); | |
634 | list_del(&hive->node); | |
635 | mutex_unlock(&xgmi_mutex); | |
636 | ||
637 | amdgpu_put_xgmi_hive(hive); | |
22d6575b | 638 | } |
0b9d3760 HZ |
639 | |
640 | return psp_xgmi_terminate(&adev->psp); | |
a82400b5 | 641 | } |
029fbd43 | 642 | |
52137ca8 | 643 | static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev) |
029fbd43 HZ |
644 | { |
645 | int r; | |
646 | struct ras_ih_if ih_info = { | |
647 | .cb = NULL, | |
648 | }; | |
649 | struct ras_fs_if fs_info = { | |
650 | .sysfs_name = "xgmi_wafl_err_count", | |
029fbd43 HZ |
651 | }; |
652 | ||
653 | if (!adev->gmc.xgmi.supported || | |
654 | adev->gmc.xgmi.num_physical_nodes == 0) | |
655 | return 0; | |
656 | ||
52137ca8 | 657 | adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); |
66399248 | 658 | |
029fbd43 HZ |
659 | if (!adev->gmc.xgmi.ras_if) { |
660 | adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); | |
661 | if (!adev->gmc.xgmi.ras_if) | |
662 | return -ENOMEM; | |
663 | adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL; | |
664 | adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
665 | adev->gmc.xgmi.ras_if->sub_block_index = 0; | |
029fbd43 HZ |
666 | } |
667 | ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if; | |
668 | r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if, | |
669 | &fs_info, &ih_info); | |
670 | if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) { | |
671 | kfree(adev->gmc.xgmi.ras_if); | |
672 | adev->gmc.xgmi.ras_if = NULL; | |
673 | } | |
674 | ||
675 | return r; | |
676 | } | |
be5b39d8 | 677 | |
52137ca8 | 678 | static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev) |
be5b39d8 TZ |
679 | { |
680 | if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) && | |
681 | adev->gmc.xgmi.ras_if) { | |
682 | struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if; | |
683 | struct ras_ih_if ih_info = { | |
684 | .cb = NULL, | |
685 | }; | |
686 | ||
687 | amdgpu_ras_late_fini(adev, ras_if, &ih_info); | |
688 | kfree(ras_if); | |
689 | } | |
690 | } | |
19744f5f HZ |
691 | |
692 | uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, | |
693 | uint64_t addr) | |
694 | { | |
890900fe HZ |
695 | struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; |
696 | return (addr + xgmi->physical_node_id * xgmi->node_segment_size); | |
19744f5f | 697 | } |
18f36157 | 698 | |
66399248 JC |
699 | static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) |
700 | { | |
701 | WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); | |
702 | WREG32_PCIE(pcs_status_reg, 0); | |
703 | } | |
704 | ||
52137ca8 | 705 | static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) |
66399248 JC |
706 | { |
707 | uint32_t i; | |
708 | ||
709 | switch (adev->asic_type) { | |
710 | case CHIP_ARCTURUS: | |
711 | for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) | |
712 | pcs_clear_status(adev, | |
713 | xgmi_pcs_err_status_reg_arct[i]); | |
714 | break; | |
715 | case CHIP_VEGA20: | |
716 | for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) | |
717 | pcs_clear_status(adev, | |
718 | xgmi_pcs_err_status_reg_vg20[i]); | |
719 | break; | |
720 | default: | |
721 | break; | |
722 | } | |
723 | } | |
724 | ||
18f36157 HZ |
725 | static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, |
726 | uint32_t value, | |
727 | uint32_t *ue_count, | |
728 | uint32_t *ce_count, | |
729 | bool is_xgmi_pcs) | |
730 | { | |
731 | int i; | |
732 | int ue_cnt; | |
733 | ||
734 | if (is_xgmi_pcs) { | |
735 | /* query xgmi pcs error status, | |
736 | * only ue is supported */ | |
737 | for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) { | |
738 | ue_cnt = (value & | |
739 | xgmi_pcs_ras_fields[i].pcs_err_mask) >> | |
740 | xgmi_pcs_ras_fields[i].pcs_err_shift; | |
741 | if (ue_cnt) { | |
742 | dev_info(adev->dev, "%s detected\n", | |
743 | xgmi_pcs_ras_fields[i].err_name); | |
744 | *ue_count += ue_cnt; | |
745 | } | |
746 | } | |
747 | } else { | |
748 | /* query wafl pcs error status, | |
749 | * only ue is supported */ | |
750 | for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) { | |
751 | ue_cnt = (value & | |
752 | wafl_pcs_ras_fields[i].pcs_err_mask) >> | |
753 | wafl_pcs_ras_fields[i].pcs_err_shift; | |
754 | if (ue_cnt) { | |
755 | dev_info(adev->dev, "%s detected\n", | |
756 | wafl_pcs_ras_fields[i].err_name); | |
757 | *ue_count += ue_cnt; | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
52137ca8 HZ |
765 | static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, |
766 | void *ras_error_status) | |
18f36157 HZ |
767 | { |
768 | struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; | |
769 | int i; | |
770 | uint32_t data; | |
771 | uint32_t ue_cnt = 0, ce_cnt = 0; | |
772 | ||
773 | if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) | |
774 | return -EINVAL; | |
775 | ||
776 | err_data->ue_count = 0; | |
777 | err_data->ce_count = 0; | |
778 | ||
779 | switch (adev->asic_type) { | |
a61f41b1 HZ |
780 | case CHIP_ARCTURUS: |
781 | /* check xgmi pcs error */ | |
782 | for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { | |
783 | data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); | |
784 | if (data) | |
785 | amdgpu_xgmi_query_pcs_error_status(adev, | |
786 | data, &ue_cnt, &ce_cnt, true); | |
787 | } | |
788 | /* check wafl pcs error */ | |
789 | for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { | |
790 | data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); | |
791 | if (data) | |
792 | amdgpu_xgmi_query_pcs_error_status(adev, | |
793 | data, &ue_cnt, &ce_cnt, false); | |
794 | } | |
795 | break; | |
18f36157 HZ |
796 | case CHIP_VEGA20: |
797 | default: | |
798 | /* check xgmi pcs error */ | |
799 | for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { | |
800 | data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); | |
801 | if (data) | |
802 | amdgpu_xgmi_query_pcs_error_status(adev, | |
803 | data, &ue_cnt, &ce_cnt, true); | |
804 | } | |
805 | /* check wafl pcs error */ | |
806 | for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { | |
807 | data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); | |
808 | if (data) | |
809 | amdgpu_xgmi_query_pcs_error_status(adev, | |
810 | data, &ue_cnt, &ce_cnt, false); | |
811 | } | |
812 | break; | |
813 | } | |
814 | ||
52137ca8 | 815 | adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); |
66399248 | 816 | |
18f36157 HZ |
817 | err_data->ue_count += ue_cnt; |
818 | err_data->ce_count += ce_cnt; | |
819 | ||
820 | return 0; | |
821 | } | |
52137ca8 HZ |
822 | |
823 | const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = { | |
824 | .ras_late_init = amdgpu_xgmi_ras_late_init, | |
825 | .ras_fini = amdgpu_xgmi_ras_fini, | |
826 | .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, | |
827 | .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, | |
828 | }; |