[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_VM_H__
#define __AMDGPU_VM_H__

#include <linux/idr.h>
#include <linux/kfifo.h>
#include <linux/rbtree.h>
#include <drm/gpu_scheduler.h>
#include <drm/drm_file.h>
#include <drm/ttm/ttm_bo_driver.h>

#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
#include "amdgpu_ids.h"

struct amdgpu_bo_va;
struct amdgpu_job;
struct amdgpu_bo_list_entry;

/*
 * GPUVM handling
 */

/* Maximum number of PTEs the hardware can write with one command */
#define AMDGPU_VM_MAX_UPDATE_SIZE	0x3FFFF

/* number of entries in page table */
#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)

#define AMDGPU_PTE_VALID	(1ULL << 0)
#define AMDGPU_PTE_SYSTEM	(1ULL << 1)
#define AMDGPU_PTE_SNOOPED	(1ULL << 2)

/* VI only */
#define AMDGPU_PTE_EXECUTABLE	(1ULL << 4)

#define AMDGPU_PTE_READABLE	(1ULL << 5)
#define AMDGPU_PTE_WRITEABLE	(1ULL << 6)

#define AMDGPU_PTE_FRAG(x)	((x & 0x1fULL) << 7)

/* TILED for VEGA10, reserved for older ASICs  */
#define AMDGPU_PTE_PRT		(1ULL << 51)

/* PDE is handled as PTE for VEGA10 */
#define AMDGPU_PDE_PTE		(1ULL << 54)

#define AMDGPU_PTE_LOG          (1ULL << 55)

/* PTE is handled as PDE for VEGA10 (Translate Further) */
#define AMDGPU_PTE_TF		(1ULL << 56)

/* PDE Block Fragment Size for VEGA10 */
#define AMDGPU_PDE_BFS(a)	((uint64_t)a << 59)


/* For GFX9 */
#define AMDGPU_PTE_MTYPE_VG10(a)	((uint64_t)(a) << 57)
#define AMDGPU_PTE_MTYPE_VG10_MASK	AMDGPU_PTE_MTYPE_VG10(3ULL)

#define AMDGPU_MTYPE_NC 0
#define AMDGPU_MTYPE_CC 2

#define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \
                                | AMDGPU_PTE_SNOOPED    \
                                | AMDGPU_PTE_EXECUTABLE \
                                | AMDGPU_PTE_READABLE   \
                                | AMDGPU_PTE_WRITEABLE  \
                                | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))

/* NAVI10 only */
#define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
#define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)

/* How to programm VM fault handling */
#define AMDGPU_VM_FAULT_STOP_NEVER	0
#define AMDGPU_VM_FAULT_STOP_FIRST	1
#define AMDGPU_VM_FAULT_STOP_ALWAYS	2

/* max number of VMHUB */
#define AMDGPU_MAX_VMHUBS			2
#define AMDGPU_GFXHUB				0
#define AMDGPU_MMHUB				1

/* hardcode that limit for now */
#define AMDGPU_VA_RESERVED_SIZE			(1ULL << 20)

/* max vmids dedicated for process */
#define AMDGPU_VM_MAX_RESERVED_VMID	1

#define AMDGPU_VM_CONTEXT_GFX 0
#define AMDGPU_VM_CONTEXT_COMPUTE 1

/* See vm_update_mode */
#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)

/* VMPT level enumerate, and the hiberachy is:
 * PDB2->PDB1->PDB0->PTB
 */
enum amdgpu_vm_level {
	AMDGPU_VM_PDB2,
	AMDGPU_VM_PDB1,
	AMDGPU_VM_PDB0,
	AMDGPU_VM_PTB
};

/* base structure for tracking BO usage in a VM */
struct amdgpu_vm_bo_base {
	/* constant after initialization */
	struct amdgpu_vm		*vm;
	struct amdgpu_bo		*bo;

	/* protected by bo being reserved */
	struct amdgpu_vm_bo_base	*next;

	/* protected by spinlock */
	struct list_head		vm_status;

	/* protected by the BO being reserved */
	bool				moved;
};

struct amdgpu_vm_pt {
	struct amdgpu_vm_bo_base	base;

	/* array of page tables, one for each directory entry */
	struct amdgpu_vm_pt		*entries;
};

/* provided by hw blocks that can write ptes, e.g., sdma */
struct amdgpu_vm_pte_funcs {
	/* number of dw to reserve per operation */
	unsigned	copy_pte_num_dw;

	/* copy pte entries from GART */
	void (*copy_pte)(struct amdgpu_ib *ib,
			 uint64_t pe, uint64_t src,
			 unsigned count);

	/* write pte one entry at a time with addr mapping */
	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
			  uint64_t value, unsigned count,
			  uint32_t incr);
	/* for linear pte/pde updates without addr mapping */
	void (*set_pte_pde)(struct amdgpu_ib *ib,
			    uint64_t pe,
			    uint64_t addr, unsigned count,
			    uint32_t incr, uint64_t flags);
};

struct amdgpu_task_info {
	char	process_name[TASK_COMM_LEN];
	char	task_name[TASK_COMM_LEN];
	pid_t	pid;
	pid_t	tgid;
};

/**
 * struct amdgpu_vm_update_params
 *
 * Encapsulate some VM table update parameters to reduce
 * the number of function parameters
 *
 */
struct amdgpu_vm_update_params {

	/**
	 * @adev: amdgpu device we do this update for
	 */
	struct amdgpu_device *adev;

	/**
	 * @vm: optional amdgpu_vm we do this update for
	 */
	struct amdgpu_vm *vm;

	/**
	 * @pages_addr:
	 *
	 * DMA addresses to use for mapping
	 */
	dma_addr_t *pages_addr;

	/**
	 * @job: job to used for hw submission
	 */
	struct amdgpu_job *job;

	/**
	 * @num_dw_left: number of dw left for the IB
	 */
	unsigned int num_dw_left;
};

struct amdgpu_vm_update_funcs {
	int (*map_table)(struct amdgpu_bo *bo);
	int (*prepare)(struct amdgpu_vm_update_params *p, void * owner,
		       struct dma_fence *exclusive);
	int (*update)(struct amdgpu_vm_update_params *p,
		      struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
		      unsigned count, uint32_t incr, uint64_t flags);
	int (*commit)(struct amdgpu_vm_update_params *p,
		      struct dma_fence **fence);
};

struct amdgpu_vm {
	/* tree of virtual addresses mapped */
	struct rb_root_cached	va;

	/* BOs who needs a validation */
	struct list_head	evicted;

	/* PT BOs which relocated and their parent need an update */
	struct list_head	relocated;

	/* per VM BOs moved, but not yet updated in the PT */
	struct list_head	moved;

	/* All BOs of this VM not currently in the state machine */
	struct list_head	idle;

	/* regular invalidated BOs, but not yet updated in the PT */
	struct list_head	invalidated;
	spinlock_t		invalidated_lock;

	/* BO mappings freed, but not yet updated in the PT */
	struct list_head	freed;

	/* contains the page directory */
	struct amdgpu_vm_pt     root;
	struct dma_fence	*last_update;

	/* Scheduler entity for page table updates */
	struct drm_sched_entity	entity;

	unsigned int		pasid;
	/* dedicated to vm */
	struct amdgpu_vmid	*reserved_vmid[AMDGPU_MAX_VMHUBS];

	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
	bool					use_cpu_for_update;

	/* Functions to use for VM table updates */
	const struct amdgpu_vm_update_funcs	*update_funcs;

	/* Flag to indicate ATS support from PTE for GFX9 */
	bool			pte_support_ats;

	/* Up to 128 pending retry page faults */
	DECLARE_KFIFO(faults, u64, 128);

	/* Points to the KFD process VM info */
	struct amdkfd_process_info *process_info;

	/* List node in amdkfd_process_info.vm_list_head */
	struct list_head	vm_list_node;

	/* Valid while the PD is reserved or fenced */
	uint64_t		pd_phys_addr;

	/* Some basic info about the task */
	struct amdgpu_task_info task_info;

	/* Store positions of group of BOs */
	struct ttm_lru_bulk_move lru_bulk_move;
	/* mark whether can do the bulk move */
	bool			bulk_moveable;
};

struct amdgpu_vm_manager {
	/* Handling of VMIDs */
	struct amdgpu_vmid_mgr			id_mgr[AMDGPU_MAX_VMHUBS];

	/* Handling of VM fences */
	u64					fence_context;
	unsigned				seqno[AMDGPU_MAX_RINGS];

	uint64_t				max_pfn;
	uint32_t				num_level;
	uint32_t				block_size;
	uint32_t				fragment_size;
	enum amdgpu_vm_level			root_level;
	/* vram base address for page table entry  */
	u64					vram_base_offset;
	/* vm pte handling */
	const struct amdgpu_vm_pte_funcs	*vm_pte_funcs;
	struct drm_sched_rq			*vm_pte_rqs[AMDGPU_MAX_RINGS];
	unsigned				vm_pte_num_rqs;
	struct amdgpu_ring			*page_fault;

	/* partial resident texture handling */
	spinlock_t				prt_lock;
	atomic_t				num_prt_users;

	/* controls how VM page tables are updated for Graphics and Compute.
	 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
	 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
	 */
	int					vm_update_mode;

	/* PASID to VM mapping, will be used in interrupt context to
	 * look up VM of a page fault
	 */
	struct idr				pasid_idr;
	spinlock_t				pasid_lock;

	/* counter of mapped memory through xgmi */
	uint32_t				xgmi_map_counter;
	struct mutex				lock_pstate;
};

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))

extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;

void amdgpu_vm_manager_init(struct amdgpu_device *adev);
void amdgpu_vm_manager_fini(struct amdgpu_device *adev);

long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
		   int vm_context, unsigned int pasid);
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid);
void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
			 struct list_head *validated,
			 struct amdgpu_bo_list_entry *entry);
bool amdgpu_vm_ready(struct amdgpu_vm *vm);
int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			      int (*callback)(void *p, struct amdgpu_bo *bo),
			      void *param);
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
				 struct amdgpu_vm *vm);
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
			  struct amdgpu_vm *vm,
			  struct dma_fence **fence);
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
			   struct amdgpu_vm *vm);
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
			struct amdgpu_bo_va *bo_va,
			bool clear);
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
			     struct amdgpu_bo *bo, bool evicted);
uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
				       struct amdgpu_bo *bo);
struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo *bo);
int amdgpu_vm_bo_map(struct amdgpu_device *adev,
		     struct amdgpu_bo_va *bo_va,
		     uint64_t addr, uint64_t offset,
		     uint64_t size, uint64_t flags);
int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
			     struct amdgpu_bo_va *bo_va,
			     uint64_t addr, uint64_t offset,
			     uint64_t size, uint64_t flags);
int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
		       struct amdgpu_bo_va *bo_va,
		       uint64_t addr);
int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
				struct amdgpu_vm *vm,
				uint64_t saddr, uint64_t size);
struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
							 uint64_t addr);
void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
		      struct amdgpu_bo_va *bo_va);
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
				  struct amdgpu_job *job);
void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);

void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
			     struct amdgpu_task_info *task_info);

void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);

void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
				struct amdgpu_vm *vm);
void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);

#endif
Commit	Line	Data
073440d2 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_VM_H__
	25	#define __AMDGPU_VM_H__
	26
02208441	27	#include <linux/idr.h>
1b1f42d8 LS	28	#include <linux/kfifo.h>
	29	#include <linux/rbtree.h>
	30	#include <drm/gpu_scheduler.h>
61b100e9	31	#include <drm/drm_file.h>
f921661b	32	#include <drm/ttm/ttm_bo_driver.h>
073440d2	33
073440d2 CK	34	#include "amdgpu_sync.h"
073440d2 CK	35	#include "amdgpu_ring.h"
620f774f	36	#include "amdgpu_ids.h"
073440d2 CK	37
	38	struct amdgpu_bo_va;
	39	struct amdgpu_job;
	40	struct amdgpu_bo_list_entry;
	41
	42	/*
	43	* GPUVM handling
	44	*/
	45
073440d2 CK	46	/* Maximum number of PTEs the hardware can write with one command */
	47	#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
	48
	49	/* number of entries in page table */
36b32a68	50	#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
073440d2	51
35ba15f0 CK	52	#define AMDGPU_PTE_VALID (1ULL << 0)
	53	#define AMDGPU_PTE_SYSTEM (1ULL << 1)
	54	#define AMDGPU_PTE_SNOOPED (1ULL << 2)
073440d2 CK	55
073440d2 CK	56	/* VI only */
35ba15f0	57	#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
073440d2	58
35ba15f0 CK	59	#define AMDGPU_PTE_READABLE (1ULL << 5)
35ba15f0 CK	60	#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
073440d2	61
982a1348	62	#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
073440d2	63
d0766e98 ZJ	64	/* TILED for VEGA10, reserved for older ASICs */
d0766e98 ZJ	65	#define AMDGPU_PTE_PRT (1ULL << 51)
284710fa	66
cf2f0a37 AD	67	/* PDE is handled as PTE for VEGA10 */
	68	#define AMDGPU_PDE_PTE (1ULL << 54)
	69
7f95167c JX	70	#define AMDGPU_PTE_LOG (1ULL << 55)
7f95167c JX	71
6a42fd6f CK	72	/* PTE is handled as PDE for VEGA10 (Translate Further) */
	73	#define AMDGPU_PTE_TF (1ULL << 56)
	74
	75	/* PDE Block Fragment Size for VEGA10 */
	76	#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
	77
959a2091 YZ	78
959a2091 YZ	79	/* For GFX9 */
7596ab68 HZ	80	#define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
7596ab68 HZ	81	#define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL)
ca02061c	82
959a2091	83	#define AMDGPU_MTYPE_NC 0
6d16dac8 YZ	84	#define AMDGPU_MTYPE_CC 2
	85
	86	#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
	87	\| AMDGPU_PTE_SNOOPED \
	88	\| AMDGPU_PTE_EXECUTABLE \
	89	\| AMDGPU_PTE_READABLE \
	90	\| AMDGPU_PTE_WRITEABLE \
7596ab68	91	\| AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
6d16dac8	92
c304b9e5 HZ	93	/* NAVI10 only */
	94	#define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
	95	#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
	96
073440d2 CK	97	/* How to programm VM fault handling */
	98	#define AMDGPU_VM_FAULT_STOP_NEVER 0
	99	#define AMDGPU_VM_FAULT_STOP_FIRST 1
	100	#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
	101
eb60ef2b CK	102	/* max number of VMHUB */
	103	#define AMDGPU_MAX_VMHUBS 2
	104	#define AMDGPU_GFXHUB 0
	105	#define AMDGPU_MMHUB 1
	106
	107	/* hardcode that limit for now */
18d09e63	108	#define AMDGPU_VA_RESERVED_SIZE (1ULL << 20)
ff4cd389	109
c3505770 CZ	110	/* max vmids dedicated for process */
c3505770 CZ	111	#define AMDGPU_VM_MAX_RESERVED_VMID 1
eb60ef2b	112
9a4b7d4c HK	113	#define AMDGPU_VM_CONTEXT_GFX 0
	114	#define AMDGPU_VM_CONTEXT_COMPUTE 1
	115
	116	/* See vm_update_mode */
	117	#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
	118	#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
	119
196f7489 CZ	120	/* VMPT level enumerate, and the hiberachy is:
	121	* PDB2->PDB1->PDB0->PTB
	122	*/
	123	enum amdgpu_vm_level {
	124	AMDGPU_VM_PDB2,
	125	AMDGPU_VM_PDB1,
	126	AMDGPU_VM_PDB0,
	127	AMDGPU_VM_PTB
	128	};
	129
ec681545 CK	130	/* base structure for tracking BO usage in a VM */
	131	struct amdgpu_vm_bo_base {
	132	/* constant after initialization */
	133	struct amdgpu_vm *vm;
	134	struct amdgpu_bo *bo;
	135
	136	/* protected by bo being reserved */
646b9025	137	struct amdgpu_vm_bo_base *next;
ec681545 CK	138
	139	/* protected by spinlock */
	140	struct list_head vm_status;
3d7d4d3a CK	141
	142	/* protected by the BO being reserved */
	143	bool moved;
ec681545	144	};
9a4b7d4c	145
073440d2	146	struct amdgpu_vm_pt {
3f3333f8	147	struct amdgpu_vm_bo_base base;
67003a15 CK	148
67003a15 CK	149	/* array of page tables, one for each directory entry */
3f3333f8	150	struct amdgpu_vm_pt *entries;
073440d2 CK	151	};
073440d2 CK	152
4473e1db HR	153	/* provided by hw blocks that can write ptes, e.g., sdma */
	154	struct amdgpu_vm_pte_funcs {
	155	/* number of dw to reserve per operation */
	156	unsigned copy_pte_num_dw;
	157
	158	/* copy pte entries from GART */
	159	void (copy_pte)(struct amdgpu_ib ib,
	160	uint64_t pe, uint64_t src,
	161	unsigned count);
	162
	163	/* write pte one entry at a time with addr mapping */
	164	void (write_pte)(struct amdgpu_ib ib, uint64_t pe,
	165	uint64_t value, unsigned count,
	166	uint32_t incr);
	167	/* for linear pte/pde updates without addr mapping */
	168	void (set_pte_pde)(struct amdgpu_ib ib,
	169	uint64_t pe,
	170	uint64_t addr, unsigned count,
	171	uint32_t incr, uint64_t flags);
	172	};
	173
2aa37bf5 AG	174	struct amdgpu_task_info {
	175	char process_name[TASK_COMM_LEN];
	176	char task_name[TASK_COMM_LEN];
	177	pid_t pid;
	178	pid_t tgid;
	179	};
	180
d1e29462 CK	181	/**
	182	* struct amdgpu_vm_update_params
	183	*
	184	* Encapsulate some VM table update parameters to reduce
	185	* the number of function parameters
	186	*
	187	*/
	188	struct amdgpu_vm_update_params {
	189
	190	/**
	191	* @adev: amdgpu device we do this update for
	192	*/
	193	struct amdgpu_device *adev;
	194
	195	/**
	196	* @vm: optional amdgpu_vm we do this update for
	197	*/
	198	struct amdgpu_vm *vm;
	199
	200	/**
	201	* @pages_addr:
	202	*
	203	* DMA addresses to use for mapping
	204	*/
	205	dma_addr_t *pages_addr;
	206
6dd09027 CK	207	/**
	208	* @job: job to used for hw submission
	209	*/
	210	struct amdgpu_job *job;
	211
6dd09027 CK	212	/**
	213	* @num_dw_left: number of dw left for the IB
	214	*/
	215	unsigned int num_dw_left;
d1e29462 CK	216	};
d1e29462 CK	217
6dd09027	218	struct amdgpu_vm_update_funcs {
ecf96b52	219	int (map_table)(struct amdgpu_bo bo);
6dd09027 CK	220	int (prepare)(struct amdgpu_vm_update_params p, void * owner,
	221	struct dma_fence *exclusive);
	222	int (update)(struct amdgpu_vm_update_params p,
	223	struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
	224	unsigned count, uint32_t incr, uint64_t flags);
	225	int (commit)(struct amdgpu_vm_update_params p,
	226	struct dma_fence **fence);
	227	};
	228
073440d2 CK	229	struct amdgpu_vm {
073440d2 CK	230	/* tree of virtual addresses mapped */
f808c13f	231	struct rb_root_cached va;
073440d2	232
3f3333f8 CK	233	/* BOs who needs a validation */
	234	struct list_head evicted;
	235
ea09729c CK	236	/* PT BOs which relocated and their parent need an update */
	237	struct list_head relocated;
	238
c12a2ee5	239	/* per VM BOs moved, but not yet updated in the PT */
27c7b9ae	240	struct list_head moved;
073440d2	241
806f043f CK	242	/* All BOs of this VM not currently in the state machine */
	243	struct list_head idle;
	244
c12a2ee5 CK	245	/* regular invalidated BOs, but not yet updated in the PT */
	246	struct list_head invalidated;
	247	spinlock_t invalidated_lock;
	248
073440d2 CK	249	/* BO mappings freed, but not yet updated in the PT */
	250	struct list_head freed;
	251
	252	/* contains the page directory */
67003a15	253	struct amdgpu_vm_pt root;
d5884513	254	struct dma_fence *last_update;
073440d2	255
073440d2	256	/* Scheduler entity for page table updates */
1b1f42d8	257	struct drm_sched_entity entity;
073440d2	258
02208441	259	unsigned int pasid;
36bbf3bf	260	/* dedicated to vm */
620f774f	261	struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
9a4b7d4c HK	262
9a4b7d4c HK	263	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
6dd09027 CK	264	bool use_cpu_for_update;
	265
	266	/* Functions to use for VM table updates */
	267	const struct amdgpu_vm_update_funcs *update_funcs;
51ac7eec YZ	268
	269	/* Flag to indicate ATS support from PTE for GFX9 */
	270	bool pte_support_ats;
a2f14820	271
c98171cc	272	/* Up to 128 pending retry page faults */
a2f14820	273	DECLARE_KFIFO(faults, u64, 128);
c98171cc	274
5b21d3e5 FK	275	/* Points to the KFD process VM info */
	276	struct amdkfd_process_info *process_info;
	277
	278	/* List node in amdkfd_process_info.vm_list_head */
	279	struct list_head vm_list_node;
	280
	281	/* Valid while the PD is reserved or fenced */
	282	uint64_t pd_phys_addr;
2aa37bf5 AG	283
	284	/* Some basic info about the task */
	285	struct amdgpu_task_info task_info;
f921661b HR	286
	287	/* Store positions of group of BOs */
	288	struct ttm_lru_bulk_move lru_bulk_move;
	289	/* mark whether can do the bulk move */
	290	bool bulk_moveable;
073440d2 CK	291	};
073440d2 CK	292
073440d2 CK	293	struct amdgpu_vm_manager {
073440d2 CK	294	/* Handling of VMIDs */
620f774f	295	struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
073440d2 CK	296
	297	/* Handling of VM fences */
	298	u64 fence_context;
	299	unsigned seqno[AMDGPU_MAX_RINGS];
	300
22770e5a	301	uint64_t max_pfn;
8437a097	302	uint32_t num_level;
36b32a68	303	uint32_t block_size;
e618d306	304	uint32_t fragment_size;
196f7489	305	enum amdgpu_vm_level root_level;
073440d2 CK	306	/* vram base address for page table entry */
073440d2 CK	307	u64 vram_base_offset;
073440d2	308	/* vm pte handling */
3798e9a6 CK	309	const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
	310	struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
	311	unsigned vm_pte_num_rqs;
c4229c6e	312	struct amdgpu_ring *page_fault;
284710fa CK	313
	314	/* partial resident texture handling */
	315	spinlock_t prt_lock;
451bc8eb	316	atomic_t num_prt_users;
9a4b7d4c HK	317
	318	/* controls how VM page tables are updated for Graphics and Compute.
	319	* BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
	320	* BIT1[= 0] Compute updated by SDMA [= 1] by CPU
	321	*/
	322	int vm_update_mode;
02208441 FK	323
	324	/* PASID to VM mapping, will be used in interrupt context to
	325	* look up VM of a page fault
	326	*/
	327	struct idr pasid_idr;
	328	spinlock_t pasid_lock;
df399b06	329
	330	/* counter of mapped memory through xgmi */
	331	uint32_t xgmi_map_counter;
	332	struct mutex lock_pstate;
073440d2 CK	333	};
073440d2 CK	334
4473e1db HR	335	#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
	336	#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
	337	#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
	338
6dd09027 CK	339	extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
	340	extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
	341
073440d2 CK	342	void amdgpu_vm_manager_init(struct amdgpu_device *adev);
073440d2 CK	343	void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
56753e73 CK	344
56753e73 CK	345	long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
9a4b7d4c	346	int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm,
02208441	347	int vm_context, unsigned int pasid);
1685b01a	348	int amdgpu_vm_make_compute(struct amdgpu_device adev, struct amdgpu_vm vm, unsigned int pasid);
bf47afba	349	void amdgpu_vm_release_compute(struct amdgpu_device adev, struct amdgpu_vm vm);
073440d2 CK	350	void amdgpu_vm_fini(struct amdgpu_device adev, struct amdgpu_vm vm);
	351	void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
	352	struct list_head *validated,
	353	struct amdgpu_bo_list_entry *entry);
3f3333f8	354	bool amdgpu_vm_ready(struct amdgpu_vm *vm);
073440d2 CK	355	int amdgpu_vm_validate_pt_bos(struct amdgpu_device adev, struct amdgpu_vm vm,
	356	int (callback)(void p, struct amdgpu_bo *bo),
	357	void *param);
8fdf074f	358	int amdgpu_vm_flush(struct amdgpu_ring ring, struct amdgpu_job job, bool need_pipe_sync);
194d2161 CK	359	int amdgpu_vm_update_directories(struct amdgpu_device *adev,
194d2161 CK	360	struct amdgpu_vm *vm);
073440d2	361	int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
f3467818 NH	362	struct amdgpu_vm *vm,
f3467818 NH	363	struct dma_fence **fence);
73fb16e7	364	int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
4e55eb38	365	struct amdgpu_vm *vm);
073440d2 CK	366	int amdgpu_vm_bo_update(struct amdgpu_device *adev,
	367	struct amdgpu_bo_va *bo_va,
	368	bool clear);
	369	void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
3f3333f8	370	struct amdgpu_bo *bo, bool evicted);
6dd09027	371	uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
073440d2 CK	372	struct amdgpu_bo_va amdgpu_vm_bo_find(struct amdgpu_vm vm,
	373	struct amdgpu_bo *bo);
	374	struct amdgpu_bo_va amdgpu_vm_bo_add(struct amdgpu_device adev,
	375	struct amdgpu_vm *vm,
	376	struct amdgpu_bo *bo);
	377	int amdgpu_vm_bo_map(struct amdgpu_device *adev,
	378	struct amdgpu_bo_va *bo_va,
	379	uint64_t addr, uint64_t offset,
268c3001	380	uint64_t size, uint64_t flags);
80f95c57 CK	381	int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
	382	struct amdgpu_bo_va *bo_va,
	383	uint64_t addr, uint64_t offset,
	384	uint64_t size, uint64_t flags);
073440d2 CK	385	int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
	386	struct amdgpu_bo_va *bo_va,
	387	uint64_t addr);
dc54d3d1 CK	388	int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
	389	struct amdgpu_vm *vm,
	390	uint64_t saddr, uint64_t size);
aebc5e6f CK	391	struct amdgpu_bo_va_mapping amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm vm,
aebc5e6f CK	392	uint64_t addr);
8ab19ea6	393	void amdgpu_vm_bo_trace_cs(struct amdgpu_vm vm, struct ww_acquire_ctx ticket);
073440d2 CK	394	void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
073440d2 CK	395	struct amdgpu_bo_va *bo_va);
43370c4c	396	void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
f3368128 CK	397	uint32_t fragment_size_default, unsigned max_level,
f3368128 CK	398	unsigned max_bits);
cfbcacf4	399	int amdgpu_vm_ioctl(struct drm_device dev, void data, struct drm_file *filp);
b9bf33d5 CZ	400	bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
b9bf33d5 CZ	401	struct amdgpu_job *job);
e59c0205	402	void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
073440d2	403
2aa37bf5	404	void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
f921661b	405	struct amdgpu_task_info *task_info);
2aa37bf5 AG	406
	407	void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
	408
f921661b HR	409	void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
f921661b HR	410	struct amdgpu_vm *vm);
b61857b5 CZ	411	void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
b61857b5 CZ	412
073440d2	413	#endif