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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
4ff37a83 CK |
53 | /* Special value that no flush is necessary */ |
54 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
55 | ||
d38ceaf9 AD |
56 | /** |
57 | * amdgpu_vm_num_pde - return the number of page directory entries | |
58 | * | |
59 | * @adev: amdgpu_device pointer | |
60 | * | |
8843dbbb | 61 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
62 | */ |
63 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
64 | { | |
65 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
66 | } | |
67 | ||
68 | /** | |
69 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
70 | * | |
71 | * @adev: amdgpu_device pointer | |
72 | * | |
8843dbbb | 73 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
74 | */ |
75 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
76 | { | |
77 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
78 | } | |
79 | ||
80 | /** | |
56467ebf | 81 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
82 | * |
83 | * @vm: vm providing the BOs | |
3c0eea6c | 84 | * @validated: head of validation list |
56467ebf | 85 | * @entry: entry to add |
d38ceaf9 AD |
86 | * |
87 | * Add the page directory to the list of BOs to | |
56467ebf | 88 | * validate for command submission. |
d38ceaf9 | 89 | */ |
56467ebf CK |
90 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
91 | struct list_head *validated, | |
92 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 93 | { |
56467ebf | 94 | entry->robj = vm->page_directory; |
56467ebf CK |
95 | entry->priority = 0; |
96 | entry->tv.bo = &vm->page_directory->tbo; | |
97 | entry->tv.shared = true; | |
98 | list_add(&entry->tv.head, validated); | |
99 | } | |
d38ceaf9 | 100 | |
56467ebf | 101 | /** |
ee1782c3 | 102 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
103 | * |
104 | * @vm: vm providing the BOs | |
3c0eea6c | 105 | * @duplicates: head of duplicates list |
d38ceaf9 | 106 | * |
ee1782c3 CK |
107 | * Add the page directory to the BO duplicates list |
108 | * for command submission. | |
d38ceaf9 | 109 | */ |
ee1782c3 | 110 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 111 | { |
ee1782c3 | 112 | unsigned i; |
d38ceaf9 AD |
113 | |
114 | /* add the vm page table to the list */ | |
ee1782c3 CK |
115 | for (i = 0; i <= vm->max_pde_used; ++i) { |
116 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
117 | ||
118 | if (!entry->robj) | |
d38ceaf9 AD |
119 | continue; |
120 | ||
ee1782c3 | 121 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 122 | } |
eceb8a15 CK |
123 | |
124 | } | |
125 | ||
126 | /** | |
127 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
128 | * | |
129 | * @adev: amdgpu device instance | |
130 | * @vm: vm providing the BOs | |
131 | * | |
132 | * Move the PT BOs to the tail of the LRU. | |
133 | */ | |
134 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
135 | struct amdgpu_vm *vm) | |
136 | { | |
137 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
138 | unsigned i; | |
139 | ||
140 | spin_lock(&glob->lru_lock); | |
141 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
142 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
143 | ||
144 | if (!entry->robj) | |
145 | continue; | |
146 | ||
147 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
148 | } | |
149 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
150 | } |
151 | ||
152 | /** | |
153 | * amdgpu_vm_grab_id - allocate the next free VMID | |
154 | * | |
d38ceaf9 | 155 | * @vm: vm to allocate id for |
7f8a5290 CK |
156 | * @ring: ring we want to submit job to |
157 | * @sync: sync object where we add dependencies | |
94dd0a4a | 158 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 159 | * |
7f8a5290 | 160 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 161 | */ |
7f8a5290 | 162 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
163 | struct amdgpu_sync *sync, struct fence *fence, |
164 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 165 | { |
4ff37a83 | 166 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
d38ceaf9 | 167 | struct amdgpu_device *adev = ring->adev; |
4ff37a83 CK |
168 | struct amdgpu_vm_id *id = &vm->ids[ring->idx]; |
169 | struct fence *updates = sync->last_vm_update; | |
a9a78b32 | 170 | int r; |
d38ceaf9 | 171 | |
94dd0a4a CK |
172 | mutex_lock(&adev->vm_manager.lock); |
173 | ||
d38ceaf9 | 174 | /* check if the id is still valid */ |
4ff37a83 CK |
175 | if (id->mgr_id) { |
176 | struct fence *flushed = id->flushed_updates; | |
177 | bool is_later; | |
1c16c0a7 CK |
178 | long owner; |
179 | ||
4ff37a83 CK |
180 | if (!flushed) |
181 | is_later = true; | |
182 | else if (!updates) | |
183 | is_later = false; | |
184 | else | |
185 | is_later = fence_is_later(updates, flushed); | |
186 | ||
187 | owner = atomic_long_read(&id->mgr_id->owner); | |
188 | if (!is_later && owner == (long)id && | |
189 | pd_addr == id->pd_gpu_addr) { | |
190 | ||
a8bd1bec CK |
191 | r = amdgpu_sync_fence(ring->adev, sync, |
192 | id->mgr_id->active); | |
193 | if (r) { | |
194 | mutex_unlock(&adev->vm_manager.lock); | |
195 | return r; | |
196 | } | |
197 | ||
4ff37a83 CK |
198 | fence_put(id->mgr_id->active); |
199 | id->mgr_id->active = fence_get(fence); | |
200 | ||
201 | list_move_tail(&id->mgr_id->list, | |
202 | &adev->vm_manager.ids_lru); | |
d38ceaf9 | 203 | |
4ff37a83 CK |
204 | *vm_id = id->mgr_id - adev->vm_manager.ids; |
205 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; | |
22073fe7 CK |
206 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, |
207 | *vm_pd_addr); | |
d38ceaf9 | 208 | |
94dd0a4a | 209 | mutex_unlock(&adev->vm_manager.lock); |
7f8a5290 | 210 | return 0; |
d38ceaf9 | 211 | } |
d38ceaf9 AD |
212 | } |
213 | ||
4ff37a83 CK |
214 | id->mgr_id = list_first_entry(&adev->vm_manager.ids_lru, |
215 | struct amdgpu_vm_manager_id, | |
216 | list); | |
7f8a5290 | 217 | |
4ff37a83 CK |
218 | r = amdgpu_sync_fence(ring->adev, sync, id->mgr_id->active); |
219 | if (!r) { | |
220 | fence_put(id->mgr_id->active); | |
221 | id->mgr_id->active = fence_get(fence); | |
94dd0a4a | 222 | |
4ff37a83 CK |
223 | fence_put(id->flushed_updates); |
224 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 225 | |
4ff37a83 | 226 | id->pd_gpu_addr = pd_addr; |
94dd0a4a | 227 | |
4ff37a83 CK |
228 | list_move_tail(&id->mgr_id->list, &adev->vm_manager.ids_lru); |
229 | atomic_long_set(&id->mgr_id->owner, (long)id); | |
230 | ||
231 | *vm_id = id->mgr_id - adev->vm_manager.ids; | |
232 | *vm_pd_addr = pd_addr; | |
22073fe7 | 233 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); |
d38ceaf9 AD |
234 | } |
235 | ||
94dd0a4a | 236 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 237 | return r; |
d38ceaf9 AD |
238 | } |
239 | ||
240 | /** | |
241 | * amdgpu_vm_flush - hardware flush the vm | |
242 | * | |
243 | * @ring: ring to use for flush | |
cffadc83 | 244 | * @vm_id: vmid number to use |
4ff37a83 | 245 | * @pd_addr: address of the page directory |
d38ceaf9 | 246 | * |
4ff37a83 | 247 | * Emit a VM flush when it is necessary. |
d38ceaf9 AD |
248 | */ |
249 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
cffadc83 CK |
250 | unsigned vm_id, uint64_t pd_addr, |
251 | uint32_t gds_base, uint32_t gds_size, | |
252 | uint32_t gws_base, uint32_t gws_size, | |
253 | uint32_t oa_base, uint32_t oa_size) | |
d38ceaf9 | 254 | { |
971fe9a9 CK |
255 | struct amdgpu_device *adev = ring->adev; |
256 | struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; | |
d564a06e CK |
257 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
258 | mgr_id->gds_base != gds_base || | |
259 | mgr_id->gds_size != gds_size || | |
260 | mgr_id->gws_base != gws_base || | |
261 | mgr_id->gws_size != gws_size || | |
262 | mgr_id->oa_base != oa_base || | |
263 | mgr_id->oa_size != oa_size); | |
264 | ||
265 | if (ring->funcs->emit_pipeline_sync && ( | |
266 | pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed)) | |
267 | amdgpu_ring_emit_pipeline_sync(ring); | |
971fe9a9 | 268 | |
4ff37a83 | 269 | if (pd_addr != AMDGPU_VM_NO_FLUSH) { |
cffadc83 CK |
270 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); |
271 | amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); | |
d38ceaf9 | 272 | } |
cffadc83 | 273 | |
d564a06e | 274 | if (gds_switch_needed) { |
971fe9a9 CK |
275 | mgr_id->gds_base = gds_base; |
276 | mgr_id->gds_size = gds_size; | |
277 | mgr_id->gws_base = gws_base; | |
278 | mgr_id->gws_size = gws_size; | |
279 | mgr_id->oa_base = oa_base; | |
280 | mgr_id->oa_size = oa_size; | |
cffadc83 CK |
281 | amdgpu_ring_emit_gds_switch(ring, vm_id, |
282 | gds_base, gds_size, | |
283 | gws_base, gws_size, | |
284 | oa_base, oa_size); | |
971fe9a9 CK |
285 | } |
286 | } | |
287 | ||
288 | /** | |
289 | * amdgpu_vm_reset_id - reset VMID to zero | |
290 | * | |
291 | * @adev: amdgpu device structure | |
292 | * @vm_id: vmid number to use | |
293 | * | |
294 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
295 | */ | |
296 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
297 | { | |
298 | struct amdgpu_vm_manager_id *mgr_id = &adev->vm_manager.ids[vm_id]; | |
299 | ||
300 | mgr_id->gds_base = 0; | |
301 | mgr_id->gds_size = 0; | |
302 | mgr_id->gws_base = 0; | |
303 | mgr_id->gws_size = 0; | |
304 | mgr_id->oa_base = 0; | |
305 | mgr_id->oa_size = 0; | |
d38ceaf9 AD |
306 | } |
307 | ||
d38ceaf9 AD |
308 | /** |
309 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
310 | * | |
311 | * @vm: requested vm | |
312 | * @bo: requested buffer object | |
313 | * | |
8843dbbb | 314 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
315 | * Search inside the @bos vm list for the requested vm |
316 | * Returns the found bo_va or NULL if none is found | |
317 | * | |
318 | * Object has to be reserved! | |
319 | */ | |
320 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
321 | struct amdgpu_bo *bo) | |
322 | { | |
323 | struct amdgpu_bo_va *bo_va; | |
324 | ||
325 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
326 | if (bo_va->vm == vm) { | |
327 | return bo_va; | |
328 | } | |
329 | } | |
330 | return NULL; | |
331 | } | |
332 | ||
333 | /** | |
334 | * amdgpu_vm_update_pages - helper to call the right asic function | |
335 | * | |
336 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
337 | * @gtt: GART instance to use for mapping |
338 | * @gtt_flags: GTT hw access flags | |
d38ceaf9 AD |
339 | * @ib: indirect buffer to fill with commands |
340 | * @pe: addr of the page entry | |
341 | * @addr: dst addr to write into pe | |
342 | * @count: number of page entries to update | |
343 | * @incr: increase next addr by incr bytes | |
344 | * @flags: hw access flags | |
d38ceaf9 AD |
345 | * |
346 | * Traces the parameters and calls the right asic functions | |
347 | * to setup the page table using the DMA. | |
348 | */ | |
349 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
9ab21462 CK |
350 | struct amdgpu_gart *gtt, |
351 | uint32_t gtt_flags, | |
d38ceaf9 AD |
352 | struct amdgpu_ib *ib, |
353 | uint64_t pe, uint64_t addr, | |
354 | unsigned count, uint32_t incr, | |
9ab21462 | 355 | uint32_t flags) |
d38ceaf9 AD |
356 | { |
357 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
358 | ||
9ab21462 CK |
359 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
360 | uint64_t src = gtt->table_addr + (addr >> 12) * 8; | |
d38ceaf9 AD |
361 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); |
362 | ||
9ab21462 CK |
363 | } else if (gtt) { |
364 | dma_addr_t *pages_addr = gtt->pages_addr; | |
b07c9d2a CK |
365 | amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, |
366 | count, incr, flags); | |
367 | ||
368 | } else if (count < 3) { | |
369 | amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, | |
370 | count, incr, flags); | |
d38ceaf9 AD |
371 | |
372 | } else { | |
373 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
374 | count, incr, flags); | |
375 | } | |
376 | } | |
377 | ||
378 | /** | |
379 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
380 | * | |
381 | * @adev: amdgpu_device pointer | |
382 | * @bo: bo to clear | |
ef9f0a83 CZ |
383 | * |
384 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
385 | */ |
386 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 387 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
388 | struct amdgpu_bo *bo) |
389 | { | |
2d55e45a | 390 | struct amdgpu_ring *ring; |
4af9f07c | 391 | struct fence *fence = NULL; |
d71518b5 | 392 | struct amdgpu_job *job; |
d38ceaf9 AD |
393 | unsigned entries; |
394 | uint64_t addr; | |
395 | int r; | |
396 | ||
2d55e45a CK |
397 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
398 | ||
ca952613 | 399 | r = reservation_object_reserve_shared(bo->tbo.resv); |
400 | if (r) | |
401 | return r; | |
402 | ||
d38ceaf9 AD |
403 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
404 | if (r) | |
ef9f0a83 | 405 | goto error; |
d38ceaf9 AD |
406 | |
407 | addr = amdgpu_bo_gpu_offset(bo); | |
408 | entries = amdgpu_bo_size(bo) / 8; | |
409 | ||
d71518b5 CK |
410 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
411 | if (r) | |
ef9f0a83 | 412 | goto error; |
d38ceaf9 | 413 | |
d71518b5 CK |
414 | amdgpu_vm_update_pages(adev, NULL, 0, &job->ibs[0], addr, 0, entries, |
415 | 0, 0); | |
416 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
417 | ||
418 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
419 | r = amdgpu_job_submit(job, ring, &vm->entity, |
420 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
421 | if (r) |
422 | goto error_free; | |
423 | ||
d71518b5 | 424 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 425 | fence_put(fence); |
cadf97b1 | 426 | return 0; |
ef9f0a83 | 427 | |
d38ceaf9 | 428 | error_free: |
d71518b5 | 429 | amdgpu_job_free(job); |
d38ceaf9 | 430 | |
ef9f0a83 | 431 | error: |
d38ceaf9 AD |
432 | return r; |
433 | } | |
434 | ||
435 | /** | |
b07c9d2a | 436 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 437 | * |
b07c9d2a | 438 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
439 | * @addr: the unmapped addr |
440 | * | |
441 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 442 | * to and return the pointer for the page table entry. |
d38ceaf9 | 443 | */ |
b07c9d2a | 444 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
445 | { |
446 | uint64_t result; | |
447 | ||
b07c9d2a CK |
448 | if (pages_addr) { |
449 | /* page table offset */ | |
450 | result = pages_addr[addr >> PAGE_SHIFT]; | |
451 | ||
452 | /* in case cpu page size != gpu page size*/ | |
453 | result |= addr & (~PAGE_MASK); | |
454 | ||
455 | } else { | |
456 | /* No mapping required */ | |
457 | result = addr; | |
458 | } | |
d38ceaf9 | 459 | |
b07c9d2a | 460 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
461 | |
462 | return result; | |
463 | } | |
464 | ||
465 | /** | |
466 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
467 | * | |
468 | * @adev: amdgpu_device pointer | |
469 | * @vm: requested vm | |
470 | * @start: start of GPU address range | |
471 | * @end: end of GPU address range | |
472 | * | |
473 | * Allocates new page tables if necessary | |
8843dbbb | 474 | * and updates the page directory. |
d38ceaf9 | 475 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
476 | */ |
477 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
478 | struct amdgpu_vm *vm) | |
479 | { | |
2d55e45a | 480 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
481 | struct amdgpu_bo *pd = vm->page_directory; |
482 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
483 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
484 | uint64_t last_pde = ~0, last_pt = ~0; | |
485 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 486 | struct amdgpu_job *job; |
d5fc5e82 | 487 | struct amdgpu_ib *ib; |
4af9f07c | 488 | struct fence *fence = NULL; |
d5fc5e82 | 489 | |
d38ceaf9 AD |
490 | int r; |
491 | ||
2d55e45a CK |
492 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
493 | ||
d38ceaf9 AD |
494 | /* padding, etc. */ |
495 | ndw = 64; | |
496 | ||
497 | /* assume the worst case */ | |
498 | ndw += vm->max_pde_used * 6; | |
499 | ||
d71518b5 CK |
500 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
501 | if (r) | |
d38ceaf9 | 502 | return r; |
d71518b5 CK |
503 | |
504 | ib = &job->ibs[0]; | |
d38ceaf9 AD |
505 | |
506 | /* walk over the address space and update the page directory */ | |
507 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 508 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
509 | uint64_t pde, pt; |
510 | ||
511 | if (bo == NULL) | |
512 | continue; | |
513 | ||
514 | pt = amdgpu_bo_gpu_offset(bo); | |
515 | if (vm->page_tables[pt_idx].addr == pt) | |
516 | continue; | |
517 | vm->page_tables[pt_idx].addr = pt; | |
518 | ||
519 | pde = pd_addr + pt_idx * 8; | |
520 | if (((last_pde + 8 * count) != pde) || | |
521 | ((last_pt + incr * count) != pt)) { | |
522 | ||
523 | if (count) { | |
9ab21462 CK |
524 | amdgpu_vm_update_pages(adev, NULL, 0, ib, |
525 | last_pde, last_pt, | |
526 | count, incr, | |
527 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
528 | } |
529 | ||
530 | count = 1; | |
531 | last_pde = pde; | |
532 | last_pt = pt; | |
533 | } else { | |
534 | ++count; | |
535 | } | |
536 | } | |
537 | ||
538 | if (count) | |
9ab21462 CK |
539 | amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt, |
540 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 541 | |
d5fc5e82 | 542 | if (ib->length_dw != 0) { |
9e5d5309 | 543 | amdgpu_ring_pad_ib(ring, ib); |
e86f9cee CK |
544 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
545 | AMDGPU_FENCE_OWNER_VM); | |
d5fc5e82 | 546 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
547 | r = amdgpu_job_submit(job, ring, &vm->entity, |
548 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
549 | if (r) |
550 | goto error_free; | |
05906dec | 551 | |
4af9f07c | 552 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
553 | fence_put(vm->page_directory_fence); |
554 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 555 | fence_put(fence); |
d5fc5e82 | 556 | |
d71518b5 CK |
557 | } else { |
558 | amdgpu_job_free(job); | |
d5fc5e82 | 559 | } |
d38ceaf9 AD |
560 | |
561 | return 0; | |
d5fc5e82 CZ |
562 | |
563 | error_free: | |
d71518b5 | 564 | amdgpu_job_free(job); |
4af9f07c | 565 | return r; |
d38ceaf9 AD |
566 | } |
567 | ||
568 | /** | |
569 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
570 | * | |
571 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
572 | * @gtt: GART instance to use for mapping |
573 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
574 | * @ib: IB for the update |
575 | * @pe_start: first PTE to handle | |
576 | * @pe_end: last PTE to handle | |
577 | * @addr: addr those PTEs should point to | |
578 | * @flags: hw mapping flags | |
d38ceaf9 AD |
579 | */ |
580 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
9ab21462 CK |
581 | struct amdgpu_gart *gtt, |
582 | uint32_t gtt_flags, | |
d38ceaf9 AD |
583 | struct amdgpu_ib *ib, |
584 | uint64_t pe_start, uint64_t pe_end, | |
9ab21462 | 585 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
586 | { |
587 | /** | |
588 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
589 | * field in the PTE. When this field is set to a non-zero value, page | |
590 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
591 | * flags are considered valid for all PTEs within the fragment range | |
592 | * and corresponding mappings are assumed to be physically contiguous. | |
593 | * | |
594 | * The L1 TLB can store a single PTE for the whole fragment, | |
595 | * significantly increasing the space available for translation | |
596 | * caching. This leads to large improvements in throughput when the | |
597 | * TLB is under pressure. | |
598 | * | |
599 | * The L2 TLB distributes small and large fragments into two | |
600 | * asymmetric partitions. The large fragment cache is significantly | |
601 | * larger. Thus, we try to use large fragments wherever possible. | |
602 | * Userspace can support this by aligning virtual base address and | |
603 | * allocation size to the fragment size. | |
604 | */ | |
605 | ||
606 | /* SI and newer are optimized for 64KB */ | |
607 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
608 | uint64_t frag_align = 0x80; | |
609 | ||
610 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
611 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
612 | ||
613 | unsigned count; | |
614 | ||
31f6c1fe CK |
615 | /* Abort early if there isn't anything to do */ |
616 | if (pe_start == pe_end) | |
617 | return; | |
618 | ||
d38ceaf9 | 619 | /* system pages are non continuously */ |
9ab21462 | 620 | if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { |
d38ceaf9 AD |
621 | |
622 | count = (pe_end - pe_start) / 8; | |
9ab21462 CK |
623 | amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start, |
624 | addr, count, AMDGPU_GPU_PAGE_SIZE, | |
625 | flags); | |
d38ceaf9 AD |
626 | return; |
627 | } | |
628 | ||
629 | /* handle the 4K area at the beginning */ | |
630 | if (pe_start != frag_start) { | |
631 | count = (frag_start - pe_start) / 8; | |
9ab21462 CK |
632 | amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr, |
633 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
634 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
635 | } | |
636 | ||
637 | /* handle the area in the middle */ | |
638 | count = (frag_end - frag_start) / 8; | |
9ab21462 CK |
639 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count, |
640 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); | |
d38ceaf9 AD |
641 | |
642 | /* handle the 4K area at the end */ | |
643 | if (frag_end != pe_end) { | |
644 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
645 | count = (pe_end - frag_end) / 8; | |
9ab21462 CK |
646 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr, |
647 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
648 | } |
649 | } | |
650 | ||
651 | /** | |
652 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
653 | * | |
654 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
655 | * @gtt: GART instance to use for mapping |
656 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
657 | * @vm: requested vm |
658 | * @start: start of GPU address range | |
659 | * @end: end of GPU address range | |
660 | * @dst: destination address to map to | |
661 | * @flags: mapping flags | |
662 | * | |
8843dbbb | 663 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 664 | */ |
a1e08d3b CK |
665 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
666 | struct amdgpu_gart *gtt, | |
667 | uint32_t gtt_flags, | |
668 | struct amdgpu_vm *vm, | |
669 | struct amdgpu_ib *ib, | |
670 | uint64_t start, uint64_t end, | |
671 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 672 | { |
31f6c1fe CK |
673 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
674 | ||
675 | uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0; | |
d38ceaf9 AD |
676 | uint64_t addr; |
677 | ||
678 | /* walk over the address space and update the page tables */ | |
679 | for (addr = start; addr < end; ) { | |
680 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 681 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 | 682 | unsigned nptes; |
31f6c1fe | 683 | uint64_t pe_start; |
d38ceaf9 AD |
684 | |
685 | if ((addr & ~mask) == (end & ~mask)) | |
686 | nptes = end - addr; | |
687 | else | |
688 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
689 | ||
31f6c1fe CK |
690 | pe_start = amdgpu_bo_gpu_offset(pt); |
691 | pe_start += (addr & mask) * 8; | |
d38ceaf9 | 692 | |
31f6c1fe | 693 | if (last_pe_end != pe_start) { |
d38ceaf9 | 694 | |
31f6c1fe CK |
695 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
696 | last_pe_start, last_pe_end, | |
697 | last_dst, flags); | |
d38ceaf9 | 698 | |
31f6c1fe CK |
699 | last_pe_start = pe_start; |
700 | last_pe_end = pe_start + 8 * nptes; | |
d38ceaf9 AD |
701 | last_dst = dst; |
702 | } else { | |
31f6c1fe | 703 | last_pe_end += 8 * nptes; |
d38ceaf9 AD |
704 | } |
705 | ||
706 | addr += nptes; | |
707 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
708 | } | |
709 | ||
31f6c1fe CK |
710 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
711 | last_pe_start, last_pe_end, | |
712 | last_dst, flags); | |
d38ceaf9 AD |
713 | } |
714 | ||
d38ceaf9 AD |
715 | /** |
716 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
717 | * | |
718 | * @adev: amdgpu_device pointer | |
9ab21462 | 719 | * @gtt: GART instance to use for mapping |
a14faa65 | 720 | * @gtt_flags: flags as they are used for GTT |
d38ceaf9 | 721 | * @vm: requested vm |
a14faa65 CK |
722 | * @start: start of mapped range |
723 | * @last: last mapped entry | |
724 | * @flags: flags for the entries | |
d38ceaf9 | 725 | * @addr: addr to set the area to |
d38ceaf9 AD |
726 | * @fence: optional resulting fence |
727 | * | |
a14faa65 | 728 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 729 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
730 | */ |
731 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
9ab21462 CK |
732 | struct amdgpu_gart *gtt, |
733 | uint32_t gtt_flags, | |
d38ceaf9 | 734 | struct amdgpu_vm *vm, |
a14faa65 CK |
735 | uint64_t start, uint64_t last, |
736 | uint32_t flags, uint64_t addr, | |
737 | struct fence **fence) | |
d38ceaf9 | 738 | { |
2d55e45a | 739 | struct amdgpu_ring *ring; |
a1e08d3b | 740 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 741 | unsigned nptes, ncmds, ndw; |
d71518b5 | 742 | struct amdgpu_job *job; |
d5fc5e82 | 743 | struct amdgpu_ib *ib; |
4af9f07c | 744 | struct fence *f = NULL; |
d38ceaf9 AD |
745 | int r; |
746 | ||
2d55e45a CK |
747 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
748 | ||
a1e08d3b CK |
749 | /* sync to everything on unmapping */ |
750 | if (!(flags & AMDGPU_PTE_VALID)) | |
751 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
752 | ||
a14faa65 | 753 | nptes = last - start + 1; |
d38ceaf9 AD |
754 | |
755 | /* | |
756 | * reserve space for one command every (1 << BLOCK_SIZE) | |
757 | * entries or 2k dwords (whatever is smaller) | |
758 | */ | |
759 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
760 | ||
761 | /* padding, etc. */ | |
762 | ndw = 64; | |
763 | ||
9ab21462 | 764 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
d38ceaf9 AD |
765 | /* only copy commands needed */ |
766 | ndw += ncmds * 7; | |
767 | ||
9ab21462 | 768 | } else if (gtt) { |
d38ceaf9 AD |
769 | /* header for write data commands */ |
770 | ndw += ncmds * 4; | |
771 | ||
772 | /* body of write data command */ | |
773 | ndw += nptes * 2; | |
774 | ||
775 | } else { | |
776 | /* set page commands needed */ | |
777 | ndw += ncmds * 10; | |
778 | ||
779 | /* two extra commands for begin/end of fragment */ | |
780 | ndw += 2 * 10; | |
781 | } | |
782 | ||
d71518b5 CK |
783 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
784 | if (r) | |
d38ceaf9 | 785 | return r; |
d71518b5 CK |
786 | |
787 | ib = &job->ibs[0]; | |
d5fc5e82 | 788 | |
e86f9cee | 789 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
790 | owner); |
791 | if (r) | |
792 | goto error_free; | |
d38ceaf9 | 793 | |
a1e08d3b CK |
794 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
795 | if (r) | |
796 | goto error_free; | |
797 | ||
798 | amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, last + 1, | |
799 | addr, flags); | |
d38ceaf9 | 800 | |
9e5d5309 | 801 | amdgpu_ring_pad_ib(ring, ib); |
d5fc5e82 | 802 | WARN_ON(ib->length_dw > ndw); |
2bd9ccfa CK |
803 | r = amdgpu_job_submit(job, ring, &vm->entity, |
804 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
805 | if (r) |
806 | goto error_free; | |
d38ceaf9 | 807 | |
bf60efd3 | 808 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
809 | if (fence) { |
810 | fence_put(*fence); | |
811 | *fence = fence_get(f); | |
812 | } | |
281b4223 | 813 | fence_put(f); |
d38ceaf9 | 814 | return 0; |
d5fc5e82 CZ |
815 | |
816 | error_free: | |
d71518b5 | 817 | amdgpu_job_free(job); |
4af9f07c | 818 | return r; |
d38ceaf9 AD |
819 | } |
820 | ||
a14faa65 CK |
821 | /** |
822 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
823 | * | |
824 | * @adev: amdgpu_device pointer | |
825 | * @gtt: GART instance to use for mapping | |
826 | * @vm: requested vm | |
827 | * @mapping: mapped range and flags to use for the update | |
828 | * @addr: addr to set the area to | |
829 | * @gtt_flags: flags as they are used for GTT | |
830 | * @fence: optional resulting fence | |
831 | * | |
832 | * Split the mapping into smaller chunks so that each update fits | |
833 | * into a SDMA IB. | |
834 | * Returns 0 for success, -EINVAL for failure. | |
835 | */ | |
836 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
837 | struct amdgpu_gart *gtt, | |
838 | uint32_t gtt_flags, | |
839 | struct amdgpu_vm *vm, | |
840 | struct amdgpu_bo_va_mapping *mapping, | |
841 | uint64_t addr, struct fence **fence) | |
842 | { | |
843 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
844 | ||
845 | uint64_t start = mapping->it.start; | |
846 | uint32_t flags = gtt_flags; | |
847 | int r; | |
848 | ||
849 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
850 | * but in case of something, we filter the flags in first place | |
851 | */ | |
852 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
853 | flags &= ~AMDGPU_PTE_READABLE; | |
854 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
855 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
856 | ||
857 | trace_amdgpu_vm_bo_update(mapping); | |
858 | ||
859 | addr += mapping->offset; | |
860 | ||
861 | if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags))) | |
862 | return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
863 | start, mapping->it.last, | |
864 | flags, addr, fence); | |
865 | ||
866 | while (start != mapping->it.last + 1) { | |
867 | uint64_t last; | |
868 | ||
869 | last = min((uint64_t)mapping->it.last, start + max_size); | |
870 | r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
871 | start, last, flags, addr, | |
872 | fence); | |
873 | if (r) | |
874 | return r; | |
875 | ||
876 | start = last + 1; | |
877 | addr += max_size; | |
878 | } | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
d38ceaf9 AD |
883 | /** |
884 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
885 | * | |
886 | * @adev: amdgpu_device pointer | |
887 | * @bo_va: requested BO and VM object | |
888 | * @mem: ttm mem | |
889 | * | |
890 | * Fill in the page table entries for @bo_va. | |
891 | * Returns 0 for success, -EINVAL for failure. | |
892 | * | |
893 | * Object have to be reserved and mutex must be locked! | |
894 | */ | |
895 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
896 | struct amdgpu_bo_va *bo_va, | |
897 | struct ttm_mem_reg *mem) | |
898 | { | |
899 | struct amdgpu_vm *vm = bo_va->vm; | |
900 | struct amdgpu_bo_va_mapping *mapping; | |
9ab21462 | 901 | struct amdgpu_gart *gtt = NULL; |
d38ceaf9 AD |
902 | uint32_t flags; |
903 | uint64_t addr; | |
904 | int r; | |
905 | ||
906 | if (mem) { | |
b7d698d7 | 907 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
908 | switch (mem->mem_type) { |
909 | case TTM_PL_TT: | |
910 | gtt = &bo_va->bo->adev->gart; | |
911 | break; | |
912 | ||
913 | case TTM_PL_VRAM: | |
d38ceaf9 | 914 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
915 | break; |
916 | ||
917 | default: | |
918 | break; | |
919 | } | |
d38ceaf9 AD |
920 | } else { |
921 | addr = 0; | |
922 | } | |
923 | ||
d38ceaf9 AD |
924 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
925 | ||
7fc11959 CK |
926 | spin_lock(&vm->status_lock); |
927 | if (!list_empty(&bo_va->vm_status)) | |
928 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
929 | spin_unlock(&vm->status_lock); | |
930 | ||
931 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a14faa65 CK |
932 | r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr, |
933 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
934 | if (r) |
935 | return r; | |
936 | } | |
937 | ||
d6c10f6b CK |
938 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
939 | list_for_each_entry(mapping, &bo_va->valids, list) | |
940 | trace_amdgpu_vm_bo_mapping(mapping); | |
941 | ||
942 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
943 | trace_amdgpu_vm_bo_mapping(mapping); | |
944 | } | |
945 | ||
d38ceaf9 | 946 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 947 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 948 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
949 | if (!mem) |
950 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
951 | spin_unlock(&vm->status_lock); |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | /** | |
957 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
958 | * | |
959 | * @adev: amdgpu_device pointer | |
960 | * @vm: requested vm | |
961 | * | |
962 | * Make sure all freed BOs are cleared in the PT. | |
963 | * Returns 0 for success. | |
964 | * | |
965 | * PTs have to be reserved and mutex must be locked! | |
966 | */ | |
967 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
968 | struct amdgpu_vm *vm) | |
969 | { | |
970 | struct amdgpu_bo_va_mapping *mapping; | |
971 | int r; | |
972 | ||
81d75a30 | 973 | spin_lock(&vm->freed_lock); |
d38ceaf9 AD |
974 | while (!list_empty(&vm->freed)) { |
975 | mapping = list_first_entry(&vm->freed, | |
976 | struct amdgpu_bo_va_mapping, list); | |
977 | list_del(&mapping->list); | |
81d75a30 | 978 | spin_unlock(&vm->freed_lock); |
a14faa65 CK |
979 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping, |
980 | 0, NULL); | |
d38ceaf9 AD |
981 | kfree(mapping); |
982 | if (r) | |
983 | return r; | |
984 | ||
81d75a30 | 985 | spin_lock(&vm->freed_lock); |
d38ceaf9 | 986 | } |
81d75a30 | 987 | spin_unlock(&vm->freed_lock); |
988 | ||
d38ceaf9 AD |
989 | return 0; |
990 | ||
991 | } | |
992 | ||
993 | /** | |
994 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
995 | * | |
996 | * @adev: amdgpu_device pointer | |
997 | * @vm: requested vm | |
998 | * | |
999 | * Make sure all invalidated BOs are cleared in the PT. | |
1000 | * Returns 0 for success. | |
1001 | * | |
1002 | * PTs have to be reserved and mutex must be locked! | |
1003 | */ | |
1004 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1005 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1006 | { |
cfe2c978 | 1007 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1008 | int r = 0; |
d38ceaf9 AD |
1009 | |
1010 | spin_lock(&vm->status_lock); | |
1011 | while (!list_empty(&vm->invalidated)) { | |
1012 | bo_va = list_first_entry(&vm->invalidated, | |
1013 | struct amdgpu_bo_va, vm_status); | |
1014 | spin_unlock(&vm->status_lock); | |
69b576a1 | 1015 | mutex_lock(&bo_va->mutex); |
d38ceaf9 | 1016 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
69b576a1 | 1017 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 AD |
1018 | if (r) |
1019 | return r; | |
1020 | ||
1021 | spin_lock(&vm->status_lock); | |
1022 | } | |
1023 | spin_unlock(&vm->status_lock); | |
1024 | ||
cfe2c978 | 1025 | if (bo_va) |
bb1e38a4 | 1026 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1027 | |
1028 | return r; | |
d38ceaf9 AD |
1029 | } |
1030 | ||
1031 | /** | |
1032 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1033 | * | |
1034 | * @adev: amdgpu_device pointer | |
1035 | * @vm: requested vm | |
1036 | * @bo: amdgpu buffer object | |
1037 | * | |
8843dbbb | 1038 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1039 | * Add @bo to the list of bos associated with the vm |
1040 | * Returns newly added bo_va or NULL for failure | |
1041 | * | |
1042 | * Object has to be reserved! | |
1043 | */ | |
1044 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1045 | struct amdgpu_vm *vm, | |
1046 | struct amdgpu_bo *bo) | |
1047 | { | |
1048 | struct amdgpu_bo_va *bo_va; | |
1049 | ||
1050 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1051 | if (bo_va == NULL) { | |
1052 | return NULL; | |
1053 | } | |
1054 | bo_va->vm = vm; | |
1055 | bo_va->bo = bo; | |
d38ceaf9 AD |
1056 | bo_va->ref_count = 1; |
1057 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1058 | INIT_LIST_HEAD(&bo_va->valids); |
1059 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1060 | INIT_LIST_HEAD(&bo_va->vm_status); |
69b576a1 | 1061 | mutex_init(&bo_va->mutex); |
d38ceaf9 | 1062 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1063 | |
1064 | return bo_va; | |
1065 | } | |
1066 | ||
1067 | /** | |
1068 | * amdgpu_vm_bo_map - map bo inside a vm | |
1069 | * | |
1070 | * @adev: amdgpu_device pointer | |
1071 | * @bo_va: bo_va to store the address | |
1072 | * @saddr: where to map the BO | |
1073 | * @offset: requested offset in the BO | |
1074 | * @flags: attributes of pages (read/write/valid/etc.) | |
1075 | * | |
1076 | * Add a mapping of the BO at the specefied addr into the VM. | |
1077 | * Returns 0 for success, error for failure. | |
1078 | * | |
49b02b18 | 1079 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1080 | */ |
1081 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1082 | struct amdgpu_bo_va *bo_va, | |
1083 | uint64_t saddr, uint64_t offset, | |
1084 | uint64_t size, uint32_t flags) | |
1085 | { | |
1086 | struct amdgpu_bo_va_mapping *mapping; | |
1087 | struct amdgpu_vm *vm = bo_va->vm; | |
1088 | struct interval_tree_node *it; | |
1089 | unsigned last_pfn, pt_idx; | |
1090 | uint64_t eaddr; | |
1091 | int r; | |
1092 | ||
0be52de9 CK |
1093 | /* validate the parameters */ |
1094 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1095 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1096 | return -EINVAL; |
0be52de9 | 1097 | |
d38ceaf9 | 1098 | /* make sure object fit at this offset */ |
005ae95e | 1099 | eaddr = saddr + size - 1; |
49b02b18 | 1100 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1101 | return -EINVAL; |
d38ceaf9 AD |
1102 | |
1103 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1104 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1105 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1106 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1107 | return -EINVAL; |
1108 | } | |
1109 | ||
d38ceaf9 AD |
1110 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1111 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1112 | ||
c25867df | 1113 | spin_lock(&vm->it_lock); |
005ae95e | 1114 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
c25867df | 1115 | spin_unlock(&vm->it_lock); |
d38ceaf9 AD |
1116 | if (it) { |
1117 | struct amdgpu_bo_va_mapping *tmp; | |
1118 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1119 | /* bo and tmp overlap, invalid addr */ | |
1120 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1121 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1122 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1123 | r = -EINVAL; |
f48b2659 | 1124 | goto error; |
d38ceaf9 AD |
1125 | } |
1126 | ||
1127 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1128 | if (!mapping) { | |
d38ceaf9 | 1129 | r = -ENOMEM; |
f48b2659 | 1130 | goto error; |
d38ceaf9 AD |
1131 | } |
1132 | ||
1133 | INIT_LIST_HEAD(&mapping->list); | |
1134 | mapping->it.start = saddr; | |
005ae95e | 1135 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1136 | mapping->offset = offset; |
1137 | mapping->flags = flags; | |
1138 | ||
69b576a1 | 1139 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1140 | list_add(&mapping->list, &bo_va->invalids); |
69b576a1 | 1141 | mutex_unlock(&bo_va->mutex); |
c25867df | 1142 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1143 | interval_tree_insert(&mapping->it, &vm->va); |
c25867df | 1144 | spin_unlock(&vm->it_lock); |
93e3e438 | 1145 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1146 | |
1147 | /* Make sure the page tables are allocated */ | |
1148 | saddr >>= amdgpu_vm_block_size; | |
1149 | eaddr >>= amdgpu_vm_block_size; | |
1150 | ||
1151 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1152 | ||
1153 | if (eaddr > vm->max_pde_used) | |
1154 | vm->max_pde_used = eaddr; | |
1155 | ||
d38ceaf9 AD |
1156 | /* walk over the address space and allocate the page tables */ |
1157 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1158 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1159 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1160 | struct amdgpu_bo *pt; |
1161 | ||
ee1782c3 CK |
1162 | entry = &vm->page_tables[pt_idx].entry; |
1163 | if (entry->robj) | |
d38ceaf9 AD |
1164 | continue; |
1165 | ||
d38ceaf9 AD |
1166 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1167 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1168 | AMDGPU_GEM_DOMAIN_VRAM, |
1169 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1170 | NULL, resv, &pt); |
49b02b18 | 1171 | if (r) |
d38ceaf9 | 1172 | goto error_free; |
49b02b18 | 1173 | |
82b9c55b CK |
1174 | /* Keep a reference to the page table to avoid freeing |
1175 | * them up in the wrong order. | |
1176 | */ | |
1177 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1178 | ||
2bd9ccfa | 1179 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1180 | if (r) { |
1181 | amdgpu_bo_unref(&pt); | |
1182 | goto error_free; | |
1183 | } | |
1184 | ||
ee1782c3 | 1185 | entry->robj = pt; |
ee1782c3 CK |
1186 | entry->priority = 0; |
1187 | entry->tv.bo = &entry->robj->tbo; | |
1188 | entry->tv.shared = true; | |
d38ceaf9 | 1189 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1190 | } |
1191 | ||
d38ceaf9 AD |
1192 | return 0; |
1193 | ||
1194 | error_free: | |
d38ceaf9 | 1195 | list_del(&mapping->list); |
c25867df | 1196 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1197 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1198 | spin_unlock(&vm->it_lock); |
93e3e438 | 1199 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1200 | kfree(mapping); |
1201 | ||
f48b2659 | 1202 | error: |
d38ceaf9 AD |
1203 | return r; |
1204 | } | |
1205 | ||
1206 | /** | |
1207 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1208 | * | |
1209 | * @adev: amdgpu_device pointer | |
1210 | * @bo_va: bo_va to remove the address from | |
1211 | * @saddr: where to the BO is mapped | |
1212 | * | |
1213 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1214 | * Returns 0 for success, error for failure. | |
1215 | * | |
49b02b18 | 1216 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1217 | */ |
1218 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1219 | struct amdgpu_bo_va *bo_va, | |
1220 | uint64_t saddr) | |
1221 | { | |
1222 | struct amdgpu_bo_va_mapping *mapping; | |
1223 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1224 | bool valid = true; |
d38ceaf9 | 1225 | |
6c7fc503 | 1226 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
69b576a1 | 1227 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1228 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1229 | if (mapping->it.start == saddr) |
1230 | break; | |
1231 | } | |
1232 | ||
7fc11959 CK |
1233 | if (&mapping->list == &bo_va->valids) { |
1234 | valid = false; | |
1235 | ||
1236 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1237 | if (mapping->it.start == saddr) | |
1238 | break; | |
1239 | } | |
1240 | ||
69b576a1 CZ |
1241 | if (&mapping->list == &bo_va->invalids) { |
1242 | mutex_unlock(&bo_va->mutex); | |
7fc11959 | 1243 | return -ENOENT; |
69b576a1 | 1244 | } |
d38ceaf9 | 1245 | } |
69b576a1 | 1246 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 | 1247 | list_del(&mapping->list); |
c25867df | 1248 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1249 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1250 | spin_unlock(&vm->it_lock); |
93e3e438 | 1251 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1252 | |
81d75a30 | 1253 | if (valid) { |
1254 | spin_lock(&vm->freed_lock); | |
d38ceaf9 | 1255 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1256 | spin_unlock(&vm->freed_lock); |
1257 | } else { | |
d38ceaf9 | 1258 | kfree(mapping); |
81d75a30 | 1259 | } |
d38ceaf9 AD |
1260 | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | /** | |
1265 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1266 | * | |
1267 | * @adev: amdgpu_device pointer | |
1268 | * @bo_va: requested bo_va | |
1269 | * | |
8843dbbb | 1270 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1271 | * |
1272 | * Object have to be reserved! | |
1273 | */ | |
1274 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1275 | struct amdgpu_bo_va *bo_va) | |
1276 | { | |
1277 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1278 | struct amdgpu_vm *vm = bo_va->vm; | |
1279 | ||
1280 | list_del(&bo_va->bo_list); | |
1281 | ||
d38ceaf9 AD |
1282 | spin_lock(&vm->status_lock); |
1283 | list_del(&bo_va->vm_status); | |
1284 | spin_unlock(&vm->status_lock); | |
1285 | ||
7fc11959 | 1286 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 1287 | list_del(&mapping->list); |
c25867df | 1288 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1289 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1290 | spin_unlock(&vm->it_lock); |
93e3e438 | 1291 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
81d75a30 | 1292 | spin_lock(&vm->freed_lock); |
7fc11959 | 1293 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1294 | spin_unlock(&vm->freed_lock); |
7fc11959 CK |
1295 | } |
1296 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1297 | list_del(&mapping->list); | |
c25867df | 1298 | spin_lock(&vm->it_lock); |
7fc11959 | 1299 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1300 | spin_unlock(&vm->it_lock); |
7fc11959 | 1301 | kfree(mapping); |
d38ceaf9 | 1302 | } |
bb1e38a4 | 1303 | fence_put(bo_va->last_pt_update); |
69b576a1 | 1304 | mutex_destroy(&bo_va->mutex); |
d38ceaf9 | 1305 | kfree(bo_va); |
d38ceaf9 AD |
1306 | } |
1307 | ||
1308 | /** | |
1309 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1310 | * | |
1311 | * @adev: amdgpu_device pointer | |
1312 | * @vm: requested vm | |
1313 | * @bo: amdgpu buffer object | |
1314 | * | |
8843dbbb | 1315 | * Mark @bo as invalid. |
d38ceaf9 AD |
1316 | */ |
1317 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1318 | struct amdgpu_bo *bo) | |
1319 | { | |
1320 | struct amdgpu_bo_va *bo_va; | |
1321 | ||
1322 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1323 | spin_lock(&bo_va->vm->status_lock); |
1324 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1325 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1326 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1327 | } |
1328 | } | |
1329 | ||
1330 | /** | |
1331 | * amdgpu_vm_init - initialize a vm instance | |
1332 | * | |
1333 | * @adev: amdgpu_device pointer | |
1334 | * @vm: requested vm | |
1335 | * | |
8843dbbb | 1336 | * Init @vm fields. |
d38ceaf9 AD |
1337 | */ |
1338 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1339 | { | |
1340 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1341 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1342 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1343 | unsigned ring_instance; |
1344 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1345 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1346 | int i, r; |
1347 | ||
1348 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4ff37a83 | 1349 | vm->ids[i].mgr_id = NULL; |
d38ceaf9 | 1350 | vm->ids[i].flushed_updates = NULL; |
d38ceaf9 | 1351 | } |
d38ceaf9 AD |
1352 | vm->va = RB_ROOT; |
1353 | spin_lock_init(&vm->status_lock); | |
1354 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1355 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1356 | INIT_LIST_HEAD(&vm->freed); |
c25867df | 1357 | spin_lock_init(&vm->it_lock); |
81d75a30 | 1358 | spin_lock_init(&vm->freed_lock); |
d38ceaf9 AD |
1359 | pd_size = amdgpu_vm_directory_size(adev); |
1360 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1361 | ||
1362 | /* allocate page table array */ | |
9571e1d8 | 1363 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1364 | if (vm->page_tables == NULL) { |
1365 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1366 | return -ENOMEM; | |
1367 | } | |
1368 | ||
2bd9ccfa | 1369 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1370 | |
1371 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1372 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1373 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1374 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1375 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1376 | rq, amdgpu_sched_jobs); | |
1377 | if (r) | |
1378 | return r; | |
1379 | ||
05906dec BN |
1380 | vm->page_directory_fence = NULL; |
1381 | ||
d38ceaf9 | 1382 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1383 | AMDGPU_GEM_DOMAIN_VRAM, |
1384 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1385 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1386 | if (r) |
2bd9ccfa CK |
1387 | goto error_free_sched_entity; |
1388 | ||
ef9f0a83 | 1389 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1390 | if (r) |
1391 | goto error_free_page_directory; | |
1392 | ||
1393 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1394 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1395 | if (r) |
1396 | goto error_free_page_directory; | |
d38ceaf9 AD |
1397 | |
1398 | return 0; | |
2bd9ccfa CK |
1399 | |
1400 | error_free_page_directory: | |
1401 | amdgpu_bo_unref(&vm->page_directory); | |
1402 | vm->page_directory = NULL; | |
1403 | ||
1404 | error_free_sched_entity: | |
1405 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1406 | ||
1407 | return r; | |
d38ceaf9 AD |
1408 | } |
1409 | ||
1410 | /** | |
1411 | * amdgpu_vm_fini - tear down a vm instance | |
1412 | * | |
1413 | * @adev: amdgpu_device pointer | |
1414 | * @vm: requested vm | |
1415 | * | |
8843dbbb | 1416 | * Tear down @vm. |
d38ceaf9 AD |
1417 | * Unbind the VM and remove all bos from the vm bo list |
1418 | */ | |
1419 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1420 | { | |
1421 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1422 | int i; | |
1423 | ||
2d55e45a | 1424 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1425 | |
d38ceaf9 AD |
1426 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1427 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1428 | } | |
1429 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1430 | list_del(&mapping->list); | |
1431 | interval_tree_remove(&mapping->it, &vm->va); | |
1432 | kfree(mapping); | |
1433 | } | |
1434 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1435 | list_del(&mapping->list); | |
1436 | kfree(mapping); | |
1437 | } | |
1438 | ||
1439 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1440 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1441 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1442 | |
1443 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1444 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1445 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4ff37a83 | 1446 | struct amdgpu_vm_id *id = &vm->ids[i]; |
1c16c0a7 | 1447 | |
4ff37a83 CK |
1448 | if (id->mgr_id) |
1449 | atomic_long_cmpxchg(&id->mgr_id->owner, | |
1450 | (long)id, 0); | |
1451 | fence_put(id->flushed_updates); | |
d38ceaf9 | 1452 | } |
d38ceaf9 | 1453 | } |
ea89f8c9 | 1454 | |
a9a78b32 CK |
1455 | /** |
1456 | * amdgpu_vm_manager_init - init the VM manager | |
1457 | * | |
1458 | * @adev: amdgpu_device pointer | |
1459 | * | |
1460 | * Initialize the VM manager structures | |
1461 | */ | |
1462 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1463 | { | |
1464 | unsigned i; | |
1465 | ||
1466 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1467 | ||
1468 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1469 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1470 | amdgpu_vm_reset_id(adev, i); | |
a9a78b32 CK |
1471 | list_add_tail(&adev->vm_manager.ids[i].list, |
1472 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1473 | } |
2d55e45a CK |
1474 | |
1475 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); | |
a9a78b32 CK |
1476 | } |
1477 | ||
ea89f8c9 CK |
1478 | /** |
1479 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1480 | * | |
1481 | * @adev: amdgpu_device pointer | |
1482 | * | |
1483 | * Cleanup the VM manager and free resources. | |
1484 | */ | |
1485 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1486 | { | |
1487 | unsigned i; | |
1488 | ||
1489 | for (i = 0; i < AMDGPU_NUM_VM; ++i) | |
1c16c0a7 | 1490 | fence_put(adev->vm_manager.ids[i].active); |
ea89f8c9 | 1491 | } |