Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
53 | /** | |
54 | * amdgpu_vm_num_pde - return the number of page directory entries | |
55 | * | |
56 | * @adev: amdgpu_device pointer | |
57 | * | |
58 | * Calculate the number of page directory entries (cayman+). | |
59 | */ | |
60 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
61 | { | |
62 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
63 | } | |
64 | ||
65 | /** | |
66 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
67 | * | |
68 | * @adev: amdgpu_device pointer | |
69 | * | |
70 | * Calculate the size of the page directory in bytes (cayman+). | |
71 | */ | |
72 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
73 | { | |
74 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
75 | } | |
76 | ||
77 | /** | |
56467ebf | 78 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
79 | * |
80 | * @vm: vm providing the BOs | |
3c0eea6c | 81 | * @validated: head of validation list |
56467ebf | 82 | * @entry: entry to add |
d38ceaf9 AD |
83 | * |
84 | * Add the page directory to the list of BOs to | |
56467ebf | 85 | * validate for command submission. |
d38ceaf9 | 86 | */ |
56467ebf CK |
87 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
88 | struct list_head *validated, | |
89 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 90 | { |
56467ebf | 91 | entry->robj = vm->page_directory; |
56467ebf CK |
92 | entry->priority = 0; |
93 | entry->tv.bo = &vm->page_directory->tbo; | |
94 | entry->tv.shared = true; | |
95 | list_add(&entry->tv.head, validated); | |
96 | } | |
d38ceaf9 | 97 | |
56467ebf | 98 | /** |
ee1782c3 | 99 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
100 | * |
101 | * @vm: vm providing the BOs | |
3c0eea6c | 102 | * @duplicates: head of duplicates list |
d38ceaf9 | 103 | * |
ee1782c3 CK |
104 | * Add the page directory to the BO duplicates list |
105 | * for command submission. | |
d38ceaf9 | 106 | */ |
ee1782c3 | 107 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 108 | { |
ee1782c3 | 109 | unsigned i; |
d38ceaf9 AD |
110 | |
111 | /* add the vm page table to the list */ | |
ee1782c3 CK |
112 | for (i = 0; i <= vm->max_pde_used; ++i) { |
113 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
114 | ||
115 | if (!entry->robj) | |
d38ceaf9 AD |
116 | continue; |
117 | ||
ee1782c3 | 118 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 119 | } |
eceb8a15 CK |
120 | |
121 | } | |
122 | ||
123 | /** | |
124 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
125 | * | |
126 | * @adev: amdgpu device instance | |
127 | * @vm: vm providing the BOs | |
128 | * | |
129 | * Move the PT BOs to the tail of the LRU. | |
130 | */ | |
131 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
132 | struct amdgpu_vm *vm) | |
133 | { | |
134 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
135 | unsigned i; | |
136 | ||
137 | spin_lock(&glob->lru_lock); | |
138 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
139 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
140 | ||
141 | if (!entry->robj) | |
142 | continue; | |
143 | ||
144 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
145 | } | |
146 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
147 | } |
148 | ||
149 | /** | |
150 | * amdgpu_vm_grab_id - allocate the next free VMID | |
151 | * | |
d38ceaf9 | 152 | * @vm: vm to allocate id for |
7f8a5290 CK |
153 | * @ring: ring we want to submit job to |
154 | * @sync: sync object where we add dependencies | |
94dd0a4a | 155 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 156 | * |
7f8a5290 | 157 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 158 | * |
7f8a5290 | 159 | * Global mutex must be locked! |
d38ceaf9 | 160 | */ |
7f8a5290 | 161 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
94dd0a4a | 162 | struct amdgpu_sync *sync, struct fence *fence) |
d38ceaf9 | 163 | { |
d38ceaf9 AD |
164 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; |
165 | struct amdgpu_device *adev = ring->adev; | |
a9a78b32 CK |
166 | struct amdgpu_vm_manager_id *id; |
167 | int r; | |
d38ceaf9 | 168 | |
94dd0a4a CK |
169 | mutex_lock(&adev->vm_manager.lock); |
170 | ||
d38ceaf9 | 171 | /* check if the id is still valid */ |
1c16c0a7 | 172 | if (vm_id->id) { |
1c16c0a7 CK |
173 | long owner; |
174 | ||
a9a78b32 CK |
175 | id = &adev->vm_manager.ids[vm_id->id]; |
176 | owner = atomic_long_read(&id->owner); | |
1c16c0a7 | 177 | if (owner == (long)vm) { |
a9a78b32 | 178 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
165e4e07 | 179 | trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx); |
d38ceaf9 | 180 | |
a9a78b32 CK |
181 | fence_put(id->active); |
182 | id->active = fence_get(fence); | |
d38ceaf9 | 183 | |
94dd0a4a | 184 | mutex_unlock(&adev->vm_manager.lock); |
7f8a5290 | 185 | return 0; |
d38ceaf9 | 186 | } |
d38ceaf9 AD |
187 | } |
188 | ||
a9a78b32 CK |
189 | /* we definately need to flush */ |
190 | vm_id->pd_gpu_addr = ~0ll; | |
7f8a5290 | 191 | |
a9a78b32 CK |
192 | id = list_first_entry(&adev->vm_manager.ids_lru, |
193 | struct amdgpu_vm_manager_id, | |
194 | list); | |
195 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); | |
196 | atomic_long_set(&id->owner, (long)vm); | |
94dd0a4a | 197 | |
a9a78b32 CK |
198 | vm_id->id = id - adev->vm_manager.ids; |
199 | trace_amdgpu_vm_grab_id(vm, vm_id->id, ring->idx); | |
94dd0a4a | 200 | |
a9a78b32 | 201 | r = amdgpu_sync_fence(ring->adev, sync, id->active); |
94dd0a4a | 202 | |
a9a78b32 CK |
203 | if (!r) { |
204 | fence_put(id->active); | |
205 | id->active = fence_get(fence); | |
d38ceaf9 AD |
206 | } |
207 | ||
94dd0a4a | 208 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 209 | return r; |
d38ceaf9 AD |
210 | } |
211 | ||
212 | /** | |
213 | * amdgpu_vm_flush - hardware flush the vm | |
214 | * | |
215 | * @ring: ring to use for flush | |
216 | * @vm: vm we want to flush | |
217 | * @updates: last vm update that we waited for | |
218 | * | |
219 | * Flush the vm (cayman+). | |
220 | * | |
221 | * Global and local mutex must be locked! | |
222 | */ | |
223 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
224 | struct amdgpu_vm *vm, | |
3c62338c | 225 | struct fence *updates) |
d38ceaf9 AD |
226 | { |
227 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
228 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; | |
3c62338c | 229 | struct fence *flushed_updates = vm_id->flushed_updates; |
b56c2285 | 230 | bool is_later; |
3c62338c | 231 | |
b56c2285 CK |
232 | if (!flushed_updates) |
233 | is_later = true; | |
234 | else if (!updates) | |
235 | is_later = false; | |
236 | else | |
237 | is_later = fence_is_later(updates, flushed_updates); | |
d38ceaf9 | 238 | |
b56c2285 | 239 | if (pd_addr != vm_id->pd_gpu_addr || is_later) { |
d38ceaf9 | 240 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); |
b56c2285 | 241 | if (is_later) { |
3c62338c CZ |
242 | vm_id->flushed_updates = fence_get(updates); |
243 | fence_put(flushed_updates); | |
244 | } | |
d38ceaf9 AD |
245 | vm_id->pd_gpu_addr = pd_addr; |
246 | amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); | |
247 | } | |
248 | } | |
249 | ||
d38ceaf9 AD |
250 | /** |
251 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
252 | * | |
253 | * @vm: requested vm | |
254 | * @bo: requested buffer object | |
255 | * | |
256 | * Find @bo inside the requested vm (cayman+). | |
257 | * Search inside the @bos vm list for the requested vm | |
258 | * Returns the found bo_va or NULL if none is found | |
259 | * | |
260 | * Object has to be reserved! | |
261 | */ | |
262 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
263 | struct amdgpu_bo *bo) | |
264 | { | |
265 | struct amdgpu_bo_va *bo_va; | |
266 | ||
267 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
268 | if (bo_va->vm == vm) { | |
269 | return bo_va; | |
270 | } | |
271 | } | |
272 | return NULL; | |
273 | } | |
274 | ||
275 | /** | |
276 | * amdgpu_vm_update_pages - helper to call the right asic function | |
277 | * | |
278 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
279 | * @gtt: GART instance to use for mapping |
280 | * @gtt_flags: GTT hw access flags | |
d38ceaf9 AD |
281 | * @ib: indirect buffer to fill with commands |
282 | * @pe: addr of the page entry | |
283 | * @addr: dst addr to write into pe | |
284 | * @count: number of page entries to update | |
285 | * @incr: increase next addr by incr bytes | |
286 | * @flags: hw access flags | |
d38ceaf9 AD |
287 | * |
288 | * Traces the parameters and calls the right asic functions | |
289 | * to setup the page table using the DMA. | |
290 | */ | |
291 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
9ab21462 CK |
292 | struct amdgpu_gart *gtt, |
293 | uint32_t gtt_flags, | |
d38ceaf9 AD |
294 | struct amdgpu_ib *ib, |
295 | uint64_t pe, uint64_t addr, | |
296 | unsigned count, uint32_t incr, | |
9ab21462 | 297 | uint32_t flags) |
d38ceaf9 AD |
298 | { |
299 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
300 | ||
9ab21462 CK |
301 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
302 | uint64_t src = gtt->table_addr + (addr >> 12) * 8; | |
d38ceaf9 AD |
303 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); |
304 | ||
9ab21462 CK |
305 | } else if (gtt) { |
306 | dma_addr_t *pages_addr = gtt->pages_addr; | |
b07c9d2a CK |
307 | amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr, |
308 | count, incr, flags); | |
309 | ||
310 | } else if (count < 3) { | |
311 | amdgpu_vm_write_pte(adev, ib, NULL, pe, addr, | |
312 | count, incr, flags); | |
d38ceaf9 AD |
313 | |
314 | } else { | |
315 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
316 | count, incr, flags); | |
317 | } | |
318 | } | |
319 | ||
4c7eb91c | 320 | int amdgpu_vm_free_job(struct amdgpu_job *job) |
d5fc5e82 CZ |
321 | { |
322 | int i; | |
4c7eb91c JZ |
323 | for (i = 0; i < job->num_ibs; i++) |
324 | amdgpu_ib_free(job->adev, &job->ibs[i]); | |
325 | kfree(job->ibs); | |
d5fc5e82 CZ |
326 | return 0; |
327 | } | |
328 | ||
d38ceaf9 AD |
329 | /** |
330 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
331 | * | |
332 | * @adev: amdgpu_device pointer | |
333 | * @bo: bo to clear | |
ef9f0a83 CZ |
334 | * |
335 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
336 | */ |
337 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
338 | struct amdgpu_bo *bo) | |
339 | { | |
340 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
4af9f07c | 341 | struct fence *fence = NULL; |
d5fc5e82 | 342 | struct amdgpu_ib *ib; |
d38ceaf9 AD |
343 | unsigned entries; |
344 | uint64_t addr; | |
345 | int r; | |
346 | ||
ca952613 | 347 | r = reservation_object_reserve_shared(bo->tbo.resv); |
348 | if (r) | |
349 | return r; | |
350 | ||
d38ceaf9 AD |
351 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
352 | if (r) | |
ef9f0a83 | 353 | goto error; |
d38ceaf9 AD |
354 | |
355 | addr = amdgpu_bo_gpu_offset(bo); | |
356 | entries = amdgpu_bo_size(bo) / 8; | |
357 | ||
d5fc5e82 CZ |
358 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
359 | if (!ib) | |
ef9f0a83 | 360 | goto error; |
d38ceaf9 | 361 | |
d5fc5e82 | 362 | r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); |
d38ceaf9 AD |
363 | if (r) |
364 | goto error_free; | |
365 | ||
d5fc5e82 CZ |
366 | ib->length_dw = 0; |
367 | ||
9ab21462 CK |
368 | amdgpu_vm_update_pages(adev, NULL, 0, ib, addr, 0, entries, 0, 0); |
369 | ||
d5fc5e82 CZ |
370 | amdgpu_vm_pad_ib(adev, ib); |
371 | WARN_ON(ib->length_dw > 64); | |
4af9f07c CZ |
372 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
373 | &amdgpu_vm_free_job, | |
374 | AMDGPU_FENCE_OWNER_VM, | |
375 | &fence); | |
376 | if (!r) | |
377 | amdgpu_bo_fence(bo, fence, true); | |
281b4223 | 378 | fence_put(fence); |
cadf97b1 | 379 | return 0; |
ef9f0a83 | 380 | |
d38ceaf9 | 381 | error_free: |
d5fc5e82 CZ |
382 | amdgpu_ib_free(adev, ib); |
383 | kfree(ib); | |
d38ceaf9 | 384 | |
ef9f0a83 | 385 | error: |
d38ceaf9 AD |
386 | return r; |
387 | } | |
388 | ||
389 | /** | |
b07c9d2a | 390 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 391 | * |
b07c9d2a | 392 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
393 | * @addr: the unmapped addr |
394 | * | |
395 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 396 | * to and return the pointer for the page table entry. |
d38ceaf9 | 397 | */ |
b07c9d2a | 398 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
399 | { |
400 | uint64_t result; | |
401 | ||
b07c9d2a CK |
402 | if (pages_addr) { |
403 | /* page table offset */ | |
404 | result = pages_addr[addr >> PAGE_SHIFT]; | |
405 | ||
406 | /* in case cpu page size != gpu page size*/ | |
407 | result |= addr & (~PAGE_MASK); | |
408 | ||
409 | } else { | |
410 | /* No mapping required */ | |
411 | result = addr; | |
412 | } | |
d38ceaf9 | 413 | |
b07c9d2a | 414 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
415 | |
416 | return result; | |
417 | } | |
418 | ||
419 | /** | |
420 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
421 | * | |
422 | * @adev: amdgpu_device pointer | |
423 | * @vm: requested vm | |
424 | * @start: start of GPU address range | |
425 | * @end: end of GPU address range | |
426 | * | |
427 | * Allocates new page tables if necessary | |
428 | * and updates the page directory (cayman+). | |
429 | * Returns 0 for success, error for failure. | |
430 | * | |
431 | * Global and local mutex must be locked! | |
432 | */ | |
433 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
434 | struct amdgpu_vm *vm) | |
435 | { | |
436 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
437 | struct amdgpu_bo *pd = vm->page_directory; | |
438 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
439 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
440 | uint64_t last_pde = ~0, last_pt = ~0; | |
441 | unsigned count = 0, pt_idx, ndw; | |
d5fc5e82 | 442 | struct amdgpu_ib *ib; |
4af9f07c | 443 | struct fence *fence = NULL; |
d5fc5e82 | 444 | |
d38ceaf9 AD |
445 | int r; |
446 | ||
447 | /* padding, etc. */ | |
448 | ndw = 64; | |
449 | ||
450 | /* assume the worst case */ | |
451 | ndw += vm->max_pde_used * 6; | |
452 | ||
d5fc5e82 CZ |
453 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
454 | if (!ib) | |
455 | return -ENOMEM; | |
456 | ||
457 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
7a574557 SM |
458 | if (r) { |
459 | kfree(ib); | |
d38ceaf9 | 460 | return r; |
7a574557 | 461 | } |
d5fc5e82 | 462 | ib->length_dw = 0; |
d38ceaf9 AD |
463 | |
464 | /* walk over the address space and update the page directory */ | |
465 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 466 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
467 | uint64_t pde, pt; |
468 | ||
469 | if (bo == NULL) | |
470 | continue; | |
471 | ||
472 | pt = amdgpu_bo_gpu_offset(bo); | |
473 | if (vm->page_tables[pt_idx].addr == pt) | |
474 | continue; | |
475 | vm->page_tables[pt_idx].addr = pt; | |
476 | ||
477 | pde = pd_addr + pt_idx * 8; | |
478 | if (((last_pde + 8 * count) != pde) || | |
479 | ((last_pt + incr * count) != pt)) { | |
480 | ||
481 | if (count) { | |
9ab21462 CK |
482 | amdgpu_vm_update_pages(adev, NULL, 0, ib, |
483 | last_pde, last_pt, | |
484 | count, incr, | |
485 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
486 | } |
487 | ||
488 | count = 1; | |
489 | last_pde = pde; | |
490 | last_pt = pt; | |
491 | } else { | |
492 | ++count; | |
493 | } | |
494 | } | |
495 | ||
496 | if (count) | |
9ab21462 CK |
497 | amdgpu_vm_update_pages(adev, NULL, 0, ib, last_pde, last_pt, |
498 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 499 | |
d5fc5e82 CZ |
500 | if (ib->length_dw != 0) { |
501 | amdgpu_vm_pad_ib(adev, ib); | |
502 | amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); | |
503 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
504 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
505 | &amdgpu_vm_free_job, | |
506 | AMDGPU_FENCE_OWNER_VM, | |
507 | &fence); | |
508 | if (r) | |
509 | goto error_free; | |
05906dec | 510 | |
4af9f07c | 511 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
512 | fence_put(vm->page_directory_fence); |
513 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 514 | fence_put(fence); |
d38ceaf9 | 515 | } |
d5fc5e82 | 516 | |
cadf97b1 | 517 | if (ib->length_dw == 0) { |
d5fc5e82 CZ |
518 | amdgpu_ib_free(adev, ib); |
519 | kfree(ib); | |
520 | } | |
d38ceaf9 AD |
521 | |
522 | return 0; | |
d5fc5e82 CZ |
523 | |
524 | error_free: | |
d5fc5e82 CZ |
525 | amdgpu_ib_free(adev, ib); |
526 | kfree(ib); | |
4af9f07c | 527 | return r; |
d38ceaf9 AD |
528 | } |
529 | ||
530 | /** | |
531 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
532 | * | |
533 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
534 | * @gtt: GART instance to use for mapping |
535 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
536 | * @ib: IB for the update |
537 | * @pe_start: first PTE to handle | |
538 | * @pe_end: last PTE to handle | |
539 | * @addr: addr those PTEs should point to | |
540 | * @flags: hw mapping flags | |
d38ceaf9 AD |
541 | * |
542 | * Global and local mutex must be locked! | |
543 | */ | |
544 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
9ab21462 CK |
545 | struct amdgpu_gart *gtt, |
546 | uint32_t gtt_flags, | |
d38ceaf9 AD |
547 | struct amdgpu_ib *ib, |
548 | uint64_t pe_start, uint64_t pe_end, | |
9ab21462 | 549 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
550 | { |
551 | /** | |
552 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
553 | * field in the PTE. When this field is set to a non-zero value, page | |
554 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
555 | * flags are considered valid for all PTEs within the fragment range | |
556 | * and corresponding mappings are assumed to be physically contiguous. | |
557 | * | |
558 | * The L1 TLB can store a single PTE for the whole fragment, | |
559 | * significantly increasing the space available for translation | |
560 | * caching. This leads to large improvements in throughput when the | |
561 | * TLB is under pressure. | |
562 | * | |
563 | * The L2 TLB distributes small and large fragments into two | |
564 | * asymmetric partitions. The large fragment cache is significantly | |
565 | * larger. Thus, we try to use large fragments wherever possible. | |
566 | * Userspace can support this by aligning virtual base address and | |
567 | * allocation size to the fragment size. | |
568 | */ | |
569 | ||
570 | /* SI and newer are optimized for 64KB */ | |
571 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
572 | uint64_t frag_align = 0x80; | |
573 | ||
574 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
575 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
576 | ||
577 | unsigned count; | |
578 | ||
579 | /* system pages are non continuously */ | |
9ab21462 | 580 | if (gtt || !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { |
d38ceaf9 AD |
581 | |
582 | count = (pe_end - pe_start) / 8; | |
9ab21462 CK |
583 | amdgpu_vm_update_pages(adev, gtt, gtt_flags, ib, pe_start, |
584 | addr, count, AMDGPU_GPU_PAGE_SIZE, | |
585 | flags); | |
d38ceaf9 AD |
586 | return; |
587 | } | |
588 | ||
589 | /* handle the 4K area at the beginning */ | |
590 | if (pe_start != frag_start) { | |
591 | count = (frag_start - pe_start) / 8; | |
9ab21462 CK |
592 | amdgpu_vm_update_pages(adev, NULL, 0, ib, pe_start, addr, |
593 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
594 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
595 | } | |
596 | ||
597 | /* handle the area in the middle */ | |
598 | count = (frag_end - frag_start) / 8; | |
9ab21462 CK |
599 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_start, addr, count, |
600 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); | |
d38ceaf9 AD |
601 | |
602 | /* handle the 4K area at the end */ | |
603 | if (frag_end != pe_end) { | |
604 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
605 | count = (pe_end - frag_end) / 8; | |
9ab21462 CK |
606 | amdgpu_vm_update_pages(adev, NULL, 0, ib, frag_end, addr, |
607 | count, AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
608 | } |
609 | } | |
610 | ||
611 | /** | |
612 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
613 | * | |
614 | * @adev: amdgpu_device pointer | |
9ab21462 CK |
615 | * @gtt: GART instance to use for mapping |
616 | * @gtt_flags: GTT hw mapping flags | |
d38ceaf9 AD |
617 | * @vm: requested vm |
618 | * @start: start of GPU address range | |
619 | * @end: end of GPU address range | |
620 | * @dst: destination address to map to | |
621 | * @flags: mapping flags | |
622 | * | |
623 | * Update the page tables in the range @start - @end (cayman+). | |
624 | * | |
625 | * Global and local mutex must be locked! | |
626 | */ | |
627 | static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, | |
9ab21462 CK |
628 | struct amdgpu_gart *gtt, |
629 | uint32_t gtt_flags, | |
d38ceaf9 AD |
630 | struct amdgpu_vm *vm, |
631 | struct amdgpu_ib *ib, | |
632 | uint64_t start, uint64_t end, | |
9ab21462 | 633 | uint64_t dst, uint32_t flags) |
d38ceaf9 AD |
634 | { |
635 | uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; | |
636 | uint64_t last_pte = ~0, last_dst = ~0; | |
a60c4232 | 637 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
638 | unsigned count = 0; |
639 | uint64_t addr; | |
640 | ||
a60c4232 CK |
641 | /* sync to everything on unmapping */ |
642 | if (!(flags & AMDGPU_PTE_VALID)) | |
643 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
644 | ||
d38ceaf9 AD |
645 | /* walk over the address space and update the page tables */ |
646 | for (addr = start; addr < end; ) { | |
647 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 648 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
649 | unsigned nptes; |
650 | uint64_t pte; | |
651 | int r; | |
652 | ||
a60c4232 | 653 | amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner); |
d38ceaf9 AD |
654 | r = reservation_object_reserve_shared(pt->tbo.resv); |
655 | if (r) | |
656 | return r; | |
657 | ||
658 | if ((addr & ~mask) == (end & ~mask)) | |
659 | nptes = end - addr; | |
660 | else | |
661 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
662 | ||
663 | pte = amdgpu_bo_gpu_offset(pt); | |
664 | pte += (addr & mask) * 8; | |
665 | ||
666 | if ((last_pte + 8 * count) != pte) { | |
667 | ||
668 | if (count) { | |
9ab21462 CK |
669 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
670 | last_pte, last_pte + 8 * count, | |
671 | last_dst, flags); | |
d38ceaf9 AD |
672 | } |
673 | ||
674 | count = nptes; | |
675 | last_pte = pte; | |
676 | last_dst = dst; | |
677 | } else { | |
678 | count += nptes; | |
679 | } | |
680 | ||
681 | addr += nptes; | |
682 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
683 | } | |
684 | ||
685 | if (count) { | |
9ab21462 CK |
686 | amdgpu_vm_frag_ptes(adev, gtt, gtt_flags, ib, |
687 | last_pte, last_pte + 8 * count, | |
688 | last_dst, flags); | |
d38ceaf9 AD |
689 | } |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
d38ceaf9 AD |
694 | /** |
695 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
696 | * | |
697 | * @adev: amdgpu_device pointer | |
9ab21462 | 698 | * @gtt: GART instance to use for mapping |
a14faa65 | 699 | * @gtt_flags: flags as they are used for GTT |
d38ceaf9 | 700 | * @vm: requested vm |
a14faa65 CK |
701 | * @start: start of mapped range |
702 | * @last: last mapped entry | |
703 | * @flags: flags for the entries | |
d38ceaf9 | 704 | * @addr: addr to set the area to |
d38ceaf9 AD |
705 | * @fence: optional resulting fence |
706 | * | |
a14faa65 | 707 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 708 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
709 | */ |
710 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
9ab21462 CK |
711 | struct amdgpu_gart *gtt, |
712 | uint32_t gtt_flags, | |
d38ceaf9 | 713 | struct amdgpu_vm *vm, |
a14faa65 CK |
714 | uint64_t start, uint64_t last, |
715 | uint32_t flags, uint64_t addr, | |
716 | struct fence **fence) | |
d38ceaf9 AD |
717 | { |
718 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
719 | unsigned nptes, ncmds, ndw; | |
d5fc5e82 | 720 | struct amdgpu_ib *ib; |
4af9f07c | 721 | struct fence *f = NULL; |
d38ceaf9 AD |
722 | int r; |
723 | ||
a14faa65 | 724 | nptes = last - start + 1; |
d38ceaf9 AD |
725 | |
726 | /* | |
727 | * reserve space for one command every (1 << BLOCK_SIZE) | |
728 | * entries or 2k dwords (whatever is smaller) | |
729 | */ | |
730 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
731 | ||
732 | /* padding, etc. */ | |
733 | ndw = 64; | |
734 | ||
9ab21462 | 735 | if ((gtt == &adev->gart) && (flags == gtt_flags)) { |
d38ceaf9 AD |
736 | /* only copy commands needed */ |
737 | ndw += ncmds * 7; | |
738 | ||
9ab21462 | 739 | } else if (gtt) { |
d38ceaf9 AD |
740 | /* header for write data commands */ |
741 | ndw += ncmds * 4; | |
742 | ||
743 | /* body of write data command */ | |
744 | ndw += nptes * 2; | |
745 | ||
746 | } else { | |
747 | /* set page commands needed */ | |
748 | ndw += ncmds * 10; | |
749 | ||
750 | /* two extra commands for begin/end of fragment */ | |
751 | ndw += 2 * 10; | |
752 | } | |
753 | ||
d5fc5e82 CZ |
754 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
755 | if (!ib) | |
756 | return -ENOMEM; | |
757 | ||
758 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
759 | if (r) { | |
760 | kfree(ib); | |
d38ceaf9 | 761 | return r; |
d5fc5e82 CZ |
762 | } |
763 | ||
764 | ib->length_dw = 0; | |
d38ceaf9 | 765 | |
a14faa65 CK |
766 | r = amdgpu_vm_update_ptes(adev, gtt, gtt_flags, vm, ib, start, |
767 | last + 1, addr, flags); | |
d38ceaf9 | 768 | if (r) { |
d5fc5e82 CZ |
769 | amdgpu_ib_free(adev, ib); |
770 | kfree(ib); | |
d38ceaf9 AD |
771 | return r; |
772 | } | |
773 | ||
d5fc5e82 CZ |
774 | amdgpu_vm_pad_ib(adev, ib); |
775 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
776 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
777 | &amdgpu_vm_free_job, | |
778 | AMDGPU_FENCE_OWNER_VM, | |
779 | &f); | |
780 | if (r) | |
781 | goto error_free; | |
d38ceaf9 | 782 | |
bf60efd3 | 783 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
784 | if (fence) { |
785 | fence_put(*fence); | |
786 | *fence = fence_get(f); | |
787 | } | |
281b4223 | 788 | fence_put(f); |
d38ceaf9 | 789 | return 0; |
d5fc5e82 CZ |
790 | |
791 | error_free: | |
d5fc5e82 CZ |
792 | amdgpu_ib_free(adev, ib); |
793 | kfree(ib); | |
4af9f07c | 794 | return r; |
d38ceaf9 AD |
795 | } |
796 | ||
a14faa65 CK |
797 | /** |
798 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
799 | * | |
800 | * @adev: amdgpu_device pointer | |
801 | * @gtt: GART instance to use for mapping | |
802 | * @vm: requested vm | |
803 | * @mapping: mapped range and flags to use for the update | |
804 | * @addr: addr to set the area to | |
805 | * @gtt_flags: flags as they are used for GTT | |
806 | * @fence: optional resulting fence | |
807 | * | |
808 | * Split the mapping into smaller chunks so that each update fits | |
809 | * into a SDMA IB. | |
810 | * Returns 0 for success, -EINVAL for failure. | |
811 | */ | |
812 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
813 | struct amdgpu_gart *gtt, | |
814 | uint32_t gtt_flags, | |
815 | struct amdgpu_vm *vm, | |
816 | struct amdgpu_bo_va_mapping *mapping, | |
817 | uint64_t addr, struct fence **fence) | |
818 | { | |
819 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
820 | ||
821 | uint64_t start = mapping->it.start; | |
822 | uint32_t flags = gtt_flags; | |
823 | int r; | |
824 | ||
825 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
826 | * but in case of something, we filter the flags in first place | |
827 | */ | |
828 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
829 | flags &= ~AMDGPU_PTE_READABLE; | |
830 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
831 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
832 | ||
833 | trace_amdgpu_vm_bo_update(mapping); | |
834 | ||
835 | addr += mapping->offset; | |
836 | ||
837 | if (!gtt || ((gtt == &adev->gart) && (flags == gtt_flags))) | |
838 | return amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
839 | start, mapping->it.last, | |
840 | flags, addr, fence); | |
841 | ||
842 | while (start != mapping->it.last + 1) { | |
843 | uint64_t last; | |
844 | ||
845 | last = min((uint64_t)mapping->it.last, start + max_size); | |
846 | r = amdgpu_vm_bo_update_mapping(adev, gtt, gtt_flags, vm, | |
847 | start, last, flags, addr, | |
848 | fence); | |
849 | if (r) | |
850 | return r; | |
851 | ||
852 | start = last + 1; | |
853 | addr += max_size; | |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
d38ceaf9 AD |
859 | /** |
860 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
861 | * | |
862 | * @adev: amdgpu_device pointer | |
863 | * @bo_va: requested BO and VM object | |
864 | * @mem: ttm mem | |
865 | * | |
866 | * Fill in the page table entries for @bo_va. | |
867 | * Returns 0 for success, -EINVAL for failure. | |
868 | * | |
869 | * Object have to be reserved and mutex must be locked! | |
870 | */ | |
871 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
872 | struct amdgpu_bo_va *bo_va, | |
873 | struct ttm_mem_reg *mem) | |
874 | { | |
875 | struct amdgpu_vm *vm = bo_va->vm; | |
876 | struct amdgpu_bo_va_mapping *mapping; | |
9ab21462 | 877 | struct amdgpu_gart *gtt = NULL; |
d38ceaf9 AD |
878 | uint32_t flags; |
879 | uint64_t addr; | |
880 | int r; | |
881 | ||
882 | if (mem) { | |
b7d698d7 | 883 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
884 | switch (mem->mem_type) { |
885 | case TTM_PL_TT: | |
886 | gtt = &bo_va->bo->adev->gart; | |
887 | break; | |
888 | ||
889 | case TTM_PL_VRAM: | |
d38ceaf9 | 890 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
891 | break; |
892 | ||
893 | default: | |
894 | break; | |
895 | } | |
d38ceaf9 AD |
896 | } else { |
897 | addr = 0; | |
898 | } | |
899 | ||
d38ceaf9 AD |
900 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
901 | ||
7fc11959 CK |
902 | spin_lock(&vm->status_lock); |
903 | if (!list_empty(&bo_va->vm_status)) | |
904 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
905 | spin_unlock(&vm->status_lock); | |
906 | ||
907 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a14faa65 CK |
908 | r = amdgpu_vm_bo_split_mapping(adev, gtt, flags, vm, mapping, addr, |
909 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
910 | if (r) |
911 | return r; | |
912 | } | |
913 | ||
d6c10f6b CK |
914 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
915 | list_for_each_entry(mapping, &bo_va->valids, list) | |
916 | trace_amdgpu_vm_bo_mapping(mapping); | |
917 | ||
918 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
919 | trace_amdgpu_vm_bo_mapping(mapping); | |
920 | } | |
921 | ||
d38ceaf9 | 922 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 923 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 924 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
925 | if (!mem) |
926 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
927 | spin_unlock(&vm->status_lock); |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | /** | |
933 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
934 | * | |
935 | * @adev: amdgpu_device pointer | |
936 | * @vm: requested vm | |
937 | * | |
938 | * Make sure all freed BOs are cleared in the PT. | |
939 | * Returns 0 for success. | |
940 | * | |
941 | * PTs have to be reserved and mutex must be locked! | |
942 | */ | |
943 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
944 | struct amdgpu_vm *vm) | |
945 | { | |
946 | struct amdgpu_bo_va_mapping *mapping; | |
947 | int r; | |
948 | ||
81d75a30 | 949 | spin_lock(&vm->freed_lock); |
d38ceaf9 AD |
950 | while (!list_empty(&vm->freed)) { |
951 | mapping = list_first_entry(&vm->freed, | |
952 | struct amdgpu_bo_va_mapping, list); | |
953 | list_del(&mapping->list); | |
81d75a30 | 954 | spin_unlock(&vm->freed_lock); |
a14faa65 CK |
955 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, vm, mapping, |
956 | 0, NULL); | |
d38ceaf9 AD |
957 | kfree(mapping); |
958 | if (r) | |
959 | return r; | |
960 | ||
81d75a30 | 961 | spin_lock(&vm->freed_lock); |
d38ceaf9 | 962 | } |
81d75a30 | 963 | spin_unlock(&vm->freed_lock); |
964 | ||
d38ceaf9 AD |
965 | return 0; |
966 | ||
967 | } | |
968 | ||
969 | /** | |
970 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
971 | * | |
972 | * @adev: amdgpu_device pointer | |
973 | * @vm: requested vm | |
974 | * | |
975 | * Make sure all invalidated BOs are cleared in the PT. | |
976 | * Returns 0 for success. | |
977 | * | |
978 | * PTs have to be reserved and mutex must be locked! | |
979 | */ | |
980 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 981 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 982 | { |
cfe2c978 | 983 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 984 | int r = 0; |
d38ceaf9 AD |
985 | |
986 | spin_lock(&vm->status_lock); | |
987 | while (!list_empty(&vm->invalidated)) { | |
988 | bo_va = list_first_entry(&vm->invalidated, | |
989 | struct amdgpu_bo_va, vm_status); | |
990 | spin_unlock(&vm->status_lock); | |
69b576a1 | 991 | mutex_lock(&bo_va->mutex); |
d38ceaf9 | 992 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
69b576a1 | 993 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 AD |
994 | if (r) |
995 | return r; | |
996 | ||
997 | spin_lock(&vm->status_lock); | |
998 | } | |
999 | spin_unlock(&vm->status_lock); | |
1000 | ||
cfe2c978 | 1001 | if (bo_va) |
bb1e38a4 | 1002 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1003 | |
1004 | return r; | |
d38ceaf9 AD |
1005 | } |
1006 | ||
1007 | /** | |
1008 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1009 | * | |
1010 | * @adev: amdgpu_device pointer | |
1011 | * @vm: requested vm | |
1012 | * @bo: amdgpu buffer object | |
1013 | * | |
1014 | * Add @bo into the requested vm (cayman+). | |
1015 | * Add @bo to the list of bos associated with the vm | |
1016 | * Returns newly added bo_va or NULL for failure | |
1017 | * | |
1018 | * Object has to be reserved! | |
1019 | */ | |
1020 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1021 | struct amdgpu_vm *vm, | |
1022 | struct amdgpu_bo *bo) | |
1023 | { | |
1024 | struct amdgpu_bo_va *bo_va; | |
1025 | ||
1026 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1027 | if (bo_va == NULL) { | |
1028 | return NULL; | |
1029 | } | |
1030 | bo_va->vm = vm; | |
1031 | bo_va->bo = bo; | |
d38ceaf9 AD |
1032 | bo_va->ref_count = 1; |
1033 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1034 | INIT_LIST_HEAD(&bo_va->valids); |
1035 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1036 | INIT_LIST_HEAD(&bo_va->vm_status); |
69b576a1 | 1037 | mutex_init(&bo_va->mutex); |
d38ceaf9 | 1038 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1039 | |
1040 | return bo_va; | |
1041 | } | |
1042 | ||
1043 | /** | |
1044 | * amdgpu_vm_bo_map - map bo inside a vm | |
1045 | * | |
1046 | * @adev: amdgpu_device pointer | |
1047 | * @bo_va: bo_va to store the address | |
1048 | * @saddr: where to map the BO | |
1049 | * @offset: requested offset in the BO | |
1050 | * @flags: attributes of pages (read/write/valid/etc.) | |
1051 | * | |
1052 | * Add a mapping of the BO at the specefied addr into the VM. | |
1053 | * Returns 0 for success, error for failure. | |
1054 | * | |
49b02b18 | 1055 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1056 | */ |
1057 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1058 | struct amdgpu_bo_va *bo_va, | |
1059 | uint64_t saddr, uint64_t offset, | |
1060 | uint64_t size, uint32_t flags) | |
1061 | { | |
1062 | struct amdgpu_bo_va_mapping *mapping; | |
1063 | struct amdgpu_vm *vm = bo_va->vm; | |
1064 | struct interval_tree_node *it; | |
1065 | unsigned last_pfn, pt_idx; | |
1066 | uint64_t eaddr; | |
1067 | int r; | |
1068 | ||
0be52de9 CK |
1069 | /* validate the parameters */ |
1070 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1071 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1072 | return -EINVAL; |
0be52de9 | 1073 | |
d38ceaf9 | 1074 | /* make sure object fit at this offset */ |
005ae95e | 1075 | eaddr = saddr + size - 1; |
49b02b18 | 1076 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1077 | return -EINVAL; |
d38ceaf9 AD |
1078 | |
1079 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1080 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1081 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1082 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1083 | return -EINVAL; |
1084 | } | |
1085 | ||
d38ceaf9 AD |
1086 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1087 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1088 | ||
c25867df | 1089 | spin_lock(&vm->it_lock); |
005ae95e | 1090 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
c25867df | 1091 | spin_unlock(&vm->it_lock); |
d38ceaf9 AD |
1092 | if (it) { |
1093 | struct amdgpu_bo_va_mapping *tmp; | |
1094 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1095 | /* bo and tmp overlap, invalid addr */ | |
1096 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1097 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1098 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1099 | r = -EINVAL; |
f48b2659 | 1100 | goto error; |
d38ceaf9 AD |
1101 | } |
1102 | ||
1103 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1104 | if (!mapping) { | |
d38ceaf9 | 1105 | r = -ENOMEM; |
f48b2659 | 1106 | goto error; |
d38ceaf9 AD |
1107 | } |
1108 | ||
1109 | INIT_LIST_HEAD(&mapping->list); | |
1110 | mapping->it.start = saddr; | |
005ae95e | 1111 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1112 | mapping->offset = offset; |
1113 | mapping->flags = flags; | |
1114 | ||
69b576a1 | 1115 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1116 | list_add(&mapping->list, &bo_va->invalids); |
69b576a1 | 1117 | mutex_unlock(&bo_va->mutex); |
c25867df | 1118 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1119 | interval_tree_insert(&mapping->it, &vm->va); |
c25867df | 1120 | spin_unlock(&vm->it_lock); |
93e3e438 | 1121 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1122 | |
1123 | /* Make sure the page tables are allocated */ | |
1124 | saddr >>= amdgpu_vm_block_size; | |
1125 | eaddr >>= amdgpu_vm_block_size; | |
1126 | ||
1127 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1128 | ||
1129 | if (eaddr > vm->max_pde_used) | |
1130 | vm->max_pde_used = eaddr; | |
1131 | ||
d38ceaf9 AD |
1132 | /* walk over the address space and allocate the page tables */ |
1133 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1134 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1135 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1136 | struct amdgpu_bo *pt; |
1137 | ||
ee1782c3 CK |
1138 | entry = &vm->page_tables[pt_idx].entry; |
1139 | if (entry->robj) | |
d38ceaf9 AD |
1140 | continue; |
1141 | ||
d38ceaf9 AD |
1142 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1143 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1144 | AMDGPU_GEM_DOMAIN_VRAM, |
1145 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1146 | NULL, resv, &pt); |
49b02b18 | 1147 | if (r) |
d38ceaf9 | 1148 | goto error_free; |
49b02b18 | 1149 | |
82b9c55b CK |
1150 | /* Keep a reference to the page table to avoid freeing |
1151 | * them up in the wrong order. | |
1152 | */ | |
1153 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1154 | ||
d38ceaf9 AD |
1155 | r = amdgpu_vm_clear_bo(adev, pt); |
1156 | if (r) { | |
1157 | amdgpu_bo_unref(&pt); | |
1158 | goto error_free; | |
1159 | } | |
1160 | ||
ee1782c3 | 1161 | entry->robj = pt; |
ee1782c3 CK |
1162 | entry->priority = 0; |
1163 | entry->tv.bo = &entry->robj->tbo; | |
1164 | entry->tv.shared = true; | |
d38ceaf9 | 1165 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1166 | } |
1167 | ||
d38ceaf9 AD |
1168 | return 0; |
1169 | ||
1170 | error_free: | |
d38ceaf9 | 1171 | list_del(&mapping->list); |
c25867df | 1172 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1173 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1174 | spin_unlock(&vm->it_lock); |
93e3e438 | 1175 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1176 | kfree(mapping); |
1177 | ||
f48b2659 | 1178 | error: |
d38ceaf9 AD |
1179 | return r; |
1180 | } | |
1181 | ||
1182 | /** | |
1183 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1184 | * | |
1185 | * @adev: amdgpu_device pointer | |
1186 | * @bo_va: bo_va to remove the address from | |
1187 | * @saddr: where to the BO is mapped | |
1188 | * | |
1189 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1190 | * Returns 0 for success, error for failure. | |
1191 | * | |
49b02b18 | 1192 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1193 | */ |
1194 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1195 | struct amdgpu_bo_va *bo_va, | |
1196 | uint64_t saddr) | |
1197 | { | |
1198 | struct amdgpu_bo_va_mapping *mapping; | |
1199 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1200 | bool valid = true; |
d38ceaf9 | 1201 | |
6c7fc503 | 1202 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
69b576a1 | 1203 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1204 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1205 | if (mapping->it.start == saddr) |
1206 | break; | |
1207 | } | |
1208 | ||
7fc11959 CK |
1209 | if (&mapping->list == &bo_va->valids) { |
1210 | valid = false; | |
1211 | ||
1212 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1213 | if (mapping->it.start == saddr) | |
1214 | break; | |
1215 | } | |
1216 | ||
69b576a1 CZ |
1217 | if (&mapping->list == &bo_va->invalids) { |
1218 | mutex_unlock(&bo_va->mutex); | |
7fc11959 | 1219 | return -ENOENT; |
69b576a1 | 1220 | } |
d38ceaf9 | 1221 | } |
69b576a1 | 1222 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 | 1223 | list_del(&mapping->list); |
c25867df | 1224 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1225 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1226 | spin_unlock(&vm->it_lock); |
93e3e438 | 1227 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1228 | |
81d75a30 | 1229 | if (valid) { |
1230 | spin_lock(&vm->freed_lock); | |
d38ceaf9 | 1231 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1232 | spin_unlock(&vm->freed_lock); |
1233 | } else { | |
d38ceaf9 | 1234 | kfree(mapping); |
81d75a30 | 1235 | } |
d38ceaf9 AD |
1236 | |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1242 | * | |
1243 | * @adev: amdgpu_device pointer | |
1244 | * @bo_va: requested bo_va | |
1245 | * | |
1246 | * Remove @bo_va->bo from the requested vm (cayman+). | |
1247 | * | |
1248 | * Object have to be reserved! | |
1249 | */ | |
1250 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1251 | struct amdgpu_bo_va *bo_va) | |
1252 | { | |
1253 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1254 | struct amdgpu_vm *vm = bo_va->vm; | |
1255 | ||
1256 | list_del(&bo_va->bo_list); | |
1257 | ||
d38ceaf9 AD |
1258 | spin_lock(&vm->status_lock); |
1259 | list_del(&bo_va->vm_status); | |
1260 | spin_unlock(&vm->status_lock); | |
1261 | ||
7fc11959 | 1262 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 1263 | list_del(&mapping->list); |
c25867df | 1264 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1265 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1266 | spin_unlock(&vm->it_lock); |
93e3e438 | 1267 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
81d75a30 | 1268 | spin_lock(&vm->freed_lock); |
7fc11959 | 1269 | list_add(&mapping->list, &vm->freed); |
81d75a30 | 1270 | spin_unlock(&vm->freed_lock); |
7fc11959 CK |
1271 | } |
1272 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1273 | list_del(&mapping->list); | |
c25867df | 1274 | spin_lock(&vm->it_lock); |
7fc11959 | 1275 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1276 | spin_unlock(&vm->it_lock); |
7fc11959 | 1277 | kfree(mapping); |
d38ceaf9 | 1278 | } |
bb1e38a4 | 1279 | fence_put(bo_va->last_pt_update); |
69b576a1 | 1280 | mutex_destroy(&bo_va->mutex); |
d38ceaf9 | 1281 | kfree(bo_va); |
d38ceaf9 AD |
1282 | } |
1283 | ||
1284 | /** | |
1285 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1286 | * | |
1287 | * @adev: amdgpu_device pointer | |
1288 | * @vm: requested vm | |
1289 | * @bo: amdgpu buffer object | |
1290 | * | |
1291 | * Mark @bo as invalid (cayman+). | |
1292 | */ | |
1293 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1294 | struct amdgpu_bo *bo) | |
1295 | { | |
1296 | struct amdgpu_bo_va *bo_va; | |
1297 | ||
1298 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1299 | spin_lock(&bo_va->vm->status_lock); |
1300 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1301 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1302 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1303 | } |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * amdgpu_vm_init - initialize a vm instance | |
1308 | * | |
1309 | * @adev: amdgpu_device pointer | |
1310 | * @vm: requested vm | |
1311 | * | |
1312 | * Init @vm fields (cayman+). | |
1313 | */ | |
1314 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1315 | { | |
1316 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1317 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1318 | unsigned pd_size, pd_entries; |
d38ceaf9 AD |
1319 | int i, r; |
1320 | ||
1321 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1322 | vm->ids[i].id = 0; | |
1323 | vm->ids[i].flushed_updates = NULL; | |
d38ceaf9 | 1324 | } |
d38ceaf9 AD |
1325 | vm->va = RB_ROOT; |
1326 | spin_lock_init(&vm->status_lock); | |
1327 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1328 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1329 | INIT_LIST_HEAD(&vm->freed); |
c25867df | 1330 | spin_lock_init(&vm->it_lock); |
81d75a30 | 1331 | spin_lock_init(&vm->freed_lock); |
d38ceaf9 AD |
1332 | pd_size = amdgpu_vm_directory_size(adev); |
1333 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1334 | ||
1335 | /* allocate page table array */ | |
9571e1d8 | 1336 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1337 | if (vm->page_tables == NULL) { |
1338 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1339 | return -ENOMEM; | |
1340 | } | |
1341 | ||
05906dec BN |
1342 | vm->page_directory_fence = NULL; |
1343 | ||
d38ceaf9 | 1344 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1345 | AMDGPU_GEM_DOMAIN_VRAM, |
1346 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1347 | NULL, NULL, &vm->page_directory); |
d38ceaf9 AD |
1348 | if (r) |
1349 | return r; | |
ef9f0a83 CZ |
1350 | r = amdgpu_bo_reserve(vm->page_directory, false); |
1351 | if (r) { | |
1352 | amdgpu_bo_unref(&vm->page_directory); | |
1353 | vm->page_directory = NULL; | |
1354 | return r; | |
1355 | } | |
d38ceaf9 | 1356 | r = amdgpu_vm_clear_bo(adev, vm->page_directory); |
ef9f0a83 | 1357 | amdgpu_bo_unreserve(vm->page_directory); |
d38ceaf9 AD |
1358 | if (r) { |
1359 | amdgpu_bo_unref(&vm->page_directory); | |
1360 | vm->page_directory = NULL; | |
1361 | return r; | |
1362 | } | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | /** | |
1368 | * amdgpu_vm_fini - tear down a vm instance | |
1369 | * | |
1370 | * @adev: amdgpu_device pointer | |
1371 | * @vm: requested vm | |
1372 | * | |
1373 | * Tear down @vm (cayman+). | |
1374 | * Unbind the VM and remove all bos from the vm bo list | |
1375 | */ | |
1376 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1377 | { | |
1378 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1379 | int i; | |
1380 | ||
1381 | if (!RB_EMPTY_ROOT(&vm->va)) { | |
1382 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1383 | } | |
1384 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1385 | list_del(&mapping->list); | |
1386 | interval_tree_remove(&mapping->it, &vm->va); | |
1387 | kfree(mapping); | |
1388 | } | |
1389 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1390 | list_del(&mapping->list); | |
1391 | kfree(mapping); | |
1392 | } | |
1393 | ||
1394 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1395 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1396 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1397 | |
1398 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1399 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1400 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
1c16c0a7 CK |
1401 | unsigned id = vm->ids[i].id; |
1402 | ||
1403 | atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner, | |
1404 | (long)vm, 0); | |
3c62338c | 1405 | fence_put(vm->ids[i].flushed_updates); |
d38ceaf9 AD |
1406 | } |
1407 | ||
d38ceaf9 | 1408 | } |
ea89f8c9 | 1409 | |
a9a78b32 CK |
1410 | /** |
1411 | * amdgpu_vm_manager_init - init the VM manager | |
1412 | * | |
1413 | * @adev: amdgpu_device pointer | |
1414 | * | |
1415 | * Initialize the VM manager structures | |
1416 | */ | |
1417 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1418 | { | |
1419 | unsigned i; | |
1420 | ||
1421 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1422 | ||
1423 | /* skip over VMID 0, since it is the system VM */ | |
1424 | for (i = 1; i < adev->vm_manager.num_ids; ++i) | |
1425 | list_add_tail(&adev->vm_manager.ids[i].list, | |
1426 | &adev->vm_manager.ids_lru); | |
1427 | } | |
1428 | ||
ea89f8c9 CK |
1429 | /** |
1430 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1431 | * | |
1432 | * @adev: amdgpu_device pointer | |
1433 | * | |
1434 | * Cleanup the VM manager and free resources. | |
1435 | */ | |
1436 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1437 | { | |
1438 | unsigned i; | |
1439 | ||
1440 | for (i = 0; i < AMDGPU_NUM_VM; ++i) | |
1c16c0a7 | 1441 | fence_put(adev->vm_manager.ids[i].active); |
ea89f8c9 | 1442 | } |