Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
1fbb2e92 | 28 | #include <linux/fence-array.h> |
d38ceaf9 AD |
29 | #include <drm/drmP.h> |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | #include "amdgpu_trace.h" | |
33 | ||
34 | /* | |
35 | * GPUVM | |
36 | * GPUVM is similar to the legacy gart on older asics, however | |
37 | * rather than there being a single global gart table | |
38 | * for the entire GPU, there are multiple VM page tables active | |
39 | * at any given time. The VM page tables can contain a mix | |
40 | * vram pages and system memory pages and system memory pages | |
41 | * can be mapped as snooped (cached system pages) or unsnooped | |
42 | * (uncached system pages). | |
43 | * Each VM has an ID associated with it and there is a page table | |
44 | * associated with each VMID. When execting a command buffer, | |
45 | * the kernel tells the the ring what VMID to use for that command | |
46 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
47 | * The userspace drivers maintain their own address space and the kernel | |
48 | * sets up their pages tables accordingly when they submit their | |
49 | * command buffers and a VMID is assigned. | |
50 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
51 | * SI supports 16. | |
52 | */ | |
53 | ||
f4833c4f HK |
54 | /* Local structure. Encapsulate some VM table update parameters to reduce |
55 | * the number of function parameters | |
56 | */ | |
29efc4f5 | 57 | struct amdgpu_pte_update_params { |
27c5f36f CK |
58 | /* amdgpu device we do this update for */ |
59 | struct amdgpu_device *adev; | |
f4833c4f HK |
60 | /* address where to copy page table entries from */ |
61 | uint64_t src; | |
f4833c4f HK |
62 | /* indirect buffer to fill with commands */ |
63 | struct amdgpu_ib *ib; | |
afef8b8f CK |
64 | /* Function which actually does the update */ |
65 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
66 | uint64_t addr, unsigned count, uint32_t incr, | |
67 | uint32_t flags); | |
4c7e8855 CZ |
68 | /* indicate update pt or its shadow */ |
69 | bool shadow; | |
f4833c4f HK |
70 | }; |
71 | ||
d38ceaf9 AD |
72 | /** |
73 | * amdgpu_vm_num_pde - return the number of page directory entries | |
74 | * | |
75 | * @adev: amdgpu_device pointer | |
76 | * | |
8843dbbb | 77 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
78 | */ |
79 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
80 | { | |
81 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
82 | } | |
83 | ||
84 | /** | |
85 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
86 | * | |
87 | * @adev: amdgpu_device pointer | |
88 | * | |
8843dbbb | 89 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
90 | */ |
91 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
92 | { | |
93 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
94 | } | |
95 | ||
96 | /** | |
56467ebf | 97 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
98 | * |
99 | * @vm: vm providing the BOs | |
3c0eea6c | 100 | * @validated: head of validation list |
56467ebf | 101 | * @entry: entry to add |
d38ceaf9 AD |
102 | * |
103 | * Add the page directory to the list of BOs to | |
56467ebf | 104 | * validate for command submission. |
d38ceaf9 | 105 | */ |
56467ebf CK |
106 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
107 | struct list_head *validated, | |
108 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 109 | { |
56467ebf | 110 | entry->robj = vm->page_directory; |
56467ebf CK |
111 | entry->priority = 0; |
112 | entry->tv.bo = &vm->page_directory->tbo; | |
113 | entry->tv.shared = true; | |
2f568dbd | 114 | entry->user_pages = NULL; |
56467ebf CK |
115 | list_add(&entry->tv.head, validated); |
116 | } | |
d38ceaf9 | 117 | |
56467ebf | 118 | /** |
ee1782c3 | 119 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf | 120 | * |
5a712a87 | 121 | * @adev: amdgpu device pointer |
56467ebf | 122 | * @vm: vm providing the BOs |
3c0eea6c | 123 | * @duplicates: head of duplicates list |
d38ceaf9 | 124 | * |
ee1782c3 CK |
125 | * Add the page directory to the BO duplicates list |
126 | * for command submission. | |
d38ceaf9 | 127 | */ |
5a712a87 CK |
128 | void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
129 | struct list_head *duplicates) | |
d38ceaf9 | 130 | { |
5a712a87 | 131 | uint64_t num_evictions; |
ee1782c3 | 132 | unsigned i; |
d38ceaf9 | 133 | |
5a712a87 CK |
134 | /* We only need to validate the page tables |
135 | * if they aren't already valid. | |
136 | */ | |
137 | num_evictions = atomic64_read(&adev->num_evictions); | |
138 | if (num_evictions == vm->last_eviction_counter) | |
139 | return; | |
140 | ||
d38ceaf9 | 141 | /* add the vm page table to the list */ |
ee1782c3 CK |
142 | for (i = 0; i <= vm->max_pde_used; ++i) { |
143 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
144 | ||
145 | if (!entry->robj) | |
d38ceaf9 AD |
146 | continue; |
147 | ||
ee1782c3 | 148 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 149 | } |
eceb8a15 CK |
150 | |
151 | } | |
152 | ||
153 | /** | |
154 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
155 | * | |
156 | * @adev: amdgpu device instance | |
157 | * @vm: vm providing the BOs | |
158 | * | |
159 | * Move the PT BOs to the tail of the LRU. | |
160 | */ | |
161 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
162 | struct amdgpu_vm *vm) | |
163 | { | |
164 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
165 | unsigned i; | |
166 | ||
167 | spin_lock(&glob->lru_lock); | |
168 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
169 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
170 | ||
171 | if (!entry->robj) | |
172 | continue; | |
173 | ||
174 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
175 | } | |
176 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
177 | } |
178 | ||
192b7dcb CZ |
179 | static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, |
180 | struct amdgpu_vm_id *id) | |
181 | { | |
182 | return id->current_gpu_reset_count != | |
183 | atomic_read(&adev->gpu_reset_counter) ? true : false; | |
184 | } | |
185 | ||
d38ceaf9 AD |
186 | /** |
187 | * amdgpu_vm_grab_id - allocate the next free VMID | |
188 | * | |
d38ceaf9 | 189 | * @vm: vm to allocate id for |
7f8a5290 CK |
190 | * @ring: ring we want to submit job to |
191 | * @sync: sync object where we add dependencies | |
94dd0a4a | 192 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 193 | * |
7f8a5290 | 194 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 195 | */ |
7f8a5290 | 196 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 | 197 | struct amdgpu_sync *sync, struct fence *fence, |
fd53be30 | 198 | struct amdgpu_job *job) |
d38ceaf9 | 199 | { |
d38ceaf9 | 200 | struct amdgpu_device *adev = ring->adev; |
090b767e | 201 | uint64_t fence_context = adev->fence_context + ring->idx; |
4ff37a83 | 202 | struct fence *updates = sync->last_vm_update; |
8d76001e | 203 | struct amdgpu_vm_id *id, *idle; |
1fbb2e92 CK |
204 | struct fence **fences; |
205 | unsigned i; | |
206 | int r = 0; | |
207 | ||
208 | fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids, | |
209 | GFP_KERNEL); | |
210 | if (!fences) | |
211 | return -ENOMEM; | |
d38ceaf9 | 212 | |
94dd0a4a CK |
213 | mutex_lock(&adev->vm_manager.lock); |
214 | ||
36fd7c5c | 215 | /* Check if we have an idle VMID */ |
1fbb2e92 | 216 | i = 0; |
8d76001e | 217 | list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) { |
1fbb2e92 CK |
218 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
219 | if (!fences[i]) | |
36fd7c5c | 220 | break; |
1fbb2e92 | 221 | ++i; |
36fd7c5c CK |
222 | } |
223 | ||
1fbb2e92 | 224 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
8d76001e | 225 | if (&idle->list == &adev->vm_manager.ids_lru) { |
1fbb2e92 CK |
226 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
227 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
228 | struct fence_array *array; | |
229 | unsigned j; | |
230 | ||
231 | for (j = 0; j < i; ++j) | |
232 | fence_get(fences[j]); | |
233 | ||
234 | array = fence_array_create(i, fences, fence_context, | |
235 | seqno, true); | |
236 | if (!array) { | |
237 | for (j = 0; j < i; ++j) | |
238 | fence_put(fences[j]); | |
239 | kfree(fences); | |
240 | r = -ENOMEM; | |
241 | goto error; | |
242 | } | |
243 | ||
244 | ||
245 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
246 | fence_put(&array->base); | |
247 | if (r) | |
248 | goto error; | |
249 | ||
250 | mutex_unlock(&adev->vm_manager.lock); | |
251 | return 0; | |
252 | ||
253 | } | |
254 | kfree(fences); | |
255 | ||
fd53be30 | 256 | job->vm_needs_flush = true; |
1fbb2e92 CK |
257 | /* Check if we can use a VMID already assigned to this VM */ |
258 | i = ring->idx; | |
259 | do { | |
260 | struct fence *flushed; | |
261 | ||
262 | id = vm->ids[i++]; | |
263 | if (i == AMDGPU_MAX_RINGS) | |
264 | i = 0; | |
8d76001e | 265 | |
1fbb2e92 CK |
266 | /* Check all the prerequisites to using this VMID */ |
267 | if (!id) | |
268 | continue; | |
192b7dcb | 269 | if (amdgpu_vm_is_gpu_reset(adev, id)) |
6adb0513 | 270 | continue; |
1fbb2e92 CK |
271 | |
272 | if (atomic64_read(&id->owner) != vm->client_id) | |
273 | continue; | |
274 | ||
fd53be30 | 275 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
276 | continue; |
277 | ||
090b767e CK |
278 | if (!id->last_flush) |
279 | continue; | |
280 | ||
281 | if (id->last_flush->context != fence_context && | |
282 | !fence_is_signaled(id->last_flush)) | |
1fbb2e92 CK |
283 | continue; |
284 | ||
285 | flushed = id->flushed_updates; | |
286 | if (updates && | |
287 | (!flushed || fence_is_later(updates, flushed))) | |
288 | continue; | |
289 | ||
3dab83be CK |
290 | /* Good we can use this VMID. Remember this submission as |
291 | * user of the VMID. | |
292 | */ | |
1fbb2e92 CK |
293 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
294 | if (r) | |
295 | goto error; | |
8d76001e | 296 | |
6adb0513 | 297 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
1fbb2e92 CK |
298 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
299 | vm->ids[ring->idx] = id; | |
8d76001e | 300 | |
fd53be30 CZ |
301 | job->vm_id = id - adev->vm_manager.ids; |
302 | job->vm_needs_flush = false; | |
0c0fdf14 | 303 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
8d76001e | 304 | |
1fbb2e92 CK |
305 | mutex_unlock(&adev->vm_manager.lock); |
306 | return 0; | |
8d76001e | 307 | |
1fbb2e92 | 308 | } while (i != ring->idx); |
8d76001e | 309 | |
1fbb2e92 CK |
310 | /* Still no ID to use? Then use the idle one found earlier */ |
311 | id = idle; | |
8e9fbeb5 | 312 | |
1fbb2e92 CK |
313 | /* Remember this submission as user of the VMID */ |
314 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
315 | if (r) |
316 | goto error; | |
94dd0a4a | 317 | |
832a902f CK |
318 | fence_put(id->first); |
319 | id->first = fence_get(fence); | |
94dd0a4a | 320 | |
41d9eb2c CK |
321 | fence_put(id->last_flush); |
322 | id->last_flush = NULL; | |
323 | ||
832a902f CK |
324 | fence_put(id->flushed_updates); |
325 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 326 | |
fd53be30 | 327 | id->pd_gpu_addr = job->vm_pd_addr; |
b46b8a87 | 328 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
832a902f | 329 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
0ea54b9b | 330 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 331 | vm->ids[ring->idx] = id; |
d38ceaf9 | 332 | |
fd53be30 | 333 | job->vm_id = id - adev->vm_manager.ids; |
0c0fdf14 | 334 | trace_amdgpu_vm_grab_id(vm, ring->idx, job); |
832a902f CK |
335 | |
336 | error: | |
94dd0a4a | 337 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 338 | return r; |
d38ceaf9 AD |
339 | } |
340 | ||
93dcc37d AD |
341 | static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) |
342 | { | |
343 | struct amdgpu_device *adev = ring->adev; | |
344 | const struct amdgpu_ip_block_version *ip_block; | |
345 | ||
346 | if (ring->type != AMDGPU_RING_TYPE_COMPUTE) | |
347 | /* only compute rings */ | |
348 | return false; | |
349 | ||
350 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
351 | if (!ip_block) | |
352 | return false; | |
353 | ||
354 | if (ip_block->major <= 7) { | |
355 | /* gfx7 has no workaround */ | |
356 | return true; | |
357 | } else if (ip_block->major == 8) { | |
358 | if (adev->gfx.mec_fw_version >= 673) | |
359 | /* gfx8 is fixed in MEC firmware 673 */ | |
360 | return false; | |
361 | else | |
362 | return true; | |
363 | } | |
364 | return false; | |
365 | } | |
366 | ||
d38ceaf9 AD |
367 | /** |
368 | * amdgpu_vm_flush - hardware flush the vm | |
369 | * | |
370 | * @ring: ring to use for flush | |
cffadc83 | 371 | * @vm_id: vmid number to use |
4ff37a83 | 372 | * @pd_addr: address of the page directory |
d38ceaf9 | 373 | * |
4ff37a83 | 374 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 375 | */ |
fd53be30 | 376 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) |
d38ceaf9 | 377 | { |
971fe9a9 | 378 | struct amdgpu_device *adev = ring->adev; |
fd53be30 | 379 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id]; |
d564a06e | 380 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
381 | id->gds_base != job->gds_base || |
382 | id->gds_size != job->gds_size || | |
383 | id->gws_base != job->gws_base || | |
384 | id->gws_size != job->gws_size || | |
385 | id->oa_base != job->oa_base || | |
386 | id->oa_size != job->oa_size); | |
41d9eb2c | 387 | int r; |
d564a06e CK |
388 | |
389 | if (ring->funcs->emit_pipeline_sync && ( | |
fd53be30 | 390 | job->vm_needs_flush || gds_switch_needed || |
93dcc37d | 391 | amdgpu_vm_ring_has_compute_vm_bug(ring))) |
d564a06e | 392 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 393 | |
aa1c8900 CZ |
394 | if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || |
395 | amdgpu_vm_is_gpu_reset(adev, id))) { | |
41d9eb2c CK |
396 | struct fence *fence; |
397 | ||
fd53be30 CZ |
398 | trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); |
399 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
41d9eb2c | 400 | |
3dab83be CK |
401 | r = amdgpu_fence_emit(ring, &fence); |
402 | if (r) | |
403 | return r; | |
404 | ||
41d9eb2c | 405 | mutex_lock(&adev->vm_manager.lock); |
3dab83be CK |
406 | fence_put(id->last_flush); |
407 | id->last_flush = fence; | |
41d9eb2c | 408 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 409 | } |
cffadc83 | 410 | |
d564a06e | 411 | if (gds_switch_needed) { |
fd53be30 CZ |
412 | id->gds_base = job->gds_base; |
413 | id->gds_size = job->gds_size; | |
414 | id->gws_base = job->gws_base; | |
415 | id->gws_size = job->gws_size; | |
416 | id->oa_base = job->oa_base; | |
417 | id->oa_size = job->oa_size; | |
418 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, | |
419 | job->gds_base, job->gds_size, | |
420 | job->gws_base, job->gws_size, | |
421 | job->oa_base, job->oa_size); | |
971fe9a9 | 422 | } |
41d9eb2c CK |
423 | |
424 | return 0; | |
971fe9a9 CK |
425 | } |
426 | ||
427 | /** | |
428 | * amdgpu_vm_reset_id - reset VMID to zero | |
429 | * | |
430 | * @adev: amdgpu device structure | |
431 | * @vm_id: vmid number to use | |
432 | * | |
433 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
434 | */ | |
435 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
436 | { | |
bcb1ba35 CK |
437 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
438 | ||
439 | id->gds_base = 0; | |
440 | id->gds_size = 0; | |
441 | id->gws_base = 0; | |
442 | id->gws_size = 0; | |
443 | id->oa_base = 0; | |
444 | id->oa_size = 0; | |
d38ceaf9 AD |
445 | } |
446 | ||
d38ceaf9 AD |
447 | /** |
448 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
449 | * | |
450 | * @vm: requested vm | |
451 | * @bo: requested buffer object | |
452 | * | |
8843dbbb | 453 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
454 | * Search inside the @bos vm list for the requested vm |
455 | * Returns the found bo_va or NULL if none is found | |
456 | * | |
457 | * Object has to be reserved! | |
458 | */ | |
459 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
460 | struct amdgpu_bo *bo) | |
461 | { | |
462 | struct amdgpu_bo_va *bo_va; | |
463 | ||
464 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
465 | if (bo_va->vm == vm) { | |
466 | return bo_va; | |
467 | } | |
468 | } | |
469 | return NULL; | |
470 | } | |
471 | ||
472 | /** | |
afef8b8f | 473 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 474 | * |
29efc4f5 | 475 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
476 | * @pe: addr of the page entry |
477 | * @addr: dst addr to write into pe | |
478 | * @count: number of page entries to update | |
479 | * @incr: increase next addr by incr bytes | |
480 | * @flags: hw access flags | |
d38ceaf9 AD |
481 | * |
482 | * Traces the parameters and calls the right asic functions | |
483 | * to setup the page table using the DMA. | |
484 | */ | |
afef8b8f CK |
485 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
486 | uint64_t pe, uint64_t addr, | |
487 | unsigned count, uint32_t incr, | |
488 | uint32_t flags) | |
d38ceaf9 | 489 | { |
ec2f05f0 | 490 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 491 | |
afef8b8f | 492 | if (count < 3) { |
de9ea7bd CK |
493 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
494 | addr | flags, count, incr); | |
d38ceaf9 AD |
495 | |
496 | } else { | |
27c5f36f | 497 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
498 | count, incr, flags); |
499 | } | |
500 | } | |
501 | ||
afef8b8f CK |
502 | /** |
503 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
504 | * | |
505 | * @params: see amdgpu_pte_update_params definition | |
506 | * @pe: addr of the page entry | |
507 | * @addr: dst addr to write into pe | |
508 | * @count: number of page entries to update | |
509 | * @incr: increase next addr by incr bytes | |
510 | * @flags: hw access flags | |
511 | * | |
512 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
513 | */ | |
514 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
515 | uint64_t pe, uint64_t addr, | |
516 | unsigned count, uint32_t incr, | |
517 | uint32_t flags) | |
518 | { | |
ec2f05f0 | 519 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 520 | |
ec2f05f0 CK |
521 | |
522 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
523 | ||
524 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
525 | } |
526 | ||
d38ceaf9 AD |
527 | /** |
528 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
529 | * | |
530 | * @adev: amdgpu_device pointer | |
531 | * @bo: bo to clear | |
ef9f0a83 CZ |
532 | * |
533 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
534 | */ |
535 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 536 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
537 | struct amdgpu_bo *bo) |
538 | { | |
2d55e45a | 539 | struct amdgpu_ring *ring; |
4af9f07c | 540 | struct fence *fence = NULL; |
d71518b5 | 541 | struct amdgpu_job *job; |
29efc4f5 | 542 | struct amdgpu_pte_update_params params; |
d38ceaf9 AD |
543 | unsigned entries; |
544 | uint64_t addr; | |
545 | int r; | |
546 | ||
2d55e45a CK |
547 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
548 | ||
ca952613 | 549 | r = reservation_object_reserve_shared(bo->tbo.resv); |
550 | if (r) | |
551 | return r; | |
552 | ||
d38ceaf9 AD |
553 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
554 | if (r) | |
ef9f0a83 | 555 | goto error; |
d38ceaf9 | 556 | |
0fc8683e CK |
557 | r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); |
558 | if (r) | |
559 | goto error; | |
560 | ||
d38ceaf9 AD |
561 | addr = amdgpu_bo_gpu_offset(bo); |
562 | entries = amdgpu_bo_size(bo) / 8; | |
563 | ||
d71518b5 CK |
564 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
565 | if (r) | |
ef9f0a83 | 566 | goto error; |
d38ceaf9 | 567 | |
27c5f36f CK |
568 | memset(¶ms, 0, sizeof(params)); |
569 | params.adev = adev; | |
29efc4f5 | 570 | params.ib = &job->ibs[0]; |
afef8b8f | 571 | amdgpu_vm_do_set_ptes(¶ms, addr, 0, entries, 0, 0); |
d71518b5 CK |
572 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
573 | ||
574 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
575 | r = amdgpu_job_submit(job, ring, &vm->entity, |
576 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
577 | if (r) |
578 | goto error_free; | |
579 | ||
d71518b5 | 580 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 581 | fence_put(fence); |
cadf97b1 | 582 | return 0; |
ef9f0a83 | 583 | |
d38ceaf9 | 584 | error_free: |
d71518b5 | 585 | amdgpu_job_free(job); |
d38ceaf9 | 586 | |
ef9f0a83 | 587 | error: |
d38ceaf9 AD |
588 | return r; |
589 | } | |
590 | ||
591 | /** | |
b07c9d2a | 592 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 593 | * |
b07c9d2a | 594 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
595 | * @addr: the unmapped addr |
596 | * | |
597 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 598 | * to and return the pointer for the page table entry. |
d38ceaf9 | 599 | */ |
de9ea7bd | 600 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
601 | { |
602 | uint64_t result; | |
603 | ||
de9ea7bd CK |
604 | /* page table offset */ |
605 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 606 | |
de9ea7bd CK |
607 | /* in case cpu page size != gpu page size*/ |
608 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 609 | |
b07c9d2a | 610 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
611 | |
612 | return result; | |
613 | } | |
614 | ||
6557e3d2 CZ |
615 | static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev, |
616 | struct amdgpu_vm *vm, | |
617 | bool shadow) | |
d38ceaf9 | 618 | { |
2d55e45a | 619 | struct amdgpu_ring *ring; |
6557e3d2 CZ |
620 | struct amdgpu_bo *pd = shadow ? vm->page_directory->shadow : |
621 | vm->page_directory; | |
622 | uint64_t pd_addr; | |
d38ceaf9 AD |
623 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; |
624 | uint64_t last_pde = ~0, last_pt = ~0; | |
625 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 626 | struct amdgpu_job *job; |
29efc4f5 | 627 | struct amdgpu_pte_update_params params; |
4af9f07c | 628 | struct fence *fence = NULL; |
d5fc5e82 | 629 | |
d38ceaf9 AD |
630 | int r; |
631 | ||
6557e3d2 CZ |
632 | if (!pd) |
633 | return 0; | |
0fc8683e CK |
634 | |
635 | r = amdgpu_ttm_bind(&pd->tbo, &pd->tbo.mem); | |
636 | if (r) | |
637 | return r; | |
638 | ||
6557e3d2 | 639 | pd_addr = amdgpu_bo_gpu_offset(pd); |
2d55e45a CK |
640 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
641 | ||
d38ceaf9 AD |
642 | /* padding, etc. */ |
643 | ndw = 64; | |
644 | ||
645 | /* assume the worst case */ | |
646 | ndw += vm->max_pde_used * 6; | |
647 | ||
d71518b5 CK |
648 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
649 | if (r) | |
d38ceaf9 | 650 | return r; |
d71518b5 | 651 | |
27c5f36f CK |
652 | memset(¶ms, 0, sizeof(params)); |
653 | params.adev = adev; | |
29efc4f5 | 654 | params.ib = &job->ibs[0]; |
d38ceaf9 AD |
655 | |
656 | /* walk over the address space and update the page directory */ | |
657 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 658 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
659 | uint64_t pde, pt; |
660 | ||
661 | if (bo == NULL) | |
662 | continue; | |
663 | ||
0fc8683e CK |
664 | if (bo->shadow) { |
665 | struct amdgpu_bo *shadow = bo->shadow; | |
666 | ||
667 | r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); | |
668 | if (r) | |
669 | return r; | |
670 | } | |
671 | ||
d38ceaf9 | 672 | pt = amdgpu_bo_gpu_offset(bo); |
6557e3d2 CZ |
673 | if (!shadow) { |
674 | if (vm->page_tables[pt_idx].addr == pt) | |
675 | continue; | |
676 | vm->page_tables[pt_idx].addr = pt; | |
677 | } else { | |
678 | if (vm->page_tables[pt_idx].shadow_addr == pt) | |
679 | continue; | |
680 | vm->page_tables[pt_idx].shadow_addr = pt; | |
681 | } | |
d38ceaf9 AD |
682 | |
683 | pde = pd_addr + pt_idx * 8; | |
684 | if (((last_pde + 8 * count) != pde) || | |
96105e53 CK |
685 | ((last_pt + incr * count) != pt) || |
686 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
687 | |
688 | if (count) { | |
afef8b8f CK |
689 | amdgpu_vm_do_set_ptes(¶ms, last_pde, |
690 | last_pt, count, incr, | |
691 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
692 | } |
693 | ||
694 | count = 1; | |
695 | last_pde = pde; | |
696 | last_pt = pt; | |
697 | } else { | |
698 | ++count; | |
699 | } | |
700 | } | |
701 | ||
702 | if (count) | |
afef8b8f CK |
703 | amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt, |
704 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 705 | |
29efc4f5 CK |
706 | if (params.ib->length_dw != 0) { |
707 | amdgpu_ring_pad_ib(ring, params.ib); | |
e86f9cee CK |
708 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
709 | AMDGPU_FENCE_OWNER_VM); | |
29efc4f5 | 710 | WARN_ON(params.ib->length_dw > ndw); |
2bd9ccfa CK |
711 | r = amdgpu_job_submit(job, ring, &vm->entity, |
712 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
713 | if (r) |
714 | goto error_free; | |
05906dec | 715 | |
4af9f07c | 716 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
717 | fence_put(vm->page_directory_fence); |
718 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 719 | fence_put(fence); |
d5fc5e82 | 720 | |
d71518b5 CK |
721 | } else { |
722 | amdgpu_job_free(job); | |
d5fc5e82 | 723 | } |
d38ceaf9 AD |
724 | |
725 | return 0; | |
d5fc5e82 CZ |
726 | |
727 | error_free: | |
d71518b5 | 728 | amdgpu_job_free(job); |
4af9f07c | 729 | return r; |
d38ceaf9 AD |
730 | } |
731 | ||
6557e3d2 CZ |
732 | /* |
733 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
734 | * | |
735 | * @adev: amdgpu_device pointer | |
736 | * @vm: requested vm | |
737 | * @start: start of GPU address range | |
738 | * @end: end of GPU address range | |
739 | * | |
740 | * Allocates new page tables if necessary | |
741 | * and updates the page directory. | |
742 | * Returns 0 for success, error for failure. | |
743 | */ | |
744 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
745 | struct amdgpu_vm *vm) | |
746 | { | |
747 | int r; | |
748 | ||
749 | r = amdgpu_vm_update_pd_or_shadow(adev, vm, true); | |
750 | if (r) | |
751 | return r; | |
752 | return amdgpu_vm_update_pd_or_shadow(adev, vm, false); | |
753 | } | |
754 | ||
d38ceaf9 AD |
755 | /** |
756 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
757 | * | |
29efc4f5 | 758 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
759 | * @vm: requested vm |
760 | * @start: start of GPU address range | |
761 | * @end: end of GPU address range | |
677131a1 | 762 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
763 | * @flags: mapping flags |
764 | * | |
8843dbbb | 765 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 766 | */ |
27c5f36f | 767 | static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 768 | struct amdgpu_vm *vm, |
a1e08d3b CK |
769 | uint64_t start, uint64_t end, |
770 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 771 | { |
31f6c1fe CK |
772 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
773 | ||
92696dd5 | 774 | uint64_t cur_pe_start, cur_nptes, cur_dst; |
677131a1 | 775 | uint64_t addr; /* next GPU address to be updated */ |
21718497 AX |
776 | uint64_t pt_idx; |
777 | struct amdgpu_bo *pt; | |
778 | unsigned nptes; /* next number of ptes to be updated */ | |
779 | uint64_t next_pe_start; | |
780 | ||
781 | /* initialize the variables */ | |
782 | addr = start; | |
783 | pt_idx = addr >> amdgpu_vm_block_size; | |
784 | pt = vm->page_tables[pt_idx].entry.robj; | |
4c7e8855 CZ |
785 | if (params->shadow) { |
786 | if (!pt->shadow) | |
787 | return; | |
788 | pt = vm->page_tables[pt_idx].entry.robj->shadow; | |
789 | } | |
21718497 AX |
790 | if ((addr & ~mask) == (end & ~mask)) |
791 | nptes = end - addr; | |
792 | else | |
793 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
794 | ||
795 | cur_pe_start = amdgpu_bo_gpu_offset(pt); | |
796 | cur_pe_start += (addr & mask) * 8; | |
92696dd5 | 797 | cur_nptes = nptes; |
21718497 AX |
798 | cur_dst = dst; |
799 | ||
800 | /* for next ptb*/ | |
801 | addr += nptes; | |
802 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
d38ceaf9 AD |
803 | |
804 | /* walk over the address space and update the page tables */ | |
21718497 AX |
805 | while (addr < end) { |
806 | pt_idx = addr >> amdgpu_vm_block_size; | |
807 | pt = vm->page_tables[pt_idx].entry.robj; | |
4c7e8855 CZ |
808 | if (params->shadow) { |
809 | if (!pt->shadow) | |
810 | return; | |
811 | pt = vm->page_tables[pt_idx].entry.robj->shadow; | |
812 | } | |
d38ceaf9 AD |
813 | |
814 | if ((addr & ~mask) == (end & ~mask)) | |
815 | nptes = end - addr; | |
816 | else | |
817 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
818 | ||
677131a1 AX |
819 | next_pe_start = amdgpu_bo_gpu_offset(pt); |
820 | next_pe_start += (addr & mask) * 8; | |
d38ceaf9 | 821 | |
96105e53 CK |
822 | if ((cur_pe_start + 8 * cur_nptes) == next_pe_start && |
823 | ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
3a6f8e0c | 824 | /* The next ptb is consecutive to current ptb. |
afef8b8f | 825 | * Don't call the update function now. |
3a6f8e0c AX |
826 | * Will update two ptbs together in future. |
827 | */ | |
92696dd5 | 828 | cur_nptes += nptes; |
3a6f8e0c | 829 | } else { |
afef8b8f CK |
830 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
831 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 | 832 | |
677131a1 | 833 | cur_pe_start = next_pe_start; |
92696dd5 | 834 | cur_nptes = nptes; |
677131a1 | 835 | cur_dst = dst; |
d38ceaf9 AD |
836 | } |
837 | ||
21718497 | 838 | /* for next ptb*/ |
d38ceaf9 AD |
839 | addr += nptes; |
840 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
841 | } | |
842 | ||
afef8b8f CK |
843 | params->func(params, cur_pe_start, cur_dst, cur_nptes, |
844 | AMDGPU_GPU_PAGE_SIZE, flags); | |
92696dd5 CK |
845 | } |
846 | ||
847 | /* | |
848 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
849 | * | |
850 | * @params: see amdgpu_pte_update_params definition | |
851 | * @vm: requested vm | |
852 | * @start: first PTE to handle | |
853 | * @end: last PTE to handle | |
854 | * @dst: addr those PTEs should point to | |
855 | * @flags: hw mapping flags | |
856 | */ | |
857 | static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, | |
858 | struct amdgpu_vm *vm, | |
859 | uint64_t start, uint64_t end, | |
860 | uint64_t dst, uint32_t flags) | |
861 | { | |
862 | /** | |
863 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
864 | * field in the PTE. When this field is set to a non-zero value, page | |
865 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
866 | * flags are considered valid for all PTEs within the fragment range | |
867 | * and corresponding mappings are assumed to be physically contiguous. | |
868 | * | |
869 | * The L1 TLB can store a single PTE for the whole fragment, | |
870 | * significantly increasing the space available for translation | |
871 | * caching. This leads to large improvements in throughput when the | |
872 | * TLB is under pressure. | |
873 | * | |
874 | * The L2 TLB distributes small and large fragments into two | |
875 | * asymmetric partitions. The large fragment cache is significantly | |
876 | * larger. Thus, we try to use large fragments wherever possible. | |
877 | * Userspace can support this by aligning virtual base address and | |
878 | * allocation size to the fragment size. | |
879 | */ | |
880 | ||
8036617e CK |
881 | /* SI and newer are optimized for 64KB */ |
882 | uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG); | |
883 | uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG; | |
92696dd5 CK |
884 | |
885 | uint64_t frag_start = ALIGN(start, frag_align); | |
886 | uint64_t frag_end = end & ~(frag_align - 1); | |
887 | ||
888 | /* system pages are non continuously */ | |
b7fc2cbd | 889 | if (params->src || !(flags & AMDGPU_PTE_VALID) || |
92696dd5 CK |
890 | (frag_start >= frag_end)) { |
891 | ||
892 | amdgpu_vm_update_ptes(params, vm, start, end, dst, flags); | |
893 | return; | |
894 | } | |
895 | ||
896 | /* handle the 4K area at the beginning */ | |
897 | if (start != frag_start) { | |
898 | amdgpu_vm_update_ptes(params, vm, start, frag_start, | |
899 | dst, flags); | |
900 | dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; | |
901 | } | |
902 | ||
903 | /* handle the area in the middle */ | |
904 | amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst, | |
8036617e | 905 | flags | frag_flags); |
92696dd5 CK |
906 | |
907 | /* handle the 4K area at the end */ | |
908 | if (frag_end != end) { | |
909 | dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; | |
910 | amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags); | |
911 | } | |
d38ceaf9 AD |
912 | } |
913 | ||
d38ceaf9 AD |
914 | /** |
915 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
916 | * | |
917 | * @adev: amdgpu_device pointer | |
3cabaa54 | 918 | * @exclusive: fence we need to sync to |
fa3ab3c7 CK |
919 | * @src: address where to copy page table entries from |
920 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 921 | * @vm: requested vm |
a14faa65 CK |
922 | * @start: start of mapped range |
923 | * @last: last mapped entry | |
924 | * @flags: flags for the entries | |
d38ceaf9 | 925 | * @addr: addr to set the area to |
d38ceaf9 AD |
926 | * @fence: optional resulting fence |
927 | * | |
a14faa65 | 928 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 929 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
930 | */ |
931 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 932 | struct fence *exclusive, |
fa3ab3c7 CK |
933 | uint64_t src, |
934 | dma_addr_t *pages_addr, | |
d38ceaf9 | 935 | struct amdgpu_vm *vm, |
a14faa65 CK |
936 | uint64_t start, uint64_t last, |
937 | uint32_t flags, uint64_t addr, | |
938 | struct fence **fence) | |
d38ceaf9 | 939 | { |
2d55e45a | 940 | struct amdgpu_ring *ring; |
a1e08d3b | 941 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 942 | unsigned nptes, ncmds, ndw; |
d71518b5 | 943 | struct amdgpu_job *job; |
29efc4f5 | 944 | struct amdgpu_pte_update_params params; |
4af9f07c | 945 | struct fence *f = NULL; |
d38ceaf9 AD |
946 | int r; |
947 | ||
afef8b8f CK |
948 | memset(¶ms, 0, sizeof(params)); |
949 | params.adev = adev; | |
950 | params.src = src; | |
951 | ||
2d55e45a | 952 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 953 | |
29efc4f5 | 954 | memset(¶ms, 0, sizeof(params)); |
27c5f36f | 955 | params.adev = adev; |
29efc4f5 | 956 | params.src = src; |
2d55e45a | 957 | |
a1e08d3b CK |
958 | /* sync to everything on unmapping */ |
959 | if (!(flags & AMDGPU_PTE_VALID)) | |
960 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
961 | ||
a14faa65 | 962 | nptes = last - start + 1; |
d38ceaf9 AD |
963 | |
964 | /* | |
965 | * reserve space for one command every (1 << BLOCK_SIZE) | |
966 | * entries or 2k dwords (whatever is smaller) | |
967 | */ | |
968 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
969 | ||
970 | /* padding, etc. */ | |
971 | ndw = 64; | |
972 | ||
b0456f93 | 973 | if (src) { |
d38ceaf9 AD |
974 | /* only copy commands needed */ |
975 | ndw += ncmds * 7; | |
976 | ||
afef8b8f CK |
977 | params.func = amdgpu_vm_do_copy_ptes; |
978 | ||
b0456f93 CK |
979 | } else if (pages_addr) { |
980 | /* copy commands needed */ | |
981 | ndw += ncmds * 7; | |
d38ceaf9 | 982 | |
b0456f93 | 983 | /* and also PTEs */ |
d38ceaf9 AD |
984 | ndw += nptes * 2; |
985 | ||
afef8b8f CK |
986 | params.func = amdgpu_vm_do_copy_ptes; |
987 | ||
d38ceaf9 AD |
988 | } else { |
989 | /* set page commands needed */ | |
990 | ndw += ncmds * 10; | |
991 | ||
992 | /* two extra commands for begin/end of fragment */ | |
993 | ndw += 2 * 10; | |
afef8b8f CK |
994 | |
995 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
996 | } |
997 | ||
d71518b5 CK |
998 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
999 | if (r) | |
d38ceaf9 | 1000 | return r; |
d71518b5 | 1001 | |
29efc4f5 | 1002 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1003 | |
b0456f93 CK |
1004 | if (!src && pages_addr) { |
1005 | uint64_t *pte; | |
1006 | unsigned i; | |
1007 | ||
1008 | /* Put the PTEs at the end of the IB. */ | |
1009 | i = ndw - nptes * 2; | |
1010 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1011 | params.src = job->ibs->gpu_addr + i * 4; | |
1012 | ||
1013 | for (i = 0; i < nptes; ++i) { | |
1014 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1015 | AMDGPU_GPU_PAGE_SIZE); | |
1016 | pte[i] |= flags; | |
1017 | } | |
d7a4ac66 | 1018 | addr = 0; |
b0456f93 CK |
1019 | } |
1020 | ||
3cabaa54 CK |
1021 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1022 | if (r) | |
1023 | goto error_free; | |
1024 | ||
e86f9cee | 1025 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
1026 | owner); |
1027 | if (r) | |
1028 | goto error_free; | |
d38ceaf9 | 1029 | |
a1e08d3b CK |
1030 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
1031 | if (r) | |
1032 | goto error_free; | |
1033 | ||
4c7e8855 CZ |
1034 | params.shadow = true; |
1035 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); | |
1036 | params.shadow = false; | |
92696dd5 | 1037 | amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags); |
d38ceaf9 | 1038 | |
29efc4f5 CK |
1039 | amdgpu_ring_pad_ib(ring, params.ib); |
1040 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1041 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1042 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1043 | if (r) |
1044 | goto error_free; | |
d38ceaf9 | 1045 | |
bf60efd3 | 1046 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
1047 | if (fence) { |
1048 | fence_put(*fence); | |
1049 | *fence = fence_get(f); | |
1050 | } | |
281b4223 | 1051 | fence_put(f); |
d38ceaf9 | 1052 | return 0; |
d5fc5e82 CZ |
1053 | |
1054 | error_free: | |
d71518b5 | 1055 | amdgpu_job_free(job); |
4af9f07c | 1056 | return r; |
d38ceaf9 AD |
1057 | } |
1058 | ||
a14faa65 CK |
1059 | /** |
1060 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1061 | * | |
1062 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1063 | * @exclusive: fence we need to sync to |
8358dcee CK |
1064 | * @gtt_flags: flags as they are used for GTT |
1065 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
1066 | * @vm: requested vm |
1067 | * @mapping: mapped range and flags to use for the update | |
1068 | * @addr: addr to set the area to | |
8358dcee | 1069 | * @flags: HW flags for the mapping |
a14faa65 CK |
1070 | * @fence: optional resulting fence |
1071 | * | |
1072 | * Split the mapping into smaller chunks so that each update fits | |
1073 | * into a SDMA IB. | |
1074 | * Returns 0 for success, -EINVAL for failure. | |
1075 | */ | |
1076 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
3cabaa54 | 1077 | struct fence *exclusive, |
a14faa65 | 1078 | uint32_t gtt_flags, |
8358dcee | 1079 | dma_addr_t *pages_addr, |
a14faa65 CK |
1080 | struct amdgpu_vm *vm, |
1081 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
1082 | uint32_t flags, uint64_t addr, |
1083 | struct fence **fence) | |
a14faa65 CK |
1084 | { |
1085 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
1086 | ||
fa3ab3c7 | 1087 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
1088 | int r; |
1089 | ||
1090 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1091 | * but in case of something, we filter the flags in first place | |
1092 | */ | |
1093 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1094 | flags &= ~AMDGPU_PTE_READABLE; | |
1095 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1096 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1097 | ||
1098 | trace_amdgpu_vm_bo_update(mapping); | |
1099 | ||
8358dcee | 1100 | if (pages_addr) { |
fa3ab3c7 CK |
1101 | if (flags == gtt_flags) |
1102 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
1103 | addr = 0; |
1104 | } | |
a14faa65 CK |
1105 | addr += mapping->offset; |
1106 | ||
8358dcee | 1107 | if (!pages_addr || src) |
3cabaa54 CK |
1108 | return amdgpu_vm_bo_update_mapping(adev, exclusive, |
1109 | src, pages_addr, vm, | |
a14faa65 CK |
1110 | start, mapping->it.last, |
1111 | flags, addr, fence); | |
1112 | ||
1113 | while (start != mapping->it.last + 1) { | |
1114 | uint64_t last; | |
1115 | ||
fb29b57c | 1116 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
3cabaa54 CK |
1117 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, |
1118 | src, pages_addr, vm, | |
a14faa65 CK |
1119 | start, last, flags, addr, |
1120 | fence); | |
1121 | if (r) | |
1122 | return r; | |
1123 | ||
1124 | start = last + 1; | |
fb29b57c | 1125 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
1126 | } |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
d38ceaf9 AD |
1131 | /** |
1132 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1133 | * | |
1134 | * @adev: amdgpu_device pointer | |
1135 | * @bo_va: requested BO and VM object | |
99e124f4 | 1136 | * @clear: if true clear the entries |
d38ceaf9 AD |
1137 | * |
1138 | * Fill in the page table entries for @bo_va. | |
1139 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1140 | */ |
1141 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1142 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1143 | bool clear) |
d38ceaf9 AD |
1144 | { |
1145 | struct amdgpu_vm *vm = bo_va->vm; | |
1146 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 1147 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 1148 | uint32_t gtt_flags, flags; |
99e124f4 | 1149 | struct ttm_mem_reg *mem; |
3cabaa54 | 1150 | struct fence *exclusive; |
d38ceaf9 AD |
1151 | uint64_t addr; |
1152 | int r; | |
1153 | ||
99e124f4 CK |
1154 | if (clear) { |
1155 | mem = NULL; | |
1156 | addr = 0; | |
1157 | exclusive = NULL; | |
1158 | } else { | |
8358dcee CK |
1159 | struct ttm_dma_tt *ttm; |
1160 | ||
99e124f4 | 1161 | mem = &bo_va->bo->tbo.mem; |
b7d698d7 | 1162 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
1163 | switch (mem->mem_type) { |
1164 | case TTM_PL_TT: | |
8358dcee CK |
1165 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
1166 | ttm_dma_tt, ttm); | |
1167 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
1168 | break; |
1169 | ||
1170 | case TTM_PL_VRAM: | |
d38ceaf9 | 1171 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
1172 | break; |
1173 | ||
1174 | default: | |
1175 | break; | |
1176 | } | |
3cabaa54 CK |
1177 | |
1178 | exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); | |
d38ceaf9 AD |
1179 | } |
1180 | ||
d38ceaf9 | 1181 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
c855e250 CK |
1182 | gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && |
1183 | adev == bo_va->bo->adev) ? flags : 0; | |
d38ceaf9 | 1184 | |
7fc11959 CK |
1185 | spin_lock(&vm->status_lock); |
1186 | if (!list_empty(&bo_va->vm_status)) | |
1187 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1188 | spin_unlock(&vm->status_lock); | |
1189 | ||
1190 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
3cabaa54 CK |
1191 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, |
1192 | gtt_flags, pages_addr, vm, | |
8358dcee CK |
1193 | mapping, flags, addr, |
1194 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
1195 | if (r) |
1196 | return r; | |
1197 | } | |
1198 | ||
d6c10f6b CK |
1199 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1200 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1201 | trace_amdgpu_vm_bo_mapping(mapping); | |
1202 | ||
1203 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1204 | trace_amdgpu_vm_bo_mapping(mapping); | |
1205 | } | |
1206 | ||
d38ceaf9 | 1207 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1208 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1209 | list_del_init(&bo_va->vm_status); |
99e124f4 | 1210 | if (clear) |
7fc11959 | 1211 | list_add(&bo_va->vm_status, &vm->cleared); |
d38ceaf9 AD |
1212 | spin_unlock(&vm->status_lock); |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | /** | |
1218 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1219 | * | |
1220 | * @adev: amdgpu_device pointer | |
1221 | * @vm: requested vm | |
1222 | * | |
1223 | * Make sure all freed BOs are cleared in the PT. | |
1224 | * Returns 0 for success. | |
1225 | * | |
1226 | * PTs have to be reserved and mutex must be locked! | |
1227 | */ | |
1228 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1229 | struct amdgpu_vm *vm) | |
1230 | { | |
1231 | struct amdgpu_bo_va_mapping *mapping; | |
1232 | int r; | |
1233 | ||
1234 | while (!list_empty(&vm->freed)) { | |
1235 | mapping = list_first_entry(&vm->freed, | |
1236 | struct amdgpu_bo_va_mapping, list); | |
1237 | list_del(&mapping->list); | |
e17841b9 | 1238 | |
3cabaa54 | 1239 | r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping, |
fa3ab3c7 | 1240 | 0, 0, NULL); |
d38ceaf9 AD |
1241 | kfree(mapping); |
1242 | if (r) | |
1243 | return r; | |
1244 | ||
1245 | } | |
1246 | return 0; | |
1247 | ||
1248 | } | |
1249 | ||
1250 | /** | |
1251 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1252 | * | |
1253 | * @adev: amdgpu_device pointer | |
1254 | * @vm: requested vm | |
1255 | * | |
1256 | * Make sure all invalidated BOs are cleared in the PT. | |
1257 | * Returns 0 for success. | |
1258 | * | |
1259 | * PTs have to be reserved and mutex must be locked! | |
1260 | */ | |
1261 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1262 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1263 | { |
cfe2c978 | 1264 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1265 | int r = 0; |
d38ceaf9 AD |
1266 | |
1267 | spin_lock(&vm->status_lock); | |
1268 | while (!list_empty(&vm->invalidated)) { | |
1269 | bo_va = list_first_entry(&vm->invalidated, | |
1270 | struct amdgpu_bo_va, vm_status); | |
1271 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1272 | |
99e124f4 | 1273 | r = amdgpu_vm_bo_update(adev, bo_va, true); |
d38ceaf9 AD |
1274 | if (r) |
1275 | return r; | |
1276 | ||
1277 | spin_lock(&vm->status_lock); | |
1278 | } | |
1279 | spin_unlock(&vm->status_lock); | |
1280 | ||
cfe2c978 | 1281 | if (bo_va) |
bb1e38a4 | 1282 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1283 | |
1284 | return r; | |
d38ceaf9 AD |
1285 | } |
1286 | ||
1287 | /** | |
1288 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1289 | * | |
1290 | * @adev: amdgpu_device pointer | |
1291 | * @vm: requested vm | |
1292 | * @bo: amdgpu buffer object | |
1293 | * | |
8843dbbb | 1294 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1295 | * Add @bo to the list of bos associated with the vm |
1296 | * Returns newly added bo_va or NULL for failure | |
1297 | * | |
1298 | * Object has to be reserved! | |
1299 | */ | |
1300 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1301 | struct amdgpu_vm *vm, | |
1302 | struct amdgpu_bo *bo) | |
1303 | { | |
1304 | struct amdgpu_bo_va *bo_va; | |
1305 | ||
1306 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1307 | if (bo_va == NULL) { | |
1308 | return NULL; | |
1309 | } | |
1310 | bo_va->vm = vm; | |
1311 | bo_va->bo = bo; | |
d38ceaf9 AD |
1312 | bo_va->ref_count = 1; |
1313 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1314 | INIT_LIST_HEAD(&bo_va->valids); |
1315 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1316 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1317 | |
d38ceaf9 | 1318 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1319 | |
1320 | return bo_va; | |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * amdgpu_vm_bo_map - map bo inside a vm | |
1325 | * | |
1326 | * @adev: amdgpu_device pointer | |
1327 | * @bo_va: bo_va to store the address | |
1328 | * @saddr: where to map the BO | |
1329 | * @offset: requested offset in the BO | |
1330 | * @flags: attributes of pages (read/write/valid/etc.) | |
1331 | * | |
1332 | * Add a mapping of the BO at the specefied addr into the VM. | |
1333 | * Returns 0 for success, error for failure. | |
1334 | * | |
49b02b18 | 1335 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1336 | */ |
1337 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1338 | struct amdgpu_bo_va *bo_va, | |
1339 | uint64_t saddr, uint64_t offset, | |
1340 | uint64_t size, uint32_t flags) | |
1341 | { | |
1342 | struct amdgpu_bo_va_mapping *mapping; | |
1343 | struct amdgpu_vm *vm = bo_va->vm; | |
1344 | struct interval_tree_node *it; | |
1345 | unsigned last_pfn, pt_idx; | |
1346 | uint64_t eaddr; | |
1347 | int r; | |
1348 | ||
0be52de9 CK |
1349 | /* validate the parameters */ |
1350 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1351 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1352 | return -EINVAL; |
0be52de9 | 1353 | |
d38ceaf9 | 1354 | /* make sure object fit at this offset */ |
005ae95e | 1355 | eaddr = saddr + size - 1; |
49b02b18 | 1356 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1357 | return -EINVAL; |
d38ceaf9 AD |
1358 | |
1359 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1360 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1361 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1362 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1363 | return -EINVAL; |
1364 | } | |
1365 | ||
d38ceaf9 AD |
1366 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1367 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1368 | ||
005ae95e | 1369 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1370 | if (it) { |
1371 | struct amdgpu_bo_va_mapping *tmp; | |
1372 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1373 | /* bo and tmp overlap, invalid addr */ | |
1374 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1375 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1376 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1377 | r = -EINVAL; |
f48b2659 | 1378 | goto error; |
d38ceaf9 AD |
1379 | } |
1380 | ||
1381 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1382 | if (!mapping) { | |
d38ceaf9 | 1383 | r = -ENOMEM; |
f48b2659 | 1384 | goto error; |
d38ceaf9 AD |
1385 | } |
1386 | ||
1387 | INIT_LIST_HEAD(&mapping->list); | |
1388 | mapping->it.start = saddr; | |
005ae95e | 1389 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1390 | mapping->offset = offset; |
1391 | mapping->flags = flags; | |
1392 | ||
7fc11959 | 1393 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1394 | interval_tree_insert(&mapping->it, &vm->va); |
1395 | ||
1396 | /* Make sure the page tables are allocated */ | |
1397 | saddr >>= amdgpu_vm_block_size; | |
1398 | eaddr >>= amdgpu_vm_block_size; | |
1399 | ||
1400 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1401 | ||
1402 | if (eaddr > vm->max_pde_used) | |
1403 | vm->max_pde_used = eaddr; | |
1404 | ||
d38ceaf9 AD |
1405 | /* walk over the address space and allocate the page tables */ |
1406 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1407 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1408 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1409 | struct amdgpu_bo *pt; |
1410 | ||
ee1782c3 CK |
1411 | entry = &vm->page_tables[pt_idx].entry; |
1412 | if (entry->robj) | |
d38ceaf9 AD |
1413 | continue; |
1414 | ||
d38ceaf9 AD |
1415 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1416 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d | 1417 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1418 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1419 | AMDGPU_GEM_CREATE_SHADOW, | |
bf60efd3 | 1420 | NULL, resv, &pt); |
49b02b18 | 1421 | if (r) |
d38ceaf9 | 1422 | goto error_free; |
49b02b18 | 1423 | |
82b9c55b CK |
1424 | /* Keep a reference to the page table to avoid freeing |
1425 | * them up in the wrong order. | |
1426 | */ | |
1427 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1428 | ||
2bd9ccfa | 1429 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 | 1430 | if (r) { |
2698f620 | 1431 | amdgpu_bo_unref(&pt->shadow); |
d38ceaf9 AD |
1432 | amdgpu_bo_unref(&pt); |
1433 | goto error_free; | |
1434 | } | |
1435 | ||
2befa60e CK |
1436 | if (pt->shadow) { |
1437 | r = amdgpu_vm_clear_bo(adev, vm, pt->shadow); | |
1438 | if (r) { | |
1439 | amdgpu_bo_unref(&pt->shadow); | |
1440 | amdgpu_bo_unref(&pt); | |
1441 | goto error_free; | |
1442 | } | |
1443 | } | |
1444 | ||
ee1782c3 | 1445 | entry->robj = pt; |
ee1782c3 CK |
1446 | entry->priority = 0; |
1447 | entry->tv.bo = &entry->robj->tbo; | |
1448 | entry->tv.shared = true; | |
2f568dbd | 1449 | entry->user_pages = NULL; |
d38ceaf9 | 1450 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1451 | } |
1452 | ||
d38ceaf9 AD |
1453 | return 0; |
1454 | ||
1455 | error_free: | |
d38ceaf9 AD |
1456 | list_del(&mapping->list); |
1457 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1458 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1459 | kfree(mapping); |
1460 | ||
f48b2659 | 1461 | error: |
d38ceaf9 AD |
1462 | return r; |
1463 | } | |
1464 | ||
1465 | /** | |
1466 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1467 | * | |
1468 | * @adev: amdgpu_device pointer | |
1469 | * @bo_va: bo_va to remove the address from | |
1470 | * @saddr: where to the BO is mapped | |
1471 | * | |
1472 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1473 | * Returns 0 for success, error for failure. | |
1474 | * | |
49b02b18 | 1475 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1476 | */ |
1477 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1478 | struct amdgpu_bo_va *bo_va, | |
1479 | uint64_t saddr) | |
1480 | { | |
1481 | struct amdgpu_bo_va_mapping *mapping; | |
1482 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1483 | bool valid = true; |
d38ceaf9 | 1484 | |
6c7fc503 | 1485 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1486 | |
7fc11959 | 1487 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1488 | if (mapping->it.start == saddr) |
1489 | break; | |
1490 | } | |
1491 | ||
7fc11959 CK |
1492 | if (&mapping->list == &bo_va->valids) { |
1493 | valid = false; | |
1494 | ||
1495 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1496 | if (mapping->it.start == saddr) | |
1497 | break; | |
1498 | } | |
1499 | ||
32b41ac2 | 1500 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1501 | return -ENOENT; |
d38ceaf9 | 1502 | } |
32b41ac2 | 1503 | |
d38ceaf9 AD |
1504 | list_del(&mapping->list); |
1505 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1506 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1507 | |
e17841b9 | 1508 | if (valid) |
d38ceaf9 | 1509 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1510 | else |
d38ceaf9 | 1511 | kfree(mapping); |
d38ceaf9 AD |
1512 | |
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | /** | |
1517 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1518 | * | |
1519 | * @adev: amdgpu_device pointer | |
1520 | * @bo_va: requested bo_va | |
1521 | * | |
8843dbbb | 1522 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1523 | * |
1524 | * Object have to be reserved! | |
1525 | */ | |
1526 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1527 | struct amdgpu_bo_va *bo_va) | |
1528 | { | |
1529 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1530 | struct amdgpu_vm *vm = bo_va->vm; | |
1531 | ||
1532 | list_del(&bo_va->bo_list); | |
1533 | ||
d38ceaf9 AD |
1534 | spin_lock(&vm->status_lock); |
1535 | list_del(&bo_va->vm_status); | |
1536 | spin_unlock(&vm->status_lock); | |
1537 | ||
7fc11959 | 1538 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1539 | list_del(&mapping->list); |
1540 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1541 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1542 | list_add(&mapping->list, &vm->freed); |
1543 | } | |
1544 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1545 | list_del(&mapping->list); | |
1546 | interval_tree_remove(&mapping->it, &vm->va); | |
1547 | kfree(mapping); | |
d38ceaf9 | 1548 | } |
32b41ac2 | 1549 | |
bb1e38a4 | 1550 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1551 | kfree(bo_va); |
d38ceaf9 AD |
1552 | } |
1553 | ||
1554 | /** | |
1555 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1556 | * | |
1557 | * @adev: amdgpu_device pointer | |
1558 | * @vm: requested vm | |
1559 | * @bo: amdgpu buffer object | |
1560 | * | |
8843dbbb | 1561 | * Mark @bo as invalid. |
d38ceaf9 AD |
1562 | */ |
1563 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1564 | struct amdgpu_bo *bo) | |
1565 | { | |
1566 | struct amdgpu_bo_va *bo_va; | |
1567 | ||
1568 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1569 | spin_lock(&bo_va->vm->status_lock); |
1570 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1571 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1572 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1573 | } |
1574 | } | |
1575 | ||
1576 | /** | |
1577 | * amdgpu_vm_init - initialize a vm instance | |
1578 | * | |
1579 | * @adev: amdgpu_device pointer | |
1580 | * @vm: requested vm | |
1581 | * | |
8843dbbb | 1582 | * Init @vm fields. |
d38ceaf9 AD |
1583 | */ |
1584 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1585 | { | |
1586 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1587 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1588 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1589 | unsigned ring_instance; |
1590 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1591 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1592 | int i, r; |
1593 | ||
bcb1ba35 CK |
1594 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1595 | vm->ids[i] = NULL; | |
d38ceaf9 | 1596 | vm->va = RB_ROOT; |
031e2983 | 1597 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1598 | spin_lock_init(&vm->status_lock); |
1599 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1600 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1601 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1602 | |
d38ceaf9 AD |
1603 | pd_size = amdgpu_vm_directory_size(adev); |
1604 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1605 | ||
1606 | /* allocate page table array */ | |
9571e1d8 | 1607 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1608 | if (vm->page_tables == NULL) { |
1609 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1610 | return -ENOMEM; | |
1611 | } | |
1612 | ||
2bd9ccfa | 1613 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1614 | |
1615 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1616 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1617 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1618 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1619 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1620 | rq, amdgpu_sched_jobs); | |
1621 | if (r) | |
64827adc | 1622 | goto err; |
2bd9ccfa | 1623 | |
05906dec BN |
1624 | vm->page_directory_fence = NULL; |
1625 | ||
d38ceaf9 | 1626 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d | 1627 | AMDGPU_GEM_DOMAIN_VRAM, |
1baa439f CZ |
1628 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | |
1629 | AMDGPU_GEM_CREATE_SHADOW, | |
72d7668b | 1630 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1631 | if (r) |
2bd9ccfa CK |
1632 | goto error_free_sched_entity; |
1633 | ||
ef9f0a83 | 1634 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1635 | if (r) |
1636 | goto error_free_page_directory; | |
1637 | ||
1638 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
2bd9ccfa | 1639 | if (r) |
2a82ec21 CK |
1640 | goto error_unreserve; |
1641 | ||
2befa60e CK |
1642 | if (vm->page_directory->shadow) { |
1643 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory->shadow); | |
1644 | if (r) | |
1645 | goto error_unreserve; | |
1646 | } | |
1647 | ||
5a712a87 | 1648 | vm->last_eviction_counter = atomic64_read(&adev->num_evictions); |
2a82ec21 | 1649 | amdgpu_bo_unreserve(vm->page_directory); |
d38ceaf9 AD |
1650 | |
1651 | return 0; | |
2bd9ccfa | 1652 | |
2a82ec21 CK |
1653 | error_unreserve: |
1654 | amdgpu_bo_unreserve(vm->page_directory); | |
1655 | ||
2bd9ccfa | 1656 | error_free_page_directory: |
2698f620 | 1657 | amdgpu_bo_unref(&vm->page_directory->shadow); |
2bd9ccfa CK |
1658 | amdgpu_bo_unref(&vm->page_directory); |
1659 | vm->page_directory = NULL; | |
1660 | ||
1661 | error_free_sched_entity: | |
1662 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1663 | ||
64827adc CZ |
1664 | err: |
1665 | drm_free_large(vm->page_tables); | |
1666 | ||
2bd9ccfa | 1667 | return r; |
d38ceaf9 AD |
1668 | } |
1669 | ||
1670 | /** | |
1671 | * amdgpu_vm_fini - tear down a vm instance | |
1672 | * | |
1673 | * @adev: amdgpu_device pointer | |
1674 | * @vm: requested vm | |
1675 | * | |
8843dbbb | 1676 | * Tear down @vm. |
d38ceaf9 AD |
1677 | * Unbind the VM and remove all bos from the vm bo list |
1678 | */ | |
1679 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1680 | { | |
1681 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1682 | int i; | |
1683 | ||
2d55e45a | 1684 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1685 | |
d38ceaf9 AD |
1686 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1687 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1688 | } | |
1689 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1690 | list_del(&mapping->list); | |
1691 | interval_tree_remove(&mapping->it, &vm->va); | |
1692 | kfree(mapping); | |
1693 | } | |
1694 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1695 | list_del(&mapping->list); | |
1696 | kfree(mapping); | |
1697 | } | |
1698 | ||
1baa439f | 1699 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { |
2698f620 CK |
1700 | struct amdgpu_bo *pt = vm->page_tables[i].entry.robj; |
1701 | ||
1702 | if (!pt) | |
1703 | continue; | |
1704 | ||
1705 | amdgpu_bo_unref(&pt->shadow); | |
1706 | amdgpu_bo_unref(&pt); | |
1baa439f | 1707 | } |
9571e1d8 | 1708 | drm_free_large(vm->page_tables); |
d38ceaf9 | 1709 | |
2698f620 | 1710 | amdgpu_bo_unref(&vm->page_directory->shadow); |
d38ceaf9 | 1711 | amdgpu_bo_unref(&vm->page_directory); |
05906dec | 1712 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1713 | } |
ea89f8c9 | 1714 | |
a9a78b32 CK |
1715 | /** |
1716 | * amdgpu_vm_manager_init - init the VM manager | |
1717 | * | |
1718 | * @adev: amdgpu_device pointer | |
1719 | * | |
1720 | * Initialize the VM manager structures | |
1721 | */ | |
1722 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1723 | { | |
1724 | unsigned i; | |
1725 | ||
1726 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1727 | ||
1728 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1729 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1730 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1731 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1732 | list_add_tail(&adev->vm_manager.ids[i].list, |
1733 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1734 | } |
2d55e45a | 1735 | |
1fbb2e92 CK |
1736 | adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); |
1737 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | |
1738 | adev->vm_manager.seqno[i] = 0; | |
1739 | ||
2d55e45a | 1740 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 1741 | atomic64_set(&adev->vm_manager.client_counter, 0); |
a9a78b32 CK |
1742 | } |
1743 | ||
ea89f8c9 CK |
1744 | /** |
1745 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1746 | * | |
1747 | * @adev: amdgpu_device pointer | |
1748 | * | |
1749 | * Cleanup the VM manager and free resources. | |
1750 | */ | |
1751 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1752 | { | |
1753 | unsigned i; | |
1754 | ||
bcb1ba35 CK |
1755 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1756 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1757 | ||
832a902f CK |
1758 | fence_put(adev->vm_manager.ids[i].first); |
1759 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1760 | fence_put(id->flushed_updates); |
1761 | } | |
ea89f8c9 | 1762 | } |