Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
ede0dd86 | 35 | #include "amdgpu_amdkfd.h" |
c8c5e569 | 36 | #include "amdgpu_gmc.h" |
d38ceaf9 | 37 | |
7fc48e59 AG |
38 | /** |
39 | * DOC: GPUVM | |
40 | * | |
d38ceaf9 AD |
41 | * GPUVM is similar to the legacy gart on older asics, however |
42 | * rather than there being a single global gart table | |
43 | * for the entire GPU, there are multiple VM page tables active | |
44 | * at any given time. The VM page tables can contain a mix | |
45 | * vram pages and system memory pages and system memory pages | |
46 | * can be mapped as snooped (cached system pages) or unsnooped | |
47 | * (uncached system pages). | |
48 | * Each VM has an ID associated with it and there is a page table | |
49 | * associated with each VMID. When execting a command buffer, | |
50 | * the kernel tells the the ring what VMID to use for that command | |
51 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
52 | * The userspace drivers maintain their own address space and the kernel | |
53 | * sets up their pages tables accordingly when they submit their | |
54 | * command buffers and a VMID is assigned. | |
55 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
56 | * SI supports 16. | |
57 | */ | |
58 | ||
a9f87f64 CK |
59 | #define START(node) ((node)->start) |
60 | #define LAST(node) ((node)->last) | |
61 | ||
62 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
63 | START, LAST, static, amdgpu_vm_it) | |
64 | ||
65 | #undef START | |
66 | #undef LAST | |
67 | ||
7fc48e59 AG |
68 | /** |
69 | * struct amdgpu_pte_update_params - Local structure | |
70 | * | |
71 | * Encapsulate some VM table update parameters to reduce | |
f4833c4f | 72 | * the number of function parameters |
7fc48e59 | 73 | * |
f4833c4f | 74 | */ |
29efc4f5 | 75 | struct amdgpu_pte_update_params { |
7fc48e59 AG |
76 | |
77 | /** | |
78 | * @adev: amdgpu device we do this update for | |
79 | */ | |
27c5f36f | 80 | struct amdgpu_device *adev; |
7fc48e59 AG |
81 | |
82 | /** | |
83 | * @vm: optional amdgpu_vm we do this update for | |
84 | */ | |
49ac8a24 | 85 | struct amdgpu_vm *vm; |
7fc48e59 AG |
86 | |
87 | /** | |
88 | * @src: address where to copy page table entries from | |
89 | */ | |
f4833c4f | 90 | uint64_t src; |
7fc48e59 AG |
91 | |
92 | /** | |
93 | * @ib: indirect buffer to fill with commands | |
94 | */ | |
f4833c4f | 95 | struct amdgpu_ib *ib; |
7fc48e59 AG |
96 | |
97 | /** | |
98 | * @func: Function which actually does the update | |
99 | */ | |
373ac645 CK |
100 | void (*func)(struct amdgpu_pte_update_params *params, |
101 | struct amdgpu_bo *bo, uint64_t pe, | |
afef8b8f | 102 | uint64_t addr, unsigned count, uint32_t incr, |
6b777607 | 103 | uint64_t flags); |
7fc48e59 AG |
104 | /** |
105 | * @pages_addr: | |
106 | * | |
107 | * DMA addresses to use for mapping, used during VM update by CPU | |
b4d42511 HK |
108 | */ |
109 | dma_addr_t *pages_addr; | |
7fc48e59 AG |
110 | |
111 | /** | |
112 | * @kptr: | |
113 | * | |
114 | * Kernel pointer of PD/PT BO that needs to be updated, | |
115 | * used during VM update by CPU | |
116 | */ | |
b4d42511 | 117 | void *kptr; |
f4833c4f HK |
118 | }; |
119 | ||
7fc48e59 AG |
120 | /** |
121 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
122 | */ | |
284710fa | 123 | struct amdgpu_prt_cb { |
7fc48e59 AG |
124 | |
125 | /** | |
126 | * @adev: amdgpu device | |
127 | */ | |
284710fa | 128 | struct amdgpu_device *adev; |
7fc48e59 AG |
129 | |
130 | /** | |
131 | * @cb: callback | |
132 | */ | |
284710fa CK |
133 | struct dma_fence_cb cb; |
134 | }; | |
135 | ||
7fc48e59 AG |
136 | /** |
137 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
138 | * | |
139 | * @base: base structure for tracking BO usage in a VM | |
140 | * @vm: vm to which bo is to be added | |
141 | * @bo: amdgpu buffer object | |
142 | * | |
143 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
144 | * | |
145 | */ | |
3f4299be CZ |
146 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, |
147 | struct amdgpu_vm *vm, | |
148 | struct amdgpu_bo *bo) | |
149 | { | |
150 | base->vm = vm; | |
151 | base->bo = bo; | |
152 | INIT_LIST_HEAD(&base->bo_list); | |
153 | INIT_LIST_HEAD(&base->vm_status); | |
154 | ||
155 | if (!bo) | |
156 | return; | |
157 | list_add_tail(&base->bo_list, &bo->va); | |
158 | ||
e8511578 AG |
159 | if (bo->tbo.type == ttm_bo_type_kernel) |
160 | list_move(&base->vm_status, &vm->relocated); | |
161 | ||
3f4299be CZ |
162 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) |
163 | return; | |
164 | ||
165 | if (bo->preferred_domains & | |
166 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
167 | return; | |
168 | ||
169 | /* | |
170 | * we checked all the prerequisites, but it looks like this per vm bo | |
171 | * is currently evicted. add the bo to the evicted list to make sure it | |
172 | * is validated on next vm use to avoid fault. | |
173 | * */ | |
3f4299be | 174 | list_move_tail(&base->vm_status, &vm->evicted); |
3f4299be CZ |
175 | } |
176 | ||
50783147 CK |
177 | /** |
178 | * amdgpu_vm_level_shift - return the addr shift for each level | |
179 | * | |
180 | * @adev: amdgpu_device pointer | |
7fc48e59 | 181 | * @level: VMPT level |
50783147 | 182 | * |
7fc48e59 AG |
183 | * Returns: |
184 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
185 | */ |
186 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
187 | unsigned level) | |
188 | { | |
196f7489 CZ |
189 | unsigned shift = 0xff; |
190 | ||
191 | switch (level) { | |
192 | case AMDGPU_VM_PDB2: | |
193 | case AMDGPU_VM_PDB1: | |
194 | case AMDGPU_VM_PDB0: | |
195 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 196 | adev->vm_manager.block_size; |
196f7489 CZ |
197 | break; |
198 | case AMDGPU_VM_PTB: | |
199 | shift = 0; | |
200 | break; | |
201 | default: | |
202 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
203 | } | |
204 | ||
205 | return shift; | |
50783147 CK |
206 | } |
207 | ||
d38ceaf9 | 208 | /** |
72a7ec5c | 209 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
210 | * |
211 | * @adev: amdgpu_device pointer | |
7fc48e59 | 212 | * @level: VMPT level |
d38ceaf9 | 213 | * |
7fc48e59 AG |
214 | * Returns: |
215 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 216 | */ |
72a7ec5c CK |
217 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
218 | unsigned level) | |
d38ceaf9 | 219 | { |
196f7489 CZ |
220 | unsigned shift = amdgpu_vm_level_shift(adev, |
221 | adev->vm_manager.root_level); | |
0410c5e5 | 222 | |
196f7489 | 223 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 224 | /* For the root directory */ |
0410c5e5 | 225 | return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; |
196f7489 | 226 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
227 | /* Everything in between */ |
228 | return 512; | |
229 | else | |
72a7ec5c | 230 | /* For the page tables on the leaves */ |
36b32a68 | 231 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
232 | } |
233 | ||
234 | /** | |
72a7ec5c | 235 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
236 | * |
237 | * @adev: amdgpu_device pointer | |
7fc48e59 | 238 | * @level: VMPT level |
d38ceaf9 | 239 | * |
7fc48e59 AG |
240 | * Returns: |
241 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 242 | */ |
72a7ec5c | 243 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 244 | { |
72a7ec5c | 245 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
246 | } |
247 | ||
248 | /** | |
56467ebf | 249 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
250 | * |
251 | * @vm: vm providing the BOs | |
3c0eea6c | 252 | * @validated: head of validation list |
56467ebf | 253 | * @entry: entry to add |
d38ceaf9 AD |
254 | * |
255 | * Add the page directory to the list of BOs to | |
56467ebf | 256 | * validate for command submission. |
d38ceaf9 | 257 | */ |
56467ebf CK |
258 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
259 | struct list_head *validated, | |
260 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 261 | { |
3f3333f8 | 262 | entry->robj = vm->root.base.bo; |
56467ebf | 263 | entry->priority = 0; |
67003a15 | 264 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 265 | entry->tv.shared = true; |
2f568dbd | 266 | entry->user_pages = NULL; |
56467ebf CK |
267 | list_add(&entry->tv.head, validated); |
268 | } | |
d38ceaf9 | 269 | |
670fecc8 | 270 | /** |
f7da30d9 | 271 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 272 | * |
5a712a87 | 273 | * @adev: amdgpu device pointer |
56467ebf | 274 | * @vm: vm providing the BOs |
670fecc8 CK |
275 | * @validate: callback to do the validation |
276 | * @param: parameter for the validation callback | |
277 | * | |
278 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
279 | * |
280 | * Returns: | |
281 | * Validation result. | |
670fecc8 | 282 | */ |
f7da30d9 CK |
283 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
284 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
285 | void *param) | |
670fecc8 | 286 | { |
3f3333f8 | 287 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
91ccdd24 CK |
288 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
289 | int r = 0; | |
670fecc8 | 290 | |
91ccdd24 CK |
291 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
292 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 293 | |
3f3333f8 CK |
294 | if (bo->parent) { |
295 | r = validate(param, bo); | |
296 | if (r) | |
91ccdd24 | 297 | break; |
670fecc8 | 298 | |
3f3333f8 CK |
299 | spin_lock(&glob->lru_lock); |
300 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
301 | if (bo->shadow) | |
302 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
303 | spin_unlock(&glob->lru_lock); | |
304 | } | |
670fecc8 | 305 | |
af4c0f65 CK |
306 | if (bo->tbo.type != ttm_bo_type_kernel) { |
307 | spin_lock(&vm->moved_lock); | |
73fb16e7 | 308 | list_move(&bo_base->vm_status, &vm->moved); |
af4c0f65 CK |
309 | spin_unlock(&vm->moved_lock); |
310 | } else { | |
73fb16e7 | 311 | list_move(&bo_base->vm_status, &vm->relocated); |
af4c0f65 | 312 | } |
670fecc8 CK |
313 | } |
314 | ||
806f043f CK |
315 | spin_lock(&glob->lru_lock); |
316 | list_for_each_entry(bo_base, &vm->idle, vm_status) { | |
317 | struct amdgpu_bo *bo = bo_base->bo; | |
318 | ||
319 | if (!bo->parent) | |
320 | continue; | |
321 | ||
322 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
323 | if (bo->shadow) | |
324 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
325 | } | |
326 | spin_unlock(&glob->lru_lock); | |
327 | ||
91ccdd24 | 328 | return r; |
670fecc8 CK |
329 | } |
330 | ||
56467ebf | 331 | /** |
34d7be5d | 332 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 333 | * |
34d7be5d | 334 | * @vm: VM to check |
d38ceaf9 | 335 | * |
34d7be5d | 336 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
337 | * |
338 | * Returns: | |
339 | * True if eviction list is empty. | |
d38ceaf9 | 340 | */ |
3f3333f8 | 341 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 342 | { |
af4c0f65 | 343 | return list_empty(&vm->evicted); |
d711e139 CK |
344 | } |
345 | ||
13307f7e CK |
346 | /** |
347 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
348 | * | |
349 | * @adev: amdgpu_device pointer | |
7fc48e59 | 350 | * @vm: VM to clear BO from |
13307f7e CK |
351 | * @bo: BO to clear |
352 | * @level: level this BO is at | |
00553cf8 | 353 | * @pte_support_ats: indicate ATS support from PTE |
13307f7e CK |
354 | * |
355 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
356 | * |
357 | * Returns: | |
358 | * 0 on success, errno otherwise. | |
13307f7e CK |
359 | */ |
360 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
4584312d CK |
361 | struct amdgpu_vm *vm, struct amdgpu_bo *bo, |
362 | unsigned level, bool pte_support_ats) | |
13307f7e CK |
363 | { |
364 | struct ttm_operation_ctx ctx = { true, false }; | |
365 | struct dma_fence *fence = NULL; | |
4584312d | 366 | unsigned entries, ats_entries; |
13307f7e CK |
367 | struct amdgpu_ring *ring; |
368 | struct amdgpu_job *job; | |
4584312d | 369 | uint64_t addr; |
13307f7e CK |
370 | int r; |
371 | ||
4584312d CK |
372 | addr = amdgpu_bo_gpu_offset(bo); |
373 | entries = amdgpu_bo_size(bo) / 8; | |
374 | ||
375 | if (pte_support_ats) { | |
376 | if (level == adev->vm_manager.root_level) { | |
377 | ats_entries = amdgpu_vm_level_shift(adev, level); | |
378 | ats_entries += AMDGPU_GPU_PAGE_SHIFT; | |
379 | ats_entries = AMDGPU_VA_HOLE_START >> ats_entries; | |
380 | ats_entries = min(ats_entries, entries); | |
381 | entries -= ats_entries; | |
382 | } else { | |
383 | ats_entries = entries; | |
384 | entries = 0; | |
385 | } | |
13307f7e | 386 | } else { |
4584312d | 387 | ats_entries = 0; |
13307f7e CK |
388 | } |
389 | ||
068c3304 | 390 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched); |
13307f7e CK |
391 | |
392 | r = reservation_object_reserve_shared(bo->tbo.resv); | |
393 | if (r) | |
394 | return r; | |
395 | ||
396 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
397 | if (r) | |
398 | goto error; | |
399 | ||
13307f7e CK |
400 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
401 | if (r) | |
402 | goto error; | |
403 | ||
4584312d CK |
404 | if (ats_entries) { |
405 | uint64_t ats_value; | |
406 | ||
407 | ats_value = AMDGPU_PTE_DEFAULT_ATC; | |
408 | if (level != AMDGPU_VM_PTB) | |
409 | ats_value |= AMDGPU_PDE_PTE; | |
410 | ||
411 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
412 | ats_entries, 0, ats_value); | |
413 | addr += ats_entries * 8; | |
414 | } | |
415 | ||
416 | if (entries) | |
417 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
418 | entries, 0, 0); | |
419 | ||
13307f7e CK |
420 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
421 | ||
422 | WARN_ON(job->ibs[0].length_dw > 64); | |
29e8357b CK |
423 | r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, |
424 | AMDGPU_FENCE_OWNER_UNDEFINED, false); | |
425 | if (r) | |
426 | goto error_free; | |
427 | ||
0e28b10f CK |
428 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED, |
429 | &fence); | |
13307f7e CK |
430 | if (r) |
431 | goto error_free; | |
432 | ||
433 | amdgpu_bo_fence(bo, fence, true); | |
434 | dma_fence_put(fence); | |
e61736da CK |
435 | |
436 | if (bo->shadow) | |
437 | return amdgpu_vm_clear_bo(adev, vm, bo->shadow, | |
438 | level, pte_support_ats); | |
439 | ||
13307f7e CK |
440 | return 0; |
441 | ||
442 | error_free: | |
443 | amdgpu_job_free(job); | |
444 | ||
445 | error: | |
446 | return r; | |
447 | } | |
448 | ||
d711e139 | 449 | /** |
f566ceb1 CK |
450 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
451 | * | |
452 | * @adev: amdgpu_device pointer | |
453 | * @vm: requested vm | |
7fc48e59 | 454 | * @parent: parent PT |
f566ceb1 CK |
455 | * @saddr: start of the address range |
456 | * @eaddr: end of the address range | |
7fc48e59 AG |
457 | * @level: VMPT level |
458 | * @ats: indicate ATS support from PTE | |
f566ceb1 CK |
459 | * |
460 | * Make sure the page directories and page tables are allocated | |
7fc48e59 AG |
461 | * |
462 | * Returns: | |
463 | * 0 on success, errno otherwise. | |
f566ceb1 CK |
464 | */ |
465 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
466 | struct amdgpu_vm *vm, | |
467 | struct amdgpu_vm_pt *parent, | |
468 | uint64_t saddr, uint64_t eaddr, | |
4584312d | 469 | unsigned level, bool ats) |
f566ceb1 | 470 | { |
50783147 | 471 | unsigned shift = amdgpu_vm_level_shift(adev, level); |
f566ceb1 | 472 | unsigned pt_idx, from, to; |
3c824172 | 473 | u64 flags; |
13307f7e | 474 | int r; |
f566ceb1 CK |
475 | |
476 | if (!parent->entries) { | |
477 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
478 | ||
2098105e MH |
479 | parent->entries = kvmalloc_array(num_entries, |
480 | sizeof(struct amdgpu_vm_pt), | |
481 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
482 | if (!parent->entries) |
483 | return -ENOMEM; | |
484 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
485 | } | |
486 | ||
1866bac8 FK |
487 | from = saddr >> shift; |
488 | to = eaddr >> shift; | |
489 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
490 | to >= amdgpu_vm_num_entries(adev, level)) | |
491 | return -EINVAL; | |
f566ceb1 | 492 | |
f566ceb1 | 493 | ++level; |
1866bac8 FK |
494 | saddr = saddr & ((1 << shift) - 1); |
495 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 496 | |
13307f7e | 497 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; |
3c824172 HK |
498 | if (vm->use_cpu_for_update) |
499 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
500 | else | |
501 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
502 | AMDGPU_GEM_CREATE_SHADOW); | |
503 | ||
f566ceb1 CK |
504 | /* walk over the address space and allocate the page tables */ |
505 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 506 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
507 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
508 | struct amdgpu_bo *pt; | |
509 | ||
3f3333f8 | 510 | if (!entry->base.bo) { |
3216c6b7 CZ |
511 | struct amdgpu_bo_param bp; |
512 | ||
513 | memset(&bp, 0, sizeof(bp)); | |
514 | bp.size = amdgpu_vm_bo_size(adev, level); | |
515 | bp.byte_align = AMDGPU_GPU_PAGE_SIZE; | |
516 | bp.domain = AMDGPU_GEM_DOMAIN_VRAM; | |
517 | bp.flags = flags; | |
518 | bp.type = ttm_bo_type_kernel; | |
519 | bp.resv = resv; | |
520 | r = amdgpu_bo_create(adev, &bp, &pt); | |
f566ceb1 CK |
521 | if (r) |
522 | return r; | |
523 | ||
4584312d | 524 | r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats); |
13307f7e | 525 | if (r) { |
e5197a4c | 526 | amdgpu_bo_unref(&pt->shadow); |
13307f7e CK |
527 | amdgpu_bo_unref(&pt); |
528 | return r; | |
529 | } | |
530 | ||
0a096fb6 CK |
531 | if (vm->use_cpu_for_update) { |
532 | r = amdgpu_bo_kmap(pt, NULL); | |
533 | if (r) { | |
e5197a4c | 534 | amdgpu_bo_unref(&pt->shadow); |
0a096fb6 CK |
535 | amdgpu_bo_unref(&pt); |
536 | return r; | |
537 | } | |
538 | } | |
539 | ||
f566ceb1 CK |
540 | /* Keep a reference to the root directory to avoid |
541 | * freeing them up in the wrong order. | |
542 | */ | |
0f2fc435 | 543 | pt->parent = amdgpu_bo_ref(parent->base.bo); |
f566ceb1 | 544 | |
3f4299be | 545 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); |
f566ceb1 CK |
546 | } |
547 | ||
196f7489 | 548 | if (level < AMDGPU_VM_PTB) { |
1866bac8 FK |
549 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
550 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
551 | ((1 << shift) - 1); | |
552 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
4584312d | 553 | sub_eaddr, level, ats); |
f566ceb1 CK |
554 | if (r) |
555 | return r; | |
556 | } | |
557 | } | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
663e4577 CK |
562 | /** |
563 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
564 | * | |
565 | * @adev: amdgpu_device pointer | |
566 | * @vm: VM to allocate page tables for | |
567 | * @saddr: Start address which needs to be allocated | |
568 | * @size: Size from start address we need. | |
569 | * | |
570 | * Make sure the page tables are allocated. | |
7fc48e59 AG |
571 | * |
572 | * Returns: | |
573 | * 0 on success, errno otherwise. | |
663e4577 CK |
574 | */ |
575 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
576 | struct amdgpu_vm *vm, | |
577 | uint64_t saddr, uint64_t size) | |
578 | { | |
663e4577 | 579 | uint64_t eaddr; |
4584312d | 580 | bool ats = false; |
663e4577 CK |
581 | |
582 | /* validate the parameters */ | |
583 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
584 | return -EINVAL; | |
585 | ||
586 | eaddr = saddr + size - 1; | |
4584312d CK |
587 | |
588 | if (vm->pte_support_ats) | |
589 | ats = saddr < AMDGPU_VA_HOLE_START; | |
663e4577 CK |
590 | |
591 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
592 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
593 | ||
4584312d CK |
594 | if (eaddr >= adev->vm_manager.max_pfn) { |
595 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", | |
596 | eaddr, adev->vm_manager.max_pfn); | |
597 | return -EINVAL; | |
598 | } | |
599 | ||
196f7489 | 600 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, |
4584312d | 601 | adev->vm_manager.root_level, ats); |
663e4577 CK |
602 | } |
603 | ||
e59c0205 AX |
604 | /** |
605 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
606 | * | |
607 | * @adev: amdgpu_device pointer | |
608 | */ | |
609 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 610 | { |
a1255107 | 611 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
612 | bool has_compute_vm_bug; |
613 | struct amdgpu_ring *ring; | |
614 | int i; | |
93dcc37d | 615 | |
e59c0205 | 616 | has_compute_vm_bug = false; |
93dcc37d | 617 | |
2990a1fc | 618 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
619 | if (ip_block) { |
620 | /* Compute has a VM bug for GFX version < 7. | |
621 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
622 | if (ip_block->version->major <= 7) | |
623 | has_compute_vm_bug = true; | |
624 | else if (ip_block->version->major == 8) | |
625 | if (adev->gfx.mec_fw_version < 673) | |
626 | has_compute_vm_bug = true; | |
627 | } | |
93dcc37d | 628 | |
e59c0205 AX |
629 | for (i = 0; i < adev->num_rings; i++) { |
630 | ring = adev->rings[i]; | |
631 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
632 | /* only compute rings */ | |
633 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 634 | else |
e59c0205 | 635 | ring->has_compute_vm_bug = false; |
93dcc37d | 636 | } |
93dcc37d AD |
637 | } |
638 | ||
7fc48e59 AG |
639 | /** |
640 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
641 | * | |
642 | * @ring: ring on which the job will be submitted | |
643 | * @job: job to submit | |
644 | * | |
645 | * Returns: | |
646 | * True if sync is needed. | |
647 | */ | |
b9bf33d5 CZ |
648 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
649 | struct amdgpu_job *job) | |
e60f8db5 | 650 | { |
b9bf33d5 CZ |
651 | struct amdgpu_device *adev = ring->adev; |
652 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
653 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
654 | struct amdgpu_vmid *id; | |
b9bf33d5 | 655 | bool gds_switch_needed; |
e59c0205 | 656 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 657 | |
c4f46f22 | 658 | if (job->vmid == 0) |
b9bf33d5 | 659 | return false; |
c4f46f22 | 660 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
661 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
662 | id->gds_base != job->gds_base || | |
663 | id->gds_size != job->gds_size || | |
664 | id->gws_base != job->gws_base || | |
665 | id->gws_size != job->gws_size || | |
666 | id->oa_base != job->oa_base || | |
667 | id->oa_size != job->oa_size); | |
e60f8db5 | 668 | |
620f774f | 669 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 670 | return true; |
e60f8db5 | 671 | |
bb37b67d | 672 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
673 | } |
674 | ||
d38ceaf9 AD |
675 | /** |
676 | * amdgpu_vm_flush - hardware flush the vm | |
677 | * | |
678 | * @ring: ring to use for flush | |
00553cf8 | 679 | * @job: related job |
7fc48e59 | 680 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 681 | * |
4ff37a83 | 682 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
683 | * |
684 | * Returns: | |
685 | * 0 on success, errno otherwise. | |
d38ceaf9 | 686 | */ |
8fdf074f | 687 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 688 | { |
971fe9a9 | 689 | struct amdgpu_device *adev = ring->adev; |
7645670d | 690 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 691 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 692 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 693 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
694 | id->gds_base != job->gds_base || |
695 | id->gds_size != job->gds_size || | |
696 | id->gws_base != job->gws_base || | |
697 | id->gws_size != job->gws_size || | |
698 | id->oa_base != job->oa_base || | |
699 | id->oa_size != job->oa_size); | |
de37e68a | 700 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f CK |
701 | bool pasid_mapping_needed = id->pasid != job->pasid || |
702 | !id->pasid_mapping || | |
703 | !dma_fence_is_signaled(id->pasid_mapping); | |
704 | struct dma_fence *fence = NULL; | |
c0e51931 | 705 | unsigned patch_offset = 0; |
41d9eb2c | 706 | int r; |
d564a06e | 707 | |
620f774f | 708 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
709 | gds_switch_needed = true; |
710 | vm_flush_needed = true; | |
b3cd285f | 711 | pasid_mapping_needed = true; |
f7d015b9 | 712 | } |
971fe9a9 | 713 | |
b3cd285f CK |
714 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
715 | vm_flush_needed &= !!ring->funcs->emit_vm_flush; | |
716 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && | |
717 | ring->funcs->emit_wreg; | |
718 | ||
8fdf074f | 719 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 720 | return 0; |
41d9eb2c | 721 | |
c0e51931 CK |
722 | if (ring->funcs->init_cond_exec) |
723 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 724 | |
8fdf074f ML |
725 | if (need_pipe_sync) |
726 | amdgpu_ring_emit_pipeline_sync(ring); | |
727 | ||
b3cd285f | 728 | if (vm_flush_needed) { |
c4f46f22 | 729 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 730 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
731 | } |
732 | ||
733 | if (pasid_mapping_needed) | |
734 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 735 | |
b3cd285f | 736 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 737 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
738 | if (r) |
739 | return r; | |
b3cd285f | 740 | } |
e9d672b2 | 741 | |
b3cd285f | 742 | if (vm_flush_needed) { |
7645670d | 743 | mutex_lock(&id_mgr->lock); |
c0e51931 | 744 | dma_fence_put(id->last_flush); |
b3cd285f CK |
745 | id->last_flush = dma_fence_get(fence); |
746 | id->current_gpu_reset_count = | |
747 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 748 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 749 | } |
e9d672b2 | 750 | |
b3cd285f CK |
751 | if (pasid_mapping_needed) { |
752 | id->pasid = job->pasid; | |
753 | dma_fence_put(id->pasid_mapping); | |
754 | id->pasid_mapping = dma_fence_get(fence); | |
755 | } | |
756 | dma_fence_put(fence); | |
757 | ||
7c4378f4 | 758 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
759 | id->gds_base = job->gds_base; |
760 | id->gds_size = job->gds_size; | |
761 | id->gws_base = job->gws_base; | |
762 | id->gws_size = job->gws_size; | |
763 | id->oa_base = job->oa_base; | |
764 | id->oa_size = job->oa_size; | |
c4f46f22 | 765 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
766 | job->gds_size, job->gws_base, |
767 | job->gws_size, job->oa_base, | |
768 | job->oa_size); | |
769 | } | |
770 | ||
771 | if (ring->funcs->patch_cond_exec) | |
772 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
773 | ||
774 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
775 | if (ring->funcs->emit_switch_buffer) { | |
776 | amdgpu_ring_emit_switch_buffer(ring); | |
777 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 778 | } |
41d9eb2c | 779 | return 0; |
971fe9a9 CK |
780 | } |
781 | ||
d38ceaf9 AD |
782 | /** |
783 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
784 | * | |
785 | * @vm: requested vm | |
786 | * @bo: requested buffer object | |
787 | * | |
8843dbbb | 788 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
789 | * Search inside the @bos vm list for the requested vm |
790 | * Returns the found bo_va or NULL if none is found | |
791 | * | |
792 | * Object has to be reserved! | |
7fc48e59 AG |
793 | * |
794 | * Returns: | |
795 | * Found bo_va or NULL. | |
d38ceaf9 AD |
796 | */ |
797 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
798 | struct amdgpu_bo *bo) | |
799 | { | |
800 | struct amdgpu_bo_va *bo_va; | |
801 | ||
ec681545 CK |
802 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
803 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
804 | return bo_va; |
805 | } | |
806 | } | |
807 | return NULL; | |
808 | } | |
809 | ||
810 | /** | |
afef8b8f | 811 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 812 | * |
29efc4f5 | 813 | * @params: see amdgpu_pte_update_params definition |
373ac645 | 814 | * @bo: PD/PT to update |
d38ceaf9 AD |
815 | * @pe: addr of the page entry |
816 | * @addr: dst addr to write into pe | |
817 | * @count: number of page entries to update | |
818 | * @incr: increase next addr by incr bytes | |
819 | * @flags: hw access flags | |
d38ceaf9 AD |
820 | * |
821 | * Traces the parameters and calls the right asic functions | |
822 | * to setup the page table using the DMA. | |
823 | */ | |
afef8b8f | 824 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
373ac645 | 825 | struct amdgpu_bo *bo, |
afef8b8f CK |
826 | uint64_t pe, uint64_t addr, |
827 | unsigned count, uint32_t incr, | |
6b777607 | 828 | uint64_t flags) |
d38ceaf9 | 829 | { |
373ac645 | 830 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 | 831 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 832 | |
afef8b8f | 833 | if (count < 3) { |
de9ea7bd CK |
834 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
835 | addr | flags, count, incr); | |
d38ceaf9 AD |
836 | |
837 | } else { | |
27c5f36f | 838 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
839 | count, incr, flags); |
840 | } | |
841 | } | |
842 | ||
afef8b8f CK |
843 | /** |
844 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
845 | * | |
846 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 847 | * @bo: PD/PT to update |
afef8b8f CK |
848 | * @pe: addr of the page entry |
849 | * @addr: dst addr to write into pe | |
850 | * @count: number of page entries to update | |
851 | * @incr: increase next addr by incr bytes | |
852 | * @flags: hw access flags | |
853 | * | |
854 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
855 | */ | |
856 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 857 | struct amdgpu_bo *bo, |
afef8b8f CK |
858 | uint64_t pe, uint64_t addr, |
859 | unsigned count, uint32_t incr, | |
6b777607 | 860 | uint64_t flags) |
afef8b8f | 861 | { |
ec2f05f0 | 862 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 863 | |
373ac645 | 864 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 CK |
865 | trace_amdgpu_vm_copy_ptes(pe, src, count); |
866 | ||
867 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
868 | } |
869 | ||
d38ceaf9 | 870 | /** |
b07c9d2a | 871 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 872 | * |
b07c9d2a | 873 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
874 | * @addr: the unmapped addr |
875 | * | |
876 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
877 | * to. |
878 | * | |
879 | * Returns: | |
880 | * The pointer for the page table entry. | |
d38ceaf9 | 881 | */ |
de9ea7bd | 882 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
883 | { |
884 | uint64_t result; | |
885 | ||
de9ea7bd CK |
886 | /* page table offset */ |
887 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 888 | |
de9ea7bd CK |
889 | /* in case cpu page size != gpu page size*/ |
890 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 891 | |
b07c9d2a | 892 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
893 | |
894 | return result; | |
895 | } | |
896 | ||
3c824172 HK |
897 | /** |
898 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
899 | * | |
900 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 901 | * @bo: PD/PT to update |
3c824172 HK |
902 | * @pe: kmap addr of the page entry |
903 | * @addr: dst addr to write into pe | |
904 | * @count: number of page entries to update | |
905 | * @incr: increase next addr by incr bytes | |
906 | * @flags: hw access flags | |
907 | * | |
908 | * Write count number of PT/PD entries directly. | |
909 | */ | |
910 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 911 | struct amdgpu_bo *bo, |
3c824172 HK |
912 | uint64_t pe, uint64_t addr, |
913 | unsigned count, uint32_t incr, | |
914 | uint64_t flags) | |
915 | { | |
916 | unsigned int i; | |
b4d42511 | 917 | uint64_t value; |
3c824172 | 918 | |
373ac645 CK |
919 | pe += (unsigned long)amdgpu_bo_kptr(bo); |
920 | ||
03918b36 CK |
921 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
922 | ||
3c824172 | 923 | for (i = 0; i < count; i++) { |
b4d42511 HK |
924 | value = params->pages_addr ? |
925 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
926 | addr; | |
132f34e4 CK |
927 | amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
928 | i, value, flags); | |
3c824172 HK |
929 | addr += incr; |
930 | } | |
3c824172 HK |
931 | } |
932 | ||
7fc48e59 AG |
933 | |
934 | /** | |
935 | * amdgpu_vm_wait_pd - Wait for PT BOs to be free. | |
936 | * | |
937 | * @adev: amdgpu_device pointer | |
938 | * @vm: related vm | |
939 | * @owner: fence owner | |
940 | * | |
941 | * Returns: | |
942 | * 0 on success, errno otherwise. | |
943 | */ | |
a33cab7a CK |
944 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
945 | void *owner) | |
3c824172 HK |
946 | { |
947 | struct amdgpu_sync sync; | |
948 | int r; | |
949 | ||
950 | amdgpu_sync_create(&sync); | |
177ae09b | 951 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); |
3c824172 HK |
952 | r = amdgpu_sync_wait(&sync, true); |
953 | amdgpu_sync_free(&sync); | |
954 | ||
955 | return r; | |
956 | } | |
957 | ||
f8991bab | 958 | /* |
6989f246 | 959 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 960 | * |
6989f246 | 961 | * @param: parameters for the update |
f8991bab | 962 | * @vm: requested vm |
194d2161 | 963 | * @parent: parent directory |
6989f246 | 964 | * @entry: entry to update |
f8991bab | 965 | * |
6989f246 | 966 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 967 | */ |
6989f246 CK |
968 | static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, |
969 | struct amdgpu_vm *vm, | |
970 | struct amdgpu_vm_pt *parent, | |
971 | struct amdgpu_vm_pt *entry) | |
d38ceaf9 | 972 | { |
373ac645 | 973 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
974 | uint64_t pde, pt, flags; |
975 | unsigned level; | |
d5fc5e82 | 976 | |
6989f246 CK |
977 | /* Don't update huge pages here */ |
978 | if (entry->huge) | |
979 | return; | |
d38ceaf9 | 980 | |
373ac645 | 981 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
982 | pbo = pbo->parent; |
983 | ||
196f7489 | 984 | level += params->adev->vm_manager.root_level; |
373ac645 | 985 | pt = amdgpu_bo_gpu_offset(entry->base.bo); |
3de676d8 | 986 | flags = AMDGPU_PTE_VALID; |
132f34e4 | 987 | amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags); |
373ac645 CK |
988 | pde = (entry - parent->entries) * 8; |
989 | if (bo->shadow) | |
990 | params->func(params, bo->shadow, pde, pt, 1, 0, flags); | |
991 | params->func(params, bo, pde, pt, 1, 0, flags); | |
d38ceaf9 AD |
992 | } |
993 | ||
92456b93 CK |
994 | /* |
995 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
996 | * | |
7fc48e59 AG |
997 | * @adev: amdgpu_device pointer |
998 | * @vm: related vm | |
92456b93 | 999 | * @parent: parent PD |
7fc48e59 | 1000 | * @level: VMPT level |
92456b93 CK |
1001 | * |
1002 | * Mark all PD level as invalid after an error. | |
1003 | */ | |
8f19cd78 CK |
1004 | static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev, |
1005 | struct amdgpu_vm *vm, | |
1006 | struct amdgpu_vm_pt *parent, | |
1007 | unsigned level) | |
92456b93 | 1008 | { |
8f19cd78 | 1009 | unsigned pt_idx, num_entries; |
92456b93 CK |
1010 | |
1011 | /* | |
1012 | * Recurse into the subdirectories. This recursion is harmless because | |
1013 | * we only have a maximum of 5 layers. | |
1014 | */ | |
8f19cd78 CK |
1015 | num_entries = amdgpu_vm_num_entries(adev, level); |
1016 | for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) { | |
92456b93 CK |
1017 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
1018 | ||
3f3333f8 | 1019 | if (!entry->base.bo) |
92456b93 CK |
1020 | continue; |
1021 | ||
862b8c57 CK |
1022 | if (!entry->base.moved) |
1023 | list_move(&entry->base.vm_status, &vm->relocated); | |
8f19cd78 | 1024 | amdgpu_vm_invalidate_level(adev, vm, entry, level + 1); |
92456b93 CK |
1025 | } |
1026 | } | |
1027 | ||
194d2161 CK |
1028 | /* |
1029 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1030 | * | |
1031 | * @adev: amdgpu_device pointer | |
1032 | * @vm: requested vm | |
1033 | * | |
1034 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1035 | * |
1036 | * Returns: | |
1037 | * 0 for success, error for failure. | |
194d2161 CK |
1038 | */ |
1039 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1040 | struct amdgpu_vm *vm) | |
1041 | { | |
6989f246 CK |
1042 | struct amdgpu_pte_update_params params; |
1043 | struct amdgpu_job *job; | |
1044 | unsigned ndw = 0; | |
78aa02c7 | 1045 | int r = 0; |
92456b93 | 1046 | |
6989f246 CK |
1047 | if (list_empty(&vm->relocated)) |
1048 | return 0; | |
1049 | ||
1050 | restart: | |
1051 | memset(¶ms, 0, sizeof(params)); | |
1052 | params.adev = adev; | |
1053 | ||
1054 | if (vm->use_cpu_for_update) { | |
a7f91061 CK |
1055 | struct amdgpu_vm_bo_base *bo_base; |
1056 | ||
1057 | list_for_each_entry(bo_base, &vm->relocated, vm_status) { | |
1058 | r = amdgpu_bo_kmap(bo_base->bo, NULL); | |
1059 | if (unlikely(r)) | |
1060 | return r; | |
1061 | } | |
1062 | ||
6989f246 CK |
1063 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
1064 | if (unlikely(r)) | |
1065 | return r; | |
1066 | ||
1067 | params.func = amdgpu_vm_cpu_set_ptes; | |
1068 | } else { | |
1069 | ndw = 512 * 8; | |
1070 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
1071 | if (r) | |
1072 | return r; | |
1073 | ||
1074 | params.ib = &job->ibs[0]; | |
1075 | params.func = amdgpu_vm_do_set_ptes; | |
1076 | } | |
1077 | ||
ea09729c | 1078 | while (!list_empty(&vm->relocated)) { |
6989f246 CK |
1079 | struct amdgpu_vm_bo_base *bo_base, *parent; |
1080 | struct amdgpu_vm_pt *pt, *entry; | |
ea09729c CK |
1081 | struct amdgpu_bo *bo; |
1082 | ||
1083 | bo_base = list_first_entry(&vm->relocated, | |
1084 | struct amdgpu_vm_bo_base, | |
1085 | vm_status); | |
862b8c57 | 1086 | bo_base->moved = false; |
a315f232 | 1087 | list_del_init(&bo_base->vm_status); |
ea09729c CK |
1088 | |
1089 | bo = bo_base->bo->parent; | |
af4c0f65 | 1090 | if (!bo) |
6989f246 | 1091 | continue; |
6989f246 CK |
1092 | |
1093 | parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base, | |
1094 | bo_list); | |
1095 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
1096 | entry = container_of(bo_base, struct amdgpu_vm_pt, base); | |
1097 | ||
1098 | amdgpu_vm_update_pde(¶ms, vm, pt, entry); | |
1099 | ||
6989f246 CK |
1100 | if (!vm->use_cpu_for_update && |
1101 | (ndw - params.ib->length_dw) < 32) | |
1102 | break; | |
ea09729c | 1103 | } |
92456b93 | 1104 | |
68c62306 CK |
1105 | if (vm->use_cpu_for_update) { |
1106 | /* Flush HDP */ | |
1107 | mb(); | |
69882565 | 1108 | amdgpu_asic_flush_hdp(adev, NULL); |
6989f246 CK |
1109 | } else if (params.ib->length_dw == 0) { |
1110 | amdgpu_job_free(job); | |
1111 | } else { | |
1112 | struct amdgpu_bo *root = vm->root.base.bo; | |
1113 | struct amdgpu_ring *ring; | |
1114 | struct dma_fence *fence; | |
1115 | ||
068c3304 | 1116 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, |
6989f246 CK |
1117 | sched); |
1118 | ||
1119 | amdgpu_ring_pad_ib(ring, params.ib); | |
1120 | amdgpu_sync_resv(adev, &job->sync, root->tbo.resv, | |
1121 | AMDGPU_FENCE_OWNER_VM, false); | |
6989f246 | 1122 | WARN_ON(params.ib->length_dw > ndw); |
0e28b10f CK |
1123 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, |
1124 | &fence); | |
6989f246 CK |
1125 | if (r) |
1126 | goto error; | |
1127 | ||
1128 | amdgpu_bo_fence(root, fence, true); | |
1129 | dma_fence_put(vm->last_update); | |
1130 | vm->last_update = fence; | |
68c62306 CK |
1131 | } |
1132 | ||
6989f246 CK |
1133 | if (!list_empty(&vm->relocated)) |
1134 | goto restart; | |
1135 | ||
1136 | return 0; | |
1137 | ||
1138 | error: | |
196f7489 CZ |
1139 | amdgpu_vm_invalidate_level(adev, vm, &vm->root, |
1140 | adev->vm_manager.root_level); | |
6989f246 | 1141 | amdgpu_job_free(job); |
92456b93 | 1142 | return r; |
194d2161 CK |
1143 | } |
1144 | ||
4e2cb640 | 1145 | /** |
cf2f0a37 | 1146 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
1147 | * |
1148 | * @p: see amdgpu_pte_update_params definition | |
1149 | * @addr: virtual address in question | |
cf2f0a37 AD |
1150 | * @entry: resulting entry or NULL |
1151 | * @parent: parent entry | |
4e2cb640 | 1152 | * |
cf2f0a37 | 1153 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 1154 | */ |
cf2f0a37 AD |
1155 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
1156 | struct amdgpu_vm_pt **entry, | |
1157 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 1158 | { |
196f7489 | 1159 | unsigned level = p->adev->vm_manager.root_level; |
4e2cb640 | 1160 | |
cf2f0a37 AD |
1161 | *parent = NULL; |
1162 | *entry = &p->vm->root; | |
1163 | while ((*entry)->entries) { | |
e3a1b32a | 1164 | unsigned shift = amdgpu_vm_level_shift(p->adev, level++); |
50783147 | 1165 | |
cf2f0a37 | 1166 | *parent = *entry; |
e3a1b32a CK |
1167 | *entry = &(*entry)->entries[addr >> shift]; |
1168 | addr &= (1ULL << shift) - 1; | |
4e2cb640 CK |
1169 | } |
1170 | ||
196f7489 | 1171 | if (level != AMDGPU_VM_PTB) |
cf2f0a37 AD |
1172 | *entry = NULL; |
1173 | } | |
1174 | ||
1175 | /** | |
1176 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1177 | * | |
1178 | * @p: see amdgpu_pte_update_params definition | |
1179 | * @entry: vm_pt entry to check | |
1180 | * @parent: parent entry | |
1181 | * @nptes: number of PTEs updated with this operation | |
1182 | * @dst: destination address where the PTEs should point to | |
1183 | * @flags: access flags fro the PTEs | |
1184 | * | |
1185 | * Check if we can update the PD with a huge page. | |
1186 | */ | |
ec5207c9 CK |
1187 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1188 | struct amdgpu_vm_pt *entry, | |
1189 | struct amdgpu_vm_pt *parent, | |
1190 | unsigned nptes, uint64_t dst, | |
1191 | uint64_t flags) | |
cf2f0a37 | 1192 | { |
373ac645 | 1193 | uint64_t pde; |
cf2f0a37 AD |
1194 | |
1195 | /* In the case of a mixed PT the PDE must point to it*/ | |
3cc1d3ea CK |
1196 | if (p->adev->asic_type >= CHIP_VEGA10 && !p->src && |
1197 | nptes == AMDGPU_VM_PTE_COUNT(p->adev)) { | |
4ab4016a | 1198 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1199 | flags |= AMDGPU_PDE_PTE; |
1200 | } | |
1201 | ||
3cc1d3ea CK |
1202 | if (!(flags & AMDGPU_PDE_PTE)) { |
1203 | if (entry->huge) { | |
1204 | /* Add the entry to the relocated list to update it. */ | |
1205 | entry->huge = false; | |
3cc1d3ea | 1206 | list_move(&entry->base.vm_status, &p->vm->relocated); |
3cc1d3ea | 1207 | } |
ec5207c9 | 1208 | return; |
3cc1d3ea | 1209 | } |
cf2f0a37 | 1210 | |
3cc1d3ea | 1211 | entry->huge = true; |
132f34e4 | 1212 | amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags); |
3de676d8 | 1213 | |
373ac645 CK |
1214 | pde = (entry - parent->entries) * 8; |
1215 | if (parent->base.bo->shadow) | |
1216 | p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags); | |
1217 | p->func(p, parent->base.bo, pde, dst, 1, 0, flags); | |
4e2cb640 CK |
1218 | } |
1219 | ||
d38ceaf9 AD |
1220 | /** |
1221 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1222 | * | |
29efc4f5 | 1223 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1224 | * @start: start of GPU address range |
1225 | * @end: end of GPU address range | |
677131a1 | 1226 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1227 | * @flags: mapping flags |
1228 | * | |
8843dbbb | 1229 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1230 | * |
1231 | * Returns: | |
1232 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1233 | */ |
cc28c4ed | 1234 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1235 | uint64_t start, uint64_t end, |
6b777607 | 1236 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1237 | { |
36b32a68 ZJ |
1238 | struct amdgpu_device *adev = params->adev; |
1239 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1240 | |
301654a4 | 1241 | uint64_t addr, pe_start; |
21718497 | 1242 | struct amdgpu_bo *pt; |
301654a4 | 1243 | unsigned nptes; |
d38ceaf9 AD |
1244 | |
1245 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1246 | for (addr = start; addr < end; addr += nptes, |
1247 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1248 | struct amdgpu_vm_pt *entry, *parent; | |
1249 | ||
1250 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1251 | if (!entry) | |
1252 | return -ENOENT; | |
4e2cb640 | 1253 | |
d38ceaf9 AD |
1254 | if ((addr & ~mask) == (end & ~mask)) |
1255 | nptes = end - addr; | |
1256 | else | |
36b32a68 | 1257 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1258 | |
ec5207c9 CK |
1259 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1260 | nptes, dst, flags); | |
4ab4016a | 1261 | /* We don't need to update PTEs for huge pages */ |
78eb2f0c | 1262 | if (entry->huge) |
cf2f0a37 AD |
1263 | continue; |
1264 | ||
3f3333f8 | 1265 | pt = entry->base.bo; |
373ac645 CK |
1266 | pe_start = (addr & mask) * 8; |
1267 | if (pt->shadow) | |
1268 | params->func(params, pt->shadow, pe_start, dst, nptes, | |
1269 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1270 | params->func(params, pt, pe_start, dst, nptes, | |
301654a4 | 1271 | AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
1272 | } |
1273 | ||
cc28c4ed | 1274 | return 0; |
92696dd5 CK |
1275 | } |
1276 | ||
1277 | /* | |
1278 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1279 | * | |
1280 | * @params: see amdgpu_pte_update_params definition | |
1281 | * @vm: requested vm | |
1282 | * @start: first PTE to handle | |
1283 | * @end: last PTE to handle | |
1284 | * @dst: addr those PTEs should point to | |
1285 | * @flags: hw mapping flags | |
7fc48e59 AG |
1286 | * |
1287 | * Returns: | |
1288 | * 0 for success, -EINVAL for failure. | |
92696dd5 | 1289 | */ |
cc28c4ed | 1290 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1291 | uint64_t start, uint64_t end, |
6b777607 | 1292 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1293 | { |
1294 | /** | |
1295 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1296 | * field in the PTE. When this field is set to a non-zero value, page | |
1297 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1298 | * flags are considered valid for all PTEs within the fragment range | |
1299 | * and corresponding mappings are assumed to be physically contiguous. | |
1300 | * | |
1301 | * The L1 TLB can store a single PTE for the whole fragment, | |
1302 | * significantly increasing the space available for translation | |
1303 | * caching. This leads to large improvements in throughput when the | |
1304 | * TLB is under pressure. | |
1305 | * | |
1306 | * The L2 TLB distributes small and large fragments into two | |
1307 | * asymmetric partitions. The large fragment cache is significantly | |
1308 | * larger. Thus, we try to use large fragments wherever possible. | |
1309 | * Userspace can support this by aligning virtual base address and | |
1310 | * allocation size to the fragment size. | |
1311 | */ | |
6849d47c RH |
1312 | unsigned max_frag = params->adev->vm_manager.fragment_size; |
1313 | int r; | |
92696dd5 CK |
1314 | |
1315 | /* system pages are non continuously */ | |
6849d47c | 1316 | if (params->src || !(flags & AMDGPU_PTE_VALID)) |
cc28c4ed | 1317 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 | 1318 | |
6849d47c RH |
1319 | while (start != end) { |
1320 | uint64_t frag_flags, frag_end; | |
1321 | unsigned frag; | |
1322 | ||
1323 | /* This intentionally wraps around if no bit is set */ | |
1324 | frag = min((unsigned)ffs(start) - 1, | |
1325 | (unsigned)fls64(end - start) - 1); | |
1326 | if (frag >= max_frag) { | |
1327 | frag_flags = AMDGPU_PTE_FRAG(max_frag); | |
1328 | frag_end = end & ~((1ULL << max_frag) - 1); | |
1329 | } else { | |
1330 | frag_flags = AMDGPU_PTE_FRAG(frag); | |
1331 | frag_end = start + (1 << frag); | |
1332 | } | |
1333 | ||
1334 | r = amdgpu_vm_update_ptes(params, start, frag_end, dst, | |
1335 | flags | frag_flags); | |
cc28c4ed HK |
1336 | if (r) |
1337 | return r; | |
92696dd5 | 1338 | |
6849d47c RH |
1339 | dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; |
1340 | start = frag_end; | |
92696dd5 | 1341 | } |
6849d47c RH |
1342 | |
1343 | return 0; | |
d38ceaf9 AD |
1344 | } |
1345 | ||
d38ceaf9 AD |
1346 | /** |
1347 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1348 | * | |
1349 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1350 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1351 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1352 | * @vm: requested vm |
a14faa65 CK |
1353 | * @start: start of mapped range |
1354 | * @last: last mapped entry | |
1355 | * @flags: flags for the entries | |
d38ceaf9 | 1356 | * @addr: addr to set the area to |
d38ceaf9 AD |
1357 | * @fence: optional resulting fence |
1358 | * | |
a14faa65 | 1359 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1360 | * |
1361 | * Returns: | |
1362 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1363 | */ |
1364 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1365 | struct dma_fence *exclusive, |
fa3ab3c7 | 1366 | dma_addr_t *pages_addr, |
d38ceaf9 | 1367 | struct amdgpu_vm *vm, |
a14faa65 | 1368 | uint64_t start, uint64_t last, |
6b777607 | 1369 | uint64_t flags, uint64_t addr, |
f54d1867 | 1370 | struct dma_fence **fence) |
d38ceaf9 | 1371 | { |
2d55e45a | 1372 | struct amdgpu_ring *ring; |
a1e08d3b | 1373 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1374 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1375 | struct amdgpu_job *job; |
29efc4f5 | 1376 | struct amdgpu_pte_update_params params; |
f54d1867 | 1377 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1378 | int r; |
1379 | ||
afef8b8f CK |
1380 | memset(¶ms, 0, sizeof(params)); |
1381 | params.adev = adev; | |
49ac8a24 | 1382 | params.vm = vm; |
afef8b8f | 1383 | |
a33cab7a CK |
1384 | /* sync to everything on unmapping */ |
1385 | if (!(flags & AMDGPU_PTE_VALID)) | |
1386 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1387 | ||
b4d42511 HK |
1388 | if (vm->use_cpu_for_update) { |
1389 | /* params.src is used as flag to indicate system Memory */ | |
1390 | if (pages_addr) | |
1391 | params.src = ~0; | |
1392 | ||
1393 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1394 | * as the root PD BO | |
1395 | */ | |
a33cab7a | 1396 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1397 | if (unlikely(r)) |
1398 | return r; | |
1399 | ||
1400 | params.func = amdgpu_vm_cpu_set_ptes; | |
1401 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1402 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1403 | addr, flags); | |
1404 | } | |
1405 | ||
068c3304 | 1406 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched); |
27c5f36f | 1407 | |
a14faa65 | 1408 | nptes = last - start + 1; |
d38ceaf9 AD |
1409 | |
1410 | /* | |
86209523 | 1411 | * reserve space for two commands every (1 << BLOCK_SIZE) |
d38ceaf9 | 1412 | * entries or 2k dwords (whatever is smaller) |
86209523 BN |
1413 | * |
1414 | * The second command is for the shadow pagetables. | |
d38ceaf9 | 1415 | */ |
104bd2ca ED |
1416 | if (vm->root.base.bo->shadow) |
1417 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; | |
1418 | else | |
1419 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1); | |
d38ceaf9 AD |
1420 | |
1421 | /* padding, etc. */ | |
1422 | ndw = 64; | |
1423 | ||
570144c6 | 1424 | if (pages_addr) { |
b0456f93 | 1425 | /* copy commands needed */ |
e6d92197 | 1426 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; |
d38ceaf9 | 1427 | |
b0456f93 | 1428 | /* and also PTEs */ |
d38ceaf9 AD |
1429 | ndw += nptes * 2; |
1430 | ||
afef8b8f CK |
1431 | params.func = amdgpu_vm_do_copy_ptes; |
1432 | ||
d38ceaf9 AD |
1433 | } else { |
1434 | /* set page commands needed */ | |
44e1baeb | 1435 | ndw += ncmds * 10; |
d38ceaf9 | 1436 | |
6849d47c | 1437 | /* extra commands for begin/end fragments */ |
11528640 ED |
1438 | if (vm->root.base.bo->shadow) |
1439 | ndw += 2 * 10 * adev->vm_manager.fragment_size * 2; | |
1440 | else | |
1441 | ndw += 2 * 10 * adev->vm_manager.fragment_size; | |
afef8b8f CK |
1442 | |
1443 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1444 | } |
1445 | ||
d71518b5 CK |
1446 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1447 | if (r) | |
d38ceaf9 | 1448 | return r; |
d71518b5 | 1449 | |
29efc4f5 | 1450 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1451 | |
570144c6 | 1452 | if (pages_addr) { |
b0456f93 CK |
1453 | uint64_t *pte; |
1454 | unsigned i; | |
1455 | ||
1456 | /* Put the PTEs at the end of the IB. */ | |
1457 | i = ndw - nptes * 2; | |
1458 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1459 | params.src = job->ibs->gpu_addr + i * 4; | |
1460 | ||
1461 | for (i = 0; i < nptes; ++i) { | |
1462 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1463 | AMDGPU_GPU_PAGE_SIZE); | |
1464 | pte[i] |= flags; | |
1465 | } | |
d7a4ac66 | 1466 | addr = 0; |
b0456f93 CK |
1467 | } |
1468 | ||
cebb52b7 | 1469 | r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); |
3cabaa54 CK |
1470 | if (r) |
1471 | goto error_free; | |
1472 | ||
3f3333f8 | 1473 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
177ae09b | 1474 | owner, false); |
a1e08d3b CK |
1475 | if (r) |
1476 | goto error_free; | |
d38ceaf9 | 1477 | |
3f3333f8 | 1478 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1479 | if (r) |
1480 | goto error_free; | |
1481 | ||
cc28c4ed HK |
1482 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1483 | if (r) | |
1484 | goto error_free; | |
d38ceaf9 | 1485 | |
29efc4f5 CK |
1486 | amdgpu_ring_pad_ib(ring, params.ib); |
1487 | WARN_ON(params.ib->length_dw > ndw); | |
0e28b10f | 1488 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f); |
4af9f07c CZ |
1489 | if (r) |
1490 | goto error_free; | |
d38ceaf9 | 1491 | |
3f3333f8 | 1492 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1493 | dma_fence_put(*fence); |
1494 | *fence = f; | |
d38ceaf9 | 1495 | return 0; |
d5fc5e82 CZ |
1496 | |
1497 | error_free: | |
d71518b5 | 1498 | amdgpu_job_free(job); |
4af9f07c | 1499 | return r; |
d38ceaf9 AD |
1500 | } |
1501 | ||
a14faa65 CK |
1502 | /** |
1503 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1504 | * | |
1505 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1506 | * @exclusive: fence we need to sync to |
8358dcee | 1507 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1508 | * @vm: requested vm |
1509 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1510 | * @flags: HW flags for the mapping |
63e0ba40 | 1511 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1512 | * @fence: optional resulting fence |
1513 | * | |
1514 | * Split the mapping into smaller chunks so that each update fits | |
1515 | * into a SDMA IB. | |
7fc48e59 AG |
1516 | * |
1517 | * Returns: | |
1518 | * 0 for success, -EINVAL for failure. | |
a14faa65 CK |
1519 | */ |
1520 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1521 | struct dma_fence *exclusive, |
8358dcee | 1522 | dma_addr_t *pages_addr, |
a14faa65 CK |
1523 | struct amdgpu_vm *vm, |
1524 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1525 | uint64_t flags, |
63e0ba40 | 1526 | struct drm_mm_node *nodes, |
f54d1867 | 1527 | struct dma_fence **fence) |
a14faa65 | 1528 | { |
9fc8fc70 | 1529 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1530 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1531 | int r; |
1532 | ||
1533 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1534 | * but in case of something, we filter the flags in first place | |
1535 | */ | |
1536 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1537 | flags &= ~AMDGPU_PTE_READABLE; | |
1538 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1539 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1540 | ||
15b31c59 AX |
1541 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1542 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1543 | ||
b0fd18b0 AX |
1544 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1545 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1546 | ||
d0766e98 ZJ |
1547 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1548 | (adev->asic_type >= CHIP_VEGA10)) { | |
1549 | flags |= AMDGPU_PTE_PRT; | |
1550 | flags &= ~AMDGPU_PTE_VALID; | |
1551 | } | |
1552 | ||
a14faa65 CK |
1553 | trace_amdgpu_vm_bo_update(mapping); |
1554 | ||
63e0ba40 CK |
1555 | pfn = mapping->offset >> PAGE_SHIFT; |
1556 | if (nodes) { | |
1557 | while (pfn >= nodes->size) { | |
1558 | pfn -= nodes->size; | |
1559 | ++nodes; | |
1560 | } | |
fa3ab3c7 | 1561 | } |
a14faa65 | 1562 | |
63e0ba40 | 1563 | do { |
9fc8fc70 | 1564 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1565 | uint64_t max_entries; |
1566 | uint64_t addr, last; | |
a14faa65 | 1567 | |
63e0ba40 CK |
1568 | if (nodes) { |
1569 | addr = nodes->start << PAGE_SHIFT; | |
1570 | max_entries = (nodes->size - pfn) * | |
463d2fe8 | 1571 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1572 | } else { |
1573 | addr = 0; | |
1574 | max_entries = S64_MAX; | |
1575 | } | |
a14faa65 | 1576 | |
63e0ba40 | 1577 | if (pages_addr) { |
9fc8fc70 CK |
1578 | uint64_t count; |
1579 | ||
457e0fee | 1580 | max_entries = min(max_entries, 16ull * 1024ull); |
38e624a1 | 1581 | for (count = 1; |
463d2fe8 | 1582 | count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
38e624a1 | 1583 | ++count) { |
9fc8fc70 CK |
1584 | uint64_t idx = pfn + count; |
1585 | ||
1586 | if (pages_addr[idx] != | |
1587 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1588 | break; | |
1589 | } | |
1590 | ||
1591 | if (count < min_linear_pages) { | |
1592 | addr = pfn << PAGE_SHIFT; | |
1593 | dma_addr = pages_addr; | |
1594 | } else { | |
1595 | addr = pages_addr[pfn]; | |
463d2fe8 | 1596 | max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
9fc8fc70 CK |
1597 | } |
1598 | ||
63e0ba40 CK |
1599 | } else if (flags & AMDGPU_PTE_VALID) { |
1600 | addr += adev->vm_manager.vram_base_offset; | |
9fc8fc70 | 1601 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1602 | } |
63e0ba40 | 1603 | |
a9f87f64 | 1604 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1605 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1606 | start, last, flags, addr, |
1607 | fence); | |
1608 | if (r) | |
1609 | return r; | |
1610 | ||
463d2fe8 | 1611 | pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1612 | if (nodes && nodes->size == pfn) { |
1613 | pfn = 0; | |
1614 | ++nodes; | |
1615 | } | |
a14faa65 | 1616 | start = last + 1; |
63e0ba40 | 1617 | |
a9f87f64 | 1618 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1619 | |
1620 | return 0; | |
1621 | } | |
1622 | ||
d38ceaf9 AD |
1623 | /** |
1624 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1625 | * | |
1626 | * @adev: amdgpu_device pointer | |
1627 | * @bo_va: requested BO and VM object | |
99e124f4 | 1628 | * @clear: if true clear the entries |
d38ceaf9 AD |
1629 | * |
1630 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1631 | * |
1632 | * Returns: | |
1633 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1634 | */ |
1635 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1636 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1637 | bool clear) |
d38ceaf9 | 1638 | { |
ec681545 CK |
1639 | struct amdgpu_bo *bo = bo_va->base.bo; |
1640 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1641 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1642 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1643 | struct ttm_mem_reg *mem; |
63e0ba40 | 1644 | struct drm_mm_node *nodes; |
4e55eb38 | 1645 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1646 | uint64_t flags; |
d38ceaf9 AD |
1647 | int r; |
1648 | ||
7eb80427 | 1649 | if (clear || !bo) { |
99e124f4 | 1650 | mem = NULL; |
63e0ba40 | 1651 | nodes = NULL; |
99e124f4 CK |
1652 | exclusive = NULL; |
1653 | } else { | |
8358dcee CK |
1654 | struct ttm_dma_tt *ttm; |
1655 | ||
7eb80427 | 1656 | mem = &bo->tbo.mem; |
63e0ba40 CK |
1657 | nodes = mem->mm_node; |
1658 | if (mem->mem_type == TTM_PL_TT) { | |
7eb80427 | 1659 | ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); |
8358dcee | 1660 | pages_addr = ttm->dma_address; |
9ab21462 | 1661 | } |
ec681545 | 1662 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1663 | } |
1664 | ||
457e0fee | 1665 | if (bo) |
ec681545 | 1666 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
457e0fee | 1667 | else |
a5f6b5b1 | 1668 | flags = 0x0; |
d38ceaf9 | 1669 | |
4e55eb38 CK |
1670 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1671 | last_update = &vm->last_update; | |
1672 | else | |
1673 | last_update = &bo_va->last_pt_update; | |
1674 | ||
3d7d4d3a CK |
1675 | if (!clear && bo_va->base.moved) { |
1676 | bo_va->base.moved = false; | |
7fc11959 | 1677 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1678 | |
cb7b6ec2 CK |
1679 | } else if (bo_va->cleared != clear) { |
1680 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1681 | } |
7fc11959 CK |
1682 | |
1683 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1684 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1685 | mapping, flags, nodes, |
4e55eb38 | 1686 | last_update); |
d38ceaf9 AD |
1687 | if (r) |
1688 | return r; | |
1689 | } | |
1690 | ||
cb7b6ec2 CK |
1691 | if (vm->use_cpu_for_update) { |
1692 | /* Flush HDP */ | |
1693 | mb(); | |
69882565 | 1694 | amdgpu_asic_flush_hdp(adev, NULL); |
d6c10f6b CK |
1695 | } |
1696 | ||
af4c0f65 | 1697 | spin_lock(&vm->moved_lock); |
bb475839 | 1698 | list_del_init(&bo_va->base.vm_status); |
af4c0f65 | 1699 | spin_unlock(&vm->moved_lock); |
36188364 | 1700 | |
bb475839 JZ |
1701 | /* If the BO is not in its preferred location add it back to |
1702 | * the evicted list so that it gets validated again on the | |
1703 | * next command submission. | |
1704 | */ | |
806f043f CK |
1705 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
1706 | uint32_t mem_type = bo->tbo.mem.mem_type; | |
1707 | ||
1708 | if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) | |
1709 | list_add_tail(&bo_va->base.vm_status, &vm->evicted); | |
1710 | else | |
1711 | list_add(&bo_va->base.vm_status, &vm->idle); | |
1712 | } | |
d38ceaf9 | 1713 | |
cb7b6ec2 CK |
1714 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1715 | bo_va->cleared = clear; | |
1716 | ||
1717 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1718 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1719 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1720 | } |
1721 | ||
d38ceaf9 AD |
1722 | return 0; |
1723 | } | |
1724 | ||
284710fa CK |
1725 | /** |
1726 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
1727 | * |
1728 | * @adev: amdgpu_device pointer | |
284710fa CK |
1729 | */ |
1730 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1731 | { | |
1732 | unsigned long flags; | |
1733 | bool enable; | |
1734 | ||
1735 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1736 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1737 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1738 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1739 | } | |
1740 | ||
451bc8eb | 1741 | /** |
4388fc2a | 1742 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
1743 | * |
1744 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
1745 | */ |
1746 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1747 | { | |
132f34e4 | 1748 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1749 | return; |
1750 | ||
451bc8eb CK |
1751 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1752 | amdgpu_vm_update_prt_state(adev); | |
1753 | } | |
1754 | ||
0b15f2fc CK |
1755 | /** |
1756 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
1757 | * |
1758 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
1759 | */ |
1760 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1761 | { | |
451bc8eb | 1762 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1763 | amdgpu_vm_update_prt_state(adev); |
1764 | } | |
1765 | ||
284710fa | 1766 | /** |
451bc8eb | 1767 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
1768 | * |
1769 | * @fence: fence for the callback | |
00553cf8 | 1770 | * @_cb: the callback function |
284710fa CK |
1771 | */ |
1772 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1773 | { | |
1774 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1775 | ||
0b15f2fc | 1776 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1777 | kfree(cb); |
1778 | } | |
1779 | ||
451bc8eb CK |
1780 | /** |
1781 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
1782 | * |
1783 | * @adev: amdgpu_device pointer | |
1784 | * @fence: fence for the callback | |
451bc8eb CK |
1785 | */ |
1786 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1787 | struct dma_fence *fence) | |
1788 | { | |
4388fc2a | 1789 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1790 | |
132f34e4 | 1791 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1792 | return; |
1793 | ||
1794 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1795 | if (!cb) { |
1796 | /* Last resort when we are OOM */ | |
1797 | if (fence) | |
1798 | dma_fence_wait(fence, false); | |
1799 | ||
486a68f5 | 1800 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1801 | } else { |
1802 | cb->adev = adev; | |
1803 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1804 | amdgpu_vm_prt_cb)) | |
1805 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1806 | } | |
1807 | } | |
1808 | ||
284710fa CK |
1809 | /** |
1810 | * amdgpu_vm_free_mapping - free a mapping | |
1811 | * | |
1812 | * @adev: amdgpu_device pointer | |
1813 | * @vm: requested vm | |
1814 | * @mapping: mapping to be freed | |
1815 | * @fence: fence of the unmap operation | |
1816 | * | |
1817 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1818 | */ | |
1819 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1820 | struct amdgpu_vm *vm, | |
1821 | struct amdgpu_bo_va_mapping *mapping, | |
1822 | struct dma_fence *fence) | |
1823 | { | |
451bc8eb CK |
1824 | if (mapping->flags & AMDGPU_PTE_PRT) |
1825 | amdgpu_vm_add_prt_cb(adev, fence); | |
1826 | kfree(mapping); | |
1827 | } | |
284710fa | 1828 | |
451bc8eb CK |
1829 | /** |
1830 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1831 | * | |
1832 | * @adev: amdgpu_device pointer | |
1833 | * @vm: requested vm | |
1834 | * | |
1835 | * Register a cleanup callback to disable PRT support after VM dies. | |
1836 | */ | |
1837 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1838 | { | |
3f3333f8 | 1839 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1840 | struct dma_fence *excl, **shared; |
1841 | unsigned i, shared_count; | |
1842 | int r; | |
0b15f2fc | 1843 | |
451bc8eb CK |
1844 | r = reservation_object_get_fences_rcu(resv, &excl, |
1845 | &shared_count, &shared); | |
1846 | if (r) { | |
1847 | /* Not enough memory to grab the fence list, as last resort | |
1848 | * block for all the fences to complete. | |
1849 | */ | |
1850 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1851 | MAX_SCHEDULE_TIMEOUT); | |
1852 | return; | |
284710fa | 1853 | } |
451bc8eb CK |
1854 | |
1855 | /* Add a callback for each fence in the reservation object */ | |
1856 | amdgpu_vm_prt_get(adev); | |
1857 | amdgpu_vm_add_prt_cb(adev, excl); | |
1858 | ||
1859 | for (i = 0; i < shared_count; ++i) { | |
1860 | amdgpu_vm_prt_get(adev); | |
1861 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1862 | } | |
1863 | ||
1864 | kfree(shared); | |
284710fa CK |
1865 | } |
1866 | ||
d38ceaf9 AD |
1867 | /** |
1868 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1869 | * | |
1870 | * @adev: amdgpu_device pointer | |
1871 | * @vm: requested vm | |
f3467818 NH |
1872 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1873 | * or if an error occurred) | |
d38ceaf9 AD |
1874 | * |
1875 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 1876 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
1877 | * |
1878 | * Returns: | |
1879 | * 0 for success. | |
1880 | * | |
d38ceaf9 AD |
1881 | */ |
1882 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1883 | struct amdgpu_vm *vm, |
1884 | struct dma_fence **fence) | |
d38ceaf9 AD |
1885 | { |
1886 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 1887 | uint64_t init_pte_value = 0; |
f3467818 | 1888 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1889 | int r; |
1890 | ||
1891 | while (!list_empty(&vm->freed)) { | |
1892 | mapping = list_first_entry(&vm->freed, | |
1893 | struct amdgpu_bo_va_mapping, list); | |
1894 | list_del(&mapping->list); | |
e17841b9 | 1895 | |
4584312d | 1896 | if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START) |
6d16dac8 | 1897 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 1898 | |
570144c6 | 1899 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1900 | mapping->start, mapping->last, |
51ac7eec | 1901 | init_pte_value, 0, &f); |
f3467818 | 1902 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1903 | if (r) { |
f3467818 | 1904 | dma_fence_put(f); |
d38ceaf9 | 1905 | return r; |
284710fa | 1906 | } |
f3467818 | 1907 | } |
d38ceaf9 | 1908 | |
f3467818 NH |
1909 | if (fence && f) { |
1910 | dma_fence_put(*fence); | |
1911 | *fence = f; | |
1912 | } else { | |
1913 | dma_fence_put(f); | |
d38ceaf9 | 1914 | } |
f3467818 | 1915 | |
d38ceaf9 AD |
1916 | return 0; |
1917 | ||
1918 | } | |
1919 | ||
1920 | /** | |
73fb16e7 | 1921 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1922 | * |
1923 | * @adev: amdgpu_device pointer | |
1924 | * @vm: requested vm | |
1925 | * | |
73fb16e7 | 1926 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
1927 | * |
1928 | * Returns: | |
1929 | * 0 for success. | |
d38ceaf9 | 1930 | * |
73fb16e7 | 1931 | * PTs have to be reserved! |
d38ceaf9 | 1932 | */ |
73fb16e7 | 1933 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 1934 | struct amdgpu_vm *vm) |
d38ceaf9 | 1935 | { |
789f3317 CK |
1936 | struct amdgpu_bo_va *bo_va, *tmp; |
1937 | struct list_head moved; | |
73fb16e7 | 1938 | bool clear; |
789f3317 | 1939 | int r; |
d38ceaf9 | 1940 | |
789f3317 | 1941 | INIT_LIST_HEAD(&moved); |
af4c0f65 | 1942 | spin_lock(&vm->moved_lock); |
789f3317 CK |
1943 | list_splice_init(&vm->moved, &moved); |
1944 | spin_unlock(&vm->moved_lock); | |
32b41ac2 | 1945 | |
789f3317 CK |
1946 | list_for_each_entry_safe(bo_va, tmp, &moved, base.vm_status) { |
1947 | struct reservation_object *resv = bo_va->base.bo->tbo.resv; | |
ec363e0d | 1948 | |
73fb16e7 | 1949 | /* Per VM BOs never need to bo cleared in the page tables */ |
ec363e0d CK |
1950 | if (resv == vm->root.base.bo->tbo.resv) |
1951 | clear = false; | |
1952 | /* Try to reserve the BO to avoid clearing its ptes */ | |
9b8cad20 | 1953 | else if (!amdgpu_vm_debug && reservation_object_trylock(resv)) |
ec363e0d CK |
1954 | clear = false; |
1955 | /* Somebody else is using the BO right now */ | |
1956 | else | |
1957 | clear = true; | |
73fb16e7 CK |
1958 | |
1959 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
789f3317 CK |
1960 | if (r) { |
1961 | spin_lock(&vm->moved_lock); | |
1962 | list_splice(&moved, &vm->moved); | |
1963 | spin_unlock(&vm->moved_lock); | |
d38ceaf9 | 1964 | return r; |
789f3317 | 1965 | } |
d38ceaf9 | 1966 | |
ec363e0d CK |
1967 | if (!clear && resv != vm->root.base.bo->tbo.resv) |
1968 | reservation_object_unlock(resv); | |
1969 | ||
d38ceaf9 | 1970 | } |
d38ceaf9 | 1971 | |
789f3317 | 1972 | return 0; |
d38ceaf9 AD |
1973 | } |
1974 | ||
1975 | /** | |
1976 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1977 | * | |
1978 | * @adev: amdgpu_device pointer | |
1979 | * @vm: requested vm | |
1980 | * @bo: amdgpu buffer object | |
1981 | * | |
8843dbbb | 1982 | * Add @bo into the requested vm. |
d38ceaf9 | 1983 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
1984 | * |
1985 | * Returns: | |
1986 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
1987 | * |
1988 | * Object has to be reserved! | |
1989 | */ | |
1990 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1991 | struct amdgpu_vm *vm, | |
1992 | struct amdgpu_bo *bo) | |
1993 | { | |
1994 | struct amdgpu_bo_va *bo_va; | |
1995 | ||
1996 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1997 | if (bo_va == NULL) { | |
1998 | return NULL; | |
1999 | } | |
3f4299be | 2000 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2001 | |
d38ceaf9 | 2002 | bo_va->ref_count = 1; |
7fc11959 CK |
2003 | INIT_LIST_HEAD(&bo_va->valids); |
2004 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2005 | |
d38ceaf9 AD |
2006 | return bo_va; |
2007 | } | |
2008 | ||
73fb16e7 CK |
2009 | |
2010 | /** | |
2011 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2012 | * | |
2013 | * @adev: amdgpu_device pointer | |
2014 | * @bo_va: bo_va to store the address | |
2015 | * @mapping: the mapping to insert | |
2016 | * | |
2017 | * Insert a new mapping into all structures. | |
2018 | */ | |
2019 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2020 | struct amdgpu_bo_va *bo_va, | |
2021 | struct amdgpu_bo_va_mapping *mapping) | |
2022 | { | |
2023 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2024 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2025 | ||
aebc5e6f | 2026 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2027 | list_add(&mapping->list, &bo_va->invalids); |
2028 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2029 | ||
2030 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2031 | amdgpu_vm_prt_get(adev); | |
2032 | ||
862b8c57 CK |
2033 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && |
2034 | !bo_va->base.moved) { | |
af4c0f65 | 2035 | spin_lock(&vm->moved_lock); |
862b8c57 | 2036 | list_move(&bo_va->base.vm_status, &vm->moved); |
af4c0f65 | 2037 | spin_unlock(&vm->moved_lock); |
73fb16e7 CK |
2038 | } |
2039 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2040 | } | |
2041 | ||
d38ceaf9 AD |
2042 | /** |
2043 | * amdgpu_vm_bo_map - map bo inside a vm | |
2044 | * | |
2045 | * @adev: amdgpu_device pointer | |
2046 | * @bo_va: bo_va to store the address | |
2047 | * @saddr: where to map the BO | |
2048 | * @offset: requested offset in the BO | |
00553cf8 | 2049 | * @size: BO size in bytes |
d38ceaf9 AD |
2050 | * @flags: attributes of pages (read/write/valid/etc.) |
2051 | * | |
2052 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2053 | * |
2054 | * Returns: | |
2055 | * 0 for success, error for failure. | |
d38ceaf9 | 2056 | * |
49b02b18 | 2057 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2058 | */ |
2059 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2060 | struct amdgpu_bo_va *bo_va, | |
2061 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2062 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2063 | { |
a9f87f64 | 2064 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2065 | struct amdgpu_bo *bo = bo_va->base.bo; |
2066 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2067 | uint64_t eaddr; |
d38ceaf9 | 2068 | |
0be52de9 CK |
2069 | /* validate the parameters */ |
2070 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2071 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2072 | return -EINVAL; |
0be52de9 | 2073 | |
d38ceaf9 | 2074 | /* make sure object fit at this offset */ |
005ae95e | 2075 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2076 | if (saddr >= eaddr || |
ec681545 | 2077 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2078 | return -EINVAL; |
d38ceaf9 | 2079 | |
d38ceaf9 AD |
2080 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2081 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2082 | ||
a9f87f64 CK |
2083 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2084 | if (tmp) { | |
d38ceaf9 AD |
2085 | /* bo and tmp overlap, invalid addr */ |
2086 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2087 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2088 | tmp->start, tmp->last + 1); |
663e4577 | 2089 | return -EINVAL; |
d38ceaf9 AD |
2090 | } |
2091 | ||
2092 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2093 | if (!mapping) |
2094 | return -ENOMEM; | |
d38ceaf9 | 2095 | |
a9f87f64 CK |
2096 | mapping->start = saddr; |
2097 | mapping->last = eaddr; | |
d38ceaf9 AD |
2098 | mapping->offset = offset; |
2099 | mapping->flags = flags; | |
2100 | ||
73fb16e7 | 2101 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2102 | |
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | /** | |
2107 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2108 | * | |
2109 | * @adev: amdgpu_device pointer | |
2110 | * @bo_va: bo_va to store the address | |
2111 | * @saddr: where to map the BO | |
2112 | * @offset: requested offset in the BO | |
00553cf8 | 2113 | * @size: BO size in bytes |
80f95c57 CK |
2114 | * @flags: attributes of pages (read/write/valid/etc.) |
2115 | * | |
2116 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2117 | * mappings as we do so. | |
7fc48e59 AG |
2118 | * |
2119 | * Returns: | |
2120 | * 0 for success, error for failure. | |
80f95c57 CK |
2121 | * |
2122 | * Object has to be reserved and unreserved outside! | |
2123 | */ | |
2124 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2125 | struct amdgpu_bo_va *bo_va, | |
2126 | uint64_t saddr, uint64_t offset, | |
2127 | uint64_t size, uint64_t flags) | |
2128 | { | |
2129 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2130 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2131 | uint64_t eaddr; |
2132 | int r; | |
2133 | ||
2134 | /* validate the parameters */ | |
2135 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2136 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2137 | return -EINVAL; | |
2138 | ||
2139 | /* make sure object fit at this offset */ | |
2140 | eaddr = saddr + size - 1; | |
2141 | if (saddr >= eaddr || | |
ec681545 | 2142 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2143 | return -EINVAL; |
2144 | ||
2145 | /* Allocate all the needed memory */ | |
2146 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2147 | if (!mapping) | |
2148 | return -ENOMEM; | |
2149 | ||
ec681545 | 2150 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2151 | if (r) { |
2152 | kfree(mapping); | |
2153 | return r; | |
2154 | } | |
2155 | ||
2156 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2157 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2158 | ||
a9f87f64 CK |
2159 | mapping->start = saddr; |
2160 | mapping->last = eaddr; | |
80f95c57 CK |
2161 | mapping->offset = offset; |
2162 | mapping->flags = flags; | |
2163 | ||
73fb16e7 | 2164 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2165 | |
d38ceaf9 | 2166 | return 0; |
d38ceaf9 AD |
2167 | } |
2168 | ||
2169 | /** | |
2170 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2171 | * | |
2172 | * @adev: amdgpu_device pointer | |
2173 | * @bo_va: bo_va to remove the address from | |
2174 | * @saddr: where to the BO is mapped | |
2175 | * | |
2176 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2177 | * |
2178 | * Returns: | |
2179 | * 0 for success, error for failure. | |
d38ceaf9 | 2180 | * |
49b02b18 | 2181 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2182 | */ |
2183 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2184 | struct amdgpu_bo_va *bo_va, | |
2185 | uint64_t saddr) | |
2186 | { | |
2187 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2188 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2189 | bool valid = true; |
d38ceaf9 | 2190 | |
6c7fc503 | 2191 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2192 | |
7fc11959 | 2193 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2194 | if (mapping->start == saddr) |
d38ceaf9 AD |
2195 | break; |
2196 | } | |
2197 | ||
7fc11959 CK |
2198 | if (&mapping->list == &bo_va->valids) { |
2199 | valid = false; | |
2200 | ||
2201 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2202 | if (mapping->start == saddr) |
7fc11959 CK |
2203 | break; |
2204 | } | |
2205 | ||
32b41ac2 | 2206 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2207 | return -ENOENT; |
d38ceaf9 | 2208 | } |
32b41ac2 | 2209 | |
d38ceaf9 | 2210 | list_del(&mapping->list); |
a9f87f64 | 2211 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2212 | mapping->bo_va = NULL; |
93e3e438 | 2213 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2214 | |
e17841b9 | 2215 | if (valid) |
d38ceaf9 | 2216 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2217 | else |
284710fa CK |
2218 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2219 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2220 | |
2221 | return 0; | |
2222 | } | |
2223 | ||
dc54d3d1 CK |
2224 | /** |
2225 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2226 | * | |
2227 | * @adev: amdgpu_device pointer | |
2228 | * @vm: VM structure to use | |
2229 | * @saddr: start of the range | |
2230 | * @size: size of the range | |
2231 | * | |
2232 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2233 | * |
2234 | * Returns: | |
2235 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2236 | */ |
2237 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2238 | struct amdgpu_vm *vm, | |
2239 | uint64_t saddr, uint64_t size) | |
2240 | { | |
2241 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2242 | LIST_HEAD(removed); |
2243 | uint64_t eaddr; | |
2244 | ||
2245 | eaddr = saddr + size - 1; | |
2246 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2247 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2248 | ||
2249 | /* Allocate all the needed memory */ | |
2250 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2251 | if (!before) | |
2252 | return -ENOMEM; | |
27f6d610 | 2253 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2254 | |
2255 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2256 | if (!after) { | |
2257 | kfree(before); | |
2258 | return -ENOMEM; | |
2259 | } | |
27f6d610 | 2260 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2261 | |
2262 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2263 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2264 | while (tmp) { | |
dc54d3d1 | 2265 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2266 | if (tmp->start < saddr) { |
2267 | before->start = tmp->start; | |
2268 | before->last = saddr - 1; | |
dc54d3d1 CK |
2269 | before->offset = tmp->offset; |
2270 | before->flags = tmp->flags; | |
387f49e5 JZ |
2271 | before->bo_va = tmp->bo_va; |
2272 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2273 | } |
2274 | ||
2275 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2276 | if (tmp->last > eaddr) { |
2277 | after->start = eaddr + 1; | |
2278 | after->last = tmp->last; | |
dc54d3d1 | 2279 | after->offset = tmp->offset; |
a9f87f64 | 2280 | after->offset += after->start - tmp->start; |
dc54d3d1 | 2281 | after->flags = tmp->flags; |
387f49e5 JZ |
2282 | after->bo_va = tmp->bo_va; |
2283 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2284 | } |
2285 | ||
2286 | list_del(&tmp->list); | |
2287 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2288 | |
2289 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2290 | } |
2291 | ||
2292 | /* And free them up */ | |
2293 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2294 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2295 | list_del(&tmp->list); |
2296 | ||
a9f87f64 CK |
2297 | if (tmp->start < saddr) |
2298 | tmp->start = saddr; | |
2299 | if (tmp->last > eaddr) | |
2300 | tmp->last = eaddr; | |
dc54d3d1 | 2301 | |
aebc5e6f | 2302 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2303 | list_add(&tmp->list, &vm->freed); |
2304 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2305 | } | |
2306 | ||
27f6d610 JZ |
2307 | /* Insert partial mapping before the range */ |
2308 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2309 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2310 | if (before->flags & AMDGPU_PTE_PRT) |
2311 | amdgpu_vm_prt_get(adev); | |
2312 | } else { | |
2313 | kfree(before); | |
2314 | } | |
2315 | ||
2316 | /* Insert partial mapping after the range */ | |
27f6d610 | 2317 | if (!list_empty(&after->list)) { |
a9f87f64 | 2318 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2319 | if (after->flags & AMDGPU_PTE_PRT) |
2320 | amdgpu_vm_prt_get(adev); | |
2321 | } else { | |
2322 | kfree(after); | |
2323 | } | |
2324 | ||
2325 | return 0; | |
2326 | } | |
2327 | ||
aebc5e6f CK |
2328 | /** |
2329 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2330 | * | |
2331 | * @vm: the requested VM | |
00553cf8 | 2332 | * @addr: the address |
aebc5e6f CK |
2333 | * |
2334 | * Find a mapping by it's address. | |
7fc48e59 AG |
2335 | * |
2336 | * Returns: | |
2337 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2338 | * | |
aebc5e6f CK |
2339 | */ |
2340 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2341 | uint64_t addr) | |
2342 | { | |
2343 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2344 | } | |
2345 | ||
8ab19ea6 CK |
2346 | /** |
2347 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2348 | * | |
2349 | * @vm: the requested vm | |
2350 | * @ticket: CS ticket | |
2351 | * | |
2352 | * Trace all mappings of BOs reserved during a command submission. | |
2353 | */ | |
2354 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2355 | { | |
2356 | struct amdgpu_bo_va_mapping *mapping; | |
2357 | ||
2358 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2359 | return; | |
2360 | ||
2361 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2362 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2363 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2364 | struct amdgpu_bo *bo; | |
2365 | ||
2366 | bo = mapping->bo_va->base.bo; | |
2367 | if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket) | |
2368 | continue; | |
2369 | } | |
2370 | ||
2371 | trace_amdgpu_vm_bo_cs(mapping); | |
2372 | } | |
2373 | } | |
2374 | ||
d38ceaf9 AD |
2375 | /** |
2376 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2377 | * | |
2378 | * @adev: amdgpu_device pointer | |
2379 | * @bo_va: requested bo_va | |
2380 | * | |
8843dbbb | 2381 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2382 | * |
2383 | * Object have to be reserved! | |
2384 | */ | |
2385 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2386 | struct amdgpu_bo_va *bo_va) | |
2387 | { | |
2388 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2389 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2390 | |
ec681545 | 2391 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2392 | |
af4c0f65 | 2393 | spin_lock(&vm->moved_lock); |
ec681545 | 2394 | list_del(&bo_va->base.vm_status); |
af4c0f65 | 2395 | spin_unlock(&vm->moved_lock); |
d38ceaf9 | 2396 | |
7fc11959 | 2397 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2398 | list_del(&mapping->list); |
a9f87f64 | 2399 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2400 | mapping->bo_va = NULL; |
93e3e438 | 2401 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2402 | list_add(&mapping->list, &vm->freed); |
2403 | } | |
2404 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2405 | list_del(&mapping->list); | |
a9f87f64 | 2406 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2407 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2408 | bo_va->last_pt_update); | |
d38ceaf9 | 2409 | } |
32b41ac2 | 2410 | |
f54d1867 | 2411 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2412 | kfree(bo_va); |
d38ceaf9 AD |
2413 | } |
2414 | ||
2415 | /** | |
2416 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2417 | * | |
2418 | * @adev: amdgpu_device pointer | |
d38ceaf9 | 2419 | * @bo: amdgpu buffer object |
00553cf8 | 2420 | * @evicted: is the BO evicted |
d38ceaf9 | 2421 | * |
8843dbbb | 2422 | * Mark @bo as invalid. |
d38ceaf9 AD |
2423 | */ |
2424 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2425 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2426 | { |
ec681545 CK |
2427 | struct amdgpu_vm_bo_base *bo_base; |
2428 | ||
4bebccee CZ |
2429 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2430 | if (bo->parent && bo->parent->shadow == bo) | |
2431 | bo = bo->parent; | |
2432 | ||
ec681545 | 2433 | list_for_each_entry(bo_base, &bo->va, bo_list) { |
3f3333f8 | 2434 | struct amdgpu_vm *vm = bo_base->vm; |
862b8c57 | 2435 | bool was_moved = bo_base->moved; |
3f3333f8 | 2436 | |
3d7d4d3a | 2437 | bo_base->moved = true; |
3f3333f8 | 2438 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
73fb16e7 CK |
2439 | if (bo->tbo.type == ttm_bo_type_kernel) |
2440 | list_move(&bo_base->vm_status, &vm->evicted); | |
2441 | else | |
2442 | list_move_tail(&bo_base->vm_status, | |
2443 | &vm->evicted); | |
3f3333f8 CK |
2444 | continue; |
2445 | } | |
2446 | ||
862b8c57 | 2447 | if (was_moved) |
3f3333f8 CK |
2448 | continue; |
2449 | ||
862b8c57 CK |
2450 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2451 | list_move(&bo_base->vm_status, &vm->relocated); | |
2452 | } else { | |
2453 | spin_lock(&bo_base->vm->moved_lock); | |
2454 | list_move(&bo_base->vm_status, &vm->moved); | |
2455 | spin_unlock(&bo_base->vm->moved_lock); | |
2456 | } | |
d38ceaf9 AD |
2457 | } |
2458 | } | |
2459 | ||
7fc48e59 AG |
2460 | /** |
2461 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2462 | * | |
2463 | * @vm_size: VM size | |
2464 | * | |
2465 | * Returns: | |
2466 | * VM page table as power of two | |
2467 | */ | |
bab4fee7 JZ |
2468 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2469 | { | |
2470 | /* Total bits covered by PD + PTs */ | |
2471 | unsigned bits = ilog2(vm_size) + 18; | |
2472 | ||
2473 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2474 | Above that split equal between PD and PTs */ | |
2475 | if (vm_size <= 8) | |
2476 | return (bits - 9); | |
2477 | else | |
2478 | return ((bits + 3) / 2); | |
2479 | } | |
2480 | ||
d07f14be RH |
2481 | /** |
2482 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2483 | * |
2484 | * @adev: amdgpu_device pointer | |
2485 | * @vm_size: the default vm size if it's set auto | |
00553cf8 AG |
2486 | * @fragment_size_default: Default PTE fragment size |
2487 | * @max_level: max VMPT level | |
2488 | * @max_bits: max address space size in bits | |
2489 | * | |
bab4fee7 | 2490 | */ |
fdd5faaa | 2491 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, |
f3368128 CK |
2492 | uint32_t fragment_size_default, unsigned max_level, |
2493 | unsigned max_bits) | |
bab4fee7 | 2494 | { |
36539dce CK |
2495 | uint64_t tmp; |
2496 | ||
2497 | /* adjust vm size first */ | |
f3368128 CK |
2498 | if (amdgpu_vm_size != -1) { |
2499 | unsigned max_size = 1 << (max_bits - 30); | |
2500 | ||
fdd5faaa | 2501 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2502 | if (vm_size > max_size) { |
2503 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2504 | amdgpu_vm_size, max_size); | |
2505 | vm_size = max_size; | |
2506 | } | |
2507 | } | |
fdd5faaa CK |
2508 | |
2509 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2510 | |
2511 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2512 | if (amdgpu_vm_block_size != -1) |
2513 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2514 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2515 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2516 | switch (adev->vm_manager.num_level) { |
2517 | case 3: | |
2518 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2519 | break; | |
2520 | case 2: | |
2521 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2522 | break; | |
2523 | case 1: | |
2524 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2525 | break; | |
2526 | default: | |
2527 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2528 | } | |
b38f41eb | 2529 | /* block size depends on vm size and hw setup*/ |
97489129 | 2530 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2531 | adev->vm_manager.block_size = |
97489129 CK |
2532 | min((unsigned)amdgpu_vm_block_size, max_bits |
2533 | - AMDGPU_GPU_PAGE_SHIFT | |
2534 | - 9 * adev->vm_manager.num_level); | |
2535 | else if (adev->vm_manager.num_level > 1) | |
2536 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2537 | else |
97489129 | 2538 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2539 | |
b38f41eb CK |
2540 | if (amdgpu_vm_fragment_size == -1) |
2541 | adev->vm_manager.fragment_size = fragment_size_default; | |
2542 | else | |
2543 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2544 | |
36539dce CK |
2545 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2546 | vm_size, adev->vm_manager.num_level + 1, | |
2547 | adev->vm_manager.block_size, | |
fdd5faaa | 2548 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2549 | } |
2550 | ||
d38ceaf9 AD |
2551 | /** |
2552 | * amdgpu_vm_init - initialize a vm instance | |
2553 | * | |
2554 | * @adev: amdgpu_device pointer | |
2555 | * @vm: requested vm | |
9a4b7d4c | 2556 | * @vm_context: Indicates if it GFX or Compute context |
00553cf8 | 2557 | * @pasid: Process address space identifier |
d38ceaf9 | 2558 | * |
8843dbbb | 2559 | * Init @vm fields. |
7fc48e59 AG |
2560 | * |
2561 | * Returns: | |
2562 | * 0 for success, error for failure. | |
d38ceaf9 | 2563 | */ |
9a4b7d4c | 2564 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2565 | int vm_context, unsigned int pasid) |
d38ceaf9 | 2566 | { |
3216c6b7 | 2567 | struct amdgpu_bo_param bp; |
3f4299be | 2568 | struct amdgpu_bo *root; |
d38ceaf9 | 2569 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, |
36b32a68 | 2570 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2571 | unsigned ring_instance; |
2572 | struct amdgpu_ring *ring; | |
1b1f42d8 | 2573 | struct drm_sched_rq *rq; |
d3aab672 | 2574 | unsigned long size; |
13307f7e | 2575 | uint64_t flags; |
36bbf3bf | 2576 | int r, i; |
d38ceaf9 | 2577 | |
f808c13f | 2578 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2579 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2580 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2581 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2582 | INIT_LIST_HEAD(&vm->relocated); |
af4c0f65 | 2583 | spin_lock_init(&vm->moved_lock); |
27c7b9ae | 2584 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2585 | INIT_LIST_HEAD(&vm->idle); |
d38ceaf9 | 2586 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2587 | |
2bd9ccfa | 2588 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2589 | |
2590 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2591 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2592 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
1b1f42d8 | 2593 | rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; |
aa16b6c6 | 2594 | r = drm_sched_entity_init(&vm->entity, &rq, 1, NULL); |
2bd9ccfa | 2595 | if (r) |
f566ceb1 | 2596 | return r; |
2bd9ccfa | 2597 | |
51ac7eec YZ |
2598 | vm->pte_support_ats = false; |
2599 | ||
2600 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2601 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2602 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2603 | |
13307f7e | 2604 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2605 | vm->pte_support_ats = true; |
13307f7e | 2606 | } else { |
9a4b7d4c HK |
2607 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2608 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2609 | } |
9a4b7d4c HK |
2610 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2611 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
c8c5e569 | 2612 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
9a4b7d4c | 2613 | "CPU update of VM recommended only for large BAR system\n"); |
d5884513 | 2614 | vm->last_update = NULL; |
05906dec | 2615 | |
13307f7e | 2616 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; |
3c824172 HK |
2617 | if (vm->use_cpu_for_update) |
2618 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2619 | else | |
810955ba | 2620 | flags |= AMDGPU_GEM_CREATE_SHADOW; |
3c824172 | 2621 | |
d3aab672 | 2622 | size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level); |
3216c6b7 CZ |
2623 | memset(&bp, 0, sizeof(bp)); |
2624 | bp.size = size; | |
2625 | bp.byte_align = align; | |
2626 | bp.domain = AMDGPU_GEM_DOMAIN_VRAM; | |
2627 | bp.flags = flags; | |
2628 | bp.type = ttm_bo_type_kernel; | |
2629 | bp.resv = NULL; | |
3f4299be | 2630 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 2631 | if (r) |
2bd9ccfa CK |
2632 | goto error_free_sched_entity; |
2633 | ||
3f4299be | 2634 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
2635 | if (r) |
2636 | goto error_free_root; | |
2637 | ||
3f4299be | 2638 | r = amdgpu_vm_clear_bo(adev, vm, root, |
4584312d CK |
2639 | adev->vm_manager.root_level, |
2640 | vm->pte_support_ats); | |
13307f7e CK |
2641 | if (r) |
2642 | goto error_unreserve; | |
2643 | ||
3f4299be | 2644 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
d3aab672 | 2645 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 2646 | |
02208441 FK |
2647 | if (pasid) { |
2648 | unsigned long flags; | |
2649 | ||
2650 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2651 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2652 | GFP_ATOMIC); | |
2653 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2654 | if (r < 0) | |
2655 | goto error_free_root; | |
2656 | ||
2657 | vm->pasid = pasid; | |
0a096fb6 CK |
2658 | } |
2659 | ||
a2f14820 | 2660 | INIT_KFIFO(vm->faults); |
c98171cc | 2661 | vm->fault_credit = 16; |
d38ceaf9 AD |
2662 | |
2663 | return 0; | |
2bd9ccfa | 2664 | |
13307f7e CK |
2665 | error_unreserve: |
2666 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2667 | ||
67003a15 | 2668 | error_free_root: |
3f3333f8 CK |
2669 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2670 | amdgpu_bo_unref(&vm->root.base.bo); | |
2671 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2672 | |
2673 | error_free_sched_entity: | |
cdc50176 | 2674 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa CK |
2675 | |
2676 | return r; | |
d38ceaf9 AD |
2677 | } |
2678 | ||
b236fa1d FK |
2679 | /** |
2680 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
2681 | * | |
7fc48e59 AG |
2682 | * @adev: amdgpu_device pointer |
2683 | * @vm: requested vm | |
2684 | * | |
b236fa1d FK |
2685 | * This only works on GFX VMs that don't have any BOs added and no |
2686 | * page tables allocated yet. | |
2687 | * | |
2688 | * Changes the following VM parameters: | |
2689 | * - use_cpu_for_update | |
2690 | * - pte_supports_ats | |
2691 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
2692 | * | |
2693 | * Reinitializes the page directory to reflect the changed ATS | |
2694 | * setting. May leave behind an unused shadow BO for the page | |
2695 | * directory when switching from SDMA updates to CPU updates. | |
2696 | * | |
7fc48e59 AG |
2697 | * Returns: |
2698 | * 0 for success, -errno for errors. | |
b236fa1d FK |
2699 | */ |
2700 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2701 | { | |
2702 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); | |
2703 | int r; | |
2704 | ||
2705 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
2706 | if (r) | |
2707 | return r; | |
2708 | ||
2709 | /* Sanity checks */ | |
2710 | if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) { | |
2711 | r = -EINVAL; | |
2712 | goto error; | |
2713 | } | |
2714 | ||
2715 | /* Check if PD needs to be reinitialized and do it before | |
2716 | * changing any other state, in case it fails. | |
2717 | */ | |
2718 | if (pte_support_ats != vm->pte_support_ats) { | |
2719 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, | |
2720 | adev->vm_manager.root_level, | |
2721 | pte_support_ats); | |
2722 | if (r) | |
2723 | goto error; | |
2724 | } | |
2725 | ||
2726 | /* Update VM state */ | |
2727 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2728 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
2729 | vm->pte_support_ats = pte_support_ats; | |
2730 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2731 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
c8c5e569 | 2732 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
b236fa1d FK |
2733 | "CPU update of VM recommended only for large BAR system\n"); |
2734 | ||
2735 | if (vm->pasid) { | |
2736 | unsigned long flags; | |
2737 | ||
2738 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2739 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2740 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2741 | ||
2742 | vm->pasid = 0; | |
2743 | } | |
2744 | ||
2745 | error: | |
2746 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2747 | return r; | |
2748 | } | |
2749 | ||
f566ceb1 CK |
2750 | /** |
2751 | * amdgpu_vm_free_levels - free PD/PT levels | |
2752 | * | |
8f19cd78 CK |
2753 | * @adev: amdgpu device structure |
2754 | * @parent: PD/PT starting level to free | |
2755 | * @level: level of parent structure | |
f566ceb1 CK |
2756 | * |
2757 | * Free the page directory or page table level and all sub levels. | |
2758 | */ | |
8f19cd78 CK |
2759 | static void amdgpu_vm_free_levels(struct amdgpu_device *adev, |
2760 | struct amdgpu_vm_pt *parent, | |
2761 | unsigned level) | |
f566ceb1 | 2762 | { |
8f19cd78 | 2763 | unsigned i, num_entries = amdgpu_vm_num_entries(adev, level); |
f566ceb1 | 2764 | |
8f19cd78 CK |
2765 | if (parent->base.bo) { |
2766 | list_del(&parent->base.bo_list); | |
2767 | list_del(&parent->base.vm_status); | |
2768 | amdgpu_bo_unref(&parent->base.bo->shadow); | |
2769 | amdgpu_bo_unref(&parent->base.bo); | |
f566ceb1 CK |
2770 | } |
2771 | ||
8f19cd78 CK |
2772 | if (parent->entries) |
2773 | for (i = 0; i < num_entries; i++) | |
2774 | amdgpu_vm_free_levels(adev, &parent->entries[i], | |
2775 | level + 1); | |
f566ceb1 | 2776 | |
8f19cd78 | 2777 | kvfree(parent->entries); |
f566ceb1 CK |
2778 | } |
2779 | ||
d38ceaf9 AD |
2780 | /** |
2781 | * amdgpu_vm_fini - tear down a vm instance | |
2782 | * | |
2783 | * @adev: amdgpu_device pointer | |
2784 | * @vm: requested vm | |
2785 | * | |
8843dbbb | 2786 | * Tear down @vm. |
d38ceaf9 AD |
2787 | * Unbind the VM and remove all bos from the vm bo list |
2788 | */ | |
2789 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2790 | { | |
2791 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 2792 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 2793 | struct amdgpu_bo *root; |
a2f14820 | 2794 | u64 fault; |
2642cf11 | 2795 | int i, r; |
d38ceaf9 | 2796 | |
ede0dd86 FK |
2797 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
2798 | ||
a2f14820 FK |
2799 | /* Clear pending page faults from IH when the VM is destroyed */ |
2800 | while (kfifo_get(&vm->faults, &fault)) | |
2801 | amdgpu_ih_clear_fault(adev, fault); | |
2802 | ||
02208441 FK |
2803 | if (vm->pasid) { |
2804 | unsigned long flags; | |
2805 | ||
2806 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2807 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2808 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2809 | } | |
2810 | ||
cdc50176 | 2811 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa | 2812 | |
f808c13f | 2813 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2814 | dev_err(adev->dev, "still active bo inside vm\n"); |
2815 | } | |
f808c13f DB |
2816 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2817 | &vm->va.rb_root, rb) { | |
d38ceaf9 | 2818 | list_del(&mapping->list); |
a9f87f64 | 2819 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2820 | kfree(mapping); |
2821 | } | |
2822 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2823 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2824 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2825 | prt_fini_needed = false; |
451bc8eb | 2826 | } |
284710fa | 2827 | |
d38ceaf9 | 2828 | list_del(&mapping->list); |
451bc8eb | 2829 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2830 | } |
2831 | ||
2642cf11 CK |
2832 | root = amdgpu_bo_ref(vm->root.base.bo); |
2833 | r = amdgpu_bo_reserve(root, true); | |
2834 | if (r) { | |
2835 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2836 | } else { | |
196f7489 CZ |
2837 | amdgpu_vm_free_levels(adev, &vm->root, |
2838 | adev->vm_manager.root_level); | |
2642cf11 CK |
2839 | amdgpu_bo_unreserve(root); |
2840 | } | |
2841 | amdgpu_bo_unref(&root); | |
d5884513 | 2842 | dma_fence_put(vm->last_update); |
1e9ef26f | 2843 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 2844 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 2845 | } |
ea89f8c9 | 2846 | |
c98171cc FK |
2847 | /** |
2848 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
2849 | * | |
2850 | * @adev: amdgpu_device pointer | |
2851 | * @pasid: PASID do identify the VM | |
2852 | * | |
7fc48e59 AG |
2853 | * This function is expected to be called in interrupt context. |
2854 | * | |
2855 | * Returns: | |
2856 | * True if there was fault credit, false otherwise | |
c98171cc FK |
2857 | */ |
2858 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
2859 | unsigned int pasid) | |
2860 | { | |
2861 | struct amdgpu_vm *vm; | |
2862 | ||
2863 | spin_lock(&adev->vm_manager.pasid_lock); | |
2864 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
d958939a | 2865 | if (!vm) { |
c98171cc | 2866 | /* VM not found, can't track fault credit */ |
d958939a | 2867 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 2868 | return true; |
d958939a | 2869 | } |
c98171cc FK |
2870 | |
2871 | /* No lock needed. only accessed by IRQ handler */ | |
d958939a | 2872 | if (!vm->fault_credit) { |
c98171cc | 2873 | /* Too many faults in this VM */ |
d958939a | 2874 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 2875 | return false; |
d958939a | 2876 | } |
c98171cc FK |
2877 | |
2878 | vm->fault_credit--; | |
d958939a | 2879 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc FK |
2880 | return true; |
2881 | } | |
2882 | ||
a9a78b32 CK |
2883 | /** |
2884 | * amdgpu_vm_manager_init - init the VM manager | |
2885 | * | |
2886 | * @adev: amdgpu_device pointer | |
2887 | * | |
2888 | * Initialize the VM manager structures | |
2889 | */ | |
2890 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2891 | { | |
620f774f | 2892 | unsigned i; |
a9a78b32 | 2893 | |
620f774f | 2894 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 2895 | |
f54d1867 CW |
2896 | adev->vm_manager.fence_context = |
2897 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2898 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2899 | adev->vm_manager.seqno[i] = 0; | |
2900 | ||
2d55e45a | 2901 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
284710fa | 2902 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2903 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2904 | |
2905 | /* If not overridden by the user, by default, only in large BAR systems | |
2906 | * Compute VM tables will be updated by CPU | |
2907 | */ | |
2908 | #ifdef CONFIG_X86_64 | |
2909 | if (amdgpu_vm_update_mode == -1) { | |
c8c5e569 | 2910 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) |
9a4b7d4c HK |
2911 | adev->vm_manager.vm_update_mode = |
2912 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2913 | else | |
2914 | adev->vm_manager.vm_update_mode = 0; | |
2915 | } else | |
2916 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2917 | #else | |
2918 | adev->vm_manager.vm_update_mode = 0; | |
2919 | #endif | |
2920 | ||
02208441 FK |
2921 | idr_init(&adev->vm_manager.pasid_idr); |
2922 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
2923 | } |
2924 | ||
ea89f8c9 CK |
2925 | /** |
2926 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2927 | * | |
2928 | * @adev: amdgpu_device pointer | |
2929 | * | |
2930 | * Cleanup the VM manager and free resources. | |
2931 | */ | |
2932 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2933 | { | |
02208441 FK |
2934 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
2935 | idr_destroy(&adev->vm_manager.pasid_idr); | |
2936 | ||
620f774f | 2937 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 2938 | } |
cfbcacf4 | 2939 | |
7fc48e59 AG |
2940 | /** |
2941 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
2942 | * | |
2943 | * @dev: drm device pointer | |
2944 | * @data: drm_amdgpu_vm | |
2945 | * @filp: drm file pointer | |
2946 | * | |
2947 | * Returns: | |
2948 | * 0 for success, -errno for errors. | |
2949 | */ | |
cfbcacf4 CZ |
2950 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
2951 | { | |
2952 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2953 | struct amdgpu_device *adev = dev->dev_private; |
2954 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2955 | int r; | |
cfbcacf4 CZ |
2956 | |
2957 | switch (args->in.op) { | |
2958 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f | 2959 | /* current, we only have requirement to reserve vmid from gfxhub */ |
620f774f | 2960 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
1e9ef26f CZ |
2961 | if (r) |
2962 | return r; | |
2963 | break; | |
cfbcacf4 | 2964 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
620f774f | 2965 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2966 | break; |
2967 | default: | |
2968 | return -EINVAL; | |
2969 | } | |
2970 | ||
2971 | return 0; | |
2972 | } | |
2aa37bf5 AG |
2973 | |
2974 | /** | |
2975 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
2976 | * | |
2977 | * @dev: drm device pointer | |
2978 | * @pasid: PASID identifier for VM | |
2979 | * @task_info: task_info to fill. | |
2980 | */ | |
2981 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, | |
2982 | struct amdgpu_task_info *task_info) | |
2983 | { | |
2984 | struct amdgpu_vm *vm; | |
2985 | ||
2986 | spin_lock(&adev->vm_manager.pasid_lock); | |
2987 | ||
2988 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
2989 | if (vm) | |
2990 | *task_info = vm->task_info; | |
2991 | ||
2992 | spin_unlock(&adev->vm_manager.pasid_lock); | |
2993 | } | |
2994 | ||
2995 | /** | |
2996 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
2997 | * | |
2998 | * @vm: vm for which to set the info | |
2999 | */ | |
3000 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3001 | { | |
3002 | if (!vm->task_info.pid) { | |
3003 | vm->task_info.pid = current->pid; | |
3004 | get_task_comm(vm->task_info.task_name, current); | |
3005 | ||
3006 | if (current->group_leader->mm == current->mm) { | |
3007 | vm->task_info.tgid = current->group_leader->pid; | |
3008 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
3009 | } | |
3010 | } | |
3011 | } |