Commit | Line | Data |
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84ec374b RT |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | ||
3 | #include <drm/drm_atomic_helper.h> | |
4 | #include <drm/drm_simple_kms_helper.h> | |
5 | #include <drm/drm_vblank.h> | |
6 | ||
7 | #include "amdgpu.h" | |
733ee71a RT |
8 | #ifdef CONFIG_DRM_AMDGPU_SI |
9 | #include "dce_v6_0.h" | |
10 | #endif | |
11 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
12 | #include "dce_v8_0.h" | |
13 | #endif | |
14 | #include "dce_v10_0.h" | |
15 | #include "dce_v11_0.h" | |
16 | #include "ivsrcid/ivsrcid_vislands30.h" | |
84ec374b RT |
17 | #include "amdgpu_vkms.h" |
18 | #include "amdgpu_display.h" | |
deefd07e FC |
19 | #include "atom.h" |
20 | #include "amdgpu_irq.h" | |
84ec374b RT |
21 | |
22 | /** | |
23 | * DOC: amdgpu_vkms | |
24 | * | |
25 | * The amdgpu vkms interface provides a virtual KMS interface for several use | |
26 | * cases: devices without display hardware, platforms where the actual display | |
27 | * hardware is not useful (e.g., servers), SR-IOV virtual functions, device | |
28 | * emulation/simulation, and device bring up prior to display hardware being | |
29 | * usable. We previously emulated a legacy KMS interface, but there was a desire | |
30 | * to move to the atomic KMS interface. The vkms driver did everything we | |
31 | * needed, but we wanted KMS support natively in the driver without buffer | |
32 | * sharing and the ability to support an instance of VKMS per device. We first | |
33 | * looked at splitting vkms into a stub driver and a helper module that other | |
34 | * drivers could use to implement a virtual display, but this strategy ended up | |
35 | * being messy due to driver specific callbacks needed for buffer management. | |
36 | * Ultimately, it proved easier to import the vkms code as it mostly used core | |
37 | * drm helpers anyway. | |
38 | */ | |
39 | ||
40 | static const u32 amdgpu_vkms_formats[] = { | |
41 | DRM_FORMAT_XRGB8888, | |
42 | }; | |
43 | ||
44 | static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) | |
45 | { | |
deefd07e FC |
46 | struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); |
47 | struct drm_crtc *crtc = &amdgpu_crtc->base; | |
48 | struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); | |
84ec374b RT |
49 | u64 ret_overrun; |
50 | bool ret; | |
51 | ||
deefd07e | 52 | ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer, |
84ec374b | 53 | output->period_ns); |
f7ed3f90 FC |
54 | if (ret_overrun != 1) |
55 | DRM_WARN("%s: vblank timer overrun\n", __func__); | |
84ec374b RT |
56 | |
57 | ret = drm_crtc_handle_vblank(crtc); | |
58 | if (!ret) | |
59 | DRM_ERROR("amdgpu_vkms failure on handling vblank"); | |
60 | ||
61 | return HRTIMER_RESTART; | |
62 | } | |
63 | ||
64 | static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc) | |
65 | { | |
66 | struct drm_device *dev = crtc->dev; | |
67 | unsigned int pipe = drm_crtc_index(crtc); | |
68 | struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; | |
69 | struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc); | |
deefd07e | 70 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
84ec374b RT |
71 | |
72 | drm_calc_timestamping_constants(crtc, &crtc->mode); | |
73 | ||
84ec374b | 74 | out->period_ns = ktime_set(0, vblank->framedur_ns); |
deefd07e | 75 | hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL); |
84ec374b RT |
76 | |
77 | return 0; | |
78 | } | |
79 | ||
80 | static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc) | |
81 | { | |
deefd07e | 82 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
84ec374b | 83 | |
deefd07e | 84 | hrtimer_cancel(&amdgpu_crtc->vblank_timer); |
84ec374b RT |
85 | } |
86 | ||
87 | static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, | |
88 | int *max_error, | |
89 | ktime_t *vblank_time, | |
90 | bool in_vblank_irq) | |
91 | { | |
92 | struct drm_device *dev = crtc->dev; | |
93 | unsigned int pipe = crtc->index; | |
94 | struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); | |
95 | struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; | |
deefd07e | 96 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
84ec374b RT |
97 | |
98 | if (!READ_ONCE(vblank->enabled)) { | |
99 | *vblank_time = ktime_get(); | |
100 | return true; | |
101 | } | |
102 | ||
deefd07e | 103 | *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); |
84ec374b RT |
104 | |
105 | if (WARN_ON(*vblank_time == vblank->time)) | |
106 | return true; | |
107 | ||
108 | /* | |
109 | * To prevent races we roll the hrtimer forward before we do any | |
110 | * interrupt processing - this is how real hw works (the interrupt is | |
111 | * only generated after all the vblank registers are updated) and what | |
112 | * the vblank core expects. Therefore we need to always correct the | |
113 | * timestampe by one frame. | |
114 | */ | |
115 | *vblank_time -= output->period_ns; | |
116 | ||
117 | return true; | |
118 | } | |
119 | ||
120 | static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { | |
121 | .set_config = drm_atomic_helper_set_config, | |
122 | .destroy = drm_crtc_cleanup, | |
123 | .page_flip = drm_atomic_helper_page_flip, | |
124 | .reset = drm_atomic_helper_crtc_reset, | |
125 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
126 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
127 | .enable_vblank = amdgpu_vkms_enable_vblank, | |
128 | .disable_vblank = amdgpu_vkms_disable_vblank, | |
129 | .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, | |
130 | }; | |
131 | ||
132 | static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, | |
133 | struct drm_atomic_state *state) | |
134 | { | |
135 | drm_crtc_vblank_on(crtc); | |
136 | } | |
137 | ||
138 | static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, | |
139 | struct drm_atomic_state *state) | |
140 | { | |
141 | drm_crtc_vblank_off(crtc); | |
142 | } | |
143 | ||
144 | static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, | |
145 | struct drm_atomic_state *state) | |
146 | { | |
2096b74b | 147 | unsigned long flags; |
84ec374b | 148 | if (crtc->state->event) { |
2096b74b | 149 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
84ec374b RT |
150 | |
151 | if (drm_crtc_vblank_get(crtc) != 0) | |
152 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
153 | else | |
154 | drm_crtc_arm_vblank_event(crtc, crtc->state->event); | |
155 | ||
2096b74b | 156 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
84ec374b RT |
157 | |
158 | crtc->state->event = NULL; | |
159 | } | |
160 | } | |
161 | ||
162 | static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { | |
163 | .atomic_flush = amdgpu_vkms_crtc_atomic_flush, | |
164 | .atomic_enable = amdgpu_vkms_crtc_atomic_enable, | |
165 | .atomic_disable = amdgpu_vkms_crtc_atomic_disable, | |
166 | }; | |
167 | ||
168 | static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, | |
169 | struct drm_plane *primary, struct drm_plane *cursor) | |
170 | { | |
deefd07e FC |
171 | struct amdgpu_device *adev = drm_to_adev(dev); |
172 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
84ec374b RT |
173 | int ret; |
174 | ||
175 | ret = drm_crtc_init_with_planes(dev, crtc, primary, cursor, | |
176 | &amdgpu_vkms_crtc_funcs, NULL); | |
177 | if (ret) { | |
178 | DRM_ERROR("Failed to init CRTC\n"); | |
179 | return ret; | |
180 | } | |
181 | ||
182 | drm_crtc_helper_add(crtc, &amdgpu_vkms_crtc_helper_funcs); | |
183 | ||
deefd07e FC |
184 | amdgpu_crtc->crtc_id = drm_crtc_index(crtc); |
185 | adev->mode_info.crtcs[drm_crtc_index(crtc)] = amdgpu_crtc; | |
186 | ||
187 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; | |
188 | amdgpu_crtc->encoder = NULL; | |
189 | amdgpu_crtc->connector = NULL; | |
190 | amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; | |
191 | ||
192 | hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
193 | amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate; | |
194 | ||
84ec374b RT |
195 | return ret; |
196 | } | |
197 | ||
198 | static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { | |
199 | .fill_modes = drm_helper_probe_single_connector_modes, | |
200 | .destroy = drm_connector_cleanup, | |
201 | .reset = drm_atomic_helper_connector_reset, | |
202 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
203 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
204 | }; | |
205 | ||
206 | static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) | |
207 | { | |
208 | struct drm_device *dev = connector->dev; | |
209 | struct drm_display_mode *mode = NULL; | |
210 | unsigned i; | |
211 | static const struct mode_size { | |
212 | int w; | |
213 | int h; | |
214 | } common_modes[] = { | |
215 | { 640, 480}, | |
216 | { 720, 480}, | |
217 | { 800, 600}, | |
218 | { 848, 480}, | |
219 | {1024, 768}, | |
220 | {1152, 768}, | |
221 | {1280, 720}, | |
222 | {1280, 800}, | |
223 | {1280, 854}, | |
224 | {1280, 960}, | |
225 | {1280, 1024}, | |
226 | {1440, 900}, | |
227 | {1400, 1050}, | |
228 | {1680, 1050}, | |
229 | {1600, 1200}, | |
230 | {1920, 1080}, | |
231 | {1920, 1200}, | |
232 | {2560, 1440}, | |
233 | {4096, 3112}, | |
234 | {3656, 2664}, | |
235 | {3840, 2160}, | |
236 | {4096, 2160}, | |
237 | }; | |
238 | ||
239 | for (i = 0; i < ARRAY_SIZE(common_modes); i++) { | |
240 | mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); | |
241 | drm_mode_probed_add(connector, mode); | |
242 | } | |
243 | ||
244 | drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF); | |
245 | ||
246 | return ARRAY_SIZE(common_modes); | |
247 | } | |
248 | ||
249 | static const struct drm_connector_helper_funcs amdgpu_vkms_conn_helper_funcs = { | |
250 | .get_modes = amdgpu_vkms_conn_get_modes, | |
251 | }; | |
252 | ||
253 | static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { | |
254 | .update_plane = drm_atomic_helper_update_plane, | |
255 | .disable_plane = drm_atomic_helper_disable_plane, | |
256 | .destroy = drm_plane_cleanup, | |
257 | .reset = drm_atomic_helper_plane_reset, | |
258 | .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, | |
259 | .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, | |
260 | }; | |
261 | ||
262 | static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, | |
263 | struct drm_atomic_state *old_state) | |
264 | { | |
265 | return; | |
266 | } | |
267 | ||
268 | static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, | |
269 | struct drm_atomic_state *state) | |
270 | { | |
271 | struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, | |
272 | plane); | |
273 | struct drm_crtc_state *crtc_state; | |
274 | int ret; | |
275 | ||
276 | if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc)) | |
277 | return 0; | |
278 | ||
279 | crtc_state = drm_atomic_get_crtc_state(state, | |
280 | new_plane_state->crtc); | |
281 | if (IS_ERR(crtc_state)) | |
282 | return PTR_ERR(crtc_state); | |
283 | ||
284 | ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, | |
cce32e4e TZ |
285 | DRM_PLANE_NO_SCALING, |
286 | DRM_PLANE_NO_SCALING, | |
84ec374b RT |
287 | false, true); |
288 | if (ret != 0) | |
289 | return ret; | |
290 | ||
291 | /* for now primary plane must be visible and full screen */ | |
292 | if (!new_plane_state->visible) | |
293 | return -EINVAL; | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, | |
299 | struct drm_plane_state *new_state) | |
300 | { | |
301 | struct amdgpu_framebuffer *afb; | |
302 | struct drm_gem_object *obj; | |
303 | struct amdgpu_device *adev; | |
304 | struct amdgpu_bo *rbo; | |
84ec374b RT |
305 | uint32_t domain; |
306 | int r; | |
307 | ||
308 | if (!new_state->fb) { | |
309 | DRM_DEBUG_KMS("No FB bound\n"); | |
310 | return 0; | |
311 | } | |
312 | afb = to_amdgpu_framebuffer(new_state->fb); | |
313 | obj = new_state->fb->obj[0]; | |
314 | rbo = gem_to_amdgpu_bo(obj); | |
315 | adev = amdgpu_ttm_adev(rbo->tbo.bdev); | |
84ec374b | 316 | |
32c2d7a5 | 317 | r = amdgpu_bo_reserve(rbo, true); |
84ec374b RT |
318 | if (r) { |
319 | dev_err(adev->dev, "fail to reserve bo (%d)\n", r); | |
320 | return r; | |
321 | } | |
322 | ||
32c2d7a5 CK |
323 | r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); |
324 | if (r) { | |
325 | dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); | |
326 | goto error_unlock; | |
327 | } | |
328 | ||
84ec374b RT |
329 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
330 | domain = amdgpu_display_supported_domains(adev, rbo->flags); | |
331 | else | |
332 | domain = AMDGPU_GEM_DOMAIN_VRAM; | |
333 | ||
334 | r = amdgpu_bo_pin(rbo, domain); | |
335 | if (unlikely(r != 0)) { | |
336 | if (r != -ERESTARTSYS) | |
337 | DRM_ERROR("Failed to pin framebuffer with error %d\n", r); | |
32c2d7a5 | 338 | goto error_unlock; |
84ec374b RT |
339 | } |
340 | ||
341 | r = amdgpu_ttm_alloc_gart(&rbo->tbo); | |
342 | if (unlikely(r != 0)) { | |
84ec374b | 343 | DRM_ERROR("%p bind failed\n", rbo); |
32c2d7a5 | 344 | goto error_unpin; |
84ec374b RT |
345 | } |
346 | ||
32c2d7a5 | 347 | amdgpu_bo_unreserve(rbo); |
84ec374b RT |
348 | |
349 | afb->address = amdgpu_bo_gpu_offset(rbo); | |
350 | ||
351 | amdgpu_bo_ref(rbo); | |
352 | ||
353 | return 0; | |
32c2d7a5 CK |
354 | |
355 | error_unpin: | |
356 | amdgpu_bo_unpin(rbo); | |
357 | ||
358 | error_unlock: | |
359 | amdgpu_bo_unreserve(rbo); | |
360 | return r; | |
84ec374b RT |
361 | } |
362 | ||
363 | static void amdgpu_vkms_cleanup_fb(struct drm_plane *plane, | |
364 | struct drm_plane_state *old_state) | |
365 | { | |
366 | struct amdgpu_bo *rbo; | |
367 | int r; | |
368 | ||
369 | if (!old_state->fb) | |
370 | return; | |
371 | ||
372 | rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); | |
373 | r = amdgpu_bo_reserve(rbo, false); | |
374 | if (unlikely(r)) { | |
375 | DRM_ERROR("failed to reserve rbo before unpin\n"); | |
376 | return; | |
377 | } | |
378 | ||
379 | amdgpu_bo_unpin(rbo); | |
380 | amdgpu_bo_unreserve(rbo); | |
381 | amdgpu_bo_unref(&rbo); | |
382 | } | |
383 | ||
384 | static const struct drm_plane_helper_funcs amdgpu_vkms_primary_helper_funcs = { | |
385 | .atomic_update = amdgpu_vkms_plane_atomic_update, | |
386 | .atomic_check = amdgpu_vkms_plane_atomic_check, | |
387 | .prepare_fb = amdgpu_vkms_prepare_fb, | |
388 | .cleanup_fb = amdgpu_vkms_cleanup_fb, | |
389 | }; | |
390 | ||
391 | static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev, | |
392 | enum drm_plane_type type, | |
393 | int index) | |
394 | { | |
395 | struct drm_plane *plane; | |
396 | int ret; | |
397 | ||
398 | plane = kzalloc(sizeof(*plane), GFP_KERNEL); | |
399 | if (!plane) | |
400 | return ERR_PTR(-ENOMEM); | |
401 | ||
402 | ret = drm_universal_plane_init(dev, plane, 1 << index, | |
403 | &amdgpu_vkms_plane_funcs, | |
404 | amdgpu_vkms_formats, | |
405 | ARRAY_SIZE(amdgpu_vkms_formats), | |
97c61e0b | 406 | NULL, type, NULL); |
84ec374b RT |
407 | if (ret) { |
408 | kfree(plane); | |
409 | return ERR_PTR(ret); | |
410 | } | |
411 | ||
412 | drm_plane_helper_add(plane, &amdgpu_vkms_primary_helper_funcs); | |
413 | ||
414 | return plane; | |
415 | } | |
416 | ||
2351b7d4 IB |
417 | static int amdgpu_vkms_output_init(struct drm_device *dev, struct |
418 | amdgpu_vkms_output *output, int index) | |
84ec374b RT |
419 | { |
420 | struct drm_connector *connector = &output->connector; | |
421 | struct drm_encoder *encoder = &output->encoder; | |
deefd07e | 422 | struct drm_crtc *crtc = &output->crtc.base; |
84ec374b RT |
423 | struct drm_plane *primary, *cursor = NULL; |
424 | int ret; | |
425 | ||
426 | primary = amdgpu_vkms_plane_init(dev, DRM_PLANE_TYPE_PRIMARY, index); | |
427 | if (IS_ERR(primary)) | |
428 | return PTR_ERR(primary); | |
429 | ||
430 | ret = amdgpu_vkms_crtc_init(dev, crtc, primary, cursor); | |
431 | if (ret) | |
432 | goto err_crtc; | |
433 | ||
434 | ret = drm_connector_init(dev, connector, &amdgpu_vkms_connector_funcs, | |
435 | DRM_MODE_CONNECTOR_VIRTUAL); | |
436 | if (ret) { | |
437 | DRM_ERROR("Failed to init connector\n"); | |
438 | goto err_connector; | |
439 | } | |
440 | ||
441 | drm_connector_helper_add(connector, &amdgpu_vkms_conn_helper_funcs); | |
442 | ||
443 | ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_VIRTUAL); | |
444 | if (ret) { | |
445 | DRM_ERROR("Failed to init encoder\n"); | |
446 | goto err_encoder; | |
447 | } | |
448 | encoder->possible_crtcs = 1 << index; | |
449 | ||
450 | ret = drm_connector_attach_encoder(connector, encoder); | |
451 | if (ret) { | |
452 | DRM_ERROR("Failed to attach connector to encoder\n"); | |
453 | goto err_attach; | |
454 | } | |
455 | ||
456 | drm_mode_config_reset(dev); | |
457 | ||
458 | return 0; | |
459 | ||
460 | err_attach: | |
461 | drm_encoder_cleanup(encoder); | |
462 | ||
463 | err_encoder: | |
464 | drm_connector_cleanup(connector); | |
465 | ||
466 | err_connector: | |
467 | drm_crtc_cleanup(crtc); | |
468 | ||
469 | err_crtc: | |
470 | drm_plane_cleanup(primary); | |
471 | ||
472 | return ret; | |
473 | } | |
733ee71a RT |
474 | |
475 | const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { | |
476 | .fb_create = amdgpu_display_user_framebuffer_create, | |
477 | .atomic_check = drm_atomic_helper_check, | |
478 | .atomic_commit = drm_atomic_helper_commit, | |
479 | }; | |
480 | ||
481 | static int amdgpu_vkms_sw_init(void *handle) | |
482 | { | |
483 | int r, i; | |
484 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
485 | ||
30c1e391 FC |
486 | adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc, |
487 | sizeof(struct amdgpu_vkms_output), GFP_KERNEL); | |
488 | if (!adev->amdgpu_vkms_output) | |
489 | return -ENOMEM; | |
490 | ||
733ee71a RT |
491 | adev_to_drm(adev)->max_vblank_count = 0; |
492 | ||
493 | adev_to_drm(adev)->mode_config.funcs = &amdgpu_vkms_mode_funcs; | |
494 | ||
495 | adev_to_drm(adev)->mode_config.max_width = XRES_MAX; | |
496 | adev_to_drm(adev)->mode_config.max_height = YRES_MAX; | |
497 | ||
498 | adev_to_drm(adev)->mode_config.preferred_depth = 24; | |
a6250bdb | 499 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; |
733ee71a RT |
500 | |
501 | adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; | |
502 | ||
89b35547 YZ |
503 | adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; |
504 | ||
733ee71a RT |
505 | r = amdgpu_display_modeset_create_props(adev); |
506 | if (r) | |
507 | return r; | |
508 | ||
733ee71a RT |
509 | /* allocate crtcs, encoders, connectors */ |
510 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
511 | r = amdgpu_vkms_output_init(adev_to_drm(adev), &adev->amdgpu_vkms_output[i], i); | |
512 | if (r) | |
513 | return r; | |
514 | } | |
515 | ||
516 | drm_kms_helper_poll_init(adev_to_drm(adev)); | |
517 | ||
518 | adev->mode_info.mode_config_initialized = true; | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static int amdgpu_vkms_sw_fini(void *handle) | |
523 | { | |
524 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
525 | int i = 0; | |
526 | ||
527 | for (i = 0; i < adev->mode_info.num_crtc; i++) | |
deefd07e FC |
528 | if (adev->mode_info.crtcs[i]) |
529 | hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); | |
733ee71a | 530 | |
733ee71a | 531 | drm_kms_helper_poll_fini(adev_to_drm(adev)); |
30c1e391 | 532 | drm_mode_config_cleanup(adev_to_drm(adev)); |
733ee71a RT |
533 | |
534 | adev->mode_info.mode_config_initialized = false; | |
30c1e391 FC |
535 | |
536 | kfree(adev->mode_info.bios_hardcoded_edid); | |
537 | kfree(adev->amdgpu_vkms_output); | |
733ee71a RT |
538 | return 0; |
539 | } | |
540 | ||
541 | static int amdgpu_vkms_hw_init(void *handle) | |
542 | { | |
543 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
544 | ||
545 | switch (adev->asic_type) { | |
546 | #ifdef CONFIG_DRM_AMDGPU_SI | |
547 | case CHIP_TAHITI: | |
548 | case CHIP_PITCAIRN: | |
549 | case CHIP_VERDE: | |
550 | case CHIP_OLAND: | |
551 | dce_v6_0_disable_dce(adev); | |
552 | break; | |
553 | #endif | |
554 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
555 | case CHIP_BONAIRE: | |
556 | case CHIP_HAWAII: | |
557 | case CHIP_KAVERI: | |
558 | case CHIP_KABINI: | |
559 | case CHIP_MULLINS: | |
560 | dce_v8_0_disable_dce(adev); | |
561 | break; | |
562 | #endif | |
563 | case CHIP_FIJI: | |
564 | case CHIP_TONGA: | |
565 | dce_v10_0_disable_dce(adev); | |
566 | break; | |
567 | case CHIP_CARRIZO: | |
568 | case CHIP_STONEY: | |
569 | case CHIP_POLARIS10: | |
570 | case CHIP_POLARIS11: | |
571 | case CHIP_VEGAM: | |
572 | dce_v11_0_disable_dce(adev); | |
573 | break; | |
574 | case CHIP_TOPAZ: | |
575 | #ifdef CONFIG_DRM_AMDGPU_SI | |
576 | case CHIP_HAINAN: | |
577 | #endif | |
578 | /* no DCE */ | |
579 | break; | |
580 | default: | |
581 | break; | |
582 | } | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int amdgpu_vkms_hw_fini(void *handle) | |
587 | { | |
588 | return 0; | |
589 | } | |
590 | ||
591 | static int amdgpu_vkms_suspend(void *handle) | |
592 | { | |
593 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
594 | int r; | |
595 | ||
596 | r = drm_mode_config_helper_suspend(adev_to_drm(adev)); | |
597 | if (r) | |
598 | return r; | |
599 | return amdgpu_vkms_hw_fini(handle); | |
600 | } | |
601 | ||
602 | static int amdgpu_vkms_resume(void *handle) | |
603 | { | |
604 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
605 | int r; | |
606 | ||
607 | r = amdgpu_vkms_hw_init(handle); | |
608 | if (r) | |
609 | return r; | |
610 | return drm_mode_config_helper_resume(adev_to_drm(adev)); | |
611 | } | |
612 | ||
613 | static bool amdgpu_vkms_is_idle(void *handle) | |
614 | { | |
615 | return true; | |
616 | } | |
617 | ||
618 | static int amdgpu_vkms_wait_for_idle(void *handle) | |
619 | { | |
620 | return 0; | |
621 | } | |
622 | ||
623 | static int amdgpu_vkms_soft_reset(void *handle) | |
624 | { | |
625 | return 0; | |
626 | } | |
627 | ||
628 | static int amdgpu_vkms_set_clockgating_state(void *handle, | |
629 | enum amd_clockgating_state state) | |
630 | { | |
631 | return 0; | |
632 | } | |
633 | ||
634 | static int amdgpu_vkms_set_powergating_state(void *handle, | |
635 | enum amd_powergating_state state) | |
636 | { | |
637 | return 0; | |
638 | } | |
639 | ||
640 | static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { | |
641 | .name = "amdgpu_vkms", | |
642 | .early_init = NULL, | |
643 | .late_init = NULL, | |
644 | .sw_init = amdgpu_vkms_sw_init, | |
645 | .sw_fini = amdgpu_vkms_sw_fini, | |
646 | .hw_init = amdgpu_vkms_hw_init, | |
647 | .hw_fini = amdgpu_vkms_hw_fini, | |
648 | .suspend = amdgpu_vkms_suspend, | |
649 | .resume = amdgpu_vkms_resume, | |
650 | .is_idle = amdgpu_vkms_is_idle, | |
651 | .wait_for_idle = amdgpu_vkms_wait_for_idle, | |
652 | .soft_reset = amdgpu_vkms_soft_reset, | |
653 | .set_clockgating_state = amdgpu_vkms_set_clockgating_state, | |
654 | .set_powergating_state = amdgpu_vkms_set_powergating_state, | |
655 | }; | |
656 | ||
657 | const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = | |
658 | { | |
659 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
660 | .major = 1, | |
661 | .minor = 0, | |
662 | .rev = 0, | |
663 | .funcs = &amdgpu_vkms_ip_funcs, | |
664 | }; | |
665 |