[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_virt.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Author: Monk.liu@amd.com
 */
#ifndef AMDGPU_VIRT_H
#define AMDGPU_VIRT_H

#include "amdgv_sriovmsg.h"

#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
#define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this GPU */
#define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */
#define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
#define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
#define AMDGPU_VF_MMIO_ACCESS_PROTECT  (1 << 5) /* MMIO write access is not allowed in sriov runtime */

/* flags for indirect register access path supported by rlcg for sriov */
#define AMDGPU_RLCG_GC_WRITE_LEGACY    (0x8 << 28)
#define AMDGPU_RLCG_GC_WRITE           (0x0 << 28)
#define AMDGPU_RLCG_GC_READ            (0x1 << 28)
#define AMDGPU_RLCG_MMHUB_WRITE        (0x2 << 28)

/* error code for indirect register access path supported by rlcg for sriov */
#define AMDGPU_RLCG_VFGATE_DISABLED		0x4000000
#define AMDGPU_RLCG_WRONG_OPERATION_TYPE	0x2000000
#define AMDGPU_RLCG_REG_NOT_IN_RANGE		0x1000000

#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK	0xFFFFF

/* all asic after AI use this offset */
#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
/* tonga/fiji use this offset */
#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503

enum amdgpu_sriov_vf_mode {
	SRIOV_VF_MODE_BARE_METAL = 0,
	SRIOV_VF_MODE_ONE_VF,
	SRIOV_VF_MODE_MULTI_VF,
};

struct amdgpu_mm_table {
	struct amdgpu_bo	*bo;
	uint32_t		*cpu_addr;
	uint64_t		gpu_addr;
};

#define AMDGPU_VF_ERROR_ENTRY_SIZE    16

/* struct error_entry - amdgpu VF error information. */
struct amdgpu_vf_error_buffer {
	struct mutex lock;
	int read_count;
	int write_count;
	uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
	uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
};

enum idh_request;

/**
 * struct amdgpu_virt_ops - amdgpu device virt operations
 */
struct amdgpu_virt_ops {
	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
	int (*req_init_data)(struct amdgpu_device *adev);
	int (*reset_gpu)(struct amdgpu_device *adev);
	int (*wait_reset)(struct amdgpu_device *adev);
	void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
			  u32 data1, u32 data2, u32 data3);
	void (*ras_poison_handler)(struct amdgpu_device *adev);
};

/*
 * Firmware Reserve Frame buffer
 */
struct amdgpu_virt_fw_reserve {
	struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
	struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
	unsigned int checksum_key;
};

/*
 * Legacy GIM header
 *
 * Defination between PF and VF
 * Structures forcibly aligned to 4 to keep the same style as PF.
 */
#define AMDGIM_DATAEXCHANGE_OFFSET		(64 * 1024)

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
		(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

enum AMDGIM_FEATURE_FLAG {
	/* GIM supports feature of Error log collecting */
	AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
	/* GIM supports feature of loading uCodes */
	AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
	/* VRAM LOST by GIM */
	AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
	/* MM bandwidth */
	AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
	/* PP ONE VF MODE in GIM */
	AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
	/* Indirect Reg Access enabled */
	AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
	/* AV1 Support MODE*/
	AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
};

enum AMDGIM_REG_ACCESS_FLAG {
	/* Use PSP to program IH_RB_CNTL */
	AMDGIM_FEATURE_IH_REG_PSP_EN     = (1 << 0),
	/* Use RLC to program MMHUB regs */
	AMDGIM_FEATURE_MMHUB_REG_RLC_EN  = (1 << 1),
	/* Use RLC to program GC regs */
	AMDGIM_FEATURE_GC_REG_RLC_EN     = (1 << 2),
};

struct amdgim_pf2vf_info_v1 {
	/* header contains size and version */
	struct amd_sriov_msg_pf2vf_info_header header;
	/* max_width * max_height */
	unsigned int uvd_enc_max_pixels_count;
	/* 16x16 pixels/sec, codec independent */
	unsigned int uvd_enc_max_bandwidth;
	/* max_width * max_height */
	unsigned int vce_enc_max_pixels_count;
	/* 16x16 pixels/sec, codec independent */
	unsigned int vce_enc_max_bandwidth;
	/* MEC FW position in kb from the start of visible frame buffer */
	unsigned int mecfw_kboffset;
	/* The features flags of the GIM driver supports. */
	unsigned int feature_flags;
	/* use private key from mailbox 2 to create chueksum */
	unsigned int checksum;
} __aligned(4);

struct amdgim_vf2pf_info_v1 {
	/* header contains size and version */
	struct amd_sriov_msg_vf2pf_info_header header;
	/* driver version */
	char driver_version[64];
	/* driver certification, 1=WHQL, 0=None */
	unsigned int driver_cert;
	/* guest OS type and version: need a define */
	unsigned int os_info;
	/* in the unit of 1M */
	unsigned int fb_usage;
	/* guest gfx engine usage percentage */
	unsigned int gfx_usage;
	/* guest gfx engine health percentage */
	unsigned int gfx_health;
	/* guest compute engine usage percentage */
	unsigned int compute_usage;
	/* guest compute engine health percentage */
	unsigned int compute_health;
	/* guest vce engine usage percentage. 0xffff means N/A. */
	unsigned int vce_enc_usage;
	/* guest vce engine health percentage. 0xffff means N/A. */
	unsigned int vce_enc_health;
	/* guest uvd engine usage percentage. 0xffff means N/A. */
	unsigned int uvd_enc_usage;
	/* guest uvd engine usage percentage. 0xffff means N/A. */
	unsigned int uvd_enc_health;
	unsigned int checksum;
} __aligned(4);

struct amdgim_vf2pf_info_v2 {
	/* header contains size and version */
	struct amd_sriov_msg_vf2pf_info_header header;
	uint32_t checksum;
	/* driver version */
	uint8_t driver_version[64];
	/* driver certification, 1=WHQL, 0=None */
	uint32_t driver_cert;
	/* guest OS type and version: need a define */
	uint32_t os_info;
	/* in the unit of 1M */
	uint32_t fb_usage;
	/* guest gfx engine usage percentage */
	uint32_t gfx_usage;
	/* guest gfx engine health percentage */
	uint32_t gfx_health;
	/* guest compute engine usage percentage */
	uint32_t compute_usage;
	/* guest compute engine health percentage */
	uint32_t compute_health;
	/* guest vce engine usage percentage. 0xffff means N/A. */
	uint32_t vce_enc_usage;
	/* guest vce engine health percentage. 0xffff means N/A. */
	uint32_t vce_enc_health;
	/* guest uvd engine usage percentage. 0xffff means N/A. */
	uint32_t uvd_enc_usage;
	/* guest uvd engine usage percentage. 0xffff means N/A. */
	uint32_t uvd_enc_health;
	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
} __aligned(4);

struct amdgpu_virt_ras_err_handler_data {
	/* point to bad page records array */
	struct eeprom_table_record *bps;
	/* point to reserved bo array */
	struct amdgpu_bo **bps_bo;
	/* the count of entries */
	int count;
	/* last reserved entry's index + 1 */
	int last_reserved;
};

/* GPU virtualization */
struct amdgpu_virt {
	uint32_t			caps;
	struct amdgpu_bo		*csa_obj;
	void				*csa_cpu_addr;
	bool chained_ib_support;
	uint32_t			reg_val_offs;
	struct amdgpu_irq_src		ack_irq;
	struct amdgpu_irq_src		rcv_irq;
	struct work_struct		flr_work;
	struct amdgpu_mm_table		mm_table;
	const struct amdgpu_virt_ops	*ops;
	struct amdgpu_vf_error_buffer	vf_errors;
	struct amdgpu_virt_fw_reserve	fw_reserve;
	uint32_t gim_feature;
	uint32_t reg_access_mode;
	int req_init_data_ver;
	bool tdr_debug;
	struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
	bool ras_init_done;
	uint32_t reg_access;

	/* vf2pf message */
	struct delayed_work vf2pf_work;
	uint32_t vf2pf_update_interval_ms;

	/* multimedia bandwidth config */
	bool     is_mm_bw_enabled;
	uint32_t decode_max_dimension_pixels;
	uint32_t decode_max_frame_pixels;
	uint32_t encode_max_dimension_pixels;
	uint32_t encode_max_frame_pixels;

	/* the ucode id to signal the autoload */
	uint32_t autoload_ucode_id;
};

struct amdgpu_video_codec_info;

#define amdgpu_sriov_enabled(adev) \
((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)

#define amdgpu_sriov_vf(adev) \
((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)

#define amdgpu_sriov_bios(adev) \
((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)

#define amdgpu_sriov_runtime(adev) \
((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)

#define amdgpu_sriov_fullaccess(adev) \
(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))

#define amdgpu_sriov_reg_indirect_en(adev) \
(amdgpu_sriov_vf((adev)) && \
	((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))

#define amdgpu_sriov_reg_indirect_ih(adev) \
(amdgpu_sriov_vf((adev)) && \
	((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))

#define amdgpu_sriov_reg_indirect_mmhub(adev) \
(amdgpu_sriov_vf((adev)) && \
	((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))

#define amdgpu_sriov_reg_indirect_gc(adev) \
(amdgpu_sriov_vf((adev)) && \
	((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))

#define amdgpu_sriov_rlcg_error_report_enabled(adev) \
        (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))

#define amdgpu_passthrough(adev) \
((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)

#define amdgpu_sriov_vf_mmio_access_protection(adev) \
((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)

static inline bool is_virtual_machine(void)
{
#if defined(CONFIG_X86)
	return boot_cpu_has(X86_FEATURE_HYPERVISOR);
#elif defined(CONFIG_ARM64)
	return !is_kernel_in_hyp_mode();
#else
	return false;
#endif
}

#define amdgpu_sriov_is_pp_one_vf(adev) \
	((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
#define amdgpu_sriov_is_debug(adev) \
	((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
#define amdgpu_sriov_is_normal(adev) \
	((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
#define amdgpu_sriov_is_av1_support(adev) \
	((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
					uint32_t reg0, uint32_t rreg1,
					uint32_t ref, uint32_t mask);
int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
void amdgpu_detect_virtualization(struct amdgpu_device *adev);

bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);

enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);

void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
			struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
			struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
void amdgpu_sriov_wreg(struct amdgpu_device *adev,
		       u32 offset, u32 value,
		       u32 acc_flags, u32 hwip);
u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
		      u32 offset, u32 acc_flags, u32 hwip);
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
			uint32_t ucode_id);
#endif
Commit	Line	Data
ceeb50ed ML	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Author: Monk.liu@amd.com
	23	*/
	24	#ifndef AMDGPU_VIRT_H
	25	#define AMDGPU_VIRT_H
	26
1721bc1b BZ	27	#include "amdgv_sriovmsg.h"
1721bc1b BZ	28
ceeb50ed ML	29	#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
	30	#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
	31	#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
	32	#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
5ec9f06e	33	#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
a7310d8d	34	#define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
bd7de27d	35
29dbcac8 HZ	36	/* flags for indirect register access path supported by rlcg for sriov */
	37	#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
	38	#define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
	39	#define AMDGPU_RLCG_GC_READ (0x1 << 28)
	40	#define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
	41
5d447e29 HZ	42	/* error code for indirect register access path supported by rlcg for sriov */
	43	#define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
	44	#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
	45	#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
	46
aa79d380 VS	47	#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
aa79d380 VS	48
3aa0115d ML	49	/* all asic after AI use this offset */
	50	#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
	51	/* tonga/fiji use this offset */
	52	#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
	53
a7f28103 KW	54	enum amdgpu_sriov_vf_mode {
	55	SRIOV_VF_MODE_BARE_METAL = 0,
	56	SRIOV_VF_MODE_ONE_VF,
	57	SRIOV_VF_MODE_MULTI_VF,
	58	};
	59
ecb2b9c6 XY	60	struct amdgpu_mm_table {
	61	struct amdgpu_bo *bo;
	62	uint32_t *cpu_addr;
	63	uint64_t gpu_addr;
	64	};
	65
e23b74aa AD	66	#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
	67
	68	/* struct error_entry - amdgpu VF error information. */
	69	struct amdgpu_vf_error_buffer {
	70	struct mutex lock;
	71	int read_count;
	72	int write_count;
	73	uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
	74	uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
	75	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
	76	};
	77
f0d0f108 NC	78	enum idh_request;
f0d0f108 NC	79
1e9f1392 XY	80	/**
	81	* struct amdgpu_virt_ops - amdgpu device virt operations
	82	*/
	83	struct amdgpu_virt_ops {
	84	int (req_full_gpu)(struct amdgpu_device adev, bool init);
	85	int (rel_full_gpu)(struct amdgpu_device adev, bool init);
aa53bc2e	86	int (req_init_data)(struct amdgpu_device adev);
1e9f1392	87	int (reset_gpu)(struct amdgpu_device adev);
b636176e	88	int (wait_reset)(struct amdgpu_device adev);
f0d0f108 NC	89	void (trans_msg)(struct amdgpu_device adev, enum idh_request req,
f0d0f108 NC	90	u32 data1, u32 data2, u32 data3);
8ede944d	91	void (ras_poison_handler)(struct amdgpu_device adev);
1e9f1392 XY	92	};
1e9f1392 XY	93
2dc8f81e HC	94	/*
	95	* Firmware Reserve Frame buffer
	96	*/
	97	struct amdgpu_virt_fw_reserve {
bed1ed36 ED	98	struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
bed1ed36 ED	99	struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
2dc8f81e HC	100	unsigned int checksum_key;
2dc8f81e HC	101	};
1721bc1b	102
2dc8f81e	103	/*
1721bc1b BZ	104	* Legacy GIM header
1721bc1b BZ	105	*
2dc8f81e HC	106	* Defination between PF and VF
	107	* Structures forcibly aligned to 4 to keep the same style as PF.
	108	*/
	109	#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
	110
	111	#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
	112	(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
	113
	114	enum AMDGIM_FEATURE_FLAG {
	115	/* GIM supports feature of Error log collecting */
	116	AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
	117	/* GIM supports feature of loading uCodes */
	118	AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
75bc6099 ML	119	/* VRAM LOST by GIM */
75bc6099 ML	120	AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
b89659b7 ML	121	/* MM bandwidth */
b89659b7 ML	122	AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
c9ffa427 YT	123	/* PP ONE VF MODE in GIM */
c9ffa427 YT	124	AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
4d675e1e RK	125	/* Indirect Reg Access enabled */
4d675e1e RK	126	AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
d71e38df JJ	127	/* AV1 Support MODE*/
d71e38df JJ	128	AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
4d675e1e RK	129	};
	130
	131	enum AMDGIM_REG_ACCESS_FLAG {
	132	/* Use PSP to program IH_RB_CNTL */
8b8a162d	133	AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
4d675e1e	134	/* Use RLC to program MMHUB regs */
8b8a162d	135	AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
4d675e1e	136	/* Use RLC to program GC regs */
8b8a162d	137	AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
2dc8f81e HC	138	};
2dc8f81e HC	139
1721bc1b	140	struct amdgim_pf2vf_info_v1 {
2dc8f81e	141	/* header contains size and version */
bed1ed36	142	struct amd_sriov_msg_pf2vf_info_header header;
2dc8f81e HC	143	/* max_width * max_height */
	144	unsigned int uvd_enc_max_pixels_count;
	145	/* 16x16 pixels/sec, codec independent */
	146	unsigned int uvd_enc_max_bandwidth;
	147	/* max_width * max_height */
	148	unsigned int vce_enc_max_pixels_count;
	149	/* 16x16 pixels/sec, codec independent */
	150	unsigned int vce_enc_max_bandwidth;
	151	/* MEC FW position in kb from the start of visible frame buffer */
	152	unsigned int mecfw_kboffset;
	153	/* The features flags of the GIM driver supports. */
	154	unsigned int feature_flags;
	155	/* use private key from mailbox 2 to create chueksum */
	156	unsigned int checksum;
	157	} __aligned(4);
	158
2dc8f81e HC	159	struct amdgim_vf2pf_info_v1 {
2dc8f81e HC	160	/* header contains size and version */
bed1ed36	161	struct amd_sriov_msg_vf2pf_info_header header;
2dc8f81e HC	162	/* driver version */
	163	char driver_version[64];
	164	/* driver certification, 1=WHQL, 0=None */
	165	unsigned int driver_cert;
	166	/* guest OS type and version: need a define */
	167	unsigned int os_info;
	168	/* in the unit of 1M */
	169	unsigned int fb_usage;
	170	/* guest gfx engine usage percentage */
	171	unsigned int gfx_usage;
	172	/* guest gfx engine health percentage */
	173	unsigned int gfx_health;
	174	/* guest compute engine usage percentage */
	175	unsigned int compute_usage;
	176	/* guest compute engine health percentage */
	177	unsigned int compute_health;
	178	/* guest vce engine usage percentage. 0xffff means N/A. */
	179	unsigned int vce_enc_usage;
	180	/* guest vce engine health percentage. 0xffff means N/A. */
	181	unsigned int vce_enc_health;
	182	/* guest uvd engine usage percentage. 0xffff means N/A. */
	183	unsigned int uvd_enc_usage;
	184	/* guest uvd engine usage percentage. 0xffff means N/A. */
	185	unsigned int uvd_enc_health;
	186	unsigned int checksum;
	187	} __aligned(4);
	188
	189	struct amdgim_vf2pf_info_v2 {
	190	/* header contains size and version */
bed1ed36	191	struct amd_sriov_msg_vf2pf_info_header header;
2dc8f81e HC	192	uint32_t checksum;
	193	/* driver version */
	194	uint8_t driver_version[64];
	195	/* driver certification, 1=WHQL, 0=None */
	196	uint32_t driver_cert;
	197	/* guest OS type and version: need a define */
	198	uint32_t os_info;
	199	/* in the unit of 1M */
	200	uint32_t fb_usage;
	201	/* guest gfx engine usage percentage */
	202	uint32_t gfx_usage;
	203	/* guest gfx engine health percentage */
	204	uint32_t gfx_health;
	205	/* guest compute engine usage percentage */
	206	uint32_t compute_usage;
	207	/* guest compute engine health percentage */
	208	uint32_t compute_health;
	209	/* guest vce engine usage percentage. 0xffff means N/A. */
	210	uint32_t vce_enc_usage;
	211	/* guest vce engine health percentage. 0xffff means N/A. */
	212	uint32_t vce_enc_health;
	213	/* guest uvd engine usage percentage. 0xffff means N/A. */
	214	uint32_t uvd_enc_usage;
	215	/* guest uvd engine usage percentage. 0xffff means N/A. */
	216	uint32_t uvd_enc_health;
bed1ed36	217	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
2dc8f81e HC	218	} __aligned(4);
2dc8f81e HC	219
5278a159 SY	220	struct amdgpu_virt_ras_err_handler_data {
	221	/* point to bad page records array */
	222	struct eeprom_table_record *bps;
	223	/* point to reserved bo array */
	224	struct amdgpu_bo **bps_bo;
	225	/* the count of entries */
	226	int count;
	227	/* last reserved entry's index + 1 */
	228	int last_reserved;
	229	};
	230
ceeb50ed	231	/* GPU virtualization */
5a5099cb	232	struct amdgpu_virt {
1e9f1392 XY	233	uint32_t caps;
1e9f1392 XY	234	struct amdgpu_bo *csa_obj;
43974dac	235	void *csa_cpu_addr;
ae65a26d	236	bool chained_ib_support;
1e9f1392	237	uint32_t reg_val_offs;
ab71ac56 XY	238	struct amdgpu_irq_src ack_irq;
ab71ac56 XY	239	struct amdgpu_irq_src rcv_irq;
480da262	240	struct work_struct flr_work;
ecb2b9c6	241	struct amdgpu_mm_table mm_table;
1e9f1392	242	const struct amdgpu_virt_ops *ops;
519b8b76	243	struct amdgpu_vf_error_buffer vf_errors;
2dc8f81e	244	struct amdgpu_virt_fw_reserve fw_reserve;
75bc6099	245	uint32_t gim_feature;
78d48112	246	uint32_t reg_access_mode;
aa53bc2e	247	int req_init_data_ver;
95a2f917	248	bool tdr_debug;
5278a159 SY	249	struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
5278a159 SY	250	bool ras_init_done;
5d238510	251	uint32_t reg_access;
519b8b76 BZ	252
	253	/* vf2pf message */
	254	struct delayed_work vf2pf_work;
	255	uint32_t vf2pf_update_interval_ms;
ed9d2053 BZ	256
	257	/* multimedia bandwidth config */
	258	bool is_mm_bw_enabled;
	259	uint32_t decode_max_dimension_pixels;
	260	uint32_t decode_max_frame_pixels;
	261	uint32_t encode_max_dimension_pixels;
	262	uint32_t encode_max_frame_pixels;
f8bd7321 HC	263
	264	/* the ucode id to signal the autoload */
	265	uint32_t autoload_ucode_id;
ceeb50ed ML	266	};
ceeb50ed ML	267
ed9d2053 BZ	268	struct amdgpu_video_codec_info;
ed9d2053 BZ	269
ceeb50ed	270	#define amdgpu_sriov_enabled(adev) \
5a5099cb	271	((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
ceeb50ed ML	272
ceeb50ed ML	273	#define amdgpu_sriov_vf(adev) \
5a5099cb	274	((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
ceeb50ed ML	275
ceeb50ed ML	276	#define amdgpu_sriov_bios(adev) \
5a5099cb	277	((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
ceeb50ed	278
5ec9f06e XY	279	#define amdgpu_sriov_runtime(adev) \
	280	((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
	281
2e0cc4d4 ML	282	#define amdgpu_sriov_fullaccess(adev) \
	283	(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
	284
5d238510 PJZ	285	#define amdgpu_sriov_reg_indirect_en(adev) \
	286	(amdgpu_sriov_vf((adev)) && \
	287	((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
	288
	289	#define amdgpu_sriov_reg_indirect_ih(adev) \
	290	(amdgpu_sriov_vf((adev)) && \
	291	((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
	292
	293	#define amdgpu_sriov_reg_indirect_mmhub(adev) \
	294	(amdgpu_sriov_vf((adev)) && \
	295	((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
	296
	297	#define amdgpu_sriov_reg_indirect_gc(adev) \
	298	(amdgpu_sriov_vf((adev)) && \
	299	((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
	300
5d447e29 HZ	301	#define amdgpu_sriov_rlcg_error_report_enabled(adev) \
	302	(amdgpu_sriov_reg_indirect_mmhub(adev) \|\| amdgpu_sriov_reg_indirect_gc(adev))
	303
ceeb50ed	304	#define amdgpu_passthrough(adev) \
5a5099cb	305	((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
ceeb50ed	306
a7310d8d DS	307	#define amdgpu_sriov_vf_mmio_access_protection(adev) \
	308	((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
	309
ceeb50ed ML	310	static inline bool is_virtual_machine(void)
ceeb50ed ML	311	{
039cacd2	312	#if defined(CONFIG_X86)
ceeb50ed	313	return boot_cpu_has(X86_FEATURE_HYPERVISOR);
039cacd2 VZ	314	#elif defined(CONFIG_ARM64)
039cacd2 VZ	315	return !is_kernel_in_hyp_mode();
ceeb50ed ML	316	#else
	317	return false;
	318	#endif
	319	}
	320
c9ffa427 YT	321	#define amdgpu_sriov_is_pp_one_vf(adev) \
c9ffa427 YT	322	((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
95a2f917	323	#define amdgpu_sriov_is_debug(adev) \
53b3f8f4	324	((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
d32709da	325	#define amdgpu_sriov_is_normal(adev) \
53b3f8f4	326	((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
d71e38df JJ	327	#define amdgpu_sriov_is_av1_support(adev) \
d71e38df JJ	328	((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
a16f8f11	329	bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
bc992ba5	330	void amdgpu_virt_init_setting(struct amdgpu_device *adev);
af5fe1e9 CK	331	void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
	332	uint32_t reg0, uint32_t rreg1,
	333	uint32_t ref, uint32_t mask);
1e9f1392 XY	334	int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
	335	int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
	336	int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
aa53bc2e	337	void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
b636176e	338	int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
904cd389 XY	339	int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
904cd389 XY	340	void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
5278a159	341	void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
2dc8f81e	342	void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
892deb48	343	void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
519b8b76	344	void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
3aa0115d	345	void amdgpu_detect_virtualization(struct amdgpu_device *adev);
95a2f917 YT	346
	347	bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
	348	int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
	349	void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
a7f28103 KW	350
a7f28103 KW	351	enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
ed9d2053 BZ	352
	353	void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
	354	struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
	355	struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
5d447e29 HZ	356	void amdgpu_sriov_wreg(struct amdgpu_device *adev,
	357	u32 offset, u32 value,
	358	u32 acc_flags, u32 hwip);
	359	u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
	360	u32 offset, u32 acc_flags, u32 hwip);
d9d86d08 HC	361	bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
d9d86d08 HC	362	uint32_t ucode_id);
5a5099cb	363	#endif