Commit | Line | Data |
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4e4bbe73 ML |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
f867723b SR |
24 | #include <linux/module.h> |
25 | ||
26 | #include <drm/drm_drv.h> | |
27 | ||
4e4bbe73 | 28 | #include "amdgpu.h" |
5278a159 | 29 | #include "amdgpu_ras.h" |
c1299461 WS |
30 | #include "vi.h" |
31 | #include "soc15.h" | |
32 | #include "nv.h" | |
4e4bbe73 | 33 | |
519b8b76 BZ |
34 | #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ |
35 | do { \ | |
36 | vf2pf_info->ucode_info[ucode].id = ucode; \ | |
37 | vf2pf_info->ucode_info[ucode].version = ver; \ | |
38 | } while (0) | |
39 | ||
a16f8f11 | 40 | bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) |
41 | { | |
42 | /* By now all MMIO pages except mailbox are blocked */ | |
43 | /* if blocking is enabled in hypervisor. Choose the */ | |
44 | /* SCRATCH_REG0 to test. */ | |
45 | return RREG32_NO_KIQ(0xc040) == 0xffffffff; | |
46 | } | |
47 | ||
bc992ba5 XY |
48 | void amdgpu_virt_init_setting(struct amdgpu_device *adev) |
49 | { | |
e431eb80 AD |
50 | struct drm_device *ddev = adev_to_drm(adev); |
51 | ||
06465d8e | 52 | /* enable virtual display */ |
02f6efb4 ED |
53 | if (adev->mode_info.num_crtc == 0) |
54 | adev->mode_info.num_crtc = 1; | |
06465d8e | 55 | adev->enable_virtual_display = true; |
e431eb80 | 56 | ddev->driver_features &= ~DRIVER_ATOMIC; |
213cacef XY |
57 | adev->cg_flags = 0; |
58 | adev->pg_flags = 0; | |
bc992ba5 XY |
59 | } |
60 | ||
af5fe1e9 CK |
61 | void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, |
62 | uint32_t reg0, uint32_t reg1, | |
63 | uint32_t ref, uint32_t mask) | |
64 | { | |
65 | struct amdgpu_kiq *kiq = &adev->gfx.kiq; | |
66 | struct amdgpu_ring *ring = &kiq->ring; | |
67 | signed long r, cnt = 0; | |
68 | unsigned long flags; | |
69 | uint32_t seq; | |
70 | ||
71 | spin_lock_irqsave(&kiq->ring_lock, flags); | |
72 | amdgpu_ring_alloc(ring, 32); | |
73 | amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, | |
74 | ref, mask); | |
04e4e2e9 YT |
75 | r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); |
76 | if (r) | |
77 | goto failed_undo; | |
78 | ||
af5fe1e9 CK |
79 | amdgpu_ring_commit(ring); |
80 | spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
81 | ||
82 | r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
83 | ||
84 | /* don't wait anymore for IRQ context */ | |
85 | if (r < 1 && in_interrupt()) | |
86 | goto failed_kiq; | |
87 | ||
88 | might_sleep(); | |
89 | while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { | |
90 | ||
91 | msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); | |
92 | r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); | |
93 | } | |
94 | ||
95 | if (cnt > MAX_KIQ_REG_TRY) | |
96 | goto failed_kiq; | |
97 | ||
98 | return; | |
99 | ||
04e4e2e9 YT |
100 | failed_undo: |
101 | amdgpu_ring_undo(ring); | |
102 | spin_unlock_irqrestore(&kiq->ring_lock, flags); | |
af5fe1e9 | 103 | failed_kiq: |
aac89168 | 104 | dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); |
af5fe1e9 CK |
105 | } |
106 | ||
1e9f1392 XY |
107 | /** |
108 | * amdgpu_virt_request_full_gpu() - request full gpu access | |
f59bf24e | 109 | * @adev: amdgpu device. |
1e9f1392 XY |
110 | * @init: is driver init time. |
111 | * When start to init/fini driver, first need to request full gpu access. | |
112 | * Return: Zero if request success, otherwise will return error. | |
113 | */ | |
114 | int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) | |
115 | { | |
116 | struct amdgpu_virt *virt = &adev->virt; | |
117 | int r; | |
118 | ||
119 | if (virt->ops && virt->ops->req_full_gpu) { | |
120 | r = virt->ops->req_full_gpu(adev, init); | |
121 | if (r) | |
122 | return r; | |
123 | ||
124 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
125 | } | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
130 | /** | |
131 | * amdgpu_virt_release_full_gpu() - release full gpu access | |
f59bf24e | 132 | * @adev: amdgpu device. |
1e9f1392 XY |
133 | * @init: is driver init time. |
134 | * When finishing driver init/fini, need to release full gpu access. | |
135 | * Return: Zero if release success, otherwise will returen error. | |
136 | */ | |
137 | int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) | |
138 | { | |
139 | struct amdgpu_virt *virt = &adev->virt; | |
140 | int r; | |
141 | ||
142 | if (virt->ops && virt->ops->rel_full_gpu) { | |
143 | r = virt->ops->rel_full_gpu(adev, init); | |
144 | if (r) | |
145 | return r; | |
146 | ||
147 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; | |
148 | } | |
149 | return 0; | |
150 | } | |
151 | ||
152 | /** | |
153 | * amdgpu_virt_reset_gpu() - reset gpu | |
f59bf24e | 154 | * @adev: amdgpu device. |
1e9f1392 XY |
155 | * Send reset command to GPU hypervisor to reset GPU that VM is using |
156 | * Return: Zero if reset success, otherwise will return error. | |
157 | */ | |
158 | int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) | |
159 | { | |
160 | struct amdgpu_virt *virt = &adev->virt; | |
161 | int r; | |
162 | ||
163 | if (virt->ops && virt->ops->reset_gpu) { | |
164 | r = virt->ops->reset_gpu(adev); | |
165 | if (r) | |
166 | return r; | |
167 | ||
168 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
904cd389 | 173 | |
aa53bc2e ML |
174 | void amdgpu_virt_request_init_data(struct amdgpu_device *adev) |
175 | { | |
176 | struct amdgpu_virt *virt = &adev->virt; | |
177 | ||
178 | if (virt->ops && virt->ops->req_init_data) | |
179 | virt->ops->req_init_data(adev); | |
180 | ||
181 | if (adev->virt.req_init_data_ver > 0) | |
182 | DRM_INFO("host supports REQ_INIT_DATA handshake\n"); | |
183 | else | |
184 | DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); | |
185 | } | |
186 | ||
b636176e | 187 | /** |
188 | * amdgpu_virt_wait_reset() - wait for reset gpu completed | |
f59bf24e | 189 | * @adev: amdgpu device. |
b636176e | 190 | * Wait for GPU reset completed. |
191 | * Return: Zero if reset success, otherwise will return error. | |
192 | */ | |
193 | int amdgpu_virt_wait_reset(struct amdgpu_device *adev) | |
194 | { | |
195 | struct amdgpu_virt *virt = &adev->virt; | |
196 | ||
197 | if (!virt->ops || !virt->ops->wait_reset) | |
198 | return -EINVAL; | |
199 | ||
200 | return virt->ops->wait_reset(adev); | |
201 | } | |
202 | ||
904cd389 XY |
203 | /** |
204 | * amdgpu_virt_alloc_mm_table() - alloc memory for mm table | |
f59bf24e | 205 | * @adev: amdgpu device. |
904cd389 XY |
206 | * MM table is used by UVD and VCE for its initialization |
207 | * Return: Zero if allocate success. | |
208 | */ | |
209 | int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) | |
210 | { | |
211 | int r; | |
212 | ||
213 | if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) | |
214 | return 0; | |
215 | ||
216 | r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, | |
217 | AMDGPU_GEM_DOMAIN_VRAM, | |
218 | &adev->virt.mm_table.bo, | |
219 | &adev->virt.mm_table.gpu_addr, | |
220 | (void *)&adev->virt.mm_table.cpu_addr); | |
221 | if (r) { | |
222 | DRM_ERROR("failed to alloc mm table and error = %d.\n", r); | |
223 | return r; | |
224 | } | |
225 | ||
226 | memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); | |
227 | DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", | |
228 | adev->virt.mm_table.gpu_addr, | |
229 | adev->virt.mm_table.cpu_addr); | |
230 | return 0; | |
231 | } | |
232 | ||
233 | /** | |
234 | * amdgpu_virt_free_mm_table() - free mm table memory | |
f59bf24e | 235 | * @adev: amdgpu device. |
904cd389 XY |
236 | * Free MM table memory |
237 | */ | |
238 | void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) | |
239 | { | |
240 | if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) | |
241 | return; | |
242 | ||
243 | amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, | |
244 | &adev->virt.mm_table.gpu_addr, | |
245 | (void *)&adev->virt.mm_table.cpu_addr); | |
246 | adev->virt.mm_table.gpu_addr = 0; | |
247 | } | |
2dc8f81e HC |
248 | |
249 | ||
519b8b76 BZ |
250 | unsigned int amd_sriov_msg_checksum(void *obj, |
251 | unsigned long obj_size, | |
252 | unsigned int key, | |
253 | unsigned int checksum) | |
2dc8f81e HC |
254 | { |
255 | unsigned int ret = key; | |
256 | unsigned long i = 0; | |
257 | unsigned char *pos; | |
258 | ||
259 | pos = (char *)obj; | |
260 | /* calculate checksum */ | |
261 | for (i = 0; i < obj_size; ++i) | |
262 | ret += *(pos + i); | |
519b8b76 BZ |
263 | /* minus the checksum itself */ |
264 | pos = (char *)&checksum; | |
265 | for (i = 0; i < sizeof(checksum); ++i) | |
2dc8f81e HC |
266 | ret -= *(pos + i); |
267 | return ret; | |
268 | } | |
269 | ||
5278a159 SY |
270 | static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) |
271 | { | |
272 | struct amdgpu_virt *virt = &adev->virt; | |
273 | struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; | |
274 | /* GPU will be marked bad on host if bp count more then 10, | |
275 | * so alloc 512 is enough. | |
276 | */ | |
277 | unsigned int align_space = 512; | |
278 | void *bps = NULL; | |
279 | struct amdgpu_bo **bps_bo = NULL; | |
280 | ||
281 | *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); | |
282 | if (!*data) | |
283 | return -ENOMEM; | |
284 | ||
95666c6c BZ |
285 | bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); |
286 | bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); | |
5278a159 SY |
287 | |
288 | if (!bps || !bps_bo) { | |
289 | kfree(bps); | |
290 | kfree(bps_bo); | |
291 | kfree(*data); | |
292 | return -ENOMEM; | |
293 | } | |
294 | ||
295 | (*data)->bps = bps; | |
296 | (*data)->bps_bo = bps_bo; | |
297 | (*data)->count = 0; | |
298 | (*data)->last_reserved = 0; | |
299 | ||
300 | virt->ras_init_done = true; | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) | |
306 | { | |
307 | struct amdgpu_virt *virt = &adev->virt; | |
308 | struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; | |
309 | struct amdgpu_bo *bo; | |
310 | int i; | |
311 | ||
312 | if (!data) | |
313 | return; | |
314 | ||
315 | for (i = data->last_reserved - 1; i >= 0; i--) { | |
316 | bo = data->bps_bo[i]; | |
317 | amdgpu_bo_free_kernel(&bo, NULL, NULL); | |
318 | data->bps_bo[i] = bo; | |
319 | data->last_reserved = i; | |
320 | } | |
321 | } | |
322 | ||
323 | void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) | |
324 | { | |
325 | struct amdgpu_virt *virt = &adev->virt; | |
326 | struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; | |
327 | ||
328 | virt->ras_init_done = false; | |
329 | ||
330 | if (!data) | |
331 | return; | |
332 | ||
333 | amdgpu_virt_ras_release_bp(adev); | |
334 | ||
335 | kfree(data->bps); | |
336 | kfree(data->bps_bo); | |
337 | kfree(data); | |
338 | virt->virt_eh_data = NULL; | |
339 | } | |
340 | ||
341 | static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, | |
342 | struct eeprom_table_record *bps, int pages) | |
343 | { | |
344 | struct amdgpu_virt *virt = &adev->virt; | |
345 | struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; | |
346 | ||
347 | if (!data) | |
348 | return; | |
349 | ||
350 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); | |
351 | data->count += pages; | |
352 | } | |
353 | ||
354 | static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) | |
355 | { | |
356 | struct amdgpu_virt *virt = &adev->virt; | |
357 | struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; | |
358 | struct amdgpu_bo *bo = NULL; | |
359 | uint64_t bp; | |
360 | int i; | |
361 | ||
362 | if (!data) | |
363 | return; | |
364 | ||
365 | for (i = data->last_reserved; i < data->count; i++) { | |
366 | bp = data->bps[i].retired_page; | |
367 | ||
368 | /* There are two cases of reserve error should be ignored: | |
369 | * 1) a ras bad page has been allocated (used by someone); | |
370 | * 2) a ras bad page has been reserved (duplicate error injection | |
371 | * for one page); | |
372 | */ | |
373 | if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, | |
374 | AMDGPU_GPU_PAGE_SIZE, | |
375 | AMDGPU_GEM_DOMAIN_VRAM, | |
376 | &bo, NULL)) | |
377 | DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); | |
378 | ||
379 | data->bps_bo[i] = bo; | |
380 | data->last_reserved = i + 1; | |
381 | bo = NULL; | |
382 | } | |
383 | } | |
384 | ||
385 | static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, | |
386 | uint64_t retired_page) | |
387 | { | |
388 | struct amdgpu_virt *virt = &adev->virt; | |
389 | struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; | |
390 | int i; | |
391 | ||
392 | if (!data) | |
393 | return true; | |
394 | ||
395 | for (i = 0; i < data->count; i++) | |
396 | if (retired_page == data->bps[i].retired_page) | |
397 | return true; | |
398 | ||
399 | return false; | |
400 | } | |
401 | ||
402 | static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, | |
403 | uint64_t bp_block_offset, uint32_t bp_block_size) | |
404 | { | |
405 | struct eeprom_table_record bp; | |
406 | uint64_t retired_page; | |
407 | uint32_t bp_idx, bp_cnt; | |
408 | ||
409 | if (bp_block_size) { | |
410 | bp_cnt = bp_block_size / sizeof(uint64_t); | |
411 | for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { | |
87ded5ca | 412 | retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va + |
5278a159 SY |
413 | bp_block_offset + bp_idx * sizeof(uint64_t)); |
414 | bp.retired_page = retired_page; | |
415 | ||
416 | if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) | |
417 | continue; | |
418 | ||
419 | amdgpu_virt_ras_add_bps(adev, &bp, 1); | |
420 | ||
421 | amdgpu_virt_ras_reserve_bps(adev); | |
422 | } | |
423 | } | |
424 | } | |
425 | ||
519b8b76 | 426 | static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) |
2dc8f81e | 427 | { |
519b8b76 BZ |
428 | struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; |
429 | uint32_t checksum; | |
2dc8f81e | 430 | uint32_t checkval; |
519b8b76 BZ |
431 | |
432 | if (adev->virt.fw_reserve.p_pf2vf == NULL) | |
433 | return -EINVAL; | |
434 | ||
435 | if (pf2vf_info->size > 1024) { | |
436 | DRM_ERROR("invalid pf2vf message size\n"); | |
437 | return -EINVAL; | |
438 | } | |
439 | ||
440 | switch (pf2vf_info->version) { | |
441 | case 1: | |
442 | checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; | |
443 | checkval = amd_sriov_msg_checksum( | |
444 | adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, | |
445 | adev->virt.fw_reserve.checksum_key, checksum); | |
446 | if (checksum != checkval) { | |
447 | DRM_ERROR("invalid pf2vf message\n"); | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | adev->virt.gim_feature = | |
452 | ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; | |
453 | break; | |
454 | case 2: | |
455 | /* TODO: missing key, need to add it later */ | |
456 | checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; | |
457 | checkval = amd_sriov_msg_checksum( | |
458 | adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, | |
459 | 0, checksum); | |
460 | if (checksum != checkval) { | |
461 | DRM_ERROR("invalid pf2vf message\n"); | |
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | adev->virt.vf2pf_update_interval_ms = | |
466 | ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; | |
467 | adev->virt.gim_feature = | |
468 | ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; | |
469 | ||
470 | break; | |
471 | default: | |
472 | DRM_ERROR("invalid pf2vf version\n"); | |
473 | return -EINVAL; | |
474 | } | |
475 | ||
476 | /* correct too large or too little interval value */ | |
477 | if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) | |
478 | adev->virt.vf2pf_update_interval_ms = 2000; | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) | |
484 | { | |
485 | struct amd_sriov_msg_vf2pf_info *vf2pf_info; | |
486 | vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; | |
487 | ||
488 | if (adev->virt.fw_reserve.p_vf2pf == NULL) | |
489 | return; | |
490 | ||
491 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); | |
492 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); | |
493 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); | |
494 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); | |
495 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); | |
496 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); | |
497 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); | |
498 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); | |
499 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); | |
500 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); | |
501 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); | |
502 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); | |
503 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos_fw_version); | |
504 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, adev->psp.asd_fw_version); | |
505 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ta_ras_ucode_version); | |
506 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, adev->psp.ta_xgmi_ucode_version); | |
507 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); | |
508 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); | |
509 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); | |
510 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); | |
511 | POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); | |
512 | } | |
513 | ||
514 | static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) | |
515 | { | |
516 | struct amd_sriov_msg_vf2pf_info *vf2pf_info; | |
517 | struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); | |
518 | ||
519 | vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; | |
520 | ||
521 | if (adev->virt.fw_reserve.p_vf2pf == NULL) | |
522 | return -EINVAL; | |
523 | ||
524 | memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); | |
525 | ||
526 | vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); | |
527 | vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; | |
528 | ||
529 | #ifdef MODULE | |
530 | if (THIS_MODULE->version != NULL) | |
531 | strcpy(vf2pf_info->driver_version, THIS_MODULE->version); | |
532 | else | |
533 | #endif | |
534 | strcpy(vf2pf_info->driver_version, "N/A"); | |
535 | ||
536 | vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all | |
537 | vf2pf_info->driver_cert = 0; | |
538 | vf2pf_info->os_info.all = 0; | |
539 | ||
540 | vf2pf_info->fb_usage = amdgpu_vram_mgr_usage(vram_man) >> 20; | |
541 | vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(vram_man) >> 20; | |
542 | vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; | |
543 | vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; | |
544 | ||
545 | amdgpu_virt_populate_vf2pf_ucode_info(adev); | |
546 | ||
547 | /* TODO: read dynamic info */ | |
548 | vf2pf_info->gfx_usage = 0; | |
549 | vf2pf_info->compute_usage = 0; | |
550 | vf2pf_info->encode_usage = 0; | |
551 | vf2pf_info->decode_usage = 0; | |
552 | ||
553 | vf2pf_info->checksum = | |
554 | amd_sriov_msg_checksum( | |
555 | vf2pf_info, vf2pf_info->header.size, 0, 0); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
05ed830e | 560 | static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) |
519b8b76 BZ |
561 | { |
562 | struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); | |
64dcf2f0 | 563 | int ret; |
519b8b76 | 564 | |
64dcf2f0 JC |
565 | ret = amdgpu_virt_read_pf2vf_data(adev); |
566 | if (ret) | |
567 | goto out; | |
519b8b76 BZ |
568 | amdgpu_virt_write_vf2pf_data(adev); |
569 | ||
64dcf2f0 | 570 | out: |
519b8b76 BZ |
571 | schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); |
572 | } | |
573 | ||
574 | void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) | |
575 | { | |
576 | if (adev->virt.vf2pf_update_interval_ms != 0) { | |
577 | DRM_INFO("clean up the vf2pf work item\n"); | |
519b8b76 | 578 | cancel_delayed_work_sync(&adev->virt.vf2pf_work); |
3c2a01cb | 579 | adev->virt.vf2pf_update_interval_ms = 0; |
519b8b76 BZ |
580 | } |
581 | } | |
582 | ||
583 | void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) | |
584 | { | |
5278a159 SY |
585 | uint64_t bp_block_offset = 0; |
586 | uint32_t bp_block_size = 0; | |
519b8b76 | 587 | struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; |
2dc8f81e HC |
588 | |
589 | adev->virt.fw_reserve.p_pf2vf = NULL; | |
590 | adev->virt.fw_reserve.p_vf2pf = NULL; | |
519b8b76 | 591 | adev->virt.vf2pf_update_interval_ms = 0; |
2dc8f81e | 592 | |
87ded5ca | 593 | if (adev->mman.fw_vram_usage_va != NULL) { |
519b8b76 BZ |
594 | adev->virt.vf2pf_update_interval_ms = 2000; |
595 | ||
2dc8f81e | 596 | adev->virt.fw_reserve.p_pf2vf = |
519b8b76 BZ |
597 | (struct amd_sriov_msg_pf2vf_info_header *) |
598 | (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); | |
599 | adev->virt.fw_reserve.p_vf2pf = | |
600 | (struct amd_sriov_msg_vf2pf_info_header *) | |
601 | (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); | |
602 | ||
603 | amdgpu_virt_read_pf2vf_data(adev); | |
604 | amdgpu_virt_write_vf2pf_data(adev); | |
605 | ||
606 | /* bad page handling for version 2 */ | |
607 | if (adev->virt.fw_reserve.p_pf2vf->version == 2) { | |
608 | pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; | |
609 | ||
610 | bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | | |
611 | ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); | |
5278a159 SY |
612 | bp_block_size = pf2vf_v2->bp_block_size; |
613 | ||
614 | if (bp_block_size && !adev->virt.ras_init_done) | |
615 | amdgpu_virt_init_ras_err_handler_data(adev); | |
616 | ||
617 | if (adev->virt.ras_init_done) | |
618 | amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); | |
619 | } | |
519b8b76 | 620 | } |
5278a159 | 621 | |
519b8b76 BZ |
622 | if (adev->virt.vf2pf_update_interval_ms != 0) { |
623 | INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); | |
624 | schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); | |
2dc8f81e HC |
625 | } |
626 | } | |
3aa0115d ML |
627 | |
628 | void amdgpu_detect_virtualization(struct amdgpu_device *adev) | |
629 | { | |
630 | uint32_t reg; | |
631 | ||
632 | switch (adev->asic_type) { | |
633 | case CHIP_TONGA: | |
634 | case CHIP_FIJI: | |
635 | reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); | |
636 | break; | |
637 | case CHIP_VEGA10: | |
638 | case CHIP_VEGA20: | |
639 | case CHIP_NAVI10: | |
640 | case CHIP_NAVI12: | |
7cf70047 | 641 | case CHIP_SIENNA_CICHLID: |
3aa0115d ML |
642 | case CHIP_ARCTURUS: |
643 | reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); | |
644 | break; | |
645 | default: /* other chip doesn't support SRIOV */ | |
646 | reg = 0; | |
647 | break; | |
648 | } | |
649 | ||
650 | if (reg & 1) | |
651 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; | |
652 | ||
653 | if (reg & 0x80000000) | |
654 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; | |
655 | ||
656 | if (!reg) { | |
657 | if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ | |
658 | adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; | |
659 | } | |
c1299461 WS |
660 | |
661 | /* we have the ability to check now */ | |
662 | if (amdgpu_sriov_vf(adev)) { | |
663 | switch (adev->asic_type) { | |
664 | case CHIP_TONGA: | |
665 | case CHIP_FIJI: | |
666 | vi_set_virt_ops(adev); | |
667 | break; | |
668 | case CHIP_VEGA10: | |
669 | case CHIP_VEGA20: | |
670 | case CHIP_ARCTURUS: | |
671 | soc15_set_virt_ops(adev); | |
672 | break; | |
673 | case CHIP_NAVI10: | |
674 | case CHIP_NAVI12: | |
675 | case CHIP_SIENNA_CICHLID: | |
676 | nv_set_virt_ops(adev); | |
677 | /* try send GPU_INIT_DATA request to host */ | |
678 | amdgpu_virt_request_init_data(adev); | |
679 | break; | |
680 | default: /* other chip doesn't support SRIOV */ | |
681 | DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); | |
682 | break; | |
683 | } | |
684 | } | |
3aa0115d | 685 | } |
95a2f917 | 686 | |
f3167919 | 687 | static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) |
95a2f917 YT |
688 | { |
689 | return amdgpu_sriov_is_debug(adev) ? true : false; | |
690 | } | |
691 | ||
f3167919 | 692 | static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) |
d32709da YT |
693 | { |
694 | return amdgpu_sriov_is_normal(adev) ? true : false; | |
695 | } | |
696 | ||
95a2f917 YT |
697 | int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) |
698 | { | |
d32709da YT |
699 | if (!amdgpu_sriov_vf(adev) || |
700 | amdgpu_virt_access_debugfs_is_kiq(adev)) | |
95a2f917 YT |
701 | return 0; |
702 | ||
d32709da | 703 | if (amdgpu_virt_access_debugfs_is_mmio(adev)) |
95a2f917 YT |
704 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; |
705 | else | |
706 | return -EPERM; | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
711 | void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) | |
712 | { | |
713 | if (amdgpu_sriov_vf(adev)) | |
714 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; | |
715 | } | |
a7f28103 KW |
716 | |
717 | enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) | |
718 | { | |
719 | enum amdgpu_sriov_vf_mode mode; | |
720 | ||
721 | if (amdgpu_sriov_vf(adev)) { | |
722 | if (amdgpu_sriov_is_pp_one_vf(adev)) | |
723 | mode = SRIOV_VF_MODE_ONE_VF; | |
724 | else | |
725 | mode = SRIOV_VF_MODE_MULTI_VF; | |
726 | } else { | |
727 | mode = SRIOV_VF_MODE_BARE_METAL; | |
728 | } | |
729 | ||
730 | return mode; | |
731 | } |