[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vcn.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_VCN_H__
#define __AMDGPU_VCN_H__

#define AMDGPU_VCN_STACK_SIZE		(200*1024)
#define AMDGPU_VCN_HEAP_SIZE		(256*1024)
#define AMDGPU_VCN_SESSION_SIZE		(50*1024)
#define AMDGPU_VCN_FIRMWARE_OFFSET	256
#define AMDGPU_VCN_MAX_ENC_RINGS	3

#define VCN_DEC_CMD_FENCE		0x00000000
#define VCN_DEC_CMD_TRAP		0x00000001
#define VCN_DEC_CMD_WRITE_REG		0x00000004
#define VCN_DEC_CMD_REG_READ_COND_WAIT	0x00000006
#define VCN_DEC_CMD_PACKET_START	0x0000000a
#define VCN_DEC_CMD_PACKET_END		0x0000000b

#define VCN_ENC_CMD_NO_OP		0x00000000
#define VCN_ENC_CMD_END 		0x00000001
#define VCN_ENC_CMD_IB			0x00000002
#define VCN_ENC_CMD_FENCE		0x00000003
#define VCN_ENC_CMD_TRAP		0x00000004
#define VCN_ENC_CMD_REG_WRITE		0x0000000b
#define VCN_ENC_CMD_REG_WAIT		0x0000000c

enum engine_status_constants {
	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
	UVD_STATUS__UVD_BUSY = 0x00000004,
	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
	UVD_STATUS__IDLE = 0x2,
	UVD_STATUS__BUSY = 0x5,
	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
	UVD_STATUS__RBC_BUSY = 0x1,
};

struct amdgpu_vcn {
	struct amdgpu_bo	*vcpu_bo;
	void			*cpu_addr;
	uint64_t		gpu_addr;
	unsigned		fw_version;
	void			*saved_bo;
	struct delayed_work	idle_work;
	const struct firmware	*fw;	/* VCN firmware */
	struct amdgpu_ring	ring_dec;
	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
	struct amdgpu_ring	ring_jpeg;
	struct amdgpu_irq_src	irq;
	unsigned		num_enc_rings;
};

int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);

int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);

int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);

int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);

#endif
Commit	Line	Data
95d0906f LL	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_VCN_H__
	25	#define __AMDGPU_VCN_H__
	26
95aa13f6 LL	27	#define AMDGPU_VCN_STACK_SIZE (200*1024)
	28	#define AMDGPU_VCN_HEAP_SIZE (256*1024)
	29	#define AMDGPU_VCN_SESSION_SIZE (50*1024)
	30	#define AMDGPU_VCN_FIRMWARE_OFFSET 256
	31	#define AMDGPU_VCN_MAX_ENC_RINGS 3
	32
3639f7d8 LL	33	#define VCN_DEC_CMD_FENCE 0x00000000
	34	#define VCN_DEC_CMD_TRAP 0x00000001
	35	#define VCN_DEC_CMD_WRITE_REG 0x00000004
	36	#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
	37	#define VCN_DEC_CMD_PACKET_START 0x0000000a
	38	#define VCN_DEC_CMD_PACKET_END 0x0000000b
7741cced	39
8ace845f LL	40	#define VCN_ENC_CMD_NO_OP 0x00000000
	41	#define VCN_ENC_CMD_END 0x00000001
	42	#define VCN_ENC_CMD_IB 0x00000002
	43	#define VCN_ENC_CMD_FENCE 0x00000003
	44	#define VCN_ENC_CMD_TRAP 0x00000004
	45	#define VCN_ENC_CMD_REG_WRITE 0x0000000b
	46	#define VCN_ENC_CMD_REG_WAIT 0x0000000c
	47
d58c5d9a RZ	48	enum engine_status_constants {
	49	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
	50	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
	51	UVD_STATUS__UVD_BUSY = 0x00000004,
	52	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
	53	UVD_STATUS__IDLE = 0x2,
	54	UVD_STATUS__BUSY = 0x5,
	55	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
	56	UVD_STATUS__RBC_BUSY = 0x1,
	57	};
	58
95aa13f6 LL	59	struct amdgpu_vcn {
	60	struct amdgpu_bo *vcpu_bo;
	61	void *cpu_addr;
	62	uint64_t gpu_addr;
	63	unsigned fw_version;
	64	void *saved_bo;
	65	struct delayed_work idle_work;
	66	const struct firmware fw; / VCN firmware */
	67	struct amdgpu_ring ring_dec;
	68	struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
fa3087f7	69	struct amdgpu_ring ring_jpeg;
95aa13f6	70	struct amdgpu_irq_src irq;
101c6fee	71	unsigned num_enc_rings;
95aa13f6 LL	72	};
95aa13f6 LL	73
95d0906f LL	74	int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
	75	int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
	76	int amdgpu_vcn_suspend(struct amdgpu_device *adev);
	77	int amdgpu_vcn_resume(struct amdgpu_device *adev);
	78	void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
	79	void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
8c303c01 LL	80
8c303c01 LL	81	int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
95d0906f LL	82	int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
95d0906f LL	83
2d531d81 LL	84	int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
	85	int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
	86
b1d37606	87	int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
6173040f	88	int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
b1d37606	89
95d0906f	90	#endif