Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <deathsimple@vodafone.de> | |
29 | */ | |
30 | ||
31 | #include <linux/firmware.h> | |
32 | #include <linux/module.h> | |
33 | #include <drm/drmP.h> | |
34 | #include <drm/drm.h> | |
35 | ||
36 | #include "amdgpu.h" | |
37 | #include "amdgpu_pm.h" | |
38 | #include "amdgpu_uvd.h" | |
39 | #include "cikd.h" | |
40 | #include "uvd/uvd_4_2_d.h" | |
41 | ||
42 | /* 1 second timeout */ | |
08086635 | 43 | #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) |
4cb5877c CK |
44 | |
45 | /* Firmware versions for VI */ | |
46 | #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) | |
47 | #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) | |
48 | #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) | |
49 | #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) | |
50 | ||
8e008dd7 | 51 | /* Polaris10/11 firmware version */ |
4cb5877c | 52 | #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) |
d38ceaf9 AD |
53 | |
54 | /* Firmware Names */ | |
55 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
56 | #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" | |
edf600da CK |
57 | #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" |
58 | #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" | |
59 | #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" | |
d38ceaf9 AD |
60 | #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" |
61 | #endif | |
c65444fe JZ |
62 | #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" |
63 | #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" | |
974ee3db | 64 | #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" |
a39c8cea | 65 | #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" |
2cc0c0b5 | 66 | #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" |
925a51c4 | 67 | #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" |
d38ceaf9 AD |
68 | |
69 | /** | |
70 | * amdgpu_uvd_cs_ctx - Command submission parser context | |
71 | * | |
72 | * Used for emulating virtual memory support on UVD 4.2. | |
73 | */ | |
74 | struct amdgpu_uvd_cs_ctx { | |
75 | struct amdgpu_cs_parser *parser; | |
76 | unsigned reg, count; | |
77 | unsigned data0, data1; | |
78 | unsigned idx; | |
79 | unsigned ib_idx; | |
80 | ||
81 | /* does the IB has a msg command */ | |
82 | bool has_msg_cmd; | |
83 | ||
84 | /* minimum buffer sizes */ | |
85 | unsigned *buf_sizes; | |
86 | }; | |
87 | ||
88 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
89 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); | |
90 | MODULE_FIRMWARE(FIRMWARE_KABINI); | |
91 | MODULE_FIRMWARE(FIRMWARE_KAVERI); | |
92 | MODULE_FIRMWARE(FIRMWARE_HAWAII); | |
93 | MODULE_FIRMWARE(FIRMWARE_MULLINS); | |
94 | #endif | |
95 | MODULE_FIRMWARE(FIRMWARE_TONGA); | |
96 | MODULE_FIRMWARE(FIRMWARE_CARRIZO); | |
974ee3db | 97 | MODULE_FIRMWARE(FIRMWARE_FIJI); |
a39c8cea | 98 | MODULE_FIRMWARE(FIRMWARE_STONEY); |
2cc0c0b5 FC |
99 | MODULE_FIRMWARE(FIRMWARE_POLARIS10); |
100 | MODULE_FIRMWARE(FIRMWARE_POLARIS11); | |
d38ceaf9 | 101 | |
d38ceaf9 AD |
102 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work); |
103 | ||
104 | int amdgpu_uvd_sw_init(struct amdgpu_device *adev) | |
105 | { | |
ead833ec CK |
106 | struct amdgpu_ring *ring; |
107 | struct amd_sched_rq *rq; | |
d38ceaf9 AD |
108 | unsigned long bo_size; |
109 | const char *fw_name; | |
110 | const struct common_firmware_header *hdr; | |
111 | unsigned version_major, version_minor, family_id; | |
112 | int i, r; | |
113 | ||
114 | INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); | |
115 | ||
116 | switch (adev->asic_type) { | |
117 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
118 | case CHIP_BONAIRE: | |
119 | fw_name = FIRMWARE_BONAIRE; | |
120 | break; | |
121 | case CHIP_KABINI: | |
122 | fw_name = FIRMWARE_KABINI; | |
123 | break; | |
124 | case CHIP_KAVERI: | |
125 | fw_name = FIRMWARE_KAVERI; | |
126 | break; | |
127 | case CHIP_HAWAII: | |
128 | fw_name = FIRMWARE_HAWAII; | |
129 | break; | |
130 | case CHIP_MULLINS: | |
131 | fw_name = FIRMWARE_MULLINS; | |
132 | break; | |
133 | #endif | |
134 | case CHIP_TONGA: | |
135 | fw_name = FIRMWARE_TONGA; | |
136 | break; | |
974ee3db DZ |
137 | case CHIP_FIJI: |
138 | fw_name = FIRMWARE_FIJI; | |
139 | break; | |
d38ceaf9 AD |
140 | case CHIP_CARRIZO: |
141 | fw_name = FIRMWARE_CARRIZO; | |
142 | break; | |
a39c8cea SL |
143 | case CHIP_STONEY: |
144 | fw_name = FIRMWARE_STONEY; | |
145 | break; | |
2cc0c0b5 FC |
146 | case CHIP_POLARIS10: |
147 | fw_name = FIRMWARE_POLARIS10; | |
38d75817 | 148 | break; |
2cc0c0b5 FC |
149 | case CHIP_POLARIS11: |
150 | fw_name = FIRMWARE_POLARIS11; | |
38d75817 | 151 | break; |
d38ceaf9 AD |
152 | default: |
153 | return -EINVAL; | |
154 | } | |
155 | ||
156 | r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); | |
157 | if (r) { | |
158 | dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", | |
159 | fw_name); | |
160 | return r; | |
161 | } | |
162 | ||
163 | r = amdgpu_ucode_validate(adev->uvd.fw); | |
164 | if (r) { | |
165 | dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", | |
166 | fw_name); | |
167 | release_firmware(adev->uvd.fw); | |
168 | adev->uvd.fw = NULL; | |
169 | return r; | |
170 | } | |
171 | ||
c0365541 AN |
172 | /* Set the default UVD handles that the firmware can handle */ |
173 | adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; | |
174 | ||
d38ceaf9 AD |
175 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
176 | family_id = le32_to_cpu(hdr->ucode_version) & 0xff; | |
177 | version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; | |
178 | version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; | |
179 | DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", | |
180 | version_major, version_minor, family_id); | |
181 | ||
c0365541 AN |
182 | /* |
183 | * Limit the number of UVD handles depending on microcode major | |
184 | * and minor versions. The firmware version which has 40 UVD | |
185 | * instances support is 1.80. So all subsequent versions should | |
186 | * also have the same support. | |
187 | */ | |
188 | if ((version_major > 0x01) || | |
189 | ((version_major == 0x01) && (version_minor >= 0x50))) | |
190 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; | |
191 | ||
562e2689 SJ |
192 | adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | |
193 | (family_id << 8)); | |
194 | ||
8e008dd7 SJ |
195 | if ((adev->asic_type == CHIP_POLARIS10 || |
196 | adev->asic_type == CHIP_POLARIS11) && | |
197 | (adev->uvd.fw_version < FW_1_66_16)) | |
198 | DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", | |
199 | version_major, version_minor); | |
200 | ||
d38ceaf9 | 201 | bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) |
c0365541 AN |
202 | + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE |
203 | + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; | |
4b62e697 CK |
204 | r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, |
205 | AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, | |
206 | &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); | |
d38ceaf9 AD |
207 | if (r) { |
208 | dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); | |
209 | return r; | |
210 | } | |
211 | ||
ead833ec CK |
212 | ring = &adev->uvd.ring; |
213 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; | |
214 | r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, | |
215 | rq, amdgpu_sched_jobs); | |
216 | if (r != 0) { | |
217 | DRM_ERROR("Failed setting up UVD run queue.\n"); | |
218 | return r; | |
219 | } | |
220 | ||
c0365541 | 221 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
222 | atomic_set(&adev->uvd.handles[i], 0); |
223 | adev->uvd.filp[i] = NULL; | |
224 | } | |
225 | ||
226 | /* from uvd v5.0 HW addressing capacity increased to 64 bits */ | |
5fc3aeeb | 227 | if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) |
d38ceaf9 AD |
228 | adev->uvd.address_64_bit = true; |
229 | ||
4cb5877c CK |
230 | switch (adev->asic_type) { |
231 | case CHIP_TONGA: | |
232 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; | |
233 | break; | |
234 | case CHIP_CARRIZO: | |
235 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; | |
236 | break; | |
237 | case CHIP_FIJI: | |
238 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; | |
239 | break; | |
240 | case CHIP_STONEY: | |
241 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; | |
242 | break; | |
243 | default: | |
244 | adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; | |
245 | } | |
246 | ||
d38ceaf9 AD |
247 | return 0; |
248 | } | |
249 | ||
250 | int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) | |
251 | { | |
252 | int r; | |
253 | ||
05f19eb5 | 254 | kfree(adev->uvd.saved_bo); |
d38ceaf9 | 255 | |
ead833ec CK |
256 | amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); |
257 | ||
05f19eb5 ML |
258 | if (adev->uvd.vcpu_bo) { |
259 | r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); | |
260 | if (!r) { | |
261 | amdgpu_bo_kunmap(adev->uvd.vcpu_bo); | |
262 | amdgpu_bo_unpin(adev->uvd.vcpu_bo); | |
263 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
264 | } | |
d38ceaf9 | 265 | |
05f19eb5 ML |
266 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); |
267 | } | |
d38ceaf9 AD |
268 | |
269 | amdgpu_ring_fini(&adev->uvd.ring); | |
270 | ||
271 | release_firmware(adev->uvd.fw); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | int amdgpu_uvd_suspend(struct amdgpu_device *adev) | |
277 | { | |
3f99dd81 LL |
278 | unsigned size; |
279 | void *ptr; | |
3f99dd81 | 280 | int i; |
d38ceaf9 AD |
281 | |
282 | if (adev->uvd.vcpu_bo == NULL) | |
283 | return 0; | |
284 | ||
c0365541 | 285 | for (i = 0; i < adev->uvd.max_handles; ++i) |
3f99dd81 LL |
286 | if (atomic_read(&adev->uvd.handles[i])) |
287 | break; | |
288 | ||
289 | if (i == AMDGPU_MAX_UVD_HANDLES) | |
290 | return 0; | |
291 | ||
85cc88f0 RZ |
292 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
293 | ||
3f99dd81 | 294 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
3f99dd81 | 295 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 296 | |
3f99dd81 LL |
297 | adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); |
298 | if (!adev->uvd.saved_bo) | |
299 | return -ENOMEM; | |
d38ceaf9 | 300 | |
3f99dd81 | 301 | memcpy(adev->uvd.saved_bo, ptr, size); |
d38ceaf9 AD |
302 | |
303 | return 0; | |
304 | } | |
305 | ||
306 | int amdgpu_uvd_resume(struct amdgpu_device *adev) | |
307 | { | |
308 | unsigned size; | |
309 | void *ptr; | |
d38ceaf9 AD |
310 | |
311 | if (adev->uvd.vcpu_bo == NULL) | |
312 | return -EINVAL; | |
313 | ||
d38ceaf9 | 314 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
d38ceaf9 | 315 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 316 | |
3f99dd81 LL |
317 | if (adev->uvd.saved_bo != NULL) { |
318 | memcpy(ptr, adev->uvd.saved_bo, size); | |
319 | kfree(adev->uvd.saved_bo); | |
320 | adev->uvd.saved_bo = NULL; | |
d23be4e3 LL |
321 | } else { |
322 | const struct common_firmware_header *hdr; | |
323 | unsigned offset; | |
324 | ||
325 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; | |
326 | offset = le32_to_cpu(hdr->ucode_array_offset_bytes); | |
327 | memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, | |
328 | (adev->uvd.fw->size) - offset); | |
329 | size -= le32_to_cpu(hdr->ucode_size_bytes); | |
330 | ptr += le32_to_cpu(hdr->ucode_size_bytes); | |
3f99dd81 | 331 | memset(ptr, 0, size); |
d23be4e3 | 332 | } |
d38ceaf9 AD |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
337 | void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) | |
338 | { | |
339 | struct amdgpu_ring *ring = &adev->uvd.ring; | |
340 | int i, r; | |
341 | ||
c0365541 | 342 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
343 | uint32_t handle = atomic_read(&adev->uvd.handles[i]); |
344 | if (handle != 0 && adev->uvd.filp[i] == filp) { | |
0e3f154a | 345 | struct fence *fence; |
d38ceaf9 | 346 | |
d7af97db CK |
347 | r = amdgpu_uvd_get_destroy_msg(ring, handle, |
348 | false, &fence); | |
d38ceaf9 AD |
349 | if (r) { |
350 | DRM_ERROR("Error destroying UVD (%d)!\n", r); | |
351 | continue; | |
352 | } | |
353 | ||
0e3f154a CZ |
354 | fence_wait(fence, false); |
355 | fence_put(fence); | |
d38ceaf9 AD |
356 | |
357 | adev->uvd.filp[i] = NULL; | |
358 | atomic_set(&adev->uvd.handles[i], 0); | |
359 | } | |
360 | } | |
361 | } | |
362 | ||
363 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) | |
364 | { | |
365 | int i; | |
366 | for (i = 0; i < rbo->placement.num_placement; ++i) { | |
367 | rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; | |
368 | rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; | |
369 | } | |
370 | } | |
371 | ||
372 | /** | |
373 | * amdgpu_uvd_cs_pass1 - first parsing round | |
374 | * | |
375 | * @ctx: UVD parser context | |
376 | * | |
377 | * Make sure UVD message and feedback buffers are in VRAM and | |
378 | * nobody is violating an 256MB boundary. | |
379 | */ | |
380 | static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) | |
381 | { | |
382 | struct amdgpu_bo_va_mapping *mapping; | |
383 | struct amdgpu_bo *bo; | |
384 | uint32_t cmd, lo, hi; | |
385 | uint64_t addr; | |
386 | int r = 0; | |
387 | ||
388 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
389 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
390 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
391 | ||
392 | mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); | |
393 | if (mapping == NULL) { | |
394 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); | |
395 | return -EINVAL; | |
396 | } | |
397 | ||
398 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
399 | /* check if it's a message or feedback command */ | |
400 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
401 | if (cmd == 0x0 || cmd == 0x3) { | |
402 | /* yes, force it into VRAM */ | |
403 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
404 | amdgpu_ttm_placement_from_domain(bo, domain); | |
405 | } | |
406 | amdgpu_uvd_force_into_uvd_segment(bo); | |
407 | ||
408 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | |
409 | } | |
410 | ||
411 | return r; | |
412 | } | |
413 | ||
414 | /** | |
415 | * amdgpu_uvd_cs_msg_decode - handle UVD decode message | |
416 | * | |
417 | * @msg: pointer to message structure | |
418 | * @buf_sizes: returned buffer sizes | |
419 | * | |
420 | * Peek into the decode message and calculate the necessary buffer sizes. | |
421 | */ | |
8e008dd7 SJ |
422 | static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, |
423 | unsigned buf_sizes[]) | |
d38ceaf9 AD |
424 | { |
425 | unsigned stream_type = msg[4]; | |
426 | unsigned width = msg[6]; | |
427 | unsigned height = msg[7]; | |
428 | unsigned dpb_size = msg[9]; | |
429 | unsigned pitch = msg[28]; | |
430 | unsigned level = msg[57]; | |
431 | ||
432 | unsigned width_in_mb = width / 16; | |
433 | unsigned height_in_mb = ALIGN(height / 16, 2); | |
434 | unsigned fs_in_mb = width_in_mb * height_in_mb; | |
435 | ||
21df89a5 | 436 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; |
e5a6858d | 437 | unsigned min_ctx_size = ~0; |
d38ceaf9 AD |
438 | |
439 | image_size = width * height; | |
440 | image_size += image_size / 2; | |
441 | image_size = ALIGN(image_size, 1024); | |
442 | ||
443 | switch (stream_type) { | |
444 | case 0: /* H264 */ | |
d38ceaf9 AD |
445 | switch(level) { |
446 | case 30: | |
447 | num_dpb_buffer = 8100 / fs_in_mb; | |
448 | break; | |
449 | case 31: | |
450 | num_dpb_buffer = 18000 / fs_in_mb; | |
451 | break; | |
452 | case 32: | |
453 | num_dpb_buffer = 20480 / fs_in_mb; | |
454 | break; | |
455 | case 41: | |
456 | num_dpb_buffer = 32768 / fs_in_mb; | |
457 | break; | |
458 | case 42: | |
459 | num_dpb_buffer = 34816 / fs_in_mb; | |
460 | break; | |
461 | case 50: | |
462 | num_dpb_buffer = 110400 / fs_in_mb; | |
463 | break; | |
464 | case 51: | |
465 | num_dpb_buffer = 184320 / fs_in_mb; | |
466 | break; | |
467 | default: | |
468 | num_dpb_buffer = 184320 / fs_in_mb; | |
469 | break; | |
470 | } | |
471 | num_dpb_buffer++; | |
472 | if (num_dpb_buffer > 17) | |
473 | num_dpb_buffer = 17; | |
474 | ||
475 | /* reference picture buffer */ | |
476 | min_dpb_size = image_size * num_dpb_buffer; | |
477 | ||
478 | /* macroblock context buffer */ | |
479 | min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
480 | ||
481 | /* IT surface buffer */ | |
482 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
483 | break; | |
484 | ||
485 | case 1: /* VC1 */ | |
486 | ||
487 | /* reference picture buffer */ | |
488 | min_dpb_size = image_size * 3; | |
489 | ||
490 | /* CONTEXT_BUFFER */ | |
491 | min_dpb_size += width_in_mb * height_in_mb * 128; | |
492 | ||
493 | /* IT surface buffer */ | |
494 | min_dpb_size += width_in_mb * 64; | |
495 | ||
496 | /* DB surface buffer */ | |
497 | min_dpb_size += width_in_mb * 128; | |
498 | ||
499 | /* BP */ | |
500 | tmp = max(width_in_mb, height_in_mb); | |
501 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); | |
502 | break; | |
503 | ||
504 | case 3: /* MPEG2 */ | |
505 | ||
506 | /* reference picture buffer */ | |
507 | min_dpb_size = image_size * 3; | |
508 | break; | |
509 | ||
510 | case 4: /* MPEG4 */ | |
511 | ||
512 | /* reference picture buffer */ | |
513 | min_dpb_size = image_size * 3; | |
514 | ||
515 | /* CM */ | |
516 | min_dpb_size += width_in_mb * height_in_mb * 64; | |
517 | ||
518 | /* IT surface buffer */ | |
519 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); | |
520 | break; | |
521 | ||
8e008dd7 SJ |
522 | case 7: /* H264 Perf */ |
523 | switch(level) { | |
524 | case 30: | |
525 | num_dpb_buffer = 8100 / fs_in_mb; | |
526 | break; | |
527 | case 31: | |
528 | num_dpb_buffer = 18000 / fs_in_mb; | |
529 | break; | |
530 | case 32: | |
531 | num_dpb_buffer = 20480 / fs_in_mb; | |
532 | break; | |
533 | case 41: | |
534 | num_dpb_buffer = 32768 / fs_in_mb; | |
535 | break; | |
536 | case 42: | |
537 | num_dpb_buffer = 34816 / fs_in_mb; | |
538 | break; | |
539 | case 50: | |
540 | num_dpb_buffer = 110400 / fs_in_mb; | |
541 | break; | |
542 | case 51: | |
543 | num_dpb_buffer = 184320 / fs_in_mb; | |
544 | break; | |
545 | default: | |
546 | num_dpb_buffer = 184320 / fs_in_mb; | |
547 | break; | |
548 | } | |
549 | num_dpb_buffer++; | |
550 | if (num_dpb_buffer > 17) | |
551 | num_dpb_buffer = 17; | |
552 | ||
553 | /* reference picture buffer */ | |
554 | min_dpb_size = image_size * num_dpb_buffer; | |
555 | ||
4cb5877c | 556 | if (!adev->uvd.use_ctx_buf){ |
8e008dd7 SJ |
557 | /* macroblock context buffer */ |
558 | min_dpb_size += | |
559 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
560 | ||
561 | /* IT surface buffer */ | |
562 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
563 | } else { | |
564 | /* macroblock context buffer */ | |
565 | min_ctx_size = | |
566 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
567 | } | |
568 | break; | |
569 | ||
86fa0bdc CK |
570 | case 16: /* H265 */ |
571 | image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; | |
572 | image_size = ALIGN(image_size, 256); | |
573 | ||
574 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; | |
575 | min_dpb_size = image_size * num_dpb_buffer; | |
8c8bac59 BZ |
576 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) |
577 | * 16 * num_dpb_buffer + 52 * 1024; | |
86fa0bdc CK |
578 | break; |
579 | ||
d38ceaf9 AD |
580 | default: |
581 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); | |
582 | return -EINVAL; | |
583 | } | |
584 | ||
585 | if (width > pitch) { | |
586 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); | |
587 | return -EINVAL; | |
588 | } | |
589 | ||
590 | if (dpb_size < min_dpb_size) { | |
591 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", | |
592 | dpb_size, min_dpb_size); | |
593 | return -EINVAL; | |
594 | } | |
595 | ||
596 | buf_sizes[0x1] = dpb_size; | |
597 | buf_sizes[0x2] = image_size; | |
8c8bac59 | 598 | buf_sizes[0x4] = min_ctx_size; |
d38ceaf9 AD |
599 | return 0; |
600 | } | |
601 | ||
602 | /** | |
603 | * amdgpu_uvd_cs_msg - handle UVD message | |
604 | * | |
605 | * @ctx: UVD parser context | |
606 | * @bo: buffer object containing the message | |
607 | * @offset: offset into the buffer object | |
608 | * | |
609 | * Peek into the UVD message and extract the session id. | |
610 | * Make sure that we don't open up to many sessions. | |
611 | */ | |
612 | static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, | |
613 | struct amdgpu_bo *bo, unsigned offset) | |
614 | { | |
615 | struct amdgpu_device *adev = ctx->parser->adev; | |
616 | int32_t *msg, msg_type, handle; | |
d38ceaf9 | 617 | void *ptr; |
4127a59e CK |
618 | long r; |
619 | int i; | |
d38ceaf9 AD |
620 | |
621 | if (offset & 0x3F) { | |
622 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
d38ceaf9 AD |
626 | r = amdgpu_bo_kmap(bo, &ptr); |
627 | if (r) { | |
4127a59e | 628 | DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); |
d38ceaf9 AD |
629 | return r; |
630 | } | |
631 | ||
632 | msg = ptr + offset; | |
633 | ||
634 | msg_type = msg[1]; | |
635 | handle = msg[2]; | |
636 | ||
637 | if (handle == 0) { | |
638 | DRM_ERROR("Invalid UVD handle!\n"); | |
639 | return -EINVAL; | |
640 | } | |
641 | ||
5146419e LL |
642 | switch (msg_type) { |
643 | case 0: | |
644 | /* it's a create msg, calc image size (width * height) */ | |
645 | amdgpu_bo_kunmap(bo); | |
646 | ||
647 | /* try to alloc a new handle */ | |
c0365541 | 648 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
649 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
650 | DRM_ERROR("Handle 0x%x already in use!\n", handle); | |
651 | return -EINVAL; | |
652 | } | |
653 | ||
654 | if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { | |
655 | adev->uvd.filp[i] = ctx->parser->filp; | |
656 | return 0; | |
657 | } | |
658 | } | |
659 | ||
660 | DRM_ERROR("No more free UVD handles!\n"); | |
7129d3ae | 661 | return -ENOSPC; |
5146419e LL |
662 | |
663 | case 1: | |
d38ceaf9 | 664 | /* it's a decode msg, calc buffer sizes */ |
8e008dd7 | 665 | r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); |
d38ceaf9 AD |
666 | amdgpu_bo_kunmap(bo); |
667 | if (r) | |
668 | return r; | |
669 | ||
5146419e | 670 | /* validate the handle */ |
c0365541 | 671 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
672 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
673 | if (adev->uvd.filp[i] != ctx->parser->filp) { | |
674 | DRM_ERROR("UVD handle collision detected!\n"); | |
675 | return -EINVAL; | |
676 | } | |
677 | return 0; | |
678 | } | |
679 | } | |
680 | ||
681 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); | |
682 | return -ENOENT; | |
683 | ||
684 | case 2: | |
d38ceaf9 | 685 | /* it's a destroy msg, free the handle */ |
c0365541 | 686 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
687 | atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); |
688 | amdgpu_bo_kunmap(bo); | |
689 | return 0; | |
d38ceaf9 | 690 | |
5146419e LL |
691 | default: |
692 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); | |
693 | return -EINVAL; | |
d38ceaf9 | 694 | } |
5146419e | 695 | BUG(); |
d38ceaf9 AD |
696 | return -EINVAL; |
697 | } | |
698 | ||
699 | /** | |
700 | * amdgpu_uvd_cs_pass2 - second parsing round | |
701 | * | |
702 | * @ctx: UVD parser context | |
703 | * | |
704 | * Patch buffer addresses, make sure buffer sizes are correct. | |
705 | */ | |
706 | static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) | |
707 | { | |
708 | struct amdgpu_bo_va_mapping *mapping; | |
709 | struct amdgpu_bo *bo; | |
d38ceaf9 AD |
710 | uint32_t cmd, lo, hi; |
711 | uint64_t start, end; | |
712 | uint64_t addr; | |
713 | int r; | |
714 | ||
715 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
716 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
717 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
718 | ||
719 | mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); | |
720 | if (mapping == NULL) | |
721 | return -EINVAL; | |
722 | ||
723 | start = amdgpu_bo_gpu_offset(bo); | |
724 | ||
725 | end = (mapping->it.last + 1 - mapping->it.start); | |
726 | end = end * AMDGPU_GPU_PAGE_SIZE + start; | |
727 | ||
728 | addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; | |
729 | start += addr; | |
730 | ||
7270f839 CK |
731 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, |
732 | lower_32_bits(start)); | |
733 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, | |
734 | upper_32_bits(start)); | |
d38ceaf9 AD |
735 | |
736 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
737 | if (cmd < 0x4) { | |
738 | if ((end - start) < ctx->buf_sizes[cmd]) { | |
739 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
740 | (unsigned)(end - start), | |
741 | ctx->buf_sizes[cmd]); | |
742 | return -EINVAL; | |
743 | } | |
744 | ||
8c8bac59 BZ |
745 | } else if (cmd == 0x206) { |
746 | if ((end - start) < ctx->buf_sizes[4]) { | |
747 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
748 | (unsigned)(end - start), | |
749 | ctx->buf_sizes[4]); | |
750 | return -EINVAL; | |
751 | } | |
d38ceaf9 AD |
752 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
753 | DRM_ERROR("invalid UVD command %X!\n", cmd); | |
754 | return -EINVAL; | |
755 | } | |
756 | ||
757 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
758 | if ((start >> 28) != ((end - 1) >> 28)) { | |
759 | DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", | |
760 | start, end); | |
761 | return -EINVAL; | |
762 | } | |
763 | ||
764 | if ((cmd == 0 || cmd == 0x3) && | |
765 | (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { | |
766 | DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", | |
767 | start, end); | |
768 | return -EINVAL; | |
769 | } | |
770 | } | |
771 | ||
772 | if (cmd == 0) { | |
773 | ctx->has_msg_cmd = true; | |
774 | r = amdgpu_uvd_cs_msg(ctx, bo, addr); | |
775 | if (r) | |
776 | return r; | |
777 | } else if (!ctx->has_msg_cmd) { | |
778 | DRM_ERROR("Message needed before other commands are send!\n"); | |
779 | return -EINVAL; | |
780 | } | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | /** | |
786 | * amdgpu_uvd_cs_reg - parse register writes | |
787 | * | |
788 | * @ctx: UVD parser context | |
789 | * @cb: callback function | |
790 | * | |
791 | * Parse the register writes, call cb on each complete command. | |
792 | */ | |
793 | static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, | |
794 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
795 | { | |
50838c8c | 796 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
797 | int i, r; |
798 | ||
799 | ctx->idx++; | |
800 | for (i = 0; i <= ctx->count; ++i) { | |
801 | unsigned reg = ctx->reg + i; | |
802 | ||
803 | if (ctx->idx >= ib->length_dw) { | |
804 | DRM_ERROR("Register command after end of CS!\n"); | |
805 | return -EINVAL; | |
806 | } | |
807 | ||
808 | switch (reg) { | |
809 | case mmUVD_GPCOM_VCPU_DATA0: | |
810 | ctx->data0 = ctx->idx; | |
811 | break; | |
812 | case mmUVD_GPCOM_VCPU_DATA1: | |
813 | ctx->data1 = ctx->idx; | |
814 | break; | |
815 | case mmUVD_GPCOM_VCPU_CMD: | |
816 | r = cb(ctx); | |
817 | if (r) | |
818 | return r; | |
819 | break; | |
820 | case mmUVD_ENGINE_CNTL: | |
821 | break; | |
822 | default: | |
823 | DRM_ERROR("Invalid reg 0x%X!\n", reg); | |
824 | return -EINVAL; | |
825 | } | |
826 | ctx->idx++; | |
827 | } | |
828 | return 0; | |
829 | } | |
830 | ||
831 | /** | |
832 | * amdgpu_uvd_cs_packets - parse UVD packets | |
833 | * | |
834 | * @ctx: UVD parser context | |
835 | * @cb: callback function | |
836 | * | |
837 | * Parse the command stream packets. | |
838 | */ | |
839 | static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, | |
840 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
841 | { | |
50838c8c | 842 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
843 | int r; |
844 | ||
845 | for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { | |
846 | uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); | |
847 | unsigned type = CP_PACKET_GET_TYPE(cmd); | |
848 | switch (type) { | |
849 | case PACKET_TYPE0: | |
850 | ctx->reg = CP_PACKET0_GET_REG(cmd); | |
851 | ctx->count = CP_PACKET_GET_COUNT(cmd); | |
852 | r = amdgpu_uvd_cs_reg(ctx, cb); | |
853 | if (r) | |
854 | return r; | |
855 | break; | |
856 | case PACKET_TYPE2: | |
857 | ++ctx->idx; | |
858 | break; | |
859 | default: | |
860 | DRM_ERROR("Unknown packet type %d !\n", type); | |
861 | return -EINVAL; | |
862 | } | |
863 | } | |
864 | return 0; | |
865 | } | |
866 | ||
867 | /** | |
868 | * amdgpu_uvd_ring_parse_cs - UVD command submission parser | |
869 | * | |
870 | * @parser: Command submission parser context | |
871 | * | |
872 | * Parse the command stream, patch in addresses as necessary. | |
873 | */ | |
874 | int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) | |
875 | { | |
876 | struct amdgpu_uvd_cs_ctx ctx = {}; | |
877 | unsigned buf_sizes[] = { | |
878 | [0x00000000] = 2048, | |
8c8bac59 BZ |
879 | [0x00000001] = 0xFFFFFFFF, |
880 | [0x00000002] = 0xFFFFFFFF, | |
d38ceaf9 | 881 | [0x00000003] = 2048, |
8c8bac59 | 882 | [0x00000004] = 0xFFFFFFFF, |
d38ceaf9 | 883 | }; |
50838c8c | 884 | struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; |
d38ceaf9 AD |
885 | int r; |
886 | ||
887 | if (ib->length_dw % 16) { | |
888 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", | |
889 | ib->length_dw); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
893 | ctx.parser = parser; | |
894 | ctx.buf_sizes = buf_sizes; | |
895 | ctx.ib_idx = ib_idx; | |
896 | ||
897 | /* first round, make sure the buffers are actually in the UVD segment */ | |
898 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); | |
899 | if (r) | |
900 | return r; | |
901 | ||
902 | /* second round, patch buffer addresses into the command stream */ | |
903 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); | |
904 | if (r) | |
905 | return r; | |
906 | ||
907 | if (!ctx.has_msg_cmd) { | |
908 | DRM_ERROR("UVD-IBs need a msg command!\n"); | |
909 | return -EINVAL; | |
910 | } | |
911 | ||
d38ceaf9 AD |
912 | return 0; |
913 | } | |
914 | ||
d7af97db CK |
915 | static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, |
916 | bool direct, struct fence **fence) | |
d38ceaf9 AD |
917 | { |
918 | struct ttm_validate_buffer tv; | |
919 | struct ww_acquire_ctx ticket; | |
920 | struct list_head head; | |
d71518b5 CK |
921 | struct amdgpu_job *job; |
922 | struct amdgpu_ib *ib; | |
1763552e | 923 | struct fence *f = NULL; |
7b5ec431 | 924 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 AD |
925 | uint64_t addr; |
926 | int i, r; | |
927 | ||
928 | memset(&tv, 0, sizeof(tv)); | |
929 | tv.bo = &bo->tbo; | |
930 | ||
931 | INIT_LIST_HEAD(&head); | |
932 | list_add(&tv.head, &head); | |
933 | ||
934 | r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); | |
935 | if (r) | |
936 | return r; | |
937 | ||
938 | if (!bo->adev->uvd.address_64_bit) { | |
939 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); | |
940 | amdgpu_uvd_force_into_uvd_segment(bo); | |
941 | } | |
942 | ||
943 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
944 | if (r) | |
945 | goto err; | |
d71518b5 CK |
946 | |
947 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); | |
7b5ec431 | 948 | if (r) |
d71518b5 | 949 | goto err; |
d38ceaf9 | 950 | |
d71518b5 | 951 | ib = &job->ibs[0]; |
d38ceaf9 | 952 | addr = amdgpu_bo_gpu_offset(bo); |
7b5ec431 CZ |
953 | ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); |
954 | ib->ptr[1] = addr; | |
955 | ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); | |
956 | ib->ptr[3] = addr >> 32; | |
957 | ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); | |
958 | ib->ptr[5] = 0; | |
d38ceaf9 | 959 | for (i = 6; i < 16; ++i) |
7b5ec431 CZ |
960 | ib->ptr[i] = PACKET2(0); |
961 | ib->length_dw = 16; | |
d38ceaf9 | 962 | |
d7af97db | 963 | if (direct) { |
c5637837 | 964 | r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); |
22a77cf6 | 965 | job->fence = fence_get(f); |
d7af97db CK |
966 | if (r) |
967 | goto err_free; | |
968 | ||
969 | amdgpu_job_free(job); | |
970 | } else { | |
ead833ec | 971 | r = amdgpu_job_submit(job, ring, &adev->uvd.entity, |
d7af97db CK |
972 | AMDGPU_FENCE_OWNER_UNDEFINED, &f); |
973 | if (r) | |
974 | goto err_free; | |
975 | } | |
d38ceaf9 | 976 | |
1763552e | 977 | ttm_eu_fence_buffer_objects(&ticket, &head, f); |
d38ceaf9 | 978 | |
7b5ec431 | 979 | if (fence) |
1763552e | 980 | *fence = fence_get(f); |
d38ceaf9 | 981 | amdgpu_bo_unref(&bo); |
281b4223 | 982 | fence_put(f); |
7b5ec431 | 983 | |
7b5ec431 | 984 | return 0; |
d71518b5 CK |
985 | |
986 | err_free: | |
987 | amdgpu_job_free(job); | |
988 | ||
d38ceaf9 AD |
989 | err: |
990 | ttm_eu_backoff_reservation(&ticket, &head); | |
991 | return r; | |
992 | } | |
993 | ||
994 | /* multiple fence commands without any stream commands in between can | |
995 | crash the vcpu so just try to emmit a dummy create/destroy msg to | |
996 | avoid this */ | |
997 | int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, | |
0e3f154a | 998 | struct fence **fence) |
d38ceaf9 AD |
999 | { |
1000 | struct amdgpu_device *adev = ring->adev; | |
1001 | struct amdgpu_bo *bo; | |
1002 | uint32_t *msg; | |
1003 | int r, i; | |
1004 | ||
1005 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d AD |
1006 | AMDGPU_GEM_DOMAIN_VRAM, |
1007 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1008 | NULL, NULL, &bo); |
d38ceaf9 AD |
1009 | if (r) |
1010 | return r; | |
1011 | ||
1012 | r = amdgpu_bo_reserve(bo, false); | |
1013 | if (r) { | |
1014 | amdgpu_bo_unref(&bo); | |
1015 | return r; | |
1016 | } | |
1017 | ||
1018 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1019 | if (r) { | |
1020 | amdgpu_bo_unreserve(bo); | |
1021 | amdgpu_bo_unref(&bo); | |
1022 | return r; | |
1023 | } | |
1024 | ||
1025 | /* stitch together an UVD create msg */ | |
1026 | msg[0] = cpu_to_le32(0x00000de4); | |
1027 | msg[1] = cpu_to_le32(0x00000000); | |
1028 | msg[2] = cpu_to_le32(handle); | |
1029 | msg[3] = cpu_to_le32(0x00000000); | |
1030 | msg[4] = cpu_to_le32(0x00000000); | |
1031 | msg[5] = cpu_to_le32(0x00000000); | |
1032 | msg[6] = cpu_to_le32(0x00000000); | |
1033 | msg[7] = cpu_to_le32(0x00000780); | |
1034 | msg[8] = cpu_to_le32(0x00000440); | |
1035 | msg[9] = cpu_to_le32(0x00000000); | |
1036 | msg[10] = cpu_to_le32(0x01b37000); | |
1037 | for (i = 11; i < 1024; ++i) | |
1038 | msg[i] = cpu_to_le32(0x0); | |
1039 | ||
1040 | amdgpu_bo_kunmap(bo); | |
1041 | amdgpu_bo_unreserve(bo); | |
1042 | ||
d7af97db | 1043 | return amdgpu_uvd_send_msg(ring, bo, true, fence); |
d38ceaf9 AD |
1044 | } |
1045 | ||
1046 | int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |
d7af97db | 1047 | bool direct, struct fence **fence) |
d38ceaf9 AD |
1048 | { |
1049 | struct amdgpu_device *adev = ring->adev; | |
1050 | struct amdgpu_bo *bo; | |
1051 | uint32_t *msg; | |
1052 | int r, i; | |
1053 | ||
1054 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d AD |
1055 | AMDGPU_GEM_DOMAIN_VRAM, |
1056 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1057 | NULL, NULL, &bo); |
d38ceaf9 AD |
1058 | if (r) |
1059 | return r; | |
1060 | ||
1061 | r = amdgpu_bo_reserve(bo, false); | |
1062 | if (r) { | |
1063 | amdgpu_bo_unref(&bo); | |
1064 | return r; | |
1065 | } | |
1066 | ||
1067 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1068 | if (r) { | |
1069 | amdgpu_bo_unreserve(bo); | |
1070 | amdgpu_bo_unref(&bo); | |
1071 | return r; | |
1072 | } | |
1073 | ||
1074 | /* stitch together an UVD destroy msg */ | |
1075 | msg[0] = cpu_to_le32(0x00000de4); | |
1076 | msg[1] = cpu_to_le32(0x00000002); | |
1077 | msg[2] = cpu_to_le32(handle); | |
1078 | msg[3] = cpu_to_le32(0x00000000); | |
1079 | for (i = 4; i < 1024; ++i) | |
1080 | msg[i] = cpu_to_le32(0x0); | |
1081 | ||
1082 | amdgpu_bo_kunmap(bo); | |
1083 | amdgpu_bo_unreserve(bo); | |
1084 | ||
d7af97db | 1085 | return amdgpu_uvd_send_msg(ring, bo, direct, fence); |
d38ceaf9 AD |
1086 | } |
1087 | ||
1088 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |
1089 | { | |
1090 | struct amdgpu_device *adev = | |
1091 | container_of(work, struct amdgpu_device, uvd.idle_work.work); | |
1092 | unsigned i, fences, handles = 0; | |
1093 | ||
1094 | fences = amdgpu_fence_count_emitted(&adev->uvd.ring); | |
1095 | ||
c0365541 | 1096 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
1097 | if (atomic_read(&adev->uvd.handles[i])) |
1098 | ++handles; | |
1099 | ||
1100 | if (fences == 0 && handles == 0) { | |
1101 | if (adev->pm.dpm_enabled) { | |
1102 | amdgpu_dpm_enable_uvd(adev, false); | |
1103 | } else { | |
1104 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
1105 | } | |
1106 | } else { | |
08086635 | 1107 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
d38ceaf9 AD |
1108 | } |
1109 | } | |
1110 | ||
c4120d55 | 1111 | void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) |
d38ceaf9 | 1112 | { |
c4120d55 | 1113 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 | 1114 | bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); |
d38ceaf9 AD |
1115 | |
1116 | if (set_clocks) { | |
1117 | if (adev->pm.dpm_enabled) { | |
1118 | amdgpu_dpm_enable_uvd(adev, true); | |
1119 | } else { | |
1120 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
1121 | } | |
1122 | } | |
1123 | } | |
c4120d55 CK |
1124 | |
1125 | void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) | |
1126 | { | |
1127 | schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); | |
1128 | } | |
8de190c9 CK |
1129 | |
1130 | /** | |
1131 | * amdgpu_uvd_ring_test_ib - test ib execution | |
1132 | * | |
1133 | * @ring: amdgpu_ring pointer | |
1134 | * | |
1135 | * Test if we can successfully execute an IB | |
1136 | */ | |
bbec97aa | 1137 | int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
8de190c9 | 1138 | { |
bbec97aa CK |
1139 | struct fence *fence; |
1140 | long r; | |
8de190c9 CK |
1141 | |
1142 | r = amdgpu_uvd_get_create_msg(ring, 1, NULL); | |
1143 | if (r) { | |
bbec97aa | 1144 | DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); |
8de190c9 CK |
1145 | goto error; |
1146 | } | |
1147 | ||
1148 | r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); | |
1149 | if (r) { | |
bbec97aa | 1150 | DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); |
8de190c9 CK |
1151 | goto error; |
1152 | } | |
1153 | ||
bbec97aa CK |
1154 | r = fence_wait_timeout(fence, false, timeout); |
1155 | if (r == 0) { | |
1156 | DRM_ERROR("amdgpu: IB test timed out.\n"); | |
1157 | r = -ETIMEDOUT; | |
1158 | } else if (r < 0) { | |
1159 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); | |
1160 | } else { | |
1161 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); | |
1162 | r = 0; | |
8de190c9 | 1163 | } |
bbec97aa | 1164 | |
8de190c9 CK |
1165 | error: |
1166 | fence_put(fence); | |
1167 | return r; | |
1168 | } |