Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <deathsimple@vodafone.de> | |
29 | */ | |
30 | ||
31 | #include <linux/firmware.h> | |
32 | #include <linux/module.h> | |
33 | #include <drm/drmP.h> | |
34 | #include <drm/drm.h> | |
35 | ||
36 | #include "amdgpu.h" | |
37 | #include "amdgpu_pm.h" | |
38 | #include "amdgpu_uvd.h" | |
39 | #include "cikd.h" | |
40 | #include "uvd/uvd_4_2_d.h" | |
41 | ||
42 | /* 1 second timeout */ | |
08086635 | 43 | #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) |
8e008dd7 SJ |
44 | /* Polaris10/11 firmware version */ |
45 | #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) | |
d38ceaf9 AD |
46 | |
47 | /* Firmware Names */ | |
48 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
49 | #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" | |
edf600da CK |
50 | #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" |
51 | #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" | |
52 | #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" | |
d38ceaf9 AD |
53 | #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" |
54 | #endif | |
c65444fe JZ |
55 | #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" |
56 | #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" | |
974ee3db | 57 | #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" |
a39c8cea | 58 | #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" |
2cc0c0b5 | 59 | #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" |
925a51c4 | 60 | #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" |
d38ceaf9 AD |
61 | |
62 | /** | |
63 | * amdgpu_uvd_cs_ctx - Command submission parser context | |
64 | * | |
65 | * Used for emulating virtual memory support on UVD 4.2. | |
66 | */ | |
67 | struct amdgpu_uvd_cs_ctx { | |
68 | struct amdgpu_cs_parser *parser; | |
69 | unsigned reg, count; | |
70 | unsigned data0, data1; | |
71 | unsigned idx; | |
72 | unsigned ib_idx; | |
73 | ||
74 | /* does the IB has a msg command */ | |
75 | bool has_msg_cmd; | |
76 | ||
77 | /* minimum buffer sizes */ | |
78 | unsigned *buf_sizes; | |
79 | }; | |
80 | ||
81 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
82 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); | |
83 | MODULE_FIRMWARE(FIRMWARE_KABINI); | |
84 | MODULE_FIRMWARE(FIRMWARE_KAVERI); | |
85 | MODULE_FIRMWARE(FIRMWARE_HAWAII); | |
86 | MODULE_FIRMWARE(FIRMWARE_MULLINS); | |
87 | #endif | |
88 | MODULE_FIRMWARE(FIRMWARE_TONGA); | |
89 | MODULE_FIRMWARE(FIRMWARE_CARRIZO); | |
974ee3db | 90 | MODULE_FIRMWARE(FIRMWARE_FIJI); |
a39c8cea | 91 | MODULE_FIRMWARE(FIRMWARE_STONEY); |
2cc0c0b5 FC |
92 | MODULE_FIRMWARE(FIRMWARE_POLARIS10); |
93 | MODULE_FIRMWARE(FIRMWARE_POLARIS11); | |
d38ceaf9 | 94 | |
d38ceaf9 AD |
95 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work); |
96 | ||
97 | int amdgpu_uvd_sw_init(struct amdgpu_device *adev) | |
98 | { | |
ead833ec CK |
99 | struct amdgpu_ring *ring; |
100 | struct amd_sched_rq *rq; | |
d38ceaf9 AD |
101 | unsigned long bo_size; |
102 | const char *fw_name; | |
103 | const struct common_firmware_header *hdr; | |
104 | unsigned version_major, version_minor, family_id; | |
105 | int i, r; | |
106 | ||
107 | INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); | |
108 | ||
109 | switch (adev->asic_type) { | |
110 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
111 | case CHIP_BONAIRE: | |
112 | fw_name = FIRMWARE_BONAIRE; | |
113 | break; | |
114 | case CHIP_KABINI: | |
115 | fw_name = FIRMWARE_KABINI; | |
116 | break; | |
117 | case CHIP_KAVERI: | |
118 | fw_name = FIRMWARE_KAVERI; | |
119 | break; | |
120 | case CHIP_HAWAII: | |
121 | fw_name = FIRMWARE_HAWAII; | |
122 | break; | |
123 | case CHIP_MULLINS: | |
124 | fw_name = FIRMWARE_MULLINS; | |
125 | break; | |
126 | #endif | |
127 | case CHIP_TONGA: | |
128 | fw_name = FIRMWARE_TONGA; | |
129 | break; | |
974ee3db DZ |
130 | case CHIP_FIJI: |
131 | fw_name = FIRMWARE_FIJI; | |
132 | break; | |
d38ceaf9 AD |
133 | case CHIP_CARRIZO: |
134 | fw_name = FIRMWARE_CARRIZO; | |
135 | break; | |
a39c8cea SL |
136 | case CHIP_STONEY: |
137 | fw_name = FIRMWARE_STONEY; | |
138 | break; | |
2cc0c0b5 FC |
139 | case CHIP_POLARIS10: |
140 | fw_name = FIRMWARE_POLARIS10; | |
38d75817 | 141 | break; |
2cc0c0b5 FC |
142 | case CHIP_POLARIS11: |
143 | fw_name = FIRMWARE_POLARIS11; | |
38d75817 | 144 | break; |
d38ceaf9 AD |
145 | default: |
146 | return -EINVAL; | |
147 | } | |
148 | ||
149 | r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); | |
150 | if (r) { | |
151 | dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", | |
152 | fw_name); | |
153 | return r; | |
154 | } | |
155 | ||
156 | r = amdgpu_ucode_validate(adev->uvd.fw); | |
157 | if (r) { | |
158 | dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", | |
159 | fw_name); | |
160 | release_firmware(adev->uvd.fw); | |
161 | adev->uvd.fw = NULL; | |
162 | return r; | |
163 | } | |
164 | ||
c0365541 AN |
165 | /* Set the default UVD handles that the firmware can handle */ |
166 | adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; | |
167 | ||
d38ceaf9 AD |
168 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
169 | family_id = le32_to_cpu(hdr->ucode_version) & 0xff; | |
170 | version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; | |
171 | version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; | |
172 | DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", | |
173 | version_major, version_minor, family_id); | |
174 | ||
c0365541 AN |
175 | /* |
176 | * Limit the number of UVD handles depending on microcode major | |
177 | * and minor versions. The firmware version which has 40 UVD | |
178 | * instances support is 1.80. So all subsequent versions should | |
179 | * also have the same support. | |
180 | */ | |
181 | if ((version_major > 0x01) || | |
182 | ((version_major == 0x01) && (version_minor >= 0x50))) | |
183 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; | |
184 | ||
562e2689 SJ |
185 | adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | |
186 | (family_id << 8)); | |
187 | ||
8e008dd7 SJ |
188 | if ((adev->asic_type == CHIP_POLARIS10 || |
189 | adev->asic_type == CHIP_POLARIS11) && | |
190 | (adev->uvd.fw_version < FW_1_66_16)) | |
191 | DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", | |
192 | version_major, version_minor); | |
193 | ||
d38ceaf9 | 194 | bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) |
c0365541 AN |
195 | + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE |
196 | + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; | |
d38ceaf9 | 197 | r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, |
857d913d AD |
198 | AMDGPU_GEM_DOMAIN_VRAM, |
199 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 200 | NULL, NULL, &adev->uvd.vcpu_bo); |
d38ceaf9 AD |
201 | if (r) { |
202 | dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); | |
203 | return r; | |
204 | } | |
205 | ||
206 | r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); | |
207 | if (r) { | |
208 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); | |
209 | dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); | |
210 | return r; | |
211 | } | |
212 | ||
213 | r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, | |
214 | &adev->uvd.gpu_addr); | |
215 | if (r) { | |
216 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
217 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); | |
218 | dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); | |
219 | return r; | |
220 | } | |
221 | ||
222 | r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); | |
223 | if (r) { | |
224 | dev_err(adev->dev, "(%d) UVD map failed\n", r); | |
225 | return r; | |
226 | } | |
227 | ||
228 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
229 | ||
ead833ec CK |
230 | ring = &adev->uvd.ring; |
231 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; | |
232 | r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, | |
233 | rq, amdgpu_sched_jobs); | |
234 | if (r != 0) { | |
235 | DRM_ERROR("Failed setting up UVD run queue.\n"); | |
236 | return r; | |
237 | } | |
238 | ||
c0365541 | 239 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
240 | atomic_set(&adev->uvd.handles[i], 0); |
241 | adev->uvd.filp[i] = NULL; | |
242 | } | |
243 | ||
244 | /* from uvd v5.0 HW addressing capacity increased to 64 bits */ | |
5fc3aeeb | 245 | if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) |
d38ceaf9 AD |
246 | adev->uvd.address_64_bit = true; |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
251 | int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) | |
252 | { | |
253 | int r; | |
254 | ||
05f19eb5 | 255 | kfree(adev->uvd.saved_bo); |
d38ceaf9 | 256 | |
ead833ec CK |
257 | amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); |
258 | ||
05f19eb5 ML |
259 | if (adev->uvd.vcpu_bo) { |
260 | r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); | |
261 | if (!r) { | |
262 | amdgpu_bo_kunmap(adev->uvd.vcpu_bo); | |
263 | amdgpu_bo_unpin(adev->uvd.vcpu_bo); | |
264 | amdgpu_bo_unreserve(adev->uvd.vcpu_bo); | |
265 | } | |
d38ceaf9 | 266 | |
05f19eb5 ML |
267 | amdgpu_bo_unref(&adev->uvd.vcpu_bo); |
268 | } | |
d38ceaf9 AD |
269 | |
270 | amdgpu_ring_fini(&adev->uvd.ring); | |
271 | ||
272 | release_firmware(adev->uvd.fw); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | int amdgpu_uvd_suspend(struct amdgpu_device *adev) | |
278 | { | |
3f99dd81 LL |
279 | unsigned size; |
280 | void *ptr; | |
3f99dd81 | 281 | int i; |
d38ceaf9 AD |
282 | |
283 | if (adev->uvd.vcpu_bo == NULL) | |
284 | return 0; | |
285 | ||
c0365541 | 286 | for (i = 0; i < adev->uvd.max_handles; ++i) |
3f99dd81 LL |
287 | if (atomic_read(&adev->uvd.handles[i])) |
288 | break; | |
289 | ||
290 | if (i == AMDGPU_MAX_UVD_HANDLES) | |
291 | return 0; | |
292 | ||
85cc88f0 RZ |
293 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
294 | ||
3f99dd81 | 295 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
3f99dd81 | 296 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 297 | |
3f99dd81 LL |
298 | adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); |
299 | if (!adev->uvd.saved_bo) | |
300 | return -ENOMEM; | |
d38ceaf9 | 301 | |
3f99dd81 | 302 | memcpy(adev->uvd.saved_bo, ptr, size); |
d38ceaf9 AD |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
307 | int amdgpu_uvd_resume(struct amdgpu_device *adev) | |
308 | { | |
309 | unsigned size; | |
310 | void *ptr; | |
d38ceaf9 AD |
311 | |
312 | if (adev->uvd.vcpu_bo == NULL) | |
313 | return -EINVAL; | |
314 | ||
d38ceaf9 | 315 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
d38ceaf9 | 316 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 317 | |
3f99dd81 LL |
318 | if (adev->uvd.saved_bo != NULL) { |
319 | memcpy(ptr, adev->uvd.saved_bo, size); | |
320 | kfree(adev->uvd.saved_bo); | |
321 | adev->uvd.saved_bo = NULL; | |
d23be4e3 LL |
322 | } else { |
323 | const struct common_firmware_header *hdr; | |
324 | unsigned offset; | |
325 | ||
326 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; | |
327 | offset = le32_to_cpu(hdr->ucode_array_offset_bytes); | |
328 | memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, | |
329 | (adev->uvd.fw->size) - offset); | |
330 | size -= le32_to_cpu(hdr->ucode_size_bytes); | |
331 | ptr += le32_to_cpu(hdr->ucode_size_bytes); | |
3f99dd81 | 332 | memset(ptr, 0, size); |
d23be4e3 | 333 | } |
d38ceaf9 AD |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
338 | void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) | |
339 | { | |
340 | struct amdgpu_ring *ring = &adev->uvd.ring; | |
341 | int i, r; | |
342 | ||
c0365541 | 343 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
344 | uint32_t handle = atomic_read(&adev->uvd.handles[i]); |
345 | if (handle != 0 && adev->uvd.filp[i] == filp) { | |
0e3f154a | 346 | struct fence *fence; |
d38ceaf9 | 347 | |
d7af97db CK |
348 | r = amdgpu_uvd_get_destroy_msg(ring, handle, |
349 | false, &fence); | |
d38ceaf9 AD |
350 | if (r) { |
351 | DRM_ERROR("Error destroying UVD (%d)!\n", r); | |
352 | continue; | |
353 | } | |
354 | ||
0e3f154a CZ |
355 | fence_wait(fence, false); |
356 | fence_put(fence); | |
d38ceaf9 AD |
357 | |
358 | adev->uvd.filp[i] = NULL; | |
359 | atomic_set(&adev->uvd.handles[i], 0); | |
360 | } | |
361 | } | |
362 | } | |
363 | ||
364 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) | |
365 | { | |
366 | int i; | |
367 | for (i = 0; i < rbo->placement.num_placement; ++i) { | |
368 | rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; | |
369 | rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; | |
370 | } | |
371 | } | |
372 | ||
373 | /** | |
374 | * amdgpu_uvd_cs_pass1 - first parsing round | |
375 | * | |
376 | * @ctx: UVD parser context | |
377 | * | |
378 | * Make sure UVD message and feedback buffers are in VRAM and | |
379 | * nobody is violating an 256MB boundary. | |
380 | */ | |
381 | static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) | |
382 | { | |
383 | struct amdgpu_bo_va_mapping *mapping; | |
384 | struct amdgpu_bo *bo; | |
385 | uint32_t cmd, lo, hi; | |
386 | uint64_t addr; | |
387 | int r = 0; | |
388 | ||
389 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
390 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
391 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
392 | ||
393 | mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); | |
394 | if (mapping == NULL) { | |
395 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); | |
396 | return -EINVAL; | |
397 | } | |
398 | ||
399 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
400 | /* check if it's a message or feedback command */ | |
401 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
402 | if (cmd == 0x0 || cmd == 0x3) { | |
403 | /* yes, force it into VRAM */ | |
404 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
405 | amdgpu_ttm_placement_from_domain(bo, domain); | |
406 | } | |
407 | amdgpu_uvd_force_into_uvd_segment(bo); | |
408 | ||
409 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | |
410 | } | |
411 | ||
412 | return r; | |
413 | } | |
414 | ||
415 | /** | |
416 | * amdgpu_uvd_cs_msg_decode - handle UVD decode message | |
417 | * | |
418 | * @msg: pointer to message structure | |
419 | * @buf_sizes: returned buffer sizes | |
420 | * | |
421 | * Peek into the decode message and calculate the necessary buffer sizes. | |
422 | */ | |
8e008dd7 SJ |
423 | static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, |
424 | unsigned buf_sizes[]) | |
d38ceaf9 AD |
425 | { |
426 | unsigned stream_type = msg[4]; | |
427 | unsigned width = msg[6]; | |
428 | unsigned height = msg[7]; | |
429 | unsigned dpb_size = msg[9]; | |
430 | unsigned pitch = msg[28]; | |
431 | unsigned level = msg[57]; | |
432 | ||
433 | unsigned width_in_mb = width / 16; | |
434 | unsigned height_in_mb = ALIGN(height / 16, 2); | |
435 | unsigned fs_in_mb = width_in_mb * height_in_mb; | |
436 | ||
21df89a5 JZ |
437 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; |
438 | unsigned min_ctx_size = 0; | |
d38ceaf9 AD |
439 | |
440 | image_size = width * height; | |
441 | image_size += image_size / 2; | |
442 | image_size = ALIGN(image_size, 1024); | |
443 | ||
444 | switch (stream_type) { | |
445 | case 0: /* H264 */ | |
d38ceaf9 AD |
446 | switch(level) { |
447 | case 30: | |
448 | num_dpb_buffer = 8100 / fs_in_mb; | |
449 | break; | |
450 | case 31: | |
451 | num_dpb_buffer = 18000 / fs_in_mb; | |
452 | break; | |
453 | case 32: | |
454 | num_dpb_buffer = 20480 / fs_in_mb; | |
455 | break; | |
456 | case 41: | |
457 | num_dpb_buffer = 32768 / fs_in_mb; | |
458 | break; | |
459 | case 42: | |
460 | num_dpb_buffer = 34816 / fs_in_mb; | |
461 | break; | |
462 | case 50: | |
463 | num_dpb_buffer = 110400 / fs_in_mb; | |
464 | break; | |
465 | case 51: | |
466 | num_dpb_buffer = 184320 / fs_in_mb; | |
467 | break; | |
468 | default: | |
469 | num_dpb_buffer = 184320 / fs_in_mb; | |
470 | break; | |
471 | } | |
472 | num_dpb_buffer++; | |
473 | if (num_dpb_buffer > 17) | |
474 | num_dpb_buffer = 17; | |
475 | ||
476 | /* reference picture buffer */ | |
477 | min_dpb_size = image_size * num_dpb_buffer; | |
478 | ||
479 | /* macroblock context buffer */ | |
480 | min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
481 | ||
482 | /* IT surface buffer */ | |
483 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
484 | break; | |
485 | ||
486 | case 1: /* VC1 */ | |
487 | ||
488 | /* reference picture buffer */ | |
489 | min_dpb_size = image_size * 3; | |
490 | ||
491 | /* CONTEXT_BUFFER */ | |
492 | min_dpb_size += width_in_mb * height_in_mb * 128; | |
493 | ||
494 | /* IT surface buffer */ | |
495 | min_dpb_size += width_in_mb * 64; | |
496 | ||
497 | /* DB surface buffer */ | |
498 | min_dpb_size += width_in_mb * 128; | |
499 | ||
500 | /* BP */ | |
501 | tmp = max(width_in_mb, height_in_mb); | |
502 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); | |
503 | break; | |
504 | ||
505 | case 3: /* MPEG2 */ | |
506 | ||
507 | /* reference picture buffer */ | |
508 | min_dpb_size = image_size * 3; | |
509 | break; | |
510 | ||
511 | case 4: /* MPEG4 */ | |
512 | ||
513 | /* reference picture buffer */ | |
514 | min_dpb_size = image_size * 3; | |
515 | ||
516 | /* CM */ | |
517 | min_dpb_size += width_in_mb * height_in_mb * 64; | |
518 | ||
519 | /* IT surface buffer */ | |
520 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); | |
521 | break; | |
522 | ||
8e008dd7 SJ |
523 | case 7: /* H264 Perf */ |
524 | switch(level) { | |
525 | case 30: | |
526 | num_dpb_buffer = 8100 / fs_in_mb; | |
527 | break; | |
528 | case 31: | |
529 | num_dpb_buffer = 18000 / fs_in_mb; | |
530 | break; | |
531 | case 32: | |
532 | num_dpb_buffer = 20480 / fs_in_mb; | |
533 | break; | |
534 | case 41: | |
535 | num_dpb_buffer = 32768 / fs_in_mb; | |
536 | break; | |
537 | case 42: | |
538 | num_dpb_buffer = 34816 / fs_in_mb; | |
539 | break; | |
540 | case 50: | |
541 | num_dpb_buffer = 110400 / fs_in_mb; | |
542 | break; | |
543 | case 51: | |
544 | num_dpb_buffer = 184320 / fs_in_mb; | |
545 | break; | |
546 | default: | |
547 | num_dpb_buffer = 184320 / fs_in_mb; | |
548 | break; | |
549 | } | |
550 | num_dpb_buffer++; | |
551 | if (num_dpb_buffer > 17) | |
552 | num_dpb_buffer = 17; | |
553 | ||
554 | /* reference picture buffer */ | |
555 | min_dpb_size = image_size * num_dpb_buffer; | |
556 | ||
557 | if (adev->asic_type < CHIP_POLARIS10){ | |
558 | /* macroblock context buffer */ | |
559 | min_dpb_size += | |
560 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
561 | ||
562 | /* IT surface buffer */ | |
563 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
564 | } else { | |
565 | /* macroblock context buffer */ | |
566 | min_ctx_size = | |
567 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
568 | } | |
569 | break; | |
570 | ||
86fa0bdc CK |
571 | case 16: /* H265 */ |
572 | image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; | |
573 | image_size = ALIGN(image_size, 256); | |
574 | ||
575 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; | |
576 | min_dpb_size = image_size * num_dpb_buffer; | |
8c8bac59 BZ |
577 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) |
578 | * 16 * num_dpb_buffer + 52 * 1024; | |
86fa0bdc CK |
579 | break; |
580 | ||
d38ceaf9 AD |
581 | default: |
582 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
586 | if (width > pitch) { | |
587 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | if (dpb_size < min_dpb_size) { | |
592 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", | |
593 | dpb_size, min_dpb_size); | |
594 | return -EINVAL; | |
595 | } | |
596 | ||
597 | buf_sizes[0x1] = dpb_size; | |
598 | buf_sizes[0x2] = image_size; | |
8c8bac59 | 599 | buf_sizes[0x4] = min_ctx_size; |
d38ceaf9 AD |
600 | return 0; |
601 | } | |
602 | ||
603 | /** | |
604 | * amdgpu_uvd_cs_msg - handle UVD message | |
605 | * | |
606 | * @ctx: UVD parser context | |
607 | * @bo: buffer object containing the message | |
608 | * @offset: offset into the buffer object | |
609 | * | |
610 | * Peek into the UVD message and extract the session id. | |
611 | * Make sure that we don't open up to many sessions. | |
612 | */ | |
613 | static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, | |
614 | struct amdgpu_bo *bo, unsigned offset) | |
615 | { | |
616 | struct amdgpu_device *adev = ctx->parser->adev; | |
617 | int32_t *msg, msg_type, handle; | |
d38ceaf9 | 618 | void *ptr; |
4127a59e CK |
619 | long r; |
620 | int i; | |
d38ceaf9 AD |
621 | |
622 | if (offset & 0x3F) { | |
623 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); | |
624 | return -EINVAL; | |
625 | } | |
626 | ||
d38ceaf9 AD |
627 | r = amdgpu_bo_kmap(bo, &ptr); |
628 | if (r) { | |
4127a59e | 629 | DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); |
d38ceaf9 AD |
630 | return r; |
631 | } | |
632 | ||
633 | msg = ptr + offset; | |
634 | ||
635 | msg_type = msg[1]; | |
636 | handle = msg[2]; | |
637 | ||
638 | if (handle == 0) { | |
639 | DRM_ERROR("Invalid UVD handle!\n"); | |
640 | return -EINVAL; | |
641 | } | |
642 | ||
5146419e LL |
643 | switch (msg_type) { |
644 | case 0: | |
645 | /* it's a create msg, calc image size (width * height) */ | |
646 | amdgpu_bo_kunmap(bo); | |
647 | ||
648 | /* try to alloc a new handle */ | |
c0365541 | 649 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
650 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
651 | DRM_ERROR("Handle 0x%x already in use!\n", handle); | |
652 | return -EINVAL; | |
653 | } | |
654 | ||
655 | if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { | |
656 | adev->uvd.filp[i] = ctx->parser->filp; | |
657 | return 0; | |
658 | } | |
659 | } | |
660 | ||
661 | DRM_ERROR("No more free UVD handles!\n"); | |
7129d3ae | 662 | return -ENOSPC; |
5146419e LL |
663 | |
664 | case 1: | |
d38ceaf9 | 665 | /* it's a decode msg, calc buffer sizes */ |
8e008dd7 | 666 | r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); |
d38ceaf9 AD |
667 | amdgpu_bo_kunmap(bo); |
668 | if (r) | |
669 | return r; | |
670 | ||
5146419e | 671 | /* validate the handle */ |
c0365541 | 672 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
673 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
674 | if (adev->uvd.filp[i] != ctx->parser->filp) { | |
675 | DRM_ERROR("UVD handle collision detected!\n"); | |
676 | return -EINVAL; | |
677 | } | |
678 | return 0; | |
679 | } | |
680 | } | |
681 | ||
682 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); | |
683 | return -ENOENT; | |
684 | ||
685 | case 2: | |
d38ceaf9 | 686 | /* it's a destroy msg, free the handle */ |
c0365541 | 687 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
688 | atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); |
689 | amdgpu_bo_kunmap(bo); | |
690 | return 0; | |
d38ceaf9 | 691 | |
5146419e LL |
692 | default: |
693 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); | |
694 | return -EINVAL; | |
d38ceaf9 | 695 | } |
5146419e | 696 | BUG(); |
d38ceaf9 AD |
697 | return -EINVAL; |
698 | } | |
699 | ||
700 | /** | |
701 | * amdgpu_uvd_cs_pass2 - second parsing round | |
702 | * | |
703 | * @ctx: UVD parser context | |
704 | * | |
705 | * Patch buffer addresses, make sure buffer sizes are correct. | |
706 | */ | |
707 | static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) | |
708 | { | |
709 | struct amdgpu_bo_va_mapping *mapping; | |
710 | struct amdgpu_bo *bo; | |
d38ceaf9 AD |
711 | uint32_t cmd, lo, hi; |
712 | uint64_t start, end; | |
713 | uint64_t addr; | |
714 | int r; | |
715 | ||
716 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
717 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
718 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
719 | ||
720 | mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); | |
721 | if (mapping == NULL) | |
722 | return -EINVAL; | |
723 | ||
724 | start = amdgpu_bo_gpu_offset(bo); | |
725 | ||
726 | end = (mapping->it.last + 1 - mapping->it.start); | |
727 | end = end * AMDGPU_GPU_PAGE_SIZE + start; | |
728 | ||
729 | addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; | |
730 | start += addr; | |
731 | ||
7270f839 CK |
732 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, |
733 | lower_32_bits(start)); | |
734 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, | |
735 | upper_32_bits(start)); | |
d38ceaf9 AD |
736 | |
737 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
738 | if (cmd < 0x4) { | |
739 | if ((end - start) < ctx->buf_sizes[cmd]) { | |
740 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
741 | (unsigned)(end - start), | |
742 | ctx->buf_sizes[cmd]); | |
743 | return -EINVAL; | |
744 | } | |
745 | ||
8c8bac59 BZ |
746 | } else if (cmd == 0x206) { |
747 | if ((end - start) < ctx->buf_sizes[4]) { | |
748 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
749 | (unsigned)(end - start), | |
750 | ctx->buf_sizes[4]); | |
751 | return -EINVAL; | |
752 | } | |
d38ceaf9 AD |
753 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
754 | DRM_ERROR("invalid UVD command %X!\n", cmd); | |
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
759 | if ((start >> 28) != ((end - 1) >> 28)) { | |
760 | DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", | |
761 | start, end); | |
762 | return -EINVAL; | |
763 | } | |
764 | ||
765 | if ((cmd == 0 || cmd == 0x3) && | |
766 | (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { | |
767 | DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", | |
768 | start, end); | |
769 | return -EINVAL; | |
770 | } | |
771 | } | |
772 | ||
773 | if (cmd == 0) { | |
774 | ctx->has_msg_cmd = true; | |
775 | r = amdgpu_uvd_cs_msg(ctx, bo, addr); | |
776 | if (r) | |
777 | return r; | |
778 | } else if (!ctx->has_msg_cmd) { | |
779 | DRM_ERROR("Message needed before other commands are send!\n"); | |
780 | return -EINVAL; | |
781 | } | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | /** | |
787 | * amdgpu_uvd_cs_reg - parse register writes | |
788 | * | |
789 | * @ctx: UVD parser context | |
790 | * @cb: callback function | |
791 | * | |
792 | * Parse the register writes, call cb on each complete command. | |
793 | */ | |
794 | static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, | |
795 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
796 | { | |
50838c8c | 797 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
798 | int i, r; |
799 | ||
800 | ctx->idx++; | |
801 | for (i = 0; i <= ctx->count; ++i) { | |
802 | unsigned reg = ctx->reg + i; | |
803 | ||
804 | if (ctx->idx >= ib->length_dw) { | |
805 | DRM_ERROR("Register command after end of CS!\n"); | |
806 | return -EINVAL; | |
807 | } | |
808 | ||
809 | switch (reg) { | |
810 | case mmUVD_GPCOM_VCPU_DATA0: | |
811 | ctx->data0 = ctx->idx; | |
812 | break; | |
813 | case mmUVD_GPCOM_VCPU_DATA1: | |
814 | ctx->data1 = ctx->idx; | |
815 | break; | |
816 | case mmUVD_GPCOM_VCPU_CMD: | |
817 | r = cb(ctx); | |
818 | if (r) | |
819 | return r; | |
820 | break; | |
821 | case mmUVD_ENGINE_CNTL: | |
822 | break; | |
823 | default: | |
824 | DRM_ERROR("Invalid reg 0x%X!\n", reg); | |
825 | return -EINVAL; | |
826 | } | |
827 | ctx->idx++; | |
828 | } | |
829 | return 0; | |
830 | } | |
831 | ||
832 | /** | |
833 | * amdgpu_uvd_cs_packets - parse UVD packets | |
834 | * | |
835 | * @ctx: UVD parser context | |
836 | * @cb: callback function | |
837 | * | |
838 | * Parse the command stream packets. | |
839 | */ | |
840 | static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, | |
841 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
842 | { | |
50838c8c | 843 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
844 | int r; |
845 | ||
846 | for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { | |
847 | uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); | |
848 | unsigned type = CP_PACKET_GET_TYPE(cmd); | |
849 | switch (type) { | |
850 | case PACKET_TYPE0: | |
851 | ctx->reg = CP_PACKET0_GET_REG(cmd); | |
852 | ctx->count = CP_PACKET_GET_COUNT(cmd); | |
853 | r = amdgpu_uvd_cs_reg(ctx, cb); | |
854 | if (r) | |
855 | return r; | |
856 | break; | |
857 | case PACKET_TYPE2: | |
858 | ++ctx->idx; | |
859 | break; | |
860 | default: | |
861 | DRM_ERROR("Unknown packet type %d !\n", type); | |
862 | return -EINVAL; | |
863 | } | |
864 | } | |
865 | return 0; | |
866 | } | |
867 | ||
868 | /** | |
869 | * amdgpu_uvd_ring_parse_cs - UVD command submission parser | |
870 | * | |
871 | * @parser: Command submission parser context | |
872 | * | |
873 | * Parse the command stream, patch in addresses as necessary. | |
874 | */ | |
875 | int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) | |
876 | { | |
877 | struct amdgpu_uvd_cs_ctx ctx = {}; | |
878 | unsigned buf_sizes[] = { | |
879 | [0x00000000] = 2048, | |
8c8bac59 BZ |
880 | [0x00000001] = 0xFFFFFFFF, |
881 | [0x00000002] = 0xFFFFFFFF, | |
d38ceaf9 | 882 | [0x00000003] = 2048, |
8c8bac59 | 883 | [0x00000004] = 0xFFFFFFFF, |
d38ceaf9 | 884 | }; |
50838c8c | 885 | struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; |
d38ceaf9 AD |
886 | int r; |
887 | ||
888 | if (ib->length_dw % 16) { | |
889 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", | |
890 | ib->length_dw); | |
891 | return -EINVAL; | |
892 | } | |
893 | ||
894 | ctx.parser = parser; | |
895 | ctx.buf_sizes = buf_sizes; | |
896 | ctx.ib_idx = ib_idx; | |
897 | ||
898 | /* first round, make sure the buffers are actually in the UVD segment */ | |
899 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); | |
900 | if (r) | |
901 | return r; | |
902 | ||
903 | /* second round, patch buffer addresses into the command stream */ | |
904 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); | |
905 | if (r) | |
906 | return r; | |
907 | ||
908 | if (!ctx.has_msg_cmd) { | |
909 | DRM_ERROR("UVD-IBs need a msg command!\n"); | |
910 | return -EINVAL; | |
911 | } | |
912 | ||
d38ceaf9 AD |
913 | return 0; |
914 | } | |
915 | ||
d7af97db CK |
916 | static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, |
917 | bool direct, struct fence **fence) | |
d38ceaf9 AD |
918 | { |
919 | struct ttm_validate_buffer tv; | |
920 | struct ww_acquire_ctx ticket; | |
921 | struct list_head head; | |
d71518b5 CK |
922 | struct amdgpu_job *job; |
923 | struct amdgpu_ib *ib; | |
1763552e | 924 | struct fence *f = NULL; |
7b5ec431 | 925 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 AD |
926 | uint64_t addr; |
927 | int i, r; | |
928 | ||
929 | memset(&tv, 0, sizeof(tv)); | |
930 | tv.bo = &bo->tbo; | |
931 | ||
932 | INIT_LIST_HEAD(&head); | |
933 | list_add(&tv.head, &head); | |
934 | ||
935 | r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); | |
936 | if (r) | |
937 | return r; | |
938 | ||
939 | if (!bo->adev->uvd.address_64_bit) { | |
940 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); | |
941 | amdgpu_uvd_force_into_uvd_segment(bo); | |
942 | } | |
943 | ||
944 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
945 | if (r) | |
946 | goto err; | |
d71518b5 CK |
947 | |
948 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); | |
7b5ec431 | 949 | if (r) |
d71518b5 | 950 | goto err; |
d38ceaf9 | 951 | |
d71518b5 | 952 | ib = &job->ibs[0]; |
d38ceaf9 | 953 | addr = amdgpu_bo_gpu_offset(bo); |
7b5ec431 CZ |
954 | ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); |
955 | ib->ptr[1] = addr; | |
956 | ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); | |
957 | ib->ptr[3] = addr >> 32; | |
958 | ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); | |
959 | ib->ptr[5] = 0; | |
d38ceaf9 | 960 | for (i = 6; i < 16; ++i) |
7b5ec431 CZ |
961 | ib->ptr[i] = PACKET2(0); |
962 | ib->length_dw = 16; | |
d38ceaf9 | 963 | |
d7af97db | 964 | if (direct) { |
c5637837 | 965 | r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); |
22a77cf6 | 966 | job->fence = fence_get(f); |
d7af97db CK |
967 | if (r) |
968 | goto err_free; | |
969 | ||
970 | amdgpu_job_free(job); | |
971 | } else { | |
ead833ec | 972 | r = amdgpu_job_submit(job, ring, &adev->uvd.entity, |
d7af97db CK |
973 | AMDGPU_FENCE_OWNER_UNDEFINED, &f); |
974 | if (r) | |
975 | goto err_free; | |
976 | } | |
d38ceaf9 | 977 | |
1763552e | 978 | ttm_eu_fence_buffer_objects(&ticket, &head, f); |
d38ceaf9 | 979 | |
7b5ec431 | 980 | if (fence) |
1763552e | 981 | *fence = fence_get(f); |
d38ceaf9 | 982 | amdgpu_bo_unref(&bo); |
281b4223 | 983 | fence_put(f); |
7b5ec431 | 984 | |
7b5ec431 | 985 | return 0; |
d71518b5 CK |
986 | |
987 | err_free: | |
988 | amdgpu_job_free(job); | |
989 | ||
d38ceaf9 AD |
990 | err: |
991 | ttm_eu_backoff_reservation(&ticket, &head); | |
992 | return r; | |
993 | } | |
994 | ||
995 | /* multiple fence commands without any stream commands in between can | |
996 | crash the vcpu so just try to emmit a dummy create/destroy msg to | |
997 | avoid this */ | |
998 | int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, | |
0e3f154a | 999 | struct fence **fence) |
d38ceaf9 AD |
1000 | { |
1001 | struct amdgpu_device *adev = ring->adev; | |
1002 | struct amdgpu_bo *bo; | |
1003 | uint32_t *msg; | |
1004 | int r, i; | |
1005 | ||
1006 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d AD |
1007 | AMDGPU_GEM_DOMAIN_VRAM, |
1008 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1009 | NULL, NULL, &bo); |
d38ceaf9 AD |
1010 | if (r) |
1011 | return r; | |
1012 | ||
1013 | r = amdgpu_bo_reserve(bo, false); | |
1014 | if (r) { | |
1015 | amdgpu_bo_unref(&bo); | |
1016 | return r; | |
1017 | } | |
1018 | ||
1019 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1020 | if (r) { | |
1021 | amdgpu_bo_unreserve(bo); | |
1022 | amdgpu_bo_unref(&bo); | |
1023 | return r; | |
1024 | } | |
1025 | ||
1026 | /* stitch together an UVD create msg */ | |
1027 | msg[0] = cpu_to_le32(0x00000de4); | |
1028 | msg[1] = cpu_to_le32(0x00000000); | |
1029 | msg[2] = cpu_to_le32(handle); | |
1030 | msg[3] = cpu_to_le32(0x00000000); | |
1031 | msg[4] = cpu_to_le32(0x00000000); | |
1032 | msg[5] = cpu_to_le32(0x00000000); | |
1033 | msg[6] = cpu_to_le32(0x00000000); | |
1034 | msg[7] = cpu_to_le32(0x00000780); | |
1035 | msg[8] = cpu_to_le32(0x00000440); | |
1036 | msg[9] = cpu_to_le32(0x00000000); | |
1037 | msg[10] = cpu_to_le32(0x01b37000); | |
1038 | for (i = 11; i < 1024; ++i) | |
1039 | msg[i] = cpu_to_le32(0x0); | |
1040 | ||
1041 | amdgpu_bo_kunmap(bo); | |
1042 | amdgpu_bo_unreserve(bo); | |
1043 | ||
d7af97db | 1044 | return amdgpu_uvd_send_msg(ring, bo, true, fence); |
d38ceaf9 AD |
1045 | } |
1046 | ||
1047 | int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |
d7af97db | 1048 | bool direct, struct fence **fence) |
d38ceaf9 AD |
1049 | { |
1050 | struct amdgpu_device *adev = ring->adev; | |
1051 | struct amdgpu_bo *bo; | |
1052 | uint32_t *msg; | |
1053 | int r, i; | |
1054 | ||
1055 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d AD |
1056 | AMDGPU_GEM_DOMAIN_VRAM, |
1057 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1058 | NULL, NULL, &bo); |
d38ceaf9 AD |
1059 | if (r) |
1060 | return r; | |
1061 | ||
1062 | r = amdgpu_bo_reserve(bo, false); | |
1063 | if (r) { | |
1064 | amdgpu_bo_unref(&bo); | |
1065 | return r; | |
1066 | } | |
1067 | ||
1068 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1069 | if (r) { | |
1070 | amdgpu_bo_unreserve(bo); | |
1071 | amdgpu_bo_unref(&bo); | |
1072 | return r; | |
1073 | } | |
1074 | ||
1075 | /* stitch together an UVD destroy msg */ | |
1076 | msg[0] = cpu_to_le32(0x00000de4); | |
1077 | msg[1] = cpu_to_le32(0x00000002); | |
1078 | msg[2] = cpu_to_le32(handle); | |
1079 | msg[3] = cpu_to_le32(0x00000000); | |
1080 | for (i = 4; i < 1024; ++i) | |
1081 | msg[i] = cpu_to_le32(0x0); | |
1082 | ||
1083 | amdgpu_bo_kunmap(bo); | |
1084 | amdgpu_bo_unreserve(bo); | |
1085 | ||
d7af97db | 1086 | return amdgpu_uvd_send_msg(ring, bo, direct, fence); |
d38ceaf9 AD |
1087 | } |
1088 | ||
1089 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |
1090 | { | |
1091 | struct amdgpu_device *adev = | |
1092 | container_of(work, struct amdgpu_device, uvd.idle_work.work); | |
1093 | unsigned i, fences, handles = 0; | |
1094 | ||
1095 | fences = amdgpu_fence_count_emitted(&adev->uvd.ring); | |
1096 | ||
c0365541 | 1097 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
1098 | if (atomic_read(&adev->uvd.handles[i])) |
1099 | ++handles; | |
1100 | ||
1101 | if (fences == 0 && handles == 0) { | |
1102 | if (adev->pm.dpm_enabled) { | |
1103 | amdgpu_dpm_enable_uvd(adev, false); | |
1104 | } else { | |
1105 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
1106 | } | |
1107 | } else { | |
08086635 | 1108 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
d38ceaf9 AD |
1109 | } |
1110 | } | |
1111 | ||
c4120d55 | 1112 | void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) |
d38ceaf9 | 1113 | { |
c4120d55 | 1114 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 | 1115 | bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); |
d38ceaf9 AD |
1116 | |
1117 | if (set_clocks) { | |
1118 | if (adev->pm.dpm_enabled) { | |
1119 | amdgpu_dpm_enable_uvd(adev, true); | |
1120 | } else { | |
1121 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
1122 | } | |
1123 | } | |
1124 | } | |
c4120d55 CK |
1125 | |
1126 | void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) | |
1127 | { | |
1128 | schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); | |
1129 | } |