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3488c79b LY |
1 | /* SPDX-License-Identifier: MIT */ |
2 | /* | |
3 | * Copyright 2023 Advanced Micro Devices, Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef __AMDGPU_UMSCH_MM_H__ | |
26 | #define __AMDGPU_UMSCH_MM_H__ | |
27 | ||
28 | enum UMSCH_SWIP_ENGINE_TYPE { | |
29 | UMSCH_SWIP_ENGINE_TYPE_VCN0 = 0, | |
30 | UMSCH_SWIP_ENGINE_TYPE_VCN1 = 1, | |
31 | UMSCH_SWIP_ENGINE_TYPE_VCN = 2, | |
32 | UMSCH_SWIP_ENGINE_TYPE_VPE = 3, | |
33 | UMSCH_SWIP_ENGINE_TYPE_MAX | |
34 | }; | |
35 | ||
3488c79b LY |
36 | enum UMSCH_CONTEXT_PRIORITY_LEVEL { |
37 | CONTEXT_PRIORITY_LEVEL_IDLE = 0, | |
38 | CONTEXT_PRIORITY_LEVEL_NORMAL = 1, | |
39 | CONTEXT_PRIORITY_LEVEL_FOCUS = 2, | |
40 | CONTEXT_PRIORITY_LEVEL_REALTIME = 3, | |
41 | CONTEXT_PRIORITY_NUM_LEVELS | |
42 | }; | |
43 | ||
44 | struct umsch_mm_set_resource_input { | |
45 | uint32_t vmid_mask_mm_vcn; | |
46 | uint32_t vmid_mask_mm_vpe; | |
6b154c00 | 47 | uint32_t collaboration_mask_vpe; |
3488c79b LY |
48 | uint32_t logging_vmid; |
49 | uint32_t engine_mask; | |
50 | union { | |
51 | struct { | |
52 | uint32_t disable_reset : 1; | |
53 | uint32_t disable_umsch_mm_log : 1; | |
6b154c00 LY |
54 | uint32_t use_rs64mem_for_proc_ctx_csa : 1; |
55 | uint32_t reserved : 29; | |
3488c79b LY |
56 | }; |
57 | uint32_t uint32_all; | |
58 | }; | |
59 | }; | |
60 | ||
61 | struct umsch_mm_add_queue_input { | |
62 | uint32_t process_id; | |
63 | uint64_t page_table_base_addr; | |
64 | uint64_t process_va_start; | |
65 | uint64_t process_va_end; | |
66 | uint64_t process_quantum; | |
67 | uint64_t process_csa_addr; | |
68 | uint64_t context_quantum; | |
69 | uint64_t context_csa_addr; | |
70 | uint32_t inprocess_context_priority; | |
71 | enum UMSCH_CONTEXT_PRIORITY_LEVEL context_global_priority_level; | |
72 | uint32_t doorbell_offset_0; | |
73 | uint32_t doorbell_offset_1; | |
74 | enum UMSCH_SWIP_ENGINE_TYPE engine_type; | |
75 | uint32_t affinity; | |
3488c79b LY |
76 | uint64_t mqd_addr; |
77 | uint64_t h_context; | |
78 | uint64_t h_queue; | |
79 | uint32_t vm_context_cntl; | |
80 | ||
6b154c00 LY |
81 | uint32_t process_csa_array_index; |
82 | uint32_t context_csa_array_index; | |
83 | ||
3488c79b LY |
84 | struct { |
85 | uint32_t is_context_suspended : 1; | |
6b154c00 LY |
86 | uint32_t collaboration_mode : 1; |
87 | uint32_t reserved : 30; | |
3488c79b LY |
88 | }; |
89 | }; | |
90 | ||
91 | struct umsch_mm_remove_queue_input { | |
92 | uint32_t doorbell_offset_0; | |
93 | uint32_t doorbell_offset_1; | |
94 | uint64_t context_csa_addr; | |
6b154c00 | 95 | uint32_t context_csa_array_index; |
3488c79b LY |
96 | }; |
97 | ||
98 | struct MQD_INFO { | |
99 | uint32_t rb_base_hi; | |
100 | uint32_t rb_base_lo; | |
101 | uint32_t rb_size; | |
102 | uint32_t wptr_val; | |
103 | uint32_t rptr_val; | |
104 | uint32_t unmapped; | |
6b154c00 | 105 | uint32_t vmid; |
3488c79b LY |
106 | }; |
107 | ||
108 | struct amdgpu_umsch_mm; | |
109 | ||
110 | struct umsch_mm_funcs { | |
111 | int (*set_hw_resources)(struct amdgpu_umsch_mm *umsch); | |
112 | int (*add_queue)(struct amdgpu_umsch_mm *umsch, | |
113 | struct umsch_mm_add_queue_input *input); | |
114 | int (*remove_queue)(struct amdgpu_umsch_mm *umsch, | |
115 | struct umsch_mm_remove_queue_input *input); | |
116 | int (*set_regs)(struct amdgpu_umsch_mm *umsch); | |
117 | int (*init_microcode)(struct amdgpu_umsch_mm *umsch); | |
118 | int (*load_microcode)(struct amdgpu_umsch_mm *umsch); | |
119 | int (*ring_init)(struct amdgpu_umsch_mm *umsch); | |
120 | int (*ring_start)(struct amdgpu_umsch_mm *umsch); | |
121 | int (*ring_stop)(struct amdgpu_umsch_mm *umsch); | |
122 | int (*ring_fini)(struct amdgpu_umsch_mm *umsch); | |
123 | }; | |
124 | ||
125 | struct amdgpu_umsch_mm { | |
126 | struct amdgpu_ring ring; | |
127 | ||
128 | uint32_t rb_wptr; | |
129 | uint32_t rb_rptr; | |
130 | ||
131 | const struct umsch_mm_funcs *funcs; | |
132 | ||
133 | const struct firmware *fw; | |
134 | uint32_t fw_version; | |
135 | uint32_t feature_version; | |
136 | ||
137 | struct amdgpu_bo *ucode_fw_obj; | |
138 | uint64_t ucode_fw_gpu_addr; | |
139 | uint32_t *ucode_fw_ptr; | |
140 | uint64_t irq_start_addr; | |
141 | uint64_t uc_start_addr; | |
142 | uint32_t ucode_size; | |
143 | ||
144 | struct amdgpu_bo *data_fw_obj; | |
145 | uint64_t data_fw_gpu_addr; | |
146 | uint32_t *data_fw_ptr; | |
147 | uint64_t data_start_addr; | |
148 | uint32_t data_size; | |
149 | ||
4f949033 LY |
150 | struct amdgpu_bo *cmd_buf_obj; |
151 | uint64_t cmd_buf_gpu_addr; | |
152 | uint32_t *cmd_buf_ptr; | |
617b4724 | 153 | uint32_t *cmd_buf_curr_ptr; |
4f949033 | 154 | |
3488c79b LY |
155 | uint32_t wb_index; |
156 | uint64_t sch_ctx_gpu_addr; | |
157 | uint32_t *sch_ctx_cpu_addr; | |
158 | ||
159 | uint32_t vmid_mask_mm_vcn; | |
160 | uint32_t vmid_mask_mm_vpe; | |
161 | uint32_t engine_mask; | |
162 | uint32_t vcn0_hqd_mask; | |
163 | uint32_t vcn1_hqd_mask; | |
164 | uint32_t vcn_hqd_mask[2]; | |
165 | uint32_t vpe_hqd_mask; | |
166 | uint32_t agdb_index[CONTEXT_PRIORITY_NUM_LEVELS]; | |
167 | ||
168 | struct mutex mutex_hidden; | |
169 | }; | |
170 | ||
171 | int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws); | |
172 | int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch); | |
173 | ||
174 | int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch); | |
175 | int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch); | |
176 | int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch); | |
617b4724 LY |
177 | |
178 | int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch); | |
3488c79b LY |
179 | |
180 | int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch); | |
181 | ||
617b4724 LY |
182 | #define WREG32_SOC15_UMSCH(reg, value) \ |
183 | do { \ | |
184 | uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \ | |
185 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { \ | |
186 | *adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2); \ | |
187 | *adev->umsch_mm.cmd_buf_curr_ptr++ = value; \ | |
188 | } else { \ | |
189 | WREG32(reg_offset, value); \ | |
190 | } \ | |
191 | } while (0) | |
192 | ||
3488c79b LY |
193 | #define umsch_mm_set_hw_resources(umsch) \ |
194 | ((umsch)->funcs->set_hw_resources ? (umsch)->funcs->set_hw_resources((umsch)) : 0) | |
195 | #define umsch_mm_add_queue(umsch, input) \ | |
196 | ((umsch)->funcs->add_queue ? (umsch)->funcs->add_queue((umsch), (input)) : 0) | |
197 | #define umsch_mm_remove_queue(umsch, input) \ | |
198 | ((umsch)->funcs->remove_queue ? (umsch)->funcs->remove_queue((umsch), (input)) : 0) | |
199 | ||
200 | #define umsch_mm_set_regs(umsch) \ | |
201 | ((umsch)->funcs->set_regs ? (umsch)->funcs->set_regs((umsch)) : 0) | |
202 | #define umsch_mm_init_microcode(umsch) \ | |
203 | ((umsch)->funcs->init_microcode ? (umsch)->funcs->init_microcode((umsch)) : 0) | |
204 | #define umsch_mm_load_microcode(umsch) \ | |
205 | ((umsch)->funcs->load_microcode ? (umsch)->funcs->load_microcode((umsch)) : 0) | |
206 | ||
207 | #define umsch_mm_ring_init(umsch) \ | |
208 | ((umsch)->funcs->ring_init ? (umsch)->funcs->ring_init((umsch)) : 0) | |
209 | #define umsch_mm_ring_start(umsch) \ | |
210 | ((umsch)->funcs->ring_start ? (umsch)->funcs->ring_start((umsch)) : 0) | |
211 | #define umsch_mm_ring_stop(umsch) \ | |
212 | ((umsch)->funcs->ring_stop ? (umsch)->funcs->ring_stop((umsch)) : 0) | |
213 | #define umsch_mm_ring_fini(umsch) \ | |
214 | ((umsch)->funcs->ring_fini ? (umsch)->funcs->ring_fini((umsch)) : 0) | |
215 | ||
216 | static inline void amdgpu_umsch_mm_lock(struct amdgpu_umsch_mm *umsch) | |
217 | { | |
218 | mutex_lock(&umsch->mutex_hidden); | |
219 | } | |
220 | ||
221 | static inline void amdgpu_umsch_mm_unlock(struct amdgpu_umsch_mm *umsch) | |
222 | { | |
223 | mutex_unlock(&umsch->mutex_hidden); | |
224 | } | |
225 | ||
226 | extern const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block; | |
227 | ||
228 | #endif |