[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_umc.h

/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __AMDGPU_UMC_H__
#define __AMDGPU_UMC_H__
#include "amdgpu_ras.h"
#include "amdgpu_mca.h"
/*
 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
 * is the index of 4KB block
 */
#define ADDR_OF_4KB_BLOCK(addr)			(((addr) & ~0xffULL) << 4)
/*
 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
 * is the index of 8KB block
 */
#define ADDR_OF_8KB_BLOCK(addr)			(((addr) & ~0xffULL) << 5)
/*
 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr
 * is the index of 8KB block
 */
#define ADDR_OF_32KB_BLOCK(addr)			(((addr) & ~0xffULL) << 7)
/* channel index is the index of 256B block */
#define ADDR_OF_256B_BLOCK(channel_index)	((channel_index) << 8)
/* offset in 256B block */
#define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)

#define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))

#define LOOP_UMC_NODE_INST(node_inst) \
		for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)

#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
		LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))


typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
			uint32_t umc_inst, uint32_t ch_inst, void *data);

struct amdgpu_umc_ras {
	struct amdgpu_ras_block_object ras_block;
	void (*err_cnt_init)(struct amdgpu_device *adev);
	bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
	void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
				      void *ras_error_status);
	void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
					void *ras_error_status);
	bool (*check_ecc_err_status)(struct amdgpu_device *adev,
			enum amdgpu_mca_error_type type, void *ras_error_status);
	/* support different eeprom table version for different asic */
	void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr);
};

struct amdgpu_umc_funcs {
	void (*init_registers)(struct amdgpu_device *adev);
};

struct amdgpu_umc {
	/* max error count in one ras query call */
	uint32_t max_ras_err_cnt_per_query;
	/* number of umc channel instance with memory map register access */
	uint32_t channel_inst_num;
	/* number of umc instance with memory map register access */
	uint32_t umc_inst_num;

	/* Total number of umc node instance including harvest one */
	uint32_t node_inst_num;

	/* UMC regiser per channel offset */
	uint32_t channel_offs;
	/* how many pages are retired in one UE */
	uint32_t retire_unit;
	/* channel index table of interleaved memory */
	const uint32_t *channel_idx_tbl;
	struct ras_common_if *ras_if;

	const struct amdgpu_umc_funcs *funcs;
	struct amdgpu_umc_ras *ras;

	/* active mask for umc node instance */
	unsigned long active_mask;
};

int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);
int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
			enum amdgpu_ras_block block, bool reset);
int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
		struct amdgpu_irq_src *source,
		struct amdgpu_iv_entry *entry);
void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
		uint64_t err_addr,
		uint64_t retired_page,
		uint32_t channel_index,
		uint32_t umc_inst);

int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
		void *ras_error_status,
		struct amdgpu_iv_entry *entry);
int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
			uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);

int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
			umc_func func, void *data);

int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,
			bool reset, uint32_t timeout_ms);
#endif
Commit	Line	Data
9e585a52 HZ	1	/*
	2	* Copyright (C) 2019 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included
	12	* in all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
	18	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	19	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*/
	21	#ifndef __AMDGPU_UMC_H__
	22	#define __AMDGPU_UMC_H__
efe17d5a	23	#include "amdgpu_ras.h"
afb617f3	24	#include "amdgpu_mca.h"
6ec598cc SY	25	/*
	26	* (addr / 256) * 4096, the higher 26 bits in ErrorAddr
	27	* is the index of 4KB block
	28	*/
	29	#define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4)
c5a4ef3e JC	30	/*
	31	* (addr / 256) * 8192, the higher 26 bits in ErrorAddr
	32	* is the index of 8KB block
	33	*/
	34	#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5)
40a08fe8 TZ	35	/*
	36	* (addr / 256) * 32768, the higher 26 bits in ErrorAddr
	37	* is the index of 8KB block
	38	*/
	39	#define ADDR_OF_32KB_BLOCK(addr) (((addr) & ~0xffULL) << 7)
c5a4ef3e JC	40	/* channel index is the index of 256B block */
	41	#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8)
	42	/* offset in 256B block */
	43	#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL)
	44
	45	#define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
	46	#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
	47	#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
	48
e4b1edf4	49	#define LOOP_UMC_NODE_INST(node_inst) \
2b595659	50	for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
e4b1edf4 YC	51
	52	#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
	53	LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
	54
e86bd8b2 YC	55
	56	typedef int (umc_func)(struct amdgpu_device adev, uint32_t node_inst,
	57	uint32_t umc_inst, uint32_t ch_inst, void *data);
	58
efe17d5a	59	struct amdgpu_umc_ras {
efe17d5a	60	struct amdgpu_ras_block_object ras_block;
d99659a0	61	void (err_cnt_init)(struct amdgpu_device adev);
aaca8c38	62	bool (query_ras_poison_mode)(struct amdgpu_device adev);
8882f90a SY	63	void (ecc_info_query_ras_error_count)(struct amdgpu_device adev,
	64	void *ras_error_status);
	65	void (ecc_info_query_ras_error_address)(struct amdgpu_device adev,
	66	void *ras_error_status);
afb617f3 YC	67	bool (check_ecc_err_status)(struct amdgpu_device adev,
afb617f3 YC	68	enum amdgpu_mca_error_type type, void *ras_error_status);
b573cf88 SY	69	/* support different eeprom table version for different asic */
b573cf88 SY	70	void (set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header hdr);
49070c4e HZ	71	};
	72
	73	struct amdgpu_umc_funcs {
e7da754b	74	void (init_registers)(struct amdgpu_device adev);
9e585a52 HZ	75	};
9e585a52 HZ	76
045c0216 TZ	77	struct amdgpu_umc {
	78	/* max error count in one ras query call */
	79	uint32_t max_ras_err_cnt_per_query;
33b97cf8 TZ	80	/* number of umc channel instance with memory map register access */
	81	uint32_t channel_inst_num;
	82	/* number of umc instance with memory map register access */
	83	uint32_t umc_inst_num;
e4b1edf4	84
2b595659	85	/* Total number of umc node instance including harvest one */
e4b1edf4 YC	86	uint32_t node_inst_num;
e4b1edf4 YC	87
33b97cf8 TZ	88	/* UMC regiser per channel offset */
33b97cf8 TZ	89	uint32_t channel_offs;
e69c7857 TZ	90	/* how many pages are retired in one UE */
e69c7857 TZ	91	uint32_t retire_unit;
33b97cf8 TZ	92	/* channel index table of interleaved memory */
33b97cf8 TZ	93	const uint32_t *channel_idx_tbl;
03740baa	94	struct ras_common_if *ras_if;
33b97cf8	95
045c0216	96	const struct amdgpu_umc_funcs *funcs;
efe17d5a	97	struct amdgpu_umc_ras *ras;
2b595659 CL	98
	99	/* active mask for umc node instance */
	100	unsigned long active_mask;
045c0216 TZ	101	};
045c0216 TZ	102
a6dcf9a7	103	int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);
4e9b1fa5	104	int amdgpu_umc_ras_late_init(struct amdgpu_device adev, struct ras_common_if ras_block);
ed1e1e42 YC	105	int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
ed1e1e42 YC	106	enum amdgpu_ras_block block, bool reset);
34cc4fd9 TZ	107	int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
	108	struct amdgpu_irq_src *source,
	109	struct amdgpu_iv_entry *entry);
400013b2 TZ	110	void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
	111	uint64_t err_addr,
	112	uint64_t retired_page,
	113	uint32_t channel_index,
	114	uint32_t umc_inst);
a3ace75c	115
	116	int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
	117	void *ras_error_status,
	118	struct amdgpu_iv_entry *entry);
cbe4d43e TZ	119	int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
cbe4d43e TZ	120	uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);
e86bd8b2 YC	121
	122	int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
	123	umc_func func, void *data);
6c23f3d1 YC	124
	125	int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,
	126	bool reset, uint32_t timeout_ms);
9e585a52	127	#endif