[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.h

/*
 * Copyright 2012 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef __AMDGPU_UCODE_H__
#define __AMDGPU_UCODE_H__

struct common_firmware_header {
	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
	uint32_t header_size_bytes; /* size of just the header in bytes */
	uint16_t header_version_major; /* header version */
	uint16_t header_version_minor; /* header version */
	uint16_t ip_version_major; /* IP version */
	uint16_t ip_version_minor; /* IP version */
	uint32_t ucode_version;
	uint32_t ucode_size_bytes; /* size of ucode in bytes */
	uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
	uint32_t crc32;  /* crc32 checksum of the payload */
};

/* version_major=1, version_minor=0 */
struct mc_firmware_header_v1_0 {
	struct common_firmware_header header;
	uint32_t io_debug_size_bytes; /* size of debug array in dwords */
	uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
};

/* version_major=1, version_minor=0 */
struct smc_firmware_header_v1_0 {
	struct common_firmware_header header;
	uint32_t ucode_start_addr;
};

/* version_major=1, version_minor=0 */
struct gfx_firmware_header_v1_0 {
	struct common_firmware_header header;
	uint32_t ucode_feature_version;
	uint32_t jt_offset; /* jt location */
	uint32_t jt_size;  /* size of jt */
};

/* version_major=1, version_minor=0 */
struct rlc_firmware_header_v1_0 {
	struct common_firmware_header header;
	uint32_t ucode_feature_version;
	uint32_t save_and_restore_offset;
	uint32_t clear_state_descriptor_offset;
	uint32_t avail_scratch_ram_locations;
	uint32_t master_pkt_description_offset;
};

/* version_major=2, version_minor=0 */
struct rlc_firmware_header_v2_0 {
	struct common_firmware_header header;
	uint32_t ucode_feature_version;
	uint32_t jt_offset; /* jt location */
	uint32_t jt_size;  /* size of jt */
	uint32_t save_and_restore_offset;
	uint32_t clear_state_descriptor_offset;
	uint32_t avail_scratch_ram_locations;
	uint32_t reg_restore_list_size;
	uint32_t reg_list_format_start;
	uint32_t reg_list_format_separate_start;
	uint32_t starting_offsets_start;
	uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
	uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
	uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
	uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
	uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
	uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
	uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
	uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
};

/* version_major=1, version_minor=0 */
struct sdma_firmware_header_v1_0 {
	struct common_firmware_header header;
	uint32_t ucode_feature_version;
	uint32_t ucode_change_version;
	uint32_t jt_offset; /* jt location */
	uint32_t jt_size; /* size of jt */
};

/* version_major=1, version_minor=1 */
struct sdma_firmware_header_v1_1 {
	struct sdma_firmware_header_v1_0 v1_0;
	uint32_t digest_size;
};

/* header is fixed size */
union amdgpu_firmware_header {
	struct common_firmware_header common;
	struct mc_firmware_header_v1_0 mc;
	struct smc_firmware_header_v1_0 smc;
	struct gfx_firmware_header_v1_0 gfx;
	struct rlc_firmware_header_v1_0 rlc;
	struct rlc_firmware_header_v2_0 rlc_v2_0;
	struct sdma_firmware_header_v1_0 sdma;
	struct sdma_firmware_header_v1_1 sdma_v1_1;
	uint8_t raw[0x100];
};

/*
 * fw loading support
 */
enum AMDGPU_UCODE_ID {
	AMDGPU_UCODE_ID_SDMA0 = 0,
	AMDGPU_UCODE_ID_SDMA1,
	AMDGPU_UCODE_ID_CP_CE,
	AMDGPU_UCODE_ID_CP_PFP,
	AMDGPU_UCODE_ID_CP_ME,
	AMDGPU_UCODE_ID_CP_MEC1,
	AMDGPU_UCODE_ID_CP_MEC2,
	AMDGPU_UCODE_ID_RLC_G,
	AMDGPU_UCODE_ID_MAXIMUM,
};

/* engine firmware status */
enum AMDGPU_UCODE_STATUS {
	AMDGPU_UCODE_STATUS_INVALID,
	AMDGPU_UCODE_STATUS_NOT_LOADED,
	AMDGPU_UCODE_STATUS_LOADED,
};

/* conform to smu_ucode_xfer_cz.h */
#define AMDGPU_SDMA0_UCODE_LOADED	0x00000001
#define AMDGPU_SDMA1_UCODE_LOADED	0x00000002
#define AMDGPU_CPCE_UCODE_LOADED	0x00000004
#define AMDGPU_CPPFP_UCODE_LOADED	0x00000008
#define AMDGPU_CPME_UCODE_LOADED	0x00000010
#define AMDGPU_CPMEC1_UCODE_LOADED	0x00000020
#define AMDGPU_CPMEC2_UCODE_LOADED	0x00000040
#define AMDGPU_CPRLC_UCODE_LOADED	0x00000100

/* amdgpu firmware info */
struct amdgpu_firmware_info {
	/* ucode ID */
	enum AMDGPU_UCODE_ID ucode_id;
	/* request_firmware */
	const struct firmware *fw;
	/* starting mc address */
	uint64_t mc_addr;
	/* kernel linear address */
	void *kaddr;
};

void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
int amdgpu_ucode_validate(const struct firmware *fw);
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
				uint16_t hdr_major, uint16_t hdr_minor);
int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2012 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __AMDGPU_UCODE_H__
	24	#define __AMDGPU_UCODE_H__
	25
	26	struct common_firmware_header {
	27	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
	28	uint32_t header_size_bytes; /* size of just the header in bytes */
	29	uint16_t header_version_major; /* header version */
	30	uint16_t header_version_minor; /* header version */
	31	uint16_t ip_version_major; /* IP version */
	32	uint16_t ip_version_minor; /* IP version */
	33	uint32_t ucode_version;
	34	uint32_t ucode_size_bytes; /* size of ucode in bytes */
	35	uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
	36	uint32_t crc32; /* crc32 checksum of the payload */
	37	};
	38
	39	/* version_major=1, version_minor=0 */
	40	struct mc_firmware_header_v1_0 {
	41	struct common_firmware_header header;
	42	uint32_t io_debug_size_bytes; /* size of debug array in dwords */
	43	uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
	44	};
	45
	46	/* version_major=1, version_minor=0 */
	47	struct smc_firmware_header_v1_0 {
	48	struct common_firmware_header header;
	49	uint32_t ucode_start_addr;
	50	};
	51
	52	/* version_major=1, version_minor=0 */
	53	struct gfx_firmware_header_v1_0 {
	54	struct common_firmware_header header;
	55	uint32_t ucode_feature_version;
	56	uint32_t jt_offset; /* jt location */
	57	uint32_t jt_size; /* size of jt */
	58	};
	59
	60	/* version_major=1, version_minor=0 */
	61	struct rlc_firmware_header_v1_0 {
	62	struct common_firmware_header header;
	63	uint32_t ucode_feature_version;
	64	uint32_t save_and_restore_offset;
65	uint32_t clear_state_descriptor_offset;
66	uint32_t avail_scratch_ram_locations;
67	uint32_t master_pkt_description_offset;
68	};
69
70	/* version_major=2, version_minor=0 */
71	struct rlc_firmware_header_v2_0 {
72	struct common_firmware_header header;
73	uint32_t ucode_feature_version;
74	uint32_t jt_offset; /* jt location */
75	uint32_t jt_size; /* size of jt */
76	uint32_t save_and_restore_offset;
77	uint32_t clear_state_descriptor_offset;
78	uint32_t avail_scratch_ram_locations;
79	uint32_t reg_restore_list_size;
80	uint32_t reg_list_format_start;
81	uint32_t reg_list_format_separate_start;
82	uint32_t starting_offsets_start;
83	uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
84	uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
85	uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
86	uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
87	uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
88	uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
89	uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
90	uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
91	};
92
93	/* version_major=1, version_minor=0 */
94	struct sdma_firmware_header_v1_0 {
95	struct common_firmware_header header;
96	uint32_t ucode_feature_version;
97	uint32_t ucode_change_version;
98	uint32_t jt_offset; /* jt location */
99	uint32_t jt_size; /* size of jt */
100	};
101
102	/* version_major=1, version_minor=1 */
103	struct sdma_firmware_header_v1_1 {
104	struct sdma_firmware_header_v1_0 v1_0;
105	uint32_t digest_size;
106	};
107
108	/* header is fixed size */
109	union amdgpu_firmware_header {
110	struct common_firmware_header common;
111	struct mc_firmware_header_v1_0 mc;
112	struct smc_firmware_header_v1_0 smc;
113	struct gfx_firmware_header_v1_0 gfx;
114	struct rlc_firmware_header_v1_0 rlc;
115	struct rlc_firmware_header_v2_0 rlc_v2_0;
116	struct sdma_firmware_header_v1_0 sdma;
117	struct sdma_firmware_header_v1_1 sdma_v1_1;
118	uint8_t raw[0x100];
119	};
120
121	/*
122	* fw loading support
123	*/
124	enum AMDGPU_UCODE_ID {
125	AMDGPU_UCODE_ID_SDMA0 = 0,
126	AMDGPU_UCODE_ID_SDMA1,
127	AMDGPU_UCODE_ID_CP_CE,
128	AMDGPU_UCODE_ID_CP_PFP,
129	AMDGPU_UCODE_ID_CP_ME,
130	AMDGPU_UCODE_ID_CP_MEC1,
131	AMDGPU_UCODE_ID_CP_MEC2,
132	AMDGPU_UCODE_ID_RLC_G,
133	AMDGPU_UCODE_ID_MAXIMUM,
134	};
135
136	/* engine firmware status */
137	enum AMDGPU_UCODE_STATUS {
138	AMDGPU_UCODE_STATUS_INVALID,
139	AMDGPU_UCODE_STATUS_NOT_LOADED,
140	AMDGPU_UCODE_STATUS_LOADED,
141	};
142
143	/* conform to smu_ucode_xfer_cz.h */
144	#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
145	#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
146	#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
147	#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
148	#define AMDGPU_CPME_UCODE_LOADED 0x00000010
149	#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
150	#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
151	#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
152
153	/* amdgpu firmware info */
154	struct amdgpu_firmware_info {
155	/* ucode ID */
156	enum AMDGPU_UCODE_ID ucode_id;
157	/* request_firmware */
158	const struct firmware *fw;
159	/* starting mc address */
160	uint64_t mc_addr;
161	/* kernel linear address */
162	void *kaddr;
163	};
164
165	void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
166	void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
167	void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
168	void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
169	void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
170	int amdgpu_ucode_validate(const struct firmware *fw);
171	bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
172	uint16_t hdr_major, uint16_t hdr_minor);
173	int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
174	int amdgpu_ucode_fini_bo(struct amdgpu_device *adev);
175
176	#endif