projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: move iommu_resume before ip init/resume
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
fdf2f6c5 27
d38ceaf9
AD		 28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
a6d64c1a
KW		 71 const struct smc_firmware_header_v1_0 *v1_0_hdr;
72 const struct smc_firmware_header_v2_0 *v2_0_hdr;
73 const struct smc_firmware_header_v2_1 *v2_1_hdr;
d38ceaf9
AD		 74
75 DRM_DEBUG("SMC\n");
76 amdgpu_ucode_print_common_hdr(hdr);
77
78 if (version_major == 1) {
a6d64c1a
KW		 79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
336a1c82 81 } else if (version_major == 2) {
a6d64c1a
KW		 82 switch (version_minor) {
83 case 0:
84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
87 break;
88 case 1:
89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
92 break;
93 default:
94 break;
95 }
336a1c82 96
d38ceaf9
AD		 97 } else {
98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
99 }
100}
101
102void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
103{
104 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
106
107 DRM_DEBUG("GFX\n");
108 amdgpu_ucode_print_common_hdr(hdr);
109
110 if (version_major == 1) {
111 const struct gfx_firmware_header_v1_0 *gfx_hdr =
112 container_of(hdr, struct gfx_firmware_header_v1_0, header);
113
114 DRM_DEBUG("ucode_feature_version: %u\n",
115 le32_to_cpu(gfx_hdr->ucode_feature_version));
116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
118 } else {
119 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
120 }
121}
122
123void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
124{
125 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
126 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
127
128 DRM_DEBUG("RLC\n");
129 amdgpu_ucode_print_common_hdr(hdr);
130
131 if (version_major == 1) {
132 const struct rlc_firmware_header_v1_0 *rlc_hdr =
133 container_of(hdr, struct rlc_firmware_header_v1_0, header);
134
135 DRM_DEBUG("ucode_feature_version: %u\n",
136 le32_to_cpu(rlc_hdr->ucode_feature_version));
137 DRM_DEBUG("save_and_restore_offset: %u\n",
138 le32_to_cpu(rlc_hdr->save_and_restore_offset));
139 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
140 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
141 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
142 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
143 DRM_DEBUG("master_pkt_description_offset: %u\n",
144 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
145 } else if (version_major == 2) {
146 const struct rlc_firmware_header_v2_0 *rlc_hdr =
147 container_of(hdr, struct rlc_firmware_header_v2_0, header);
148
149 DRM_DEBUG("ucode_feature_version: %u\n",
150 le32_to_cpu(rlc_hdr->ucode_feature_version));
151 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
152 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
153 DRM_DEBUG("save_and_restore_offset: %u\n",
154 le32_to_cpu(rlc_hdr->save_and_restore_offset));
155 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
156 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
157 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
158 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
159 DRM_DEBUG("reg_restore_list_size: %u\n",
160 le32_to_cpu(rlc_hdr->reg_restore_list_size));
161 DRM_DEBUG("reg_list_format_start: %u\n",
162 le32_to_cpu(rlc_hdr->reg_list_format_start));
163 DRM_DEBUG("reg_list_format_separate_start: %u\n",
164 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
165 DRM_DEBUG("starting_offsets_start: %u\n",
166 le32_to_cpu(rlc_hdr->starting_offsets_start));
167 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
168 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
169 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
170 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
171 DRM_DEBUG("reg_list_size_bytes: %u\n",
172 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
173 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
174 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
175 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
176 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
177 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
178 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
179 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
180 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
d40e9b13
HR		 181 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
182 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
183 if (version_minor == 1) {
184 const struct rlc_firmware_header_v2_1 *v2_1 =
185 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
186 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
187 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
188 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
189 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
190 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
191 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
192 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
193 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
194 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
195 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
196 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
197 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
198 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
199 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
200 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
201 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
202 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
203 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
204 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
205 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
206 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
207 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
208 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
209 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
210 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
211 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
212 }
d38ceaf9
AD		 213 } else {
214 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
215 }
216}
217
218void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
219{
220 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
221 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
222
223 DRM_DEBUG("SDMA\n");
224 amdgpu_ucode_print_common_hdr(hdr);
225
226 if (version_major == 1) {
227 const struct sdma_firmware_header_v1_0 *sdma_hdr =
228 container_of(hdr, struct sdma_firmware_header_v1_0, header);
229
230 DRM_DEBUG("ucode_feature_version: %u\n",
231 le32_to_cpu(sdma_hdr->ucode_feature_version));
232 DRM_DEBUG("ucode_change_version: %u\n",
233 le32_to_cpu(sdma_hdr->ucode_change_version));
234 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
235 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
236 if (version_minor >= 1) {
237 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
238 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
239 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
240 }
241 } else {
242 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
243 version_major, version_minor);
244 }
245}
246
6fa40564
HZ		 247void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
248{
249 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
250 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
251
252 DRM_DEBUG("PSP\n");
253 amdgpu_ucode_print_common_hdr(hdr);
254
255 if (version_major == 1) {
256 const struct psp_firmware_header_v1_0 *psp_hdr =
257 container_of(hdr, struct psp_firmware_header_v1_0, header);
258
259 DRM_DEBUG("ucode_feature_version: %u\n",
79a0f441 260 le32_to_cpu(psp_hdr->sos.fw_version));
6fa40564 261 DRM_DEBUG("sos_offset_bytes: %u\n",
79a0f441 262 le32_to_cpu(psp_hdr->sos.offset_bytes));
6fa40564 263 DRM_DEBUG("sos_size_bytes: %u\n",
79a0f441 264 le32_to_cpu(psp_hdr->sos.size_bytes));
434dbb2a
HZ		 265 if (version_minor == 1) {
266 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
267 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
268 DRM_DEBUG("toc_header_version: %u\n",
79a0f441 269 le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
434dbb2a 270 DRM_DEBUG("toc_offset_bytes: %u\n",
79a0f441 271 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
434dbb2a 272 DRM_DEBUG("toc_size_bytes: %u\n",
79a0f441 273 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
42989359 274 DRM_DEBUG("kdb_header_version: %u\n",
79a0f441 275 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
42989359 276 DRM_DEBUG("kdb_offset_bytes: %u\n",
79a0f441 277 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
42989359 278 DRM_DEBUG("kdb_size_bytes: %u\n",
79a0f441 279 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
434dbb2a 280 }
dc0d9622
JC		 281 if (version_minor == 2) {
282 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
283 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
284 DRM_DEBUG("kdb_header_version: %u\n",
79a0f441 285 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
dc0d9622 286 DRM_DEBUG("kdb_offset_bytes: %u\n",
79a0f441 287 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
dc0d9622 288 DRM_DEBUG("kdb_size_bytes: %u\n",
79a0f441 289 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
dc0d9622 290 }
43a188e0
LG		 291 if (version_minor == 3) {
292 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
293 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
294 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
295 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
296 DRM_DEBUG("toc_header_version: %u\n",
79a0f441 297 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
43a188e0 298 DRM_DEBUG("toc_offset_bytes: %u\n",
79a0f441 299 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
43a188e0 300 DRM_DEBUG("toc_size_bytes: %u\n",
79a0f441 301 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
43a188e0 302 DRM_DEBUG("kdb_header_version: %u\n",
79a0f441 303 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
43a188e0 304 DRM_DEBUG("kdb_offset_bytes: %u\n",
79a0f441 305 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
43a188e0 306 DRM_DEBUG("kdb_size_bytes: %u\n",
79a0f441 307 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
43a188e0 308 DRM_DEBUG("spl_header_version: %u\n",
79a0f441 309 le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
43a188e0 310 DRM_DEBUG("spl_offset_bytes: %u\n",
79a0f441 311 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
43a188e0 312 DRM_DEBUG("spl_size_bytes: %u\n",
79a0f441 313 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
43a188e0 314 }
6fa40564
HZ		 315 } else {
316 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
317 version_major, version_minor);
318 }
319}
320
8ae1a336
AD		 321void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
322{
323 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
324 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
325
326 DRM_DEBUG("GPU_INFO\n");
327 amdgpu_ucode_print_common_hdr(hdr);
328
329 if (version_major == 1) {
330 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
331 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
332
333 DRM_DEBUG("version_major: %u\n",
334 le16_to_cpu(gpu_info_hdr->version_major));
335 DRM_DEBUG("version_minor: %u\n",
336 le16_to_cpu(gpu_info_hdr->version_minor));
337 } else {
338 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
339 }
340}
341
d38ceaf9
AD		 342int amdgpu_ucode_validate(const struct firmware *fw)
343{
344 const struct common_firmware_header *hdr =
345 (const struct common_firmware_header *)fw->data;
346
347 if (fw->size == le32_to_cpu(hdr->size_bytes))
348 return 0;
349
350 return -EINVAL;
351}
352
353bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
354 uint16_t hdr_major, uint16_t hdr_minor)
355{
356 if ((hdr->common.header_version_major == hdr_major) &&
357 (hdr->common.header_version_minor == hdr_minor))
358 return false;
359 return true;
360}
361
e635ee07
HR		 362enum amdgpu_firmware_load_type
363amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
364{
365 switch (adev->asic_type) {
366#ifdef CONFIG_DRM_AMDGPU_SI
367 case CHIP_TAHITI:
368 case CHIP_PITCAIRN:
369 case CHIP_VERDE:
370 case CHIP_OLAND:
d9997b64 371 case CHIP_HAINAN:
e635ee07
HR		 372 return AMDGPU_FW_LOAD_DIRECT;
373#endif
374#ifdef CONFIG_DRM_AMDGPU_CIK
375 case CHIP_BONAIRE:
376 case CHIP_KAVERI:
377 case CHIP_KABINI:
378 case CHIP_HAWAII:
379 case CHIP_MULLINS:
380 return AMDGPU_FW_LOAD_DIRECT;
381#endif
382 case CHIP_TOPAZ:
383 case CHIP_TONGA:
384 case CHIP_FIJI:
385 case CHIP_CARRIZO:
386 case CHIP_STONEY:
387 case CHIP_POLARIS10:
388 case CHIP_POLARIS11:
389 case CHIP_POLARIS12:
34fd54bc 390 case CHIP_VEGAM:
9b008fb7 391 return AMDGPU_FW_LOAD_SMU;
e635ee07 392 case CHIP_VEGA10:
4456ef4e 393 case CHIP_RAVEN:
6b9c6e1b 394 case CHIP_VEGA12:
0df5295c 395 case CHIP_VEGA20:
90c88dab 396 case CHIP_ARCTURUS:
8deac236 397 case CHIP_RENOIR:
bb67469e 398 case CHIP_NAVI10:
e2d2607f 399 case CHIP_NAVI14:
d4d838ba 400 case CHIP_NAVI12:
d4f3c390 401 case CHIP_SIENNA_CICHLID:
f081e697 402 case CHIP_NAVY_FLOUNDER:
ed3b7353 403 case CHIP_VANGOGH:
f897ea35 404 case CHIP_DIMGREY_CAVEFISH:
2f669734 405 case CHIP_ALDEBARAN:
c0729819 406 case CHIP_BEIGE_GOBY:
531d6e5d 407 case CHIP_YELLOW_CARP:
50811c71 408 if (!load_type)
4456ef4e
CZ		 409 return AMDGPU_FW_LOAD_DIRECT;
410 else
411 return AMDGPU_FW_LOAD_PSP;
d594e3cc 412 case CHIP_CYAN_SKILLFISH:
b8e42844
HR		 413 if (!(load_type &&
414 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
415 return AMDGPU_FW_LOAD_DIRECT;
416 else
c5d0aa48 417 return AMDGPU_FW_LOAD_PSP;
e635ee07 418 default:
bc8282a7 419 DRM_ERROR("Unknown firmware load type\n");
e635ee07
HR		 420 }
421
422 return AMDGPU_FW_LOAD_DIRECT;
423}
424
aae435c6
LY		 425const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
426{
427 switch (ucode_id) {
428 case AMDGPU_UCODE_ID_SDMA0:
429 return "SDMA0";
430 case AMDGPU_UCODE_ID_SDMA1:
431 return "SDMA1";
432 case AMDGPU_UCODE_ID_SDMA2:
433 return "SDMA2";
434 case AMDGPU_UCODE_ID_SDMA3:
435 return "SDMA3";
436 case AMDGPU_UCODE_ID_SDMA4:
437 return "SDMA4";
438 case AMDGPU_UCODE_ID_SDMA5:
439 return "SDMA5";
440 case AMDGPU_UCODE_ID_SDMA6:
441 return "SDMA6";
442 case AMDGPU_UCODE_ID_SDMA7:
443 return "SDMA7";
444 case AMDGPU_UCODE_ID_CP_CE:
445 return "CP_CE";
446 case AMDGPU_UCODE_ID_CP_PFP:
447 return "CP_PFP";
448 case AMDGPU_UCODE_ID_CP_ME:
449 return "CP_ME";
450 case AMDGPU_UCODE_ID_CP_MEC1:
451 return "CP_MEC1";
452 case AMDGPU_UCODE_ID_CP_MEC1_JT:
453 return "CP_MEC1_JT";
454 case AMDGPU_UCODE_ID_CP_MEC2:
455 return "CP_MEC2";
456 case AMDGPU_UCODE_ID_CP_MEC2_JT:
457 return "CP_MEC2_JT";
458 case AMDGPU_UCODE_ID_CP_MES:
459 return "CP_MES";
460 case AMDGPU_UCODE_ID_CP_MES_DATA:
461 return "CP_MES_DATA";
462 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
463 return "RLC_RESTORE_LIST_CNTL";
464 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
465 return "RLC_RESTORE_LIST_GPM_MEM";
466 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
467 return "RLC_RESTORE_LIST_SRM_MEM";
468 case AMDGPU_UCODE_ID_RLC_IRAM:
469 return "RLC_IRAM";
470 case AMDGPU_UCODE_ID_RLC_DRAM:
471 return "RLC_DRAM";
472 case AMDGPU_UCODE_ID_RLC_G:
473 return "RLC_G";
474 case AMDGPU_UCODE_ID_STORAGE:
475 return "STORAGE";
476 case AMDGPU_UCODE_ID_SMC:
477 return "SMC";
478 case AMDGPU_UCODE_ID_UVD:
479 return "UVD";
480 case AMDGPU_UCODE_ID_UVD1:
481 return "UVD1";
482 case AMDGPU_UCODE_ID_VCE:
483 return "VCE";
484 case AMDGPU_UCODE_ID_VCN:
485 return "VCN";
486 case AMDGPU_UCODE_ID_VCN1:
487 return "VCN1";
488 case AMDGPU_UCODE_ID_DMCU_ERAM:
489 return "DMCU_ERAM";
490 case AMDGPU_UCODE_ID_DMCU_INTV:
491 return "DMCU_INTV";
492 case AMDGPU_UCODE_ID_VCN0_RAM:
493 return "VCN0_RAM";
494 case AMDGPU_UCODE_ID_VCN1_RAM:
495 return "VCN1_RAM";
496 case AMDGPU_UCODE_ID_DMCUB:
497 return "DMCUB";
498 default:
499 return "UNKNOWN UCODE";
500 }
501}
502
5bb23532
OM		 503#define FW_VERSION_ATTR(name, mode, field) \
504static ssize_t show_##name(struct device *dev, \
505 struct device_attribute *attr, \
506 char *buf) \
507{ \
508 struct drm_device *ddev = dev_get_drvdata(dev); \
1348969a 509 struct amdgpu_device *adev = drm_to_adev(ddev); \
5bb23532
OM		 510 \
511 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \
512} \
513static DEVICE_ATTR(name, mode, show_##name, NULL)
514
515FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
516FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
517FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
518FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
519FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
520FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
521FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
522FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
523FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
524FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
525FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
526FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
222e0a71 527FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
6457205c
CL		 528FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd.fw_version);
529FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras.feature_version);
530FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi.feature_version);
5bb23532
OM		 531FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
532FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
533FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
534FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
535FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
536
537static struct attribute *fw_attrs[] = {
538 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
539 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
540 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
541 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
542 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
543 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
544 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
545 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
546 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
547 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
548 &dev_attr_dmcu_fw_version.attr, NULL
549};
550
551static const struct attribute_group fw_attr_group = {
552 .name = "fw_version",
553 .attrs = fw_attrs
554};
555
556int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
557{
558 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
559}
560
561void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
562{
563 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
564}
565
2445b227
HR		 566static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
567 struct amdgpu_firmware_info *ucode,
568 uint64_t mc_addr, void *kptr)
d38ceaf9
AD		 569{
570 const struct common_firmware_header *header = NULL;
2445b227 571 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
01fcfc83 572 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
02350f0b 573 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
aa1faaa1 574 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
02f958a2 575 u8 *ucode_addr;
d38ceaf9
AD		 576
577 if (NULL == ucode->fw)
578 return 0;
579
580 ucode->mc_addr = mc_addr;
581 ucode->kaddr = kptr;
582
bed5712e
ML		 583 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
584 return 0;
585
d38ceaf9 586 header = (const struct common_firmware_header *)ucode->fw->data;
2445b227 587 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
01fcfc83 588 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
02350f0b 589 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
aa1faaa1 590 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
2445b227 591
02f958a2
LG		 592 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
593 switch (ucode->ucode_id) {
594 case AMDGPU_UCODE_ID_CP_MEC1:
595 case AMDGPU_UCODE_ID_CP_MEC2:
596 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
597 le32_to_cpu(cp_hdr->jt_size) * 4;
598 ucode_addr = (u8 *)ucode->fw->data +
599 le32_to_cpu(header->ucode_array_offset_bytes);
600 break;
601 case AMDGPU_UCODE_ID_CP_MEC1_JT:
602 case AMDGPU_UCODE_ID_CP_MEC2_JT:
603 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
604 ucode_addr = (u8 *)ucode->fw->data +
605 le32_to_cpu(header->ucode_array_offset_bytes) +
606 le32_to_cpu(cp_hdr->jt_offset) * 4;
607 break;
608 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
609 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
610 ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
611 break;
612 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
613 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
614 ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
615 break;
616 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
617 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
618 ucode_addr = adev->gfx.rlc.save_restore_list_srm;
619 break;
620 case AMDGPU_UCODE_ID_RLC_IRAM:
621 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
622 ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
623 break;
624 case AMDGPU_UCODE_ID_RLC_DRAM:
625 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
626 ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
627 break;
628 case AMDGPU_UCODE_ID_CP_MES:
629 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
630 ucode_addr = (u8 *)ucode->fw->data +
631 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
632 break;
633 case AMDGPU_UCODE_ID_CP_MES_DATA:
634 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
635 ucode_addr = (u8 *)ucode->fw->data +
636 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
637 break;
638 case AMDGPU_UCODE_ID_DMCU_ERAM:
639 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
01fcfc83 640 le32_to_cpu(dmcu_hdr->intv_size_bytes);
02f958a2
LG		 641 ucode_addr = (u8 *)ucode->fw->data +
642 le32_to_cpu(header->ucode_array_offset_bytes);
643 break;
644 case AMDGPU_UCODE_ID_DMCU_INTV:
645 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
646 ucode_addr = (u8 *)ucode->fw->data +
647 le32_to_cpu(header->ucode_array_offset_bytes) +
648 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
649 break;
650 case AMDGPU_UCODE_ID_DMCUB:
651 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
652 ucode_addr = (u8 *)ucode->fw->data +
653 le32_to_cpu(header->ucode_array_offset_bytes);
654 break;
655 default:
656 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
657 ucode_addr = (u8 *)ucode->fw->data +
658 le32_to_cpu(header->ucode_array_offset_bytes);
659 break;
660 }
661 } else {
662 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
663 ucode_addr = (u8 *)ucode->fw->data +
664 le32_to_cpu(header->ucode_array_offset_bytes);
2445b227 665 }
d38ceaf9 666
02f958a2
LG		 667 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
668
d38ceaf9
AD		 669 return 0;
670}
671
4c2b2453
ML		 672static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
673 uint64_t mc_addr, void *kptr)
674{
675 const struct gfx_firmware_header_v1_0 *header = NULL;
676 const struct common_firmware_header *comm_hdr = NULL;
c4c5ae67
DV		 677 uint8_t *src_addr = NULL;
678 uint8_t *dst_addr = NULL;
4c2b2453
ML		 679
680 if (NULL == ucode->fw)
681 return 0;
682
683 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
684 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
685 dst_addr = ucode->kaddr +
686 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
687 PAGE_SIZE);
688 src_addr = (uint8_t *)ucode->fw->data +
689 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
690 (le32_to_cpu(header->jt_offset) * 4);
691 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
692
693 return 0;
694}
695
c8963ea4
RZ		 696int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
697{
698 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
699 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
700 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
701 &adev->firmware.fw_buf,
702 &adev->firmware.fw_buf_mc,
703 &adev->firmware.fw_buf_ptr);
704 if (!adev->firmware.fw_buf) {
705 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
706 return -ENOMEM;
707 } else if (amdgpu_sriov_vf(adev)) {
708 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
709 }
710 }
711 return 0;
712}
713
714void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
715{
716 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
717 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
718 &adev->firmware.fw_buf_mc,
719 &adev->firmware.fw_buf_ptr);
720}
721
d38ceaf9
AD		 722int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
723{
d38ceaf9 724 uint64_t fw_offset = 0;
c8963ea4 725 int i;
d38ceaf9 726 struct amdgpu_firmware_info *ucode = NULL;
d38ceaf9 727
c8963ea4 728 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
53b3f8f4 729 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
7504938f 730 return 0;
e635ee07
HR		 731 /*
732 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
733 * ucode info here
734 */
bc108ec7
TH		 735 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
736 if (amdgpu_sriov_vf(adev))
737 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
738 else
739 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
740 } else {
2445b227 741 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
bc108ec7 742 }
e635ee07 743
2445b227 744 for (i = 0; i < adev->firmware.max_ucodes; i++) {
d38ceaf9
AD		 745 ucode = &adev->firmware.ucode[i];
746 if (ucode->fw) {
d59c026b
ML		 747 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
748 adev->firmware.fw_buf_ptr + fw_offset);
2445b227
HR		 749 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
750 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
4c2b2453
ML		 751 const struct gfx_firmware_header_v1_0 *cp_hdr;
752 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
d59c026b
ML		 753 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
754 adev->firmware.fw_buf_ptr + fw_offset);
4c2b2453
ML		 755 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
756 }
2445b227 757 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
d38ceaf9
AD		 758 }
759 }
fd506558 760 return 0;
d38ceaf9 761}
Linux 6.x block layer and io_uring tree(s)