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drm/amdgpu: enable HDP clock gatting
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
fdf2f6c5 27
d38ceaf9
AD		 28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71
72 DRM_DEBUG("SMC\n");
73 amdgpu_ucode_print_common_hdr(hdr);
74
75 if (version_major == 1) {
76 const struct smc_firmware_header_v1_0 *smc_hdr =
77 container_of(hdr, struct smc_firmware_header_v1_0, header);
78
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
336a1c82
HR		 80 } else if (version_major == 2) {
81 const struct smc_firmware_header_v1_0 *v1_hdr =
82 container_of(hdr, struct smc_firmware_header_v1_0, header);
83 const struct smc_firmware_header_v2_0 *v2_hdr =
84 container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0);
85
6c2243ef
XY		 86 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
87 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
d38ceaf9
AD		 88 } else {
89 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
90 }
91}
92
93void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
94{
95 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
96 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
97
98 DRM_DEBUG("GFX\n");
99 amdgpu_ucode_print_common_hdr(hdr);
100
101 if (version_major == 1) {
102 const struct gfx_firmware_header_v1_0 *gfx_hdr =
103 container_of(hdr, struct gfx_firmware_header_v1_0, header);
104
105 DRM_DEBUG("ucode_feature_version: %u\n",
106 le32_to_cpu(gfx_hdr->ucode_feature_version));
107 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
108 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
109 } else {
110 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
111 }
112}
113
114void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
115{
116 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
117 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
118
119 DRM_DEBUG("RLC\n");
120 amdgpu_ucode_print_common_hdr(hdr);
121
122 if (version_major == 1) {
123 const struct rlc_firmware_header_v1_0 *rlc_hdr =
124 container_of(hdr, struct rlc_firmware_header_v1_0, header);
125
126 DRM_DEBUG("ucode_feature_version: %u\n",
127 le32_to_cpu(rlc_hdr->ucode_feature_version));
128 DRM_DEBUG("save_and_restore_offset: %u\n",
129 le32_to_cpu(rlc_hdr->save_and_restore_offset));
130 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
131 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
132 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
133 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
134 DRM_DEBUG("master_pkt_description_offset: %u\n",
135 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
136 } else if (version_major == 2) {
137 const struct rlc_firmware_header_v2_0 *rlc_hdr =
138 container_of(hdr, struct rlc_firmware_header_v2_0, header);
139
140 DRM_DEBUG("ucode_feature_version: %u\n",
141 le32_to_cpu(rlc_hdr->ucode_feature_version));
142 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
143 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
144 DRM_DEBUG("save_and_restore_offset: %u\n",
145 le32_to_cpu(rlc_hdr->save_and_restore_offset));
146 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
147 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
148 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
149 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
150 DRM_DEBUG("reg_restore_list_size: %u\n",
151 le32_to_cpu(rlc_hdr->reg_restore_list_size));
152 DRM_DEBUG("reg_list_format_start: %u\n",
153 le32_to_cpu(rlc_hdr->reg_list_format_start));
154 DRM_DEBUG("reg_list_format_separate_start: %u\n",
155 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
156 DRM_DEBUG("starting_offsets_start: %u\n",
157 le32_to_cpu(rlc_hdr->starting_offsets_start));
158 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
159 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
160 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
161 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
162 DRM_DEBUG("reg_list_size_bytes: %u\n",
163 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
164 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
165 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
166 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
167 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
168 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
169 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
170 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
171 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
d40e9b13
HR		 172 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
173 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
174 if (version_minor == 1) {
175 const struct rlc_firmware_header_v2_1 *v2_1 =
176 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
177 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
178 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
179 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
180 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
181 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
182 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
183 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
184 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
185 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
186 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
187 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
188 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
189 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
190 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
191 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
192 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
193 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
194 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
195 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
196 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
197 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
198 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
199 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
200 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
201 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
202 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
203 }
d38ceaf9
AD		 204 } else {
205 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
206 }
207}
208
209void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
210{
211 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
212 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
213
214 DRM_DEBUG("SDMA\n");
215 amdgpu_ucode_print_common_hdr(hdr);
216
217 if (version_major == 1) {
218 const struct sdma_firmware_header_v1_0 *sdma_hdr =
219 container_of(hdr, struct sdma_firmware_header_v1_0, header);
220
221 DRM_DEBUG("ucode_feature_version: %u\n",
222 le32_to_cpu(sdma_hdr->ucode_feature_version));
223 DRM_DEBUG("ucode_change_version: %u\n",
224 le32_to_cpu(sdma_hdr->ucode_change_version));
225 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
226 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
227 if (version_minor >= 1) {
228 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
229 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
230 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
231 }
232 } else {
233 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
234 version_major, version_minor);
235 }
236}
237
6fa40564
HZ		 238void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
239{
240 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
241 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
242
243 DRM_DEBUG("PSP\n");
244 amdgpu_ucode_print_common_hdr(hdr);
245
246 if (version_major == 1) {
247 const struct psp_firmware_header_v1_0 *psp_hdr =
248 container_of(hdr, struct psp_firmware_header_v1_0, header);
249
250 DRM_DEBUG("ucode_feature_version: %u\n",
251 le32_to_cpu(psp_hdr->ucode_feature_version));
252 DRM_DEBUG("sos_offset_bytes: %u\n",
253 le32_to_cpu(psp_hdr->sos_offset_bytes));
254 DRM_DEBUG("sos_size_bytes: %u\n",
255 le32_to_cpu(psp_hdr->sos_size_bytes));
434dbb2a
HZ		 256 if (version_minor == 1) {
257 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
258 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
259 DRM_DEBUG("toc_header_version: %u\n",
260 le32_to_cpu(psp_hdr_v1_1->toc_header_version));
261 DRM_DEBUG("toc_offset_bytes: %u\n",
262 le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
263 DRM_DEBUG("toc_size_bytes: %u\n",
264 le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
42989359
HZ		 265 DRM_DEBUG("kdb_header_version: %u\n",
266 le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
267 DRM_DEBUG("kdb_offset_bytes: %u\n",
268 le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
269 DRM_DEBUG("kdb_size_bytes: %u\n",
270 le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
434dbb2a 271 }
dc0d9622
JC		 272 if (version_minor == 2) {
273 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
274 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
275 DRM_DEBUG("kdb_header_version: %u\n",
276 le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
277 DRM_DEBUG("kdb_offset_bytes: %u\n",
278 le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
279 DRM_DEBUG("kdb_size_bytes: %u\n",
280 le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
281 }
43a188e0
LG		 282 if (version_minor == 3) {
283 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
284 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
285 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
286 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
287 DRM_DEBUG("toc_header_version: %u\n",
288 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version));
289 DRM_DEBUG("toc_offset_bytes: %u\n",
290 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes));
291 DRM_DEBUG("toc_size_bytes: %u\n",
292 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes));
293 DRM_DEBUG("kdb_header_version: %u\n",
294 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version));
295 DRM_DEBUG("kdb_offset_bytes: %u\n",
296 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes));
297 DRM_DEBUG("kdb_size_bytes: %u\n",
298 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes));
299 DRM_DEBUG("spl_header_version: %u\n",
300 le32_to_cpu(psp_hdr_v1_3->spl_header_version));
301 DRM_DEBUG("spl_offset_bytes: %u\n",
302 le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes));
303 DRM_DEBUG("spl_size_bytes: %u\n",
304 le32_to_cpu(psp_hdr_v1_3->spl_size_bytes));
305 }
6fa40564
HZ		 306 } else {
307 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
308 version_major, version_minor);
309 }
310}
311
8ae1a336
AD		 312void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
313{
314 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
315 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
316
317 DRM_DEBUG("GPU_INFO\n");
318 amdgpu_ucode_print_common_hdr(hdr);
319
320 if (version_major == 1) {
321 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
322 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
323
324 DRM_DEBUG("version_major: %u\n",
325 le16_to_cpu(gpu_info_hdr->version_major));
326 DRM_DEBUG("version_minor: %u\n",
327 le16_to_cpu(gpu_info_hdr->version_minor));
328 } else {
329 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
330 }
331}
332
d38ceaf9
AD		 333int amdgpu_ucode_validate(const struct firmware *fw)
334{
335 const struct common_firmware_header *hdr =
336 (const struct common_firmware_header *)fw->data;
337
338 if (fw->size == le32_to_cpu(hdr->size_bytes))
339 return 0;
340
341 return -EINVAL;
342}
343
344bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
345 uint16_t hdr_major, uint16_t hdr_minor)
346{
347 if ((hdr->common.header_version_major == hdr_major) &&
348 (hdr->common.header_version_minor == hdr_minor))
349 return false;
350 return true;
351}
352
e635ee07
HR		 353enum amdgpu_firmware_load_type
354amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
355{
356 switch (adev->asic_type) {
357#ifdef CONFIG_DRM_AMDGPU_SI
358 case CHIP_TAHITI:
359 case CHIP_PITCAIRN:
360 case CHIP_VERDE:
361 case CHIP_OLAND:
d9997b64 362 case CHIP_HAINAN:
e635ee07
HR		 363 return AMDGPU_FW_LOAD_DIRECT;
364#endif
365#ifdef CONFIG_DRM_AMDGPU_CIK
366 case CHIP_BONAIRE:
367 case CHIP_KAVERI:
368 case CHIP_KABINI:
369 case CHIP_HAWAII:
370 case CHIP_MULLINS:
371 return AMDGPU_FW_LOAD_DIRECT;
372#endif
373 case CHIP_TOPAZ:
374 case CHIP_TONGA:
375 case CHIP_FIJI:
376 case CHIP_CARRIZO:
377 case CHIP_STONEY:
378 case CHIP_POLARIS10:
379 case CHIP_POLARIS11:
380 case CHIP_POLARIS12:
34fd54bc 381 case CHIP_VEGAM:
9b008fb7 382 return AMDGPU_FW_LOAD_SMU;
e635ee07 383 case CHIP_VEGA10:
4456ef4e 384 case CHIP_RAVEN:
6b9c6e1b 385 case CHIP_VEGA12:
0df5295c 386 case CHIP_VEGA20:
90c88dab 387 case CHIP_ARCTURUS:
8deac236 388 case CHIP_RENOIR:
bb67469e 389 case CHIP_NAVI10:
e2d2607f 390 case CHIP_NAVI14:
d4d838ba 391 case CHIP_NAVI12:
d4f3c390 392 case CHIP_SIENNA_CICHLID:
f081e697 393 case CHIP_NAVY_FLOUNDER:
50811c71 394 if (!load_type)
4456ef4e
CZ		 395 return AMDGPU_FW_LOAD_DIRECT;
396 else
397 return AMDGPU_FW_LOAD_PSP;
e635ee07 398 default:
bc8282a7 399 DRM_ERROR("Unknown firmware load type\n");
e635ee07
HR		 400 }
401
402 return AMDGPU_FW_LOAD_DIRECT;
403}
404
5bb23532
OM		 405#define FW_VERSION_ATTR(name, mode, field) \
406static ssize_t show_##name(struct device *dev, \
407 struct device_attribute *attr, \
408 char *buf) \
409{ \
410 struct drm_device *ddev = dev_get_drvdata(dev); \
411 struct amdgpu_device *adev = ddev->dev_private; \
412 \
413 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \
414} \
415static DEVICE_ATTR(name, mode, show_##name, NULL)
416
417FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
418FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
419FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
420FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
421FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
422FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
423FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
424FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
425FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
426FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
427FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
428FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
429FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version);
430FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version);
358e00e0
KR		 431FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version);
432FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version);
5bb23532
OM		 433FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
434FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
435FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
436FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
437FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
438
439static struct attribute *fw_attrs[] = {
440 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
441 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
442 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
443 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
444 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
445 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
446 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
447 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
448 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
449 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
450 &dev_attr_dmcu_fw_version.attr, NULL
451};
452
453static const struct attribute_group fw_attr_group = {
454 .name = "fw_version",
455 .attrs = fw_attrs
456};
457
458int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
459{
460 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
461}
462
463void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
464{
465 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
466}
467
2445b227
HR		 468static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
469 struct amdgpu_firmware_info *ucode,
470 uint64_t mc_addr, void *kptr)
d38ceaf9
AD		 471{
472 const struct common_firmware_header *header = NULL;
2445b227 473 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
01fcfc83 474 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
02350f0b 475 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
aa1faaa1 476 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
d38ceaf9
AD		 477
478 if (NULL == ucode->fw)
479 return 0;
480
481 ucode->mc_addr = mc_addr;
482 ucode->kaddr = kptr;
483
bed5712e
ML		 484 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
485 return 0;
486
d38ceaf9 487 header = (const struct common_firmware_header *)ucode->fw->data;
2445b227 488 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
01fcfc83 489 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
02350f0b 490 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
aa1faaa1 491 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
2445b227
HR		 492
493 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
494 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
495 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
496 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
621a6318 497 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
aa1faaa1
JX		 498 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&
499 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&
621a6318
HR		 500 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
501 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
01fcfc83
DF		 502 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
503 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
02350f0b
NK		 504 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
505 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
2445b227
HR		 506 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
507
508 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
509 le32_to_cpu(header->ucode_array_offset_bytes)),
510 ucode->ucode_size);
511 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
512 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
513 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
514 le32_to_cpu(cp_hdr->jt_size) * 4;
515
516 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
517 le32_to_cpu(header->ucode_array_offset_bytes)),
518 ucode->ucode_size);
519 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
520 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
521 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
522
523 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
524 le32_to_cpu(header->ucode_array_offset_bytes) +
525 le32_to_cpu(cp_hdr->jt_offset) * 4),
526 ucode->ucode_size);
01fcfc83
DF		 527 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
528 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
529 le32_to_cpu(dmcu_hdr->intv_size_bytes);
530
531 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
532 le32_to_cpu(header->ucode_array_offset_bytes)),
533 ucode->ucode_size);
534 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
535 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
536
537 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
538 le32_to_cpu(header->ucode_array_offset_bytes) +
539 le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
540 ucode->ucode_size);
02350f0b
NK		 541 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
542 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
543 memcpy(ucode->kaddr,
544 (void *)((uint8_t *)ucode->fw->data +
545 le32_to_cpu(header->ucode_array_offset_bytes)),
546 ucode->ucode_size);
621a6318
HR		 547 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
548 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
549 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
550 ucode->ucode_size);
551 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
552 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
553 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
554 ucode->ucode_size);
555 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
556 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
557 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
558 ucode->ucode_size);
aa1faaa1
JX		 559 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
560 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
561 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
562 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),
563 ucode->ucode_size);
564 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {
565 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
566 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
567 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),
568 ucode->ucode_size);
2445b227 569 }
d38ceaf9
AD		 570
571 return 0;
572}
573
4c2b2453
ML		 574static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
575 uint64_t mc_addr, void *kptr)
576{
577 const struct gfx_firmware_header_v1_0 *header = NULL;
578 const struct common_firmware_header *comm_hdr = NULL;
579 uint8_t* src_addr = NULL;
580 uint8_t* dst_addr = NULL;
581
582 if (NULL == ucode->fw)
583 return 0;
584
585 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
586 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
587 dst_addr = ucode->kaddr +
588 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
589 PAGE_SIZE);
590 src_addr = (uint8_t *)ucode->fw->data +
591 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
592 (le32_to_cpu(header->jt_offset) * 4);
593 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
594
595 return 0;
596}
597
c8963ea4
RZ		 598int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
599{
600 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
601 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
602 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
603 &adev->firmware.fw_buf,
604 &adev->firmware.fw_buf_mc,
605 &adev->firmware.fw_buf_ptr);
606 if (!adev->firmware.fw_buf) {
607 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
608 return -ENOMEM;
609 } else if (amdgpu_sriov_vf(adev)) {
610 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
611 }
612 }
613 return 0;
614}
615
616void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
617{
618 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
619 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
620 &adev->firmware.fw_buf_mc,
621 &adev->firmware.fw_buf_ptr);
622}
623
d38ceaf9
AD		 624int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
625{
d38ceaf9 626 uint64_t fw_offset = 0;
c8963ea4 627 int i;
d38ceaf9 628 struct amdgpu_firmware_info *ucode = NULL;
d38ceaf9 629
c8963ea4 630 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
53b3f8f4 631 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
7504938f 632 return 0;
e635ee07
HR		 633 /*
634 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
635 * ucode info here
636 */
bc108ec7
TH		 637 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
638 if (amdgpu_sriov_vf(adev))
639 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
640 else
641 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
642 } else {
2445b227 643 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
bc108ec7 644 }
e635ee07 645
2445b227 646 for (i = 0; i < adev->firmware.max_ucodes; i++) {
d38ceaf9
AD		 647 ucode = &adev->firmware.ucode[i];
648 if (ucode->fw) {
d59c026b
ML		 649 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
650 adev->firmware.fw_buf_ptr + fw_offset);
2445b227
HR		 651 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
652 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
4c2b2453
ML		 653 const struct gfx_firmware_header_v1_0 *cp_hdr;
654 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
d59c026b
ML		 655 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
656 adev->firmware.fw_buf_ptr + fw_offset);
4c2b2453
ML		 657 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
658 }
2445b227 659 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
d38ceaf9
AD		 660 }
661 }
fd506558 662 return 0;
d38ceaf9 663}
Linux 6.x block layer and io_uring tree(s)