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drm/amdgpu: Adding CAP firmware initialization
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
fdf2f6c5 27
d38ceaf9
AD		 28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30
31static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32{
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44}
45
46void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47{
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65}
66
67void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68{
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
a6d64c1a
KW		 71 const struct smc_firmware_header_v1_0 *v1_0_hdr;
72 const struct smc_firmware_header_v2_0 *v2_0_hdr;
73 const struct smc_firmware_header_v2_1 *v2_1_hdr;
d38ceaf9
AD		 74
75 DRM_DEBUG("SMC\n");
76 amdgpu_ucode_print_common_hdr(hdr);
77
78 if (version_major == 1) {
a6d64c1a
KW		 79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
336a1c82 81 } else if (version_major == 2) {
a6d64c1a
KW		 82 switch (version_minor) {
83 case 0:
84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
87 break;
88 case 1:
89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
92 break;
93 default:
94 break;
95 }
336a1c82 96
d38ceaf9
AD		 97 } else {
98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
99 }
100}
101
102void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
103{
104 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
106
107 DRM_DEBUG("GFX\n");
108 amdgpu_ucode_print_common_hdr(hdr);
109
110 if (version_major == 1) {
111 const struct gfx_firmware_header_v1_0 *gfx_hdr =
112 container_of(hdr, struct gfx_firmware_header_v1_0, header);
113
114 DRM_DEBUG("ucode_feature_version: %u\n",
115 le32_to_cpu(gfx_hdr->ucode_feature_version));
116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
641f053e
LG		 118 } else if (version_major == 2) {
119 const struct gfx_firmware_header_v2_0 *gfx_hdr =
120 container_of(hdr, struct gfx_firmware_header_v2_0, header);
121
122 DRM_DEBUG("ucode_feature_version: %u\n",
123 le32_to_cpu(gfx_hdr->ucode_feature_version));
d38ceaf9
AD		 124 } else {
125 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
126 }
127}
128
289bcffb
LG		 129void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr)
130{
131 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
132 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
133
134 DRM_DEBUG("IMU\n");
135 amdgpu_ucode_print_common_hdr(hdr);
136
137 if (version_major != 1) {
138 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
139 }
140}
141
d38ceaf9
AD		 142void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
143{
144 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
145 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
146
147 DRM_DEBUG("RLC\n");
148 amdgpu_ucode_print_common_hdr(hdr);
149
150 if (version_major == 1) {
151 const struct rlc_firmware_header_v1_0 *rlc_hdr =
152 container_of(hdr, struct rlc_firmware_header_v1_0, header);
153
154 DRM_DEBUG("ucode_feature_version: %u\n",
155 le32_to_cpu(rlc_hdr->ucode_feature_version));
156 DRM_DEBUG("save_and_restore_offset: %u\n",
157 le32_to_cpu(rlc_hdr->save_and_restore_offset));
158 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
159 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
160 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
161 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
162 DRM_DEBUG("master_pkt_description_offset: %u\n",
163 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
164 } else if (version_major == 2) {
165 const struct rlc_firmware_header_v2_0 *rlc_hdr =
166 container_of(hdr, struct rlc_firmware_header_v2_0, header);
d5c6ad72
HZ		 167 const struct rlc_firmware_header_v2_1 *rlc_hdr_v2_1 =
168 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
169 const struct rlc_firmware_header_v2_2 *rlc_hdr_v2_2 =
170 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1);
171 const struct rlc_firmware_header_v2_3 *rlc_hdr_v2_3 =
172 container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
173 const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
174 container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
d38ceaf9 175
d5c6ad72
HZ		 176 switch (version_minor) {
177 case 0:
178 /* rlc_hdr v2_0 */
179 DRM_DEBUG("ucode_feature_version: %u\n",
180 le32_to_cpu(rlc_hdr->ucode_feature_version));
181 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
182 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
183 DRM_DEBUG("save_and_restore_offset: %u\n",
184 le32_to_cpu(rlc_hdr->save_and_restore_offset));
185 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
186 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
187 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
188 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
189 DRM_DEBUG("reg_restore_list_size: %u\n",
190 le32_to_cpu(rlc_hdr->reg_restore_list_size));
191 DRM_DEBUG("reg_list_format_start: %u\n",
192 le32_to_cpu(rlc_hdr->reg_list_format_start));
193 DRM_DEBUG("reg_list_format_separate_start: %u\n",
194 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
195 DRM_DEBUG("starting_offsets_start: %u\n",
196 le32_to_cpu(rlc_hdr->starting_offsets_start));
197 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
198 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
199 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
200 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
201 DRM_DEBUG("reg_list_size_bytes: %u\n",
202 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
203 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
204 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
205 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
206 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
207 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
208 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
209 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
210 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
211 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
212 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
213 break;
214 case 1:
215 /* rlc_hdr v2_1 */
d40e9b13 216 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
d5c6ad72 217 le32_to_cpu(rlc_hdr_v2_1->reg_list_format_direct_reg_list_length));
d40e9b13 218 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
d5c6ad72 219 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_ucode_ver));
d40e9b13 220 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
d5c6ad72 221 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_feature_ver));
d40e9b13 222 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
d5c6ad72 223 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_size_bytes));
d40e9b13 224 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
d5c6ad72 225 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_cntl_offset_bytes));
d40e9b13 226 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
d5c6ad72 227 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_ucode_ver));
d40e9b13 228 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
d5c6ad72 229 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_feature_ver));
d40e9b13 230 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
d5c6ad72 231 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_size_bytes));
d40e9b13 232 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
d5c6ad72 233 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_gpm_offset_bytes));
d40e9b13 234 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
d5c6ad72 235 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_ucode_ver));
d40e9b13 236 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
d5c6ad72 237 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_feature_ver));
d40e9b13 238 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
d5c6ad72 239 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_size_bytes));
d40e9b13 240 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
d5c6ad72
HZ		 241 le32_to_cpu(rlc_hdr_v2_1->save_restore_list_srm_offset_bytes));
242 break;
243 case 2:
244 /* rlc_hdr v2_2 */
245 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",
246 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_size_bytes));
247 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",
248 le32_to_cpu(rlc_hdr_v2_2->rlc_iram_ucode_offset_bytes));
249 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",
250 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_size_bytes));
251 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",
252 le32_to_cpu(rlc_hdr_v2_2->rlc_dram_ucode_offset_bytes));
253 break;
254 case 3:
255 /* rlc_hdr v2_3 */
256 DRM_DEBUG("rlcp_ucode_version: %u\n",
257 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_version));
258 DRM_DEBUG("rlcp_ucode_feature_version: %u\n",
259 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_feature_version));
260 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",
261 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_size_bytes));
262 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",
263 le32_to_cpu(rlc_hdr_v2_3->rlcp_ucode_offset_bytes));
264 DRM_DEBUG("rlcv_ucode_version: %u\n",
265 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_version));
266 DRM_DEBUG("rlcv_ucode_feature_version: %u\n",
267 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_feature_version));
268 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",
269 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_size_bytes));
270 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",
271 le32_to_cpu(rlc_hdr_v2_3->rlcv_ucode_offset_bytes));
272 break;
273 case 4:
274 /* rlc_hdr v2_4 */
275 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",
276 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_size_bytes));
277 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",
278 le32_to_cpu(rlc_hdr_v2_4->global_tap_delays_ucode_offset_bytes));
279 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",
280 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_size_bytes));
281 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",
282 le32_to_cpu(rlc_hdr_v2_4->se0_tap_delays_ucode_offset_bytes));
283 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",
284 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_size_bytes));
285 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",
286 le32_to_cpu(rlc_hdr_v2_4->se1_tap_delays_ucode_offset_bytes));
287 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",
288 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_size_bytes));
289 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",
290 le32_to_cpu(rlc_hdr_v2_4->se2_tap_delays_ucode_offset_bytes));
291 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",
292 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
293 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
294 le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
295 break;
296 default:
297 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
298 break;
d40e9b13 299 }
d38ceaf9
AD		 300 } else {
301 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
302 }
303}
304
305void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
306{
307 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
308 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
309
310 DRM_DEBUG("SDMA\n");
311 amdgpu_ucode_print_common_hdr(hdr);
312
313 if (version_major == 1) {
314 const struct sdma_firmware_header_v1_0 *sdma_hdr =
315 container_of(hdr, struct sdma_firmware_header_v1_0, header);
316
317 DRM_DEBUG("ucode_feature_version: %u\n",
318 le32_to_cpu(sdma_hdr->ucode_feature_version));
319 DRM_DEBUG("ucode_change_version: %u\n",
320 le32_to_cpu(sdma_hdr->ucode_change_version));
321 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
322 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
323 if (version_minor >= 1) {
324 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
325 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
326 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
327 }
8e070831
LG		 328 } else if (version_major == 2) {
329 const struct sdma_firmware_header_v2_0 *sdma_hdr =
330 container_of(hdr, struct sdma_firmware_header_v2_0, header);
331
332 DRM_DEBUG("ucode_feature_version: %u\n",
333 le32_to_cpu(sdma_hdr->ucode_feature_version));
334 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
335 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
336 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
337 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
338 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
d38ceaf9
AD		 339 } else {
340 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
341 version_major, version_minor);
342 }
343}
344
6fa40564
HZ		 345void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
346{
347 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
348 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
5fea10d5
HZ		 349 uint32_t fw_index;
350 const struct psp_fw_bin_desc *desc;
6fa40564
HZ		 351
352 DRM_DEBUG("PSP\n");
353 amdgpu_ucode_print_common_hdr(hdr);
354
355 if (version_major == 1) {
356 const struct psp_firmware_header_v1_0 *psp_hdr =
357 container_of(hdr, struct psp_firmware_header_v1_0, header);
358
359 DRM_DEBUG("ucode_feature_version: %u\n",
79a0f441 360 le32_to_cpu(psp_hdr->sos.fw_version));
6fa40564 361 DRM_DEBUG("sos_offset_bytes: %u\n",
79a0f441 362 le32_to_cpu(psp_hdr->sos.offset_bytes));
6fa40564 363 DRM_DEBUG("sos_size_bytes: %u\n",
79a0f441 364 le32_to_cpu(psp_hdr->sos.size_bytes));
434dbb2a
HZ		 365 if (version_minor == 1) {
366 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
367 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
368 DRM_DEBUG("toc_header_version: %u\n",
79a0f441 369 le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
434dbb2a 370 DRM_DEBUG("toc_offset_bytes: %u\n",
79a0f441 371 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
434dbb2a 372 DRM_DEBUG("toc_size_bytes: %u\n",
79a0f441 373 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
42989359 374 DRM_DEBUG("kdb_header_version: %u\n",
79a0f441 375 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
42989359 376 DRM_DEBUG("kdb_offset_bytes: %u\n",
79a0f441 377 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
42989359 378 DRM_DEBUG("kdb_size_bytes: %u\n",
79a0f441 379 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
434dbb2a 380 }
dc0d9622
JC		 381 if (version_minor == 2) {
382 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
383 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
384 DRM_DEBUG("kdb_header_version: %u\n",
79a0f441 385 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
dc0d9622 386 DRM_DEBUG("kdb_offset_bytes: %u\n",
79a0f441 387 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
dc0d9622 388 DRM_DEBUG("kdb_size_bytes: %u\n",
79a0f441 389 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
dc0d9622 390 }
43a188e0
LG		 391 if (version_minor == 3) {
392 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
393 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
394 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
395 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
396 DRM_DEBUG("toc_header_version: %u\n",
79a0f441 397 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
43a188e0 398 DRM_DEBUG("toc_offset_bytes: %u\n",
79a0f441 399 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
43a188e0 400 DRM_DEBUG("toc_size_bytes: %u\n",
79a0f441 401 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
43a188e0 402 DRM_DEBUG("kdb_header_version: %u\n",
79a0f441 403 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
43a188e0 404 DRM_DEBUG("kdb_offset_bytes: %u\n",
79a0f441 405 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
43a188e0 406 DRM_DEBUG("kdb_size_bytes: %u\n",
79a0f441 407 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
43a188e0 408 DRM_DEBUG("spl_header_version: %u\n",
79a0f441 409 le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
43a188e0 410 DRM_DEBUG("spl_offset_bytes: %u\n",
79a0f441 411 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
43a188e0 412 DRM_DEBUG("spl_size_bytes: %u\n",
79a0f441 413 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
43a188e0 414 }
5fea10d5
HZ		 415 } else if (version_major == 2) {
416 const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
417 container_of(hdr, struct psp_firmware_header_v2_0, header);
418 for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
419 desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
420 switch (desc->fw_type) {
421 case PSP_FW_TYPE_PSP_SOS:
422 DRM_DEBUG("psp_sos_version: %u\n",
423 le32_to_cpu(desc->fw_version));
424 DRM_DEBUG("psp_sos_size_bytes: %u\n",
425 le32_to_cpu(desc->size_bytes));
426 break;
427 case PSP_FW_TYPE_PSP_SYS_DRV:
428 DRM_DEBUG("psp_sys_drv_version: %u\n",
429 le32_to_cpu(desc->fw_version));
430 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
431 le32_to_cpu(desc->size_bytes));
432 break;
433 case PSP_FW_TYPE_PSP_KDB:
434 DRM_DEBUG("psp_kdb_version: %u\n",
435 le32_to_cpu(desc->fw_version));
436 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
437 le32_to_cpu(desc->size_bytes));
438 break;
439 case PSP_FW_TYPE_PSP_TOC:
440 DRM_DEBUG("psp_toc_version: %u\n",
441 le32_to_cpu(desc->fw_version));
442 DRM_DEBUG("psp_toc_size_bytes: %u\n",
443 le32_to_cpu(desc->size_bytes));
444 break;
445 case PSP_FW_TYPE_PSP_SPL:
446 DRM_DEBUG("psp_spl_version: %u\n",
447 le32_to_cpu(desc->fw_version));
448 DRM_DEBUG("psp_spl_size_bytes: %u\n",
449 le32_to_cpu(desc->size_bytes));
450 break;
451 case PSP_FW_TYPE_PSP_RL:
452 DRM_DEBUG("psp_rl_version: %u\n",
453 le32_to_cpu(desc->fw_version));
454 DRM_DEBUG("psp_rl_size_bytes: %u\n",
455 le32_to_cpu(desc->size_bytes));
456 break;
457 case PSP_FW_TYPE_PSP_SOC_DRV:
458 DRM_DEBUG("psp_soc_drv_version: %u\n",
459 le32_to_cpu(desc->fw_version));
460 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
461 le32_to_cpu(desc->size_bytes));
462 break;
463 case PSP_FW_TYPE_PSP_INTF_DRV:
464 DRM_DEBUG("psp_intf_drv_version: %u\n",
465 le32_to_cpu(desc->fw_version));
466 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
467 le32_to_cpu(desc->size_bytes));
468 break;
469 case PSP_FW_TYPE_PSP_DBG_DRV:
470 DRM_DEBUG("psp_dbg_drv_version: %u\n",
471 le32_to_cpu(desc->fw_version));
472 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
473 le32_to_cpu(desc->size_bytes));
474 break;
475 default:
476 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
477 break;
478 }
479 }
6fa40564
HZ		 480 } else {
481 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
482 version_major, version_minor);
483 }
484}
485
8ae1a336
AD		 486void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
487{
488 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
489 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
490
491 DRM_DEBUG("GPU_INFO\n");
492 amdgpu_ucode_print_common_hdr(hdr);
493
494 if (version_major == 1) {
495 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
496 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
497
498 DRM_DEBUG("version_major: %u\n",
499 le16_to_cpu(gpu_info_hdr->version_major));
500 DRM_DEBUG("version_minor: %u\n",
501 le16_to_cpu(gpu_info_hdr->version_minor));
502 } else {
503 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
504 }
505}
506
03000128 507static int amdgpu_ucode_validate(const struct firmware *fw)
d38ceaf9
AD		 508{
509 const struct common_firmware_header *hdr =
510 (const struct common_firmware_header *)fw->data;
511
512 if (fw->size == le32_to_cpu(hdr->size_bytes))
513 return 0;
514
515 return -EINVAL;
516}
517
518bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
519 uint16_t hdr_major, uint16_t hdr_minor)
520{
521 if ((hdr->common.header_version_major == hdr_major) &&
522 (hdr->common.header_version_minor == hdr_minor))
7edda674
LG		 523 return true;
524 return false;
d38ceaf9
AD		 525}
526
e635ee07
HR		 527enum amdgpu_firmware_load_type
528amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
529{
530 switch (adev->asic_type) {
531#ifdef CONFIG_DRM_AMDGPU_SI
532 case CHIP_TAHITI:
533 case CHIP_PITCAIRN:
534 case CHIP_VERDE:
535 case CHIP_OLAND:
d9997b64 536 case CHIP_HAINAN:
e635ee07
HR		 537 return AMDGPU_FW_LOAD_DIRECT;
538#endif
539#ifdef CONFIG_DRM_AMDGPU_CIK
540 case CHIP_BONAIRE:
541 case CHIP_KAVERI:
542 case CHIP_KABINI:
543 case CHIP_HAWAII:
544 case CHIP_MULLINS:
545 return AMDGPU_FW_LOAD_DIRECT;
546#endif
547 case CHIP_TOPAZ:
548 case CHIP_TONGA:
549 case CHIP_FIJI:
550 case CHIP_CARRIZO:
551 case CHIP_STONEY:
552 case CHIP_POLARIS10:
553 case CHIP_POLARIS11:
554 case CHIP_POLARIS12:
34fd54bc 555 case CHIP_VEGAM:
9b008fb7 556 return AMDGPU_FW_LOAD_SMU;
d594e3cc 557 case CHIP_CYAN_SKILLFISH:
b8e42844
HR		 558 if (!(load_type &&
559 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
560 return AMDGPU_FW_LOAD_DIRECT;
561 else
c5d0aa48 562 return AMDGPU_FW_LOAD_PSP;
e635ee07 563 default:
aa9f8cc3
AD		 564 if (!load_type)
565 return AMDGPU_FW_LOAD_DIRECT;
566 else
567 return AMDGPU_FW_LOAD_PSP;
e635ee07 568 }
e635ee07
HR		 569}
570
aae435c6
LY		 571const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
572{
573 switch (ucode_id) {
574 case AMDGPU_UCODE_ID_SDMA0:
575 return "SDMA0";
576 case AMDGPU_UCODE_ID_SDMA1:
577 return "SDMA1";
578 case AMDGPU_UCODE_ID_SDMA2:
579 return "SDMA2";
580 case AMDGPU_UCODE_ID_SDMA3:
581 return "SDMA3";
582 case AMDGPU_UCODE_ID_SDMA4:
583 return "SDMA4";
584 case AMDGPU_UCODE_ID_SDMA5:
585 return "SDMA5";
586 case AMDGPU_UCODE_ID_SDMA6:
587 return "SDMA6";
588 case AMDGPU_UCODE_ID_SDMA7:
589 return "SDMA7";
619c94c3
LG		 590 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
591 return "SDMA_CTX";
592 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
593 return "SDMA_CTL";
aae435c6
LY		 594 case AMDGPU_UCODE_ID_CP_CE:
595 return "CP_CE";
596 case AMDGPU_UCODE_ID_CP_PFP:
597 return "CP_PFP";
598 case AMDGPU_UCODE_ID_CP_ME:
599 return "CP_ME";
600 case AMDGPU_UCODE_ID_CP_MEC1:
601 return "CP_MEC1";
602 case AMDGPU_UCODE_ID_CP_MEC1_JT:
603 return "CP_MEC1_JT";
604 case AMDGPU_UCODE_ID_CP_MEC2:
605 return "CP_MEC2";
606 case AMDGPU_UCODE_ID_CP_MEC2_JT:
607 return "CP_MEC2_JT";
608 case AMDGPU_UCODE_ID_CP_MES:
609 return "CP_MES";
610 case AMDGPU_UCODE_ID_CP_MES_DATA:
611 return "CP_MES_DATA";
619c94c3
LG		 612 case AMDGPU_UCODE_ID_CP_MES1:
613 return "CP_MES_KIQ";
614 case AMDGPU_UCODE_ID_CP_MES1_DATA:
615 return "CP_MES_KIQ_DATA";
aae435c6
LY		 616 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
617 return "RLC_RESTORE_LIST_CNTL";
618 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
619 return "RLC_RESTORE_LIST_GPM_MEM";
620 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
621 return "RLC_RESTORE_LIST_SRM_MEM";
622 case AMDGPU_UCODE_ID_RLC_IRAM:
623 return "RLC_IRAM";
624 case AMDGPU_UCODE_ID_RLC_DRAM:
625 return "RLC_DRAM";
626 case AMDGPU_UCODE_ID_RLC_G:
627 return "RLC_G";
619c94c3
LG		 628 case AMDGPU_UCODE_ID_RLC_P:
629 return "RLC_P";
630 case AMDGPU_UCODE_ID_RLC_V:
631 return "RLC_V";
2207efdd
CG		 632 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
633 return "GLOBAL_TAP_DELAYS";
634 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
635 return "SE0_TAP_DELAYS";
636 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
637 return "SE1_TAP_DELAYS";
638 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
639 return "SE2_TAP_DELAYS";
640 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
641 return "SE3_TAP_DELAYS";
619c94c3
LG		 642 case AMDGPU_UCODE_ID_IMU_I:
643 return "IMU_I";
644 case AMDGPU_UCODE_ID_IMU_D:
645 return "IMU_D";
aae435c6
LY		 646 case AMDGPU_UCODE_ID_STORAGE:
647 return "STORAGE";
648 case AMDGPU_UCODE_ID_SMC:
649 return "SMC";
b37c41f2
EQ		 650 case AMDGPU_UCODE_ID_PPTABLE:
651 return "PPTABLE";
aae435c6
LY		 652 case AMDGPU_UCODE_ID_UVD:
653 return "UVD";
654 case AMDGPU_UCODE_ID_UVD1:
655 return "UVD1";
656 case AMDGPU_UCODE_ID_VCE:
657 return "VCE";
658 case AMDGPU_UCODE_ID_VCN:
659 return "VCN";
660 case AMDGPU_UCODE_ID_VCN1:
661 return "VCN1";
662 case AMDGPU_UCODE_ID_DMCU_ERAM:
663 return "DMCU_ERAM";
664 case AMDGPU_UCODE_ID_DMCU_INTV:
665 return "DMCU_INTV";
666 case AMDGPU_UCODE_ID_VCN0_RAM:
667 return "VCN0_RAM";
668 case AMDGPU_UCODE_ID_VCN1_RAM:
669 return "VCN1_RAM";
670 case AMDGPU_UCODE_ID_DMCUB:
671 return "DMCUB";
3cd658de
BL		 672 case AMDGPU_UCODE_ID_CAP:
673 return "CAP";
aae435c6
LY		 674 default:
675 return "UNKNOWN UCODE";
676 }
677}
678
5bb23532
OM		 679#define FW_VERSION_ATTR(name, mode, field) \
680static ssize_t show_##name(struct device *dev, \
681 struct device_attribute *attr, \
682 char *buf) \
683{ \
684 struct drm_device *ddev = dev_get_drvdata(dev); \
1348969a 685 struct amdgpu_device *adev = drm_to_adev(ddev); \
5bb23532 686 \
40320159 687 return sysfs_emit(buf, "0x%08x\n", adev->field); \
5bb23532
OM		 688} \
689static DEVICE_ATTR(name, mode, show_##name, NULL)
690
691FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
692FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
693FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
694FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
695FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
696FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
697FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
698FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
699FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
700FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
701FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
702FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
b7236296 703FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
222e0a71 704FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
de3a1e33 705FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
4320e6f8
CL		 706FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
707FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
5bb23532
OM		 708FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
709FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
710FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
711FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
712FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
713
714static struct attribute *fw_attrs[] = {
715 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
716 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
717 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
718 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
719 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
720 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
721 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
722 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
723 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
724 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
b7236296
DF		 725 &dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
726 NULL
5bb23532
OM		 727};
728
729static const struct attribute_group fw_attr_group = {
730 .name = "fw_version",
731 .attrs = fw_attrs
732};
733
734int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
735{
736 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
737}
738
739void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
740{
741 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
742}
743
2445b227
HR		 744static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
745 struct amdgpu_firmware_info *ucode,
746 uint64_t mc_addr, void *kptr)
d38ceaf9
AD		 747{
748 const struct common_firmware_header *header = NULL;
2445b227 749 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
14ab2924 750 const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
01fcfc83 751 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
02350f0b 752 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
aa1faaa1 753 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
6777c8cf 754 const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
a32fa029 755 const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
02f958a2 756 u8 *ucode_addr;
d38ceaf9
AD		 757
758 if (NULL == ucode->fw)
759 return 0;
760
761 ucode->mc_addr = mc_addr;
762 ucode->kaddr = kptr;
763
bed5712e
ML		 764 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
765 return 0;
766
d38ceaf9 767 header = (const struct common_firmware_header *)ucode->fw->data;
2445b227 768 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
14ab2924 769 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
01fcfc83 770 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
02350f0b 771 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
aa1faaa1 772 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
6777c8cf 773 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
a32fa029 774 imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
2445b227 775
02f958a2
LG		 776 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
777 switch (ucode->ucode_id) {
6777c8cf 778 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
aca670e4 779 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
6777c8cf
LG		 780 ucode_addr = (u8 *)ucode->fw->data +
781 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
782 break;
783 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
aca670e4 784 ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
6777c8cf
LG		 785 ucode_addr = (u8 *)ucode->fw->data +
786 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
787 break;
02f958a2
LG		 788 case AMDGPU_UCODE_ID_CP_MEC1:
789 case AMDGPU_UCODE_ID_CP_MEC2:
790 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
791 le32_to_cpu(cp_hdr->jt_size) * 4;
792 ucode_addr = (u8 *)ucode->fw->data +
793 le32_to_cpu(header->ucode_array_offset_bytes);
794 break;
795 case AMDGPU_UCODE_ID_CP_MEC1_JT:
796 case AMDGPU_UCODE_ID_CP_MEC2_JT:
797 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
798 ucode_addr = (u8 *)ucode->fw->data +
799 le32_to_cpu(header->ucode_array_offset_bytes) +
800 le32_to_cpu(cp_hdr->jt_offset) * 4;
801 break;
802 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
803 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
804 ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
805 break;
806 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
807 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
808 ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
809 break;
810 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
811 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
812 ucode_addr = adev->gfx.rlc.save_restore_list_srm;
813 break;
814 case AMDGPU_UCODE_ID_RLC_IRAM:
815 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
816 ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
817 break;
818 case AMDGPU_UCODE_ID_RLC_DRAM:
819 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
820 ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
821 break;
a0fe38b4
LG		 822 case AMDGPU_UCODE_ID_RLC_P:
823 ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
824 ucode_addr = adev->gfx.rlc.rlcp_ucode;
825 break;
8e41a56a
LG		 826 case AMDGPU_UCODE_ID_RLC_V:
827 ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
828 ucode_addr = adev->gfx.rlc.rlcv_ucode;
829 break;
2207efdd
CG		 830 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
831 ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
832 ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
833 break;
834 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
835 ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
836 ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
837 break;
838 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
839 ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
840 ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
841 break;
842 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
843 ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
844 ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
845 break;
846 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
847 ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
848 ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
849 break;
02f958a2
LG		 850 case AMDGPU_UCODE_ID_CP_MES:
851 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
852 ucode_addr = (u8 *)ucode->fw->data +
853 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
854 break;
855 case AMDGPU_UCODE_ID_CP_MES_DATA:
856 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
857 ucode_addr = (u8 *)ucode->fw->data +
858 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
859 break;
b0f34028
JX		 860 case AMDGPU_UCODE_ID_CP_MES1:
861 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
862 ucode_addr = (u8 *)ucode->fw->data +
863 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
864 break;
865 case AMDGPU_UCODE_ID_CP_MES1_DATA:
866 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
867 ucode_addr = (u8 *)ucode->fw->data +
868 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
869 break;
02f958a2
LG		 870 case AMDGPU_UCODE_ID_DMCU_ERAM:
871 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
01fcfc83 872 le32_to_cpu(dmcu_hdr->intv_size_bytes);
02f958a2
LG		 873 ucode_addr = (u8 *)ucode->fw->data +
874 le32_to_cpu(header->ucode_array_offset_bytes);
875 break;
876 case AMDGPU_UCODE_ID_DMCU_INTV:
877 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
878 ucode_addr = (u8 *)ucode->fw->data +
879 le32_to_cpu(header->ucode_array_offset_bytes) +
880 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
881 break;
882 case AMDGPU_UCODE_ID_DMCUB:
883 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
884 ucode_addr = (u8 *)ucode->fw->data +
885 le32_to_cpu(header->ucode_array_offset_bytes);
886 break;
b37c41f2
EQ		 887 case AMDGPU_UCODE_ID_PPTABLE:
888 ucode->ucode_size = ucode->fw->size;
889 ucode_addr = (u8 *)ucode->fw->data;
890 break;
a32fa029
LG		 891 case AMDGPU_UCODE_ID_IMU_I:
892 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
893 ucode_addr = (u8 *)ucode->fw->data +
894 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
895 break;
896 case AMDGPU_UCODE_ID_IMU_D:
897 ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
898 ucode_addr = (u8 *)ucode->fw->data +
899 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
900 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
901 break;
14ab2924
LG		 902 case AMDGPU_UCODE_ID_CP_RS64_PFP:
903 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
904 ucode_addr = (u8 *)ucode->fw->data +
905 le32_to_cpu(header->ucode_array_offset_bytes);
906 break;
907 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
908 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
909 ucode_addr = (u8 *)ucode->fw->data +
910 le32_to_cpu(cpv2_hdr->data_offset_bytes);
911 break;
912 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
913 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
914 ucode_addr = (u8 *)ucode->fw->data +
915 le32_to_cpu(cpv2_hdr->data_offset_bytes);
916 break;
917 case AMDGPU_UCODE_ID_CP_RS64_ME:
918 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
919 ucode_addr = (u8 *)ucode->fw->data +
920 le32_to_cpu(header->ucode_array_offset_bytes);
921 break;
922 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
923 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
924 ucode_addr = (u8 *)ucode->fw->data +
925 le32_to_cpu(cpv2_hdr->data_offset_bytes);
926 break;
927 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
928 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
929 ucode_addr = (u8 *)ucode->fw->data +
930 le32_to_cpu(cpv2_hdr->data_offset_bytes);
931 break;
932 case AMDGPU_UCODE_ID_CP_RS64_MEC:
933 ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
934 ucode_addr = (u8 *)ucode->fw->data +
935 le32_to_cpu(header->ucode_array_offset_bytes);
936 break;
937 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
938 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
939 ucode_addr = (u8 *)ucode->fw->data +
940 le32_to_cpu(cpv2_hdr->data_offset_bytes);
941 break;
942 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
943 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
944 ucode_addr = (u8 *)ucode->fw->data +
945 le32_to_cpu(cpv2_hdr->data_offset_bytes);
946 break;
947 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
948 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
949 ucode_addr = (u8 *)ucode->fw->data +
950 le32_to_cpu(cpv2_hdr->data_offset_bytes);
951 break;
952 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
953 ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
954 ucode_addr = (u8 *)ucode->fw->data +
955 le32_to_cpu(cpv2_hdr->data_offset_bytes);
956 break;
02f958a2
LG		 957 default:
958 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
959 ucode_addr = (u8 *)ucode->fw->data +
960 le32_to_cpu(header->ucode_array_offset_bytes);
961 break;
962 }
963 } else {
964 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
965 ucode_addr = (u8 *)ucode->fw->data +
966 le32_to_cpu(header->ucode_array_offset_bytes);
2445b227 967 }
d38ceaf9 968
02f958a2
LG		 969 memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
970
d38ceaf9
AD		 971 return 0;
972}
973
4c2b2453
ML		 974static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
975 uint64_t mc_addr, void *kptr)
976{
977 const struct gfx_firmware_header_v1_0 *header = NULL;
978 const struct common_firmware_header *comm_hdr = NULL;
c4c5ae67
DV		 979 uint8_t *src_addr = NULL;
980 uint8_t *dst_addr = NULL;
4c2b2453
ML		 981
982 if (NULL == ucode->fw)
983 return 0;
984
985 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
986 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
987 dst_addr = ucode->kaddr +
988 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
989 PAGE_SIZE);
990 src_addr = (uint8_t *)ucode->fw->data +
991 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
992 (le32_to_cpu(header->jt_offset) * 4);
993 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
994
995 return 0;
996}
997
c8963ea4
RZ		 998int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
999{
1000 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
1001 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
1002 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
1003 &adev->firmware.fw_buf,
1004 &adev->firmware.fw_buf_mc,
1005 &adev->firmware.fw_buf_ptr);
1006 if (!adev->firmware.fw_buf) {
1007 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
1008 return -ENOMEM;
1009 } else if (amdgpu_sriov_vf(adev)) {
1010 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
1011 }
1012 }
1013 return 0;
1014}
1015
1016void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
1017{
ab0cd4a9 1018 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
c8963ea4
RZ		 1019 &adev->firmware.fw_buf_mc,
1020 &adev->firmware.fw_buf_ptr);
1021}
1022
d38ceaf9
AD		 1023int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
1024{
d38ceaf9 1025 uint64_t fw_offset = 0;
c8963ea4 1026 int i;
d38ceaf9 1027 struct amdgpu_firmware_info *ucode = NULL;
d38ceaf9 1028
c8963ea4 1029 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
53b3f8f4 1030 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
7504938f 1031 return 0;
e635ee07
HR		 1032 /*
1033 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
1034 * ucode info here
1035 */
bc108ec7
TH		 1036 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1037 if (amdgpu_sriov_vf(adev))
1038 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
1039 else
1040 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
1041 } else {
2445b227 1042 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
bc108ec7 1043 }
e635ee07 1044
2445b227 1045 for (i = 0; i < adev->firmware.max_ucodes; i++) {
d38ceaf9
AD		 1046 ucode = &adev->firmware.ucode[i];
1047 if (ucode->fw) {
d59c026b
ML		 1048 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
1049 adev->firmware.fw_buf_ptr + fw_offset);
2445b227
HR		 1050 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
1051 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
4c2b2453
ML		 1052 const struct gfx_firmware_header_v1_0 *cp_hdr;
1053 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
d59c026b
ML		 1054 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
1055 adev->firmware.fw_buf_ptr + fw_offset);
4c2b2453
ML		 1056 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1057 }
2445b227 1058 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
d38ceaf9
AD		 1059 }
1060 }
fd506558 1061 return 0;
d38ceaf9 1062}
1d5eee7d 1063
54a3e032
ML		 1064static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int block_type)
1065{
1066 if (block_type == MP0_HWIP) {
1067 switch (adev->ip_versions[MP0_HWIP][0]) {
1068 case IP_VERSION(9, 0, 0):
1069 switch (adev->asic_type) {
1070 case CHIP_VEGA10:
1071 return "vega10";
1072 case CHIP_VEGA12:
1073 return "vega12";
1074 default:
1075 return NULL;
1076 }
54a3e032
ML		 1077 case IP_VERSION(10, 0, 0):
1078 case IP_VERSION(10, 0, 1):
1079 if (adev->asic_type == CHIP_RAVEN) {
1080 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1081 return "raven2";
1082 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1083 return "picasso";
1084 return "raven";
1085 }
1086 break;
1087 case IP_VERSION(11, 0, 0):
1088 return "navi10";
1089 case IP_VERSION(11, 0, 2):
1090 return "vega20";
0604897b
ML		 1091 case IP_VERSION(11, 0, 3):
1092 return "renoir";
54a3e032
ML		 1093 case IP_VERSION(11, 0, 4):
1094 return "arcturus";
1095 case IP_VERSION(11, 0, 5):
1096 return "navi14";
1097 case IP_VERSION(11, 0, 7):
1098 return "sienna_cichlid";
1099 case IP_VERSION(11, 0, 9):
1100 return "navi12";
1101 case IP_VERSION(11, 0, 11):
1102 return "navy_flounder";
1103 case IP_VERSION(11, 0, 12):
1104 return "dimgrey_cavefish";
1105 case IP_VERSION(11, 0, 13):
1106 return "beige_goby";
1107 case IP_VERSION(11, 5, 0):
1108 return "vangogh";
1109 case IP_VERSION(12, 0, 1):
0604897b 1110 return "green_sardine";
54a3e032
ML		 1111 case IP_VERSION(13, 0, 2):
1112 return "aldebaran";
1113 case IP_VERSION(13, 0, 1):
1114 case IP_VERSION(13, 0, 3):
1115 return "yellow_carp";
1116 }
1117 } else if (block_type == MP1_HWIP) {
1118 switch (adev->ip_versions[MP1_HWIP][0]) {
1119 case IP_VERSION(9, 0, 0):
1120 case IP_VERSION(10, 0, 0):
1121 case IP_VERSION(10, 0, 1):
1122 case IP_VERSION(11, 0, 2):
1123 if (adev->asic_type == CHIP_ARCTURUS)
1124 return "arcturus_smc";
1125 return NULL;
1126 case IP_VERSION(11, 0, 0):
1127 return "navi10_smc";
1128 case IP_VERSION(11, 0, 5):
1129 return "navi14_smc";
1130 case IP_VERSION(11, 0, 9):
1131 return "navi12_smc";
1132 case IP_VERSION(11, 0, 7):
1133 return "sienna_cichlid_smc";
1134 case IP_VERSION(11, 0, 11):
1135 return "navy_flounder_smc";
1136 case IP_VERSION(11, 0, 12):
1137 return "dimgrey_cavefish_smc";
1138 case IP_VERSION(11, 0, 13):
1139 return "beige_goby_smc";
1140 case IP_VERSION(13, 0, 2):
1141 return "aldebaran_smc";
1142 }
1143 } else if (block_type == SDMA0_HWIP) {
1144 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1145 case IP_VERSION(4, 0, 0):
1146 return "vega10_sdma";
1147 case IP_VERSION(4, 0, 1):
1148 return "vega12_sdma";
1149 case IP_VERSION(4, 1, 0):
1150 case IP_VERSION(4, 1, 1):
1151 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1152 return "raven2_sdma";
1153 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1154 return "picasso_sdma";
1155 return "raven_sdma";
1156 case IP_VERSION(4, 1, 2):
1157 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1158 return "renoir_sdma";
1159 return "green_sardine_sdma";
1160 case IP_VERSION(4, 2, 0):
1161 return "vega20_sdma";
1162 case IP_VERSION(4, 2, 2):
1163 return "arcturus_sdma";
1164 case IP_VERSION(4, 4, 0):
1165 return "aldebaran_sdma";
1166 case IP_VERSION(5, 0, 0):
1167 return "navi10_sdma";
1168 case IP_VERSION(5, 0, 1):
1169 return "cyan_skillfish2_sdma";
1170 case IP_VERSION(5, 0, 2):
1171 return "navi14_sdma";
1172 case IP_VERSION(5, 0, 5):
1173 return "navi12_sdma";
1174 case IP_VERSION(5, 2, 0):
1175 return "sienna_cichlid_sdma";
1176 case IP_VERSION(5, 2, 2):
1177 return "navy_flounder_sdma";
1178 case IP_VERSION(5, 2, 4):
1179 return "dimgrey_cavefish_sdma";
1180 case IP_VERSION(5, 2, 5):
1181 return "beige_goby_sdma";
1182 case IP_VERSION(5, 2, 3):
1183 return "yellow_carp_sdma";
1184 case IP_VERSION(5, 2, 1):
1185 return "vangogh_sdma";
1186 }
1187 } else if (block_type == UVD_HWIP) {
1188 switch (adev->ip_versions[UVD_HWIP][0]) {
1189 case IP_VERSION(1, 0, 0):
1190 case IP_VERSION(1, 0, 1):
1191 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1192 return "raven2_vcn";
1193 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1194 return "picasso_vcn";
1195 return "raven_vcn";
1196 case IP_VERSION(2, 5, 0):
1197 return "arcturus_vcn";
1198 case IP_VERSION(2, 2, 0):
1199 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1200 return "renoir_vcn";
1201 return "green_sardine_vcn";
1202 case IP_VERSION(2, 6, 0):
1203 return "aldebaran_vcn";
1204 case IP_VERSION(2, 0, 0):
1205 return "navi10_vcn";
1206 case IP_VERSION(2, 0, 2):
1207 if (adev->asic_type == CHIP_NAVI12)
1208 return "navi12_vcn";
1209 return "navi14_vcn";
1210 case IP_VERSION(3, 0, 0):
1211 case IP_VERSION(3, 0, 64):
1212 case IP_VERSION(3, 0, 192):
1213 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
1214 return "sienna_cichlid_vcn";
1215 return "navy_flounder_vcn";
1216 case IP_VERSION(3, 0, 2):
1217 return "vangogh_vcn";
1218 case IP_VERSION(3, 0, 16):
1219 return "dimgrey_cavefish_vcn";
1220 case IP_VERSION(3, 0, 33):
1221 return "beige_goby_vcn";
1222 case IP_VERSION(3, 1, 1):
1223 return "yellow_carp_vcn";
1224 }
1225 } else if (block_type == GC_HWIP) {
1226 switch (adev->ip_versions[GC_HWIP][0]) {
1227 case IP_VERSION(9, 0, 1):
1228 return "vega10";
1229 case IP_VERSION(9, 2, 1):
1230 return "vega12";
1231 case IP_VERSION(9, 4, 0):
1232 return "vega20";
1233 case IP_VERSION(9, 2, 2):
1234 case IP_VERSION(9, 1, 0):
1235 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1236 return "raven2";
1237 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1238 return "picasso";
1239 return "raven";
1240 case IP_VERSION(9, 4, 1):
1241 return "arcturus";
1242 case IP_VERSION(9, 3, 0):
1243 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1244 return "renoir";
1245 return "green_sardine";
1246 case IP_VERSION(9, 4, 2):
1247 return "aldebaran";
1248 case IP_VERSION(10, 1, 10):
1249 return "navi10";
1250 case IP_VERSION(10, 1, 1):
1251 return "navi14";
1252 case IP_VERSION(10, 1, 2):
1253 return "navi12";
1254 case IP_VERSION(10, 3, 0):
1255 return "sienna_cichlid";
1256 case IP_VERSION(10, 3, 2):
1257 return "navy_flounder";
1258 case IP_VERSION(10, 3, 1):
1259 return "vangogh";
1260 case IP_VERSION(10, 3, 4):
1261 return "dimgrey_cavefish";
1262 case IP_VERSION(10, 3, 5):
1263 return "beige_goby";
1264 case IP_VERSION(10, 3, 3):
1265 return "yellow_carp";
1266 case IP_VERSION(10, 1, 3):
1267 case IP_VERSION(10, 1, 4):
1268 return "cyan_skillfish2";
1269 }
1270 }
1271 return NULL;
1272}
1273
1d5eee7d
LG		 1274void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
1275{
1276 int maj, min, rev;
1277 char *ip_name;
54a3e032 1278 const char *legacy;
1d5eee7d
LG		 1279 uint32_t version = adev->ip_versions[block_type][0];
1280
54a3e032
ML		 1281 legacy = amdgpu_ucode_legacy_naming(adev, block_type);
1282 if (legacy) {
1283 snprintf(ucode_prefix, len, "%s", legacy);
1284 return;
1285 }
1286
1d5eee7d
LG		 1287 switch (block_type) {
1288 case GC_HWIP:
1289 ip_name = "gc";
1290 break;
1291 case SDMA0_HWIP:
1292 ip_name = "sdma";
1293 break;
1294 case MP0_HWIP:
1295 ip_name = "psp";
1296 break;
1297 case MP1_HWIP:
1298 ip_name = "smu";
1299 break;
1300 case UVD_HWIP:
1301 ip_name = "vcn";
1302 break;
1303 default:
1304 BUG();
1305 }
1306
1307 maj = IP_VERSION_MAJ(version);
1308 min = IP_VERSION_MIN(version);
1309 rev = IP_VERSION_REV(version);
1310
1311 snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1312}
2210af50
ML		 1313
1314/*
1315 * amdgpu_ucode_request - Fetch and validate amdgpu microcode
1316 *
1317 * @adev: amdgpu device
1318 * @fw: pointer to load firmware to
1319 * @fw_name: firmware to load
1320 *
1321 * This is a helper that will use request_firmware and amdgpu_ucode_validate
1322 * to load and run basic validation on firmware. If the load fails, remap
1323 * the error code to -ENODEV, so that early_init functions will fail to load.
1324 */
1325int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
1326 const char *fw_name)
1327{
1328 int err = request_firmware(fw, fw_name, adev->dev);
1329
1330 if (err)
1331 return -ENODEV;
1332 err = amdgpu_ucode_validate(*fw);
1333 if (err)
1334 dev_dbg(adev->dev, "\"%s\" failed to validate\n", fw_name);
1335
1336 return err;
1337}
1338
1339/*
1340 * amdgpu_ucode_release - Release firmware microcode
1341 *
1342 * @fw: pointer to firmware to release
1343 */
1344void amdgpu_ucode_release(const struct firmware **fw)
1345{
1346 release_firmware(*fw);
1347 *fw = NULL;
1348}
Linux 6.x block layer and io_uring tree(s)