[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_ucode.h"

static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
{
	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
	DRM_DEBUG("ucode_array_offset_bytes: %u\n",
		  le32_to_cpu(hdr->ucode_array_offset_bytes));
	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
}

void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
{
	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);

	DRM_DEBUG("MC\n");
	amdgpu_ucode_print_common_hdr(hdr);

	if (version_major == 1) {
		const struct mc_firmware_header_v1_0 *mc_hdr =
			container_of(hdr, struct mc_firmware_header_v1_0, header);

		DRM_DEBUG("io_debug_size_bytes: %u\n",
			  le32_to_cpu(mc_hdr->io_debug_size_bytes));
		DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
			  le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
	} else {
		DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
	}
}

void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
{
	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);

	DRM_DEBUG("SMC\n");
	amdgpu_ucode_print_common_hdr(hdr);

	if (version_major == 1) {
		const struct smc_firmware_header_v1_0 *smc_hdr =
			container_of(hdr, struct smc_firmware_header_v1_0, header);

		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
	} else {
		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
	}
}

void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
{
	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);

	DRM_DEBUG("GFX\n");
	amdgpu_ucode_print_common_hdr(hdr);

	if (version_major == 1) {
		const struct gfx_firmware_header_v1_0 *gfx_hdr =
			container_of(hdr, struct gfx_firmware_header_v1_0, header);

		DRM_DEBUG("ucode_feature_version: %u\n",
			  le32_to_cpu(gfx_hdr->ucode_feature_version));
		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
	} else {
		DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
	}
}

void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
{
	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);

	DRM_DEBUG("RLC\n");
	amdgpu_ucode_print_common_hdr(hdr);

	if (version_major == 1) {
		const struct rlc_firmware_header_v1_0 *rlc_hdr =
			container_of(hdr, struct rlc_firmware_header_v1_0, header);

		DRM_DEBUG("ucode_feature_version: %u\n",
			  le32_to_cpu(rlc_hdr->ucode_feature_version));
		DRM_DEBUG("save_and_restore_offset: %u\n",
			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
		DRM_DEBUG("master_pkt_description_offset: %u\n",
			  le32_to_cpu(rlc_hdr->master_pkt_description_offset));
	} else if (version_major == 2) {
		const struct rlc_firmware_header_v2_0 *rlc_hdr =
			container_of(hdr, struct rlc_firmware_header_v2_0, header);

		DRM_DEBUG("ucode_feature_version: %u\n",
			  le32_to_cpu(rlc_hdr->ucode_feature_version));
		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
		DRM_DEBUG("save_and_restore_offset: %u\n",
			  le32_to_cpu(rlc_hdr->save_and_restore_offset));
		DRM_DEBUG("clear_state_descriptor_offset: %u\n",
			  le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
		DRM_DEBUG("avail_scratch_ram_locations: %u\n",
			  le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
		DRM_DEBUG("reg_restore_list_size: %u\n",
			  le32_to_cpu(rlc_hdr->reg_restore_list_size));
		DRM_DEBUG("reg_list_format_start: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_format_start));
		DRM_DEBUG("reg_list_format_separate_start: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
		DRM_DEBUG("starting_offsets_start: %u\n",
			  le32_to_cpu(rlc_hdr->starting_offsets_start));
		DRM_DEBUG("reg_list_format_size_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
		DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
		DRM_DEBUG("reg_list_size_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_size_bytes));
		DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
		DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
		DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
		DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
		DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
			  le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
		if (version_minor == 1) {
			const struct rlc_firmware_header_v2_1 *v2_1 =
				container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
			DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
				  le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
			DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
			DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
			DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
				  le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
			DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
			DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
			DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
			DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
				  le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
			DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
			DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
			DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
			DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
				  le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
			DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
				  le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
		}
	} else {
		DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
	}
}

void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
{
	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);

	DRM_DEBUG("SDMA\n");
	amdgpu_ucode_print_common_hdr(hdr);

	if (version_major == 1) {
		const struct sdma_firmware_header_v1_0 *sdma_hdr =
			container_of(hdr, struct sdma_firmware_header_v1_0, header);

		DRM_DEBUG("ucode_feature_version: %u\n",
			  le32_to_cpu(sdma_hdr->ucode_feature_version));
		DRM_DEBUG("ucode_change_version: %u\n",
			  le32_to_cpu(sdma_hdr->ucode_change_version));
		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
		if (version_minor >= 1) {
			const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
				container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
			DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
		}
	} else {
		DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
			  version_major, version_minor);
	}
}

void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
{
	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);

	DRM_DEBUG("GPU_INFO\n");
	amdgpu_ucode_print_common_hdr(hdr);

	if (version_major == 1) {
		const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
			container_of(hdr, struct gpu_info_firmware_header_v1_0, header);

		DRM_DEBUG("version_major: %u\n",
			  le16_to_cpu(gpu_info_hdr->version_major));
		DRM_DEBUG("version_minor: %u\n",
			  le16_to_cpu(gpu_info_hdr->version_minor));
	} else {
		DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
	}
}

int amdgpu_ucode_validate(const struct firmware *fw)
{
	const struct common_firmware_header *hdr =
		(const struct common_firmware_header *)fw->data;

	if (fw->size == le32_to_cpu(hdr->size_bytes))
		return 0;

	return -EINVAL;
}

bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
				uint16_t hdr_major, uint16_t hdr_minor)
{
	if ((hdr->common.header_version_major == hdr_major) &&
		(hdr->common.header_version_minor == hdr_minor))
		return false;
	return true;
}

enum amdgpu_firmware_load_type
amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
{
	switch (adev->asic_type) {
#ifdef CONFIG_DRM_AMDGPU_SI
	case CHIP_TAHITI:
	case CHIP_PITCAIRN:
	case CHIP_VERDE:
	case CHIP_OLAND:
		return AMDGPU_FW_LOAD_DIRECT;
#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
	case CHIP_BONAIRE:
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_HAWAII:
	case CHIP_MULLINS:
		return AMDGPU_FW_LOAD_DIRECT;
#endif
	case CHIP_TOPAZ:
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_POLARIS10:
	case CHIP_POLARIS11:
	case CHIP_POLARIS12:
	case CHIP_VEGAM:
		if (!load_type)
			return AMDGPU_FW_LOAD_DIRECT;
		else
			return AMDGPU_FW_LOAD_SMU;
	case CHIP_VEGA10:
	case CHIP_RAVEN:
	case CHIP_VEGA12:
		if (!load_type)
			return AMDGPU_FW_LOAD_DIRECT;
		else
			return AMDGPU_FW_LOAD_PSP;
	case CHIP_VEGA20:
		return AMDGPU_FW_LOAD_DIRECT;
	default:
		DRM_ERROR("Unknown firmware load type\n");
	}

	return AMDGPU_FW_LOAD_DIRECT;
}

static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
				       struct amdgpu_firmware_info *ucode,
				       uint64_t mc_addr, void *kptr)
{
	const struct common_firmware_header *header = NULL;
	const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;

	if (NULL == ucode->fw)
		return 0;

	ucode->mc_addr = mc_addr;
	ucode->kaddr = kptr;

	if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
		return 0;

	header = (const struct common_firmware_header *)ucode->fw->data;

	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;

	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);

		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
					      le32_to_cpu(header->ucode_array_offset_bytes)),
		       ucode->ucode_size);
	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
			le32_to_cpu(cp_hdr->jt_size) * 4;

		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
					      le32_to_cpu(header->ucode_array_offset_bytes)),
		       ucode->ucode_size);
	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
		ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;

		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
					      le32_to_cpu(header->ucode_array_offset_bytes) +
					      le32_to_cpu(cp_hdr->jt_offset) * 4),
		       ucode->ucode_size);
	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
		ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
		       ucode->ucode_size);
	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
		ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
		       ucode->ucode_size);
	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
		       ucode->ucode_size);
	}

	return 0;
}

static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
				uint64_t mc_addr, void *kptr)
{
	const struct gfx_firmware_header_v1_0 *header = NULL;
	const struct common_firmware_header *comm_hdr = NULL;
	uint8_t* src_addr = NULL;
	uint8_t* dst_addr = NULL;

	if (NULL == ucode->fw)
		return 0;

	comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
	dst_addr = ucode->kaddr +
			   ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
			   PAGE_SIZE);
	src_addr = (uint8_t *)ucode->fw->data +
			   le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
			   (le32_to_cpu(header->jt_offset) * 4);
	memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);

	return 0;
}

int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
{
	uint64_t fw_offset = 0;
	int i, err;
	struct amdgpu_firmware_info *ucode = NULL;
	const struct common_firmware_header *header = NULL;

	if (!adev->firmware.fw_size) {
		dev_warn(adev->dev, "No ip firmware need to load\n");
		return 0;
	}

	if (!adev->in_gpu_reset) {
		err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
					amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
					&adev->firmware.fw_buf,
					&adev->firmware.fw_buf_mc,
					&adev->firmware.fw_buf_ptr);
		if (err) {
			dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
			goto failed;
		}
	}

	memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);

	/*
	 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
	 * ucode info here
	 */
	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
		if (amdgpu_sriov_vf(adev))
			adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
		else
			adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
	} else {
		adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
	}

	for (i = 0; i < adev->firmware.max_ucodes; i++) {
		ucode = &adev->firmware.ucode[i];
		if (ucode->fw) {
			header = (const struct common_firmware_header *)ucode->fw->data;
			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
						    adev->firmware.fw_buf_ptr + fw_offset);
			if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
			    adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
				const struct gfx_firmware_header_v1_0 *cp_hdr;
				cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
						    adev->firmware.fw_buf_ptr + fw_offset);
				fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
			}
			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
		}
	}
	return 0;

failed:
	if (err)
		adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;

	return err;
}

int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
{
	int i;
	struct amdgpu_firmware_info *ucode = NULL;

	if (!adev->firmware.fw_size)
		return 0;

	for (i = 0; i < adev->firmware.max_ucodes; i++) {
		ucode = &adev->firmware.ucode[i];
		if (ucode->fw) {
			ucode->mc_addr = 0;
			ucode->kaddr = NULL;
		}
	}

	amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
				&adev->firmware.fw_buf_mc,
				&adev->firmware.fw_buf_ptr);

	return 0;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include <linux/firmware.h>
	25	#include <linux/slab.h>
	26	#include <linux/module.h>
	27	#include <drm/drmP.h>
	28	#include "amdgpu.h"
	29	#include "amdgpu_ucode.h"
	30
	31	static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
	32	{
	33	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
	34	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
	35	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
	36	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
	37	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
	38	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
	39	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
	40	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
	41	DRM_DEBUG("ucode_array_offset_bytes: %u\n",
	42	le32_to_cpu(hdr->ucode_array_offset_bytes));
	43	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
	44	}
	45
	46	void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
	47	{
	48	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	49	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
	50
	51	DRM_DEBUG("MC\n");
	52	amdgpu_ucode_print_common_hdr(hdr);
	53
	54	if (version_major == 1) {
	55	const struct mc_firmware_header_v1_0 *mc_hdr =
	56	container_of(hdr, struct mc_firmware_header_v1_0, header);
	57
	58	DRM_DEBUG("io_debug_size_bytes: %u\n",
	59	le32_to_cpu(mc_hdr->io_debug_size_bytes));
	60	DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
	61	le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
	62	} else {
	63	DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
	64	}
65	}
66
67	void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68	{
69	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71
72	DRM_DEBUG("SMC\n");
73	amdgpu_ucode_print_common_hdr(hdr);
74
75	if (version_major == 1) {
76	const struct smc_firmware_header_v1_0 *smc_hdr =
77	container_of(hdr, struct smc_firmware_header_v1_0, header);
78
79	DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
80	} else {
81	DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
82	}
83	}
84
85	void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
86	{
87	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
88	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
89
90	DRM_DEBUG("GFX\n");
91	amdgpu_ucode_print_common_hdr(hdr);
92
93	if (version_major == 1) {
94	const struct gfx_firmware_header_v1_0 *gfx_hdr =
95	container_of(hdr, struct gfx_firmware_header_v1_0, header);
96
97	DRM_DEBUG("ucode_feature_version: %u\n",
98	le32_to_cpu(gfx_hdr->ucode_feature_version));
99	DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
100	DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
101	} else {
102	DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
103	}
104	}
105
106	void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
107	{
108	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
109	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
110
111	DRM_DEBUG("RLC\n");
112	amdgpu_ucode_print_common_hdr(hdr);
113
114	if (version_major == 1) {
115	const struct rlc_firmware_header_v1_0 *rlc_hdr =
116	container_of(hdr, struct rlc_firmware_header_v1_0, header);
117
118	DRM_DEBUG("ucode_feature_version: %u\n",
119	le32_to_cpu(rlc_hdr->ucode_feature_version));
120	DRM_DEBUG("save_and_restore_offset: %u\n",
121	le32_to_cpu(rlc_hdr->save_and_restore_offset));
122	DRM_DEBUG("clear_state_descriptor_offset: %u\n",
123	le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
124	DRM_DEBUG("avail_scratch_ram_locations: %u\n",
125	le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
126	DRM_DEBUG("master_pkt_description_offset: %u\n",
127	le32_to_cpu(rlc_hdr->master_pkt_description_offset));
128	} else if (version_major == 2) {
129	const struct rlc_firmware_header_v2_0 *rlc_hdr =
130	container_of(hdr, struct rlc_firmware_header_v2_0, header);
131
132	DRM_DEBUG("ucode_feature_version: %u\n",
133	le32_to_cpu(rlc_hdr->ucode_feature_version));
134	DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
135	DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
136	DRM_DEBUG("save_and_restore_offset: %u\n",
137	le32_to_cpu(rlc_hdr->save_and_restore_offset));
138	DRM_DEBUG("clear_state_descriptor_offset: %u\n",
139	le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
140	DRM_DEBUG("avail_scratch_ram_locations: %u\n",
141	le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
142	DRM_DEBUG("reg_restore_list_size: %u\n",
143	le32_to_cpu(rlc_hdr->reg_restore_list_size));
144	DRM_DEBUG("reg_list_format_start: %u\n",
145	le32_to_cpu(rlc_hdr->reg_list_format_start));
146	DRM_DEBUG("reg_list_format_separate_start: %u\n",
147	le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
148	DRM_DEBUG("starting_offsets_start: %u\n",
149	le32_to_cpu(rlc_hdr->starting_offsets_start));
150	DRM_DEBUG("reg_list_format_size_bytes: %u\n",
151	le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
152	DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
153	le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
154	DRM_DEBUG("reg_list_size_bytes: %u\n",
155	le32_to_cpu(rlc_hdr->reg_list_size_bytes));
156	DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
157	le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
158	DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
159	le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
160	DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
161	le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162	DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163	le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
d40e9b13 HR	164	DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
	165	le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
	166	if (version_minor == 1) {
	167	const struct rlc_firmware_header_v2_1 *v2_1 =
	168	container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
	169	DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
	170	le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
	171	DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
	172	le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
	173	DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
	174	le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
	175	DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
	176	le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
	177	DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
	178	le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
	179	DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
	180	le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
	181	DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
	182	le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
	183	DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
	184	le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
	185	DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
	186	le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
	187	DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
	188	le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
	189	DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
	190	le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
	191	DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
	192	le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
	193	DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
	194	le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
	195	}
d38ceaf9 AD	196	} else {
	197	DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
	198	}
	199	}
	200
	201	void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
	202	{
	203	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	204	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
	205
	206	DRM_DEBUG("SDMA\n");
	207	amdgpu_ucode_print_common_hdr(hdr);
	208
	209	if (version_major == 1) {
	210	const struct sdma_firmware_header_v1_0 *sdma_hdr =
	211	container_of(hdr, struct sdma_firmware_header_v1_0, header);
	212
	213	DRM_DEBUG("ucode_feature_version: %u\n",
	214	le32_to_cpu(sdma_hdr->ucode_feature_version));
	215	DRM_DEBUG("ucode_change_version: %u\n",
	216	le32_to_cpu(sdma_hdr->ucode_change_version));
	217	DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
	218	DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
	219	if (version_minor >= 1) {
	220	const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
	221	container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
	222	DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
	223	}
	224	} else {
	225	DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
	226	version_major, version_minor);
	227	}
	228	}
	229
8ae1a336 AD	230	void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
	231	{
	232	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
	233	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
	234
	235	DRM_DEBUG("GPU_INFO\n");
	236	amdgpu_ucode_print_common_hdr(hdr);
	237
	238	if (version_major == 1) {
	239	const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
	240	container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
	241
	242	DRM_DEBUG("version_major: %u\n",
	243	le16_to_cpu(gpu_info_hdr->version_major));
	244	DRM_DEBUG("version_minor: %u\n",
	245	le16_to_cpu(gpu_info_hdr->version_minor));
	246	} else {
	247	DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
	248	}
	249	}
	250
d38ceaf9 AD	251	int amdgpu_ucode_validate(const struct firmware *fw)
	252	{
	253	const struct common_firmware_header *hdr =
	254	(const struct common_firmware_header *)fw->data;
	255
	256	if (fw->size == le32_to_cpu(hdr->size_bytes))
	257	return 0;
	258
	259	return -EINVAL;
	260	}
	261
	262	bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
	263	uint16_t hdr_major, uint16_t hdr_minor)
	264	{
	265	if ((hdr->common.header_version_major == hdr_major) &&
	266	(hdr->common.header_version_minor == hdr_minor))
	267	return false;
	268	return true;
	269	}
	270
e635ee07 HR	271	enum amdgpu_firmware_load_type
	272	amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
	273	{
	274	switch (adev->asic_type) {
	275	#ifdef CONFIG_DRM_AMDGPU_SI
	276	case CHIP_TAHITI:
	277	case CHIP_PITCAIRN:
	278	case CHIP_VERDE:
	279	case CHIP_OLAND:
	280	return AMDGPU_FW_LOAD_DIRECT;
	281	#endif
	282	#ifdef CONFIG_DRM_AMDGPU_CIK
	283	case CHIP_BONAIRE:
	284	case CHIP_KAVERI:
	285	case CHIP_KABINI:
	286	case CHIP_HAWAII:
	287	case CHIP_MULLINS:
	288	return AMDGPU_FW_LOAD_DIRECT;
	289	#endif
	290	case CHIP_TOPAZ:
	291	case CHIP_TONGA:
	292	case CHIP_FIJI:
	293	case CHIP_CARRIZO:
	294	case CHIP_STONEY:
	295	case CHIP_POLARIS10:
	296	case CHIP_POLARIS11:
	297	case CHIP_POLARIS12:
34fd54bc	298	case CHIP_VEGAM:
e635ee07 HR	299	if (!load_type)
	300	return AMDGPU_FW_LOAD_DIRECT;
	301	else
	302	return AMDGPU_FW_LOAD_SMU;
	303	case CHIP_VEGA10:
4456ef4e	304	case CHIP_RAVEN:
6b9c6e1b	305	case CHIP_VEGA12:
50811c71	306	if (!load_type)
4456ef4e CZ	307	return AMDGPU_FW_LOAD_DIRECT;
	308	else
	309	return AMDGPU_FW_LOAD_PSP;
24e6bc78 FX	310	case CHIP_VEGA20:
24e6bc78 FX	311	return AMDGPU_FW_LOAD_DIRECT;
e635ee07	312	default:
bc8282a7	313	DRM_ERROR("Unknown firmware load type\n");
e635ee07 HR	314	}
	315
	316	return AMDGPU_FW_LOAD_DIRECT;
	317	}
	318
2445b227 HR	319	static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
	320	struct amdgpu_firmware_info *ucode,
	321	uint64_t mc_addr, void *kptr)
d38ceaf9 AD	322	{
d38ceaf9 AD	323	const struct common_firmware_header *header = NULL;
2445b227	324	const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
d38ceaf9 AD	325
	326	if (NULL == ucode->fw)
	327	return 0;
	328
	329	ucode->mc_addr = mc_addr;
	330	ucode->kaddr = kptr;
	331
bed5712e ML	332	if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
	333	return 0;
	334
d38ceaf9	335	header = (const struct common_firmware_header *)ucode->fw->data;
daf42c31	336
2445b227 HR	337	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
	338
	339	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP \|\|
	340	(ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
	341	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
	342	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
621a6318 HR	343	ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
	344	ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
	345	ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
	346	ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
2445b227 HR	347	ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
	348
	349	memcpy(ucode->kaddr, (void )((uint8_t )ucode->fw->data +
	350	le32_to_cpu(header->ucode_array_offset_bytes)),
	351	ucode->ucode_size);
	352	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 \|\|
	353	ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
	354	ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
	355	le32_to_cpu(cp_hdr->jt_size) * 4;
	356
	357	memcpy(ucode->kaddr, (void )((uint8_t )ucode->fw->data +
	358	le32_to_cpu(header->ucode_array_offset_bytes)),
	359	ucode->ucode_size);
	360	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT \|\|
	361	ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
	362	ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
	363
	364	memcpy(ucode->kaddr, (void )((uint8_t )ucode->fw->data +
	365	le32_to_cpu(header->ucode_array_offset_bytes) +
	366	le32_to_cpu(cp_hdr->jt_offset) * 4),
	367	ucode->ucode_size);
621a6318 HR	368	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
	369	ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
	370	memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
	371	ucode->ucode_size);
	372	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
	373	ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
	374	memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
	375	ucode->ucode_size);
	376	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
	377	ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
	378	memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
	379	ucode->ucode_size);
2445b227	380	}
d38ceaf9 AD	381
	382	return 0;
	383	}
	384
4c2b2453 ML	385	static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
	386	uint64_t mc_addr, void *kptr)
	387	{
	388	const struct gfx_firmware_header_v1_0 *header = NULL;
	389	const struct common_firmware_header *comm_hdr = NULL;
	390	uint8_t* src_addr = NULL;
	391	uint8_t* dst_addr = NULL;
	392
	393	if (NULL == ucode->fw)
	394	return 0;
	395
	396	comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
	397	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
	398	dst_addr = ucode->kaddr +
	399	ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
	400	PAGE_SIZE);
	401	src_addr = (uint8_t *)ucode->fw->data +
	402	le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
	403	(le32_to_cpu(header->jt_offset) * 4);
	404	memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
	405
	406	return 0;
	407	}
	408
d38ceaf9 AD	409	int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
d38ceaf9 AD	410	{
d38ceaf9	411	uint64_t fw_offset = 0;
2445b227	412	int i, err;
d38ceaf9 AD	413	struct amdgpu_firmware_info *ucode = NULL;
	414	const struct common_firmware_header *header = NULL;
	415
7504938f HR	416	if (!adev->firmware.fw_size) {
	417	dev_warn(adev->dev, "No ip firmware need to load\n");
	418	return 0;
	419	}
	420
503846e0	421	if (!adev->in_gpu_reset) {
a95b0275	422	err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
d59c026b	423	amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
a95b0275 ML	424	&adev->firmware.fw_buf,
	425	&adev->firmware.fw_buf_mc,
	426	&adev->firmware.fw_buf_ptr);
d59c026b	427	if (err) {
a95b0275	428	dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
d59c026b ML	429	goto failed;
d59c026b ML	430	}
d59c026b	431	}
d38ceaf9	432
d59c026b	433	memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
2445b227	434
e635ee07 HR	435	/*
	436	* if SMU loaded firmware, it needn't add SMC, UVD, and VCE
	437	* ucode info here
	438	*/
bc108ec7 TH	439	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
	440	if (amdgpu_sriov_vf(adev))
	441	adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
	442	else
	443	adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
	444	} else {
2445b227	445	adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
bc108ec7	446	}
e635ee07	447
2445b227	448	for (i = 0; i < adev->firmware.max_ucodes; i++) {
d38ceaf9 AD	449	ucode = &adev->firmware.ucode[i];
	450	if (ucode->fw) {
	451	header = (const struct common_firmware_header *)ucode->fw->data;
d59c026b ML	452	amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
d59c026b ML	453	adev->firmware.fw_buf_ptr + fw_offset);
2445b227 HR	454	if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
2445b227 HR	455	adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
4c2b2453 ML	456	const struct gfx_firmware_header_v1_0 *cp_hdr;
4c2b2453 ML	457	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
d59c026b ML	458	amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
d59c026b ML	459	adev->firmware.fw_buf_ptr + fw_offset);
4c2b2453 ML	460	fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
4c2b2453 ML	461	}
2445b227	462	fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
d38ceaf9 AD	463	}
d38ceaf9 AD	464	}
fd506558	465	return 0;
d38ceaf9 AD	466
d38ceaf9 AD	467	failed:
e635ee07 HR	468	if (err)
e635ee07 HR	469	adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
d38ceaf9 AD	470
	471	return err;
	472	}
	473
	474	int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
	475	{
	476	int i;
	477	struct amdgpu_firmware_info *ucode = NULL;
	478
7504938f HR	479	if (!adev->firmware.fw_size)
	480	return 0;
	481
2445b227	482	for (i = 0; i < adev->firmware.max_ucodes; i++) {
d38ceaf9 AD	483	ucode = &adev->firmware.ucode[i];
	484	if (ucode->fw) {
	485	ucode->mc_addr = 0;
	486	ucode->kaddr = NULL;
	487	}
	488	}
a95b0275 ML	489
	490	amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
	491	&adev->firmware.fw_buf_mc,
	492	&adev->firmware.fw_buf_ptr);
d38ceaf9 AD	493
	494	return 0;
	495	}