[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_TTM_H__
#define __AMDGPU_TTM_H__

#include <linux/dma-direction.h>
#include <drm/gpu_scheduler.h>
#include "amdgpu.h"

#define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
#define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)
#define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)

#define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2

#define AMDGPU_POISON	0xd0bed0be

struct amdgpu_vram_mgr {
	struct ttm_resource_manager manager;
	struct drm_mm mm;
	spinlock_t lock;
	struct list_head reservations_pending;
	struct list_head reserved_pages;
	atomic64_t usage;
	atomic64_t vis_usage;
};

struct amdgpu_gtt_mgr {
	struct ttm_resource_manager manager;
	struct drm_mm mm;
	spinlock_t lock;
	atomic64_t available;
};

struct amdgpu_mman {
	struct ttm_device		bdev;
	bool				initialized;
	void __iomem			*aper_base_kaddr;

	/* buffer handling */
	const struct amdgpu_buffer_funcs	*buffer_funcs;
	struct amdgpu_ring			*buffer_funcs_ring;
	bool					buffer_funcs_enabled;

	struct mutex				gtt_window_lock;
	/* Scheduler entity for buffer moves */
	struct drm_sched_entity			entity;

	struct amdgpu_vram_mgr vram_mgr;
	struct amdgpu_gtt_mgr gtt_mgr;

	uint64_t		stolen_vga_size;
	struct amdgpu_bo	*stolen_vga_memory;
	uint64_t		stolen_extended_size;
	struct amdgpu_bo	*stolen_extended_memory;
	bool			keep_stolen_vga_memory;

	/* discovery */
	uint8_t				*discovery_bin;
	uint32_t			discovery_tmr_size;
	struct amdgpu_bo		*discovery_memory;

	/* firmware VRAM reservation */
	u64		fw_vram_usage_start_offset;
	u64		fw_vram_usage_size;
	struct amdgpu_bo	*fw_vram_usage_reserved_bo;
	void		*fw_vram_usage_va;
};

struct amdgpu_copy_mem {
	struct ttm_buffer_object	*bo;
	struct ttm_resource		*mem;
	unsigned long			offset;
};

int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);

bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man);
int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man);

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
			      struct ttm_resource *mem,
			      u64 offset, u64 size,
			      struct device *dev,
			      enum dma_data_direction dir,
			      struct sg_table **sgt);
void amdgpu_vram_mgr_free_sgt(struct device *dev,
			      enum dma_data_direction dir,
			      struct sg_table *sgt);
uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man);
uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_resource_manager *man);
int amdgpu_vram_mgr_reserve_range(struct ttm_resource_manager *man,
				  uint64_t start, uint64_t size);
int amdgpu_vram_mgr_query_page_status(struct ttm_resource_manager *man,
				      uint64_t start);

int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
					bool enable);

int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
		       uint64_t dst_offset, uint32_t byte_count,
		       struct dma_resv *resv,
		       struct dma_fence **fence, bool direct_submit,
		       bool vm_needs_flush, bool tmz);
int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
			       const struct amdgpu_copy_mem *src,
			       const struct amdgpu_copy_mem *dst,
			       uint64_t size, bool tmz,
			       struct dma_resv *resv,
			       struct dma_fence **f);
int amdgpu_fill_buffer(struct amdgpu_bo *bo,
			uint32_t src_data,
			struct dma_resv *resv,
			struct dma_fence **fence);

int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);

#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
#else
static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
					       struct page **pages)
{
	return -EPERM;
}
static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
{
	return false;
}
#endif

void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
			      uint64_t addr, uint32_t flags);
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
				  unsigned long end);
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
				       int *last_invalidated);
bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
				 struct ttm_resource *mem);

void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);

#endif
Commit	Line	Data
c632d799 FC	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_TTM_H__
	25	#define __AMDGPU_TTM_H__
	26
f44ffd67	27	#include <linux/dma-direction.h>
1b1f42d8	28	#include <drm/gpu_scheduler.h>
f44ffd67	29	#include "amdgpu.h"
c632d799	30
283cde69 CK	31	#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
	32	#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
	33	#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
c632d799	34
cc25188a CK	35	#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
	36	#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
	37
ab2f7a5c FK	38	#define AMDGPU_POISON 0xd0bed0be
ab2f7a5c FK	39
4f297b9c DA	40	struct amdgpu_vram_mgr {
	41	struct ttm_resource_manager manager;
	42	struct drm_mm mm;
	43	spinlock_t lock;
676deb38 DL	44	struct list_head reservations_pending;
676deb38 DL	45	struct list_head reserved_pages;
4f297b9c DA	46	atomic64_t usage;
4f297b9c DA	47	atomic64_t vis_usage;
4f297b9c DA	48	};
	49
	50	struct amdgpu_gtt_mgr {
	51	struct ttm_resource_manager manager;
	52	struct drm_mm mm;
	53	spinlock_t lock;
	54	atomic64_t available;
	55	};
	56
c632d799	57	struct amdgpu_mman {
8af8a109	58	struct ttm_device bdev;
c632d799	59	bool initialized;
f8f4b9a6	60	void __iomem *aper_base_kaddr;
c632d799	61
c632d799 FC	62	/* buffer handling */
	63	const struct amdgpu_buffer_funcs *buffer_funcs;
	64	struct amdgpu_ring *buffer_funcs_ring;
81988f9c	65	bool buffer_funcs_enabled;
abca90f1 CK	66
abca90f1 CK	67	struct mutex gtt_window_lock;
c632d799	68	/* Scheduler entity for buffer moves */
1b1f42d8	69	struct drm_sched_entity entity;
4f297b9c DA	70
	71	struct amdgpu_vram_mgr vram_mgr;
	72	struct amdgpu_gtt_mgr gtt_mgr;
0c8d22fc	73
cacbbe7c AD	74	uint64_t stolen_vga_size;
	75	struct amdgpu_bo *stolen_vga_memory;
	76	uint64_t stolen_extended_size;
	77	struct amdgpu_bo *stolen_extended_memory;
	78	bool keep_stolen_vga_memory;
72de33f8 AD	79
	80	/* discovery */
	81	uint8_t *discovery_bin;
	82	uint32_t discovery_tmr_size;
	83	struct amdgpu_bo *discovery_memory;
87ded5ca AD	84
	85	/* firmware VRAM reservation */
	86	u64 fw_vram_usage_start_offset;
	87	u64 fw_vram_usage_size;
	88	struct amdgpu_bo *fw_vram_usage_reserved_bo;
	89	void *fw_vram_usage_va;
c632d799 FC	90	};
c632d799 FC	91
1eca5a53 HK	92	struct amdgpu_copy_mem {
1eca5a53 HK	93	struct ttm_buffer_object *bo;
2966141a	94	struct ttm_resource *mem;
1eca5a53 HK	95	unsigned long offset;
	96	};
	97
158d20d1	98	int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
6fe1c543	99	void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
158d20d1	100	int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
6fe1c543	101	void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
bb990bb0	102
2966141a	103	bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
9de59bc2 DA	104	uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man);
9de59bc2 DA	105	int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man);
bb990bb0	106
ddc21af4	107	u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
f44ffd67	108	int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
2966141a	109	struct ttm_resource *mem,
ba5b662c	110	u64 offset, u64 size,
f44ffd67 CK	111	struct device *dev,
	112	enum dma_data_direction dir,
	113	struct sg_table **sgt);
5392b2af	114	void amdgpu_vram_mgr_free_sgt(struct device *dev,
f44ffd67 CK	115	enum dma_data_direction dir,
f44ffd67 CK	116	struct sg_table *sgt);
9de59bc2 DA	117	uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man);
9de59bc2 DA	118	uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_resource_manager *man);
676deb38 DL	119	int amdgpu_vram_mgr_reserve_range(struct ttm_resource_manager *man,
	120	uint64_t start, uint64_t size);
	121	int amdgpu_vram_mgr_query_page_status(struct ttm_resource_manager *man,
	122	uint64_t start);
3c848bb3	123
c396ef9b CK	124	int amdgpu_ttm_init(struct amdgpu_device *adev);
c396ef9b CK	125	void amdgpu_ttm_fini(struct amdgpu_device *adev);
57adc4ce CK	126	void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
57adc4ce CK	127	bool enable);
c396ef9b	128
fc9c8f54 CK	129	int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
fc9c8f54 CK	130	uint64_t dst_offset, uint32_t byte_count,
52791eee	131	struct dma_resv *resv,
fc9c8f54	132	struct dma_fence **fence, bool direct_submit,
c9dc9cfe	133	bool vm_needs_flush, bool tmz);
1eca5a53	134	int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
f0ee63cb CK	135	const struct amdgpu_copy_mem *src,
f0ee63cb CK	136	const struct amdgpu_copy_mem *dst,
effb97cc	137	uint64_t size, bool tmz,
52791eee	138	struct dma_resv *resv,
1eca5a53	139	struct dma_fence **f);
c632d799	140	int amdgpu_fill_buffer(struct amdgpu_bo *bo,
44e1baeb	141	uint32_t src_data,
52791eee	142	struct dma_resv *resv,
f54d1867	143	struct dma_fence **fence);
c632d799	144
c5835bbb	145	int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
c1c7ce8f	146	int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
b1a8ef95	147	uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
c855e250	148
ad595b86	149	#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
e5eaa7cc	150	int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo bo, struct page *pages);
899fbde1	151	bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
ad595b86	152	#else
e5eaa7cc PY	153	static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
e5eaa7cc PY	154	struct page **pages)
ad595b86 PY	155	{
	156	return -EPERM;
	157	}
	158	static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
	159	{
	160	return false;
	161	}
	162	#endif
	163
711becf0	164	void amdgpu_ttm_tt_set_user_pages(struct ttm_tt ttm, struct page *pages);
77f47d23 CK	165	int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
77f47d23 CK	166	uint64_t addr, uint32_t flags);
711becf0 CK	167	bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
	168	struct mm_struct amdgpu_ttm_tt_get_usermm(struct ttm_tt ttm);
	169	bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
	170	unsigned long end);
	171	bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
	172	int *last_invalidated);
899fbde1	173	bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
711becf0	174	bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2966141a	175	uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt ttm, struct ttm_resource mem);
711becf0	176	uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device adev, struct ttm_tt ttm,
2966141a	177	struct ttm_resource *mem);
711becf0	178
98d28ac2	179	void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
c5820361	180
c632d799	181	#endif