[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_TTM_H__
#define __AMDGPU_TTM_H__

#include "amdgpu.h"
#include <drm/gpu_scheduler.h>

#define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
#define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)
#define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)

#define AMDGPU_PL_FLAG_GDS		(TTM_PL_FLAG_PRIV << 0)
#define AMDGPU_PL_FLAG_GWS		(TTM_PL_FLAG_PRIV << 1)
#define AMDGPU_PL_FLAG_OA		(TTM_PL_FLAG_PRIV << 2)

#define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2

struct amdgpu_mman {
	struct ttm_bo_device		bdev;
	bool				mem_global_referenced;
	bool				initialized;
	void __iomem			*aper_base_kaddr;

#if defined(CONFIG_DEBUG_FS)
	struct dentry			*debugfs_entries[8];
#endif

	/* buffer handling */
	const struct amdgpu_buffer_funcs	*buffer_funcs;
	struct amdgpu_ring			*buffer_funcs_ring;
	bool					buffer_funcs_enabled;

	struct mutex				gtt_window_lock;
	/* Scheduler entity for buffer moves */
	struct drm_sched_entity			entity;
};

struct amdgpu_copy_mem {
	struct ttm_buffer_object	*bo;
	struct ttm_mem_reg		*mem;
	unsigned long			offset;
};

extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;

bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);

int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_late_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
					bool enable);

int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
		       uint64_t dst_offset, uint32_t byte_count,
		       struct reservation_object *resv,
		       struct dma_fence **fence, bool direct_submit,
		       bool vm_needs_flush);
int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
			       struct amdgpu_copy_mem *src,
			       struct amdgpu_copy_mem *dst,
			       uint64_t size,
			       struct reservation_object *resv,
			       struct dma_fence **f);
int amdgpu_fill_buffer(struct amdgpu_bo *bo,
			uint32_t src_data,
			struct reservation_object *resv,
			struct dma_fence **fence);

int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);

#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
#else
static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
					       struct page **pages)
{
	return -EPERM;
}
static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
{
	return false;
}
#endif

void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
				     uint32_t flags);
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
				  unsigned long end);
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
				       int *last_invalidated);
bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
				 struct ttm_mem_reg *mem);

#endif
Commit	Line	Data
c632d799 FC	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_TTM_H__
	25	#define __AMDGPU_TTM_H__
	26
a40cfa0b	27	#include "amdgpu.h"
1b1f42d8	28	#include <drm/gpu_scheduler.h>
c632d799	29
283cde69 CK	30	#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
	31	#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
	32	#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
c632d799	33
283cde69 CK	34	#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
	35	#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
	36	#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
c632d799	37
cc25188a CK	38	#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
	39	#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
	40
c632d799	41	struct amdgpu_mman {
c632d799 FC	42	struct ttm_bo_device bdev;
	43	bool mem_global_referenced;
	44	bool initialized;
f8f4b9a6	45	void __iomem *aper_base_kaddr;
c632d799 FC	46
c632d799 FC	47	#if defined(CONFIG_DEBUG_FS)
a40cfa0b	48	struct dentry *debugfs_entries[8];
c632d799 FC	49	#endif
	50
	51	/* buffer handling */
	52	const struct amdgpu_buffer_funcs *buffer_funcs;
	53	struct amdgpu_ring *buffer_funcs_ring;
81988f9c	54	bool buffer_funcs_enabled;
abca90f1 CK	55
abca90f1 CK	56	struct mutex gtt_window_lock;
c632d799	57	/* Scheduler entity for buffer moves */
1b1f42d8	58	struct drm_sched_entity entity;
c632d799 FC	59	};
c632d799 FC	60
1eca5a53 HK	61	struct amdgpu_copy_mem {
	62	struct ttm_buffer_object *bo;
	63	struct ttm_mem_reg *mem;
	64	unsigned long offset;
	65	};
	66
bb990bb0	67	extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
6a7f76e7	68	extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
bb990bb0	69
3da917b6	70	bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
9255d77d	71	uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
c1c7ce8f	72	int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
bb990bb0	73
ddc21af4	74	u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
3c848bb3 CK	75	uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
	76	uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
	77
c396ef9b	78	int amdgpu_ttm_init(struct amdgpu_device *adev);
6f752ec2	79	void amdgpu_ttm_late_init(struct amdgpu_device *adev);
c396ef9b	80	void amdgpu_ttm_fini(struct amdgpu_device *adev);
57adc4ce CK	81	void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
57adc4ce CK	82	bool enable);
c396ef9b	83
fc9c8f54 CK	84	int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
fc9c8f54 CK	85	uint64_t dst_offset, uint32_t byte_count,
c632d799	86	struct reservation_object *resv,
fc9c8f54 CK	87	struct dma_fence **fence, bool direct_submit,
fc9c8f54 CK	88	bool vm_needs_flush);
1eca5a53 HK	89	int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
	90	struct amdgpu_copy_mem *src,
	91	struct amdgpu_copy_mem *dst,
	92	uint64_t size,
	93	struct reservation_object *resv,
	94	struct dma_fence **f);
c632d799	95	int amdgpu_fill_buffer(struct amdgpu_bo *bo,
44e1baeb	96	uint32_t src_data,
c632d799	97	struct reservation_object *resv,
f54d1867	98	struct dma_fence **fence);
c632d799 FC	99
c632d799 FC	100	int amdgpu_mmap(struct file filp, struct vm_area_struct vma);
c5835bbb	101	int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
c1c7ce8f	102	int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
c855e250	103
ad595b86	104	#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
e5eaa7cc	105	int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo bo, struct page *pages);
899fbde1	106	bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
ad595b86	107	#else
e5eaa7cc PY	108	static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
e5eaa7cc PY	109	struct page **pages)
ad595b86 PY	110	{
	111	return -EPERM;
	112	}
	113	static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
	114	{
	115	return false;
	116	}
	117	#endif
	118
711becf0	119	void amdgpu_ttm_tt_set_user_pages(struct ttm_tt ttm, struct page *pages);
711becf0 CK	120	int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
	121	uint32_t flags);
	122	bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
	123	struct mm_struct amdgpu_ttm_tt_get_usermm(struct ttm_tt ttm);
	124	bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
	125	unsigned long end);
	126	bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
	127	int *last_invalidated);
899fbde1	128	bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
711becf0	129	bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
24a8d289	130	uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt ttm, struct ttm_mem_reg mem);
711becf0 CK	131	uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device adev, struct ttm_tt ttm,
	132	struct ttm_mem_reg *mem);
	133
c632d799	134	#endif