Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
248a1d6f MY |
32 | #include <drm/ttm/ttm_bo_api.h> |
33 | #include <drm/ttm/ttm_bo_driver.h> | |
34 | #include <drm/ttm/ttm_placement.h> | |
35 | #include <drm/ttm/ttm_module.h> | |
36 | #include <drm/ttm/ttm_page_alloc.h> | |
d38ceaf9 AD |
37 | #include <drm/drmP.h> |
38 | #include <drm/amdgpu_drm.h> | |
39 | #include <linux/seq_file.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/swiotlb.h> | |
42 | #include <linux/swap.h> | |
43 | #include <linux/pagemap.h> | |
44 | #include <linux/debugfs.h> | |
38290b2c | 45 | #include <linux/iommu.h> |
d38ceaf9 | 46 | #include "amdgpu.h" |
b82485fd | 47 | #include "amdgpu_object.h" |
aca81718 | 48 | #include "amdgpu_trace.h" |
d8d019cc | 49 | #include "amdgpu_amdkfd.h" |
bb7743bc | 50 | #include "amdgpu_sdma.h" |
d38ceaf9 AD |
51 | #include "bif/bif_4_1_d.h" |
52 | ||
53 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
54 | ||
abca90f1 CK |
55 | static int amdgpu_map_buffer(struct ttm_buffer_object *bo, |
56 | struct ttm_mem_reg *mem, unsigned num_pages, | |
57 | uint64_t offset, unsigned window, | |
58 | struct amdgpu_ring *ring, | |
59 | uint64_t *addr); | |
60 | ||
d38ceaf9 AD |
61 | static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); |
62 | static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); | |
63 | ||
d38ceaf9 AD |
64 | /* |
65 | * Global memory. | |
66 | */ | |
50da5174 | 67 | |
50da5174 | 68 | /** |
2e603d04 | 69 | * amdgpu_ttm_global_init - Initialize global TTM memory reference structures. |
50da5174 | 70 | * |
2e603d04 | 71 | * @adev: AMDGPU device for which the global structures need to be registered. |
50da5174 TSD |
72 | * |
73 | * This is called as part of the AMDGPU ttm init from amdgpu_ttm_init() | |
74 | * during bring up. | |
75 | */ | |
70b5c5aa | 76 | static int amdgpu_ttm_global_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
77 | { |
78 | struct drm_global_reference *global_ref; | |
79 | int r; | |
80 | ||
50da5174 | 81 | /* ensure reference is false in case init fails */ |
d38ceaf9 | 82 | adev->mman.mem_global_referenced = false; |
50da5174 | 83 | |
d38ceaf9 AD |
84 | global_ref = &adev->mman.bo_global_ref.ref; |
85 | global_ref->global_type = DRM_GLOBAL_TTM_BO; | |
86 | global_ref->size = sizeof(struct ttm_bo_global); | |
e55a5c9b TZ |
87 | global_ref->init = &ttm_bo_global_ref_init; |
88 | global_ref->release = &ttm_bo_global_ref_release; | |
d38ceaf9 | 89 | r = drm_global_item_ref(global_ref); |
e9d035ec | 90 | if (r) { |
d38ceaf9 | 91 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
e9d035ec | 92 | goto error_bo; |
d38ceaf9 AD |
93 | } |
94 | ||
abca90f1 CK |
95 | mutex_init(&adev->mman.gtt_window_lock); |
96 | ||
d38ceaf9 | 97 | adev->mman.mem_global_referenced = true; |
703297c1 | 98 | |
d38ceaf9 | 99 | return 0; |
e9d035ec | 100 | |
e9d035ec | 101 | error_bo: |
e9d035ec | 102 | return r; |
d38ceaf9 AD |
103 | } |
104 | ||
105 | static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) | |
106 | { | |
107 | if (adev->mman.mem_global_referenced) { | |
abca90f1 | 108 | mutex_destroy(&adev->mman.gtt_window_lock); |
d38ceaf9 | 109 | drm_global_item_unref(&adev->mman.bo_global_ref.ref); |
d38ceaf9 AD |
110 | adev->mman.mem_global_referenced = false; |
111 | } | |
112 | } | |
113 | ||
114 | static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
115 | { | |
116 | return 0; | |
117 | } | |
118 | ||
50da5174 | 119 | /** |
2e603d04 HR |
120 | * amdgpu_init_mem_type - Initialize a memory manager for a specific type of |
121 | * memory request. | |
50da5174 | 122 | * |
2e603d04 HR |
123 | * @bdev: The TTM BO device object (contains a reference to amdgpu_device) |
124 | * @type: The type of memory requested | |
125 | * @man: The memory type manager for each domain | |
50da5174 TSD |
126 | * |
127 | * This is called by ttm_bo_init_mm() when a buffer object is being | |
128 | * initialized. | |
129 | */ | |
d38ceaf9 AD |
130 | static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
131 | struct ttm_mem_type_manager *man) | |
132 | { | |
133 | struct amdgpu_device *adev; | |
134 | ||
a7d64de6 | 135 | adev = amdgpu_ttm_adev(bdev); |
d38ceaf9 AD |
136 | |
137 | switch (type) { | |
138 | case TTM_PL_SYSTEM: | |
139 | /* System memory */ | |
140 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
141 | man->available_caching = TTM_PL_MASK_CACHING; | |
142 | man->default_caching = TTM_PL_FLAG_CACHED; | |
143 | break; | |
144 | case TTM_PL_TT: | |
50da5174 | 145 | /* GTT memory */ |
bb990bb0 | 146 | man->func = &amdgpu_gtt_mgr_func; |
0957dc70 | 147 | man->gpu_offset = adev->gmc.gart_start; |
d38ceaf9 AD |
148 | man->available_caching = TTM_PL_MASK_CACHING; |
149 | man->default_caching = TTM_PL_FLAG_CACHED; | |
150 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; | |
151 | break; | |
152 | case TTM_PL_VRAM: | |
153 | /* "On-card" video ram */ | |
6a7f76e7 | 154 | man->func = &amdgpu_vram_mgr_func; |
770d13b1 | 155 | man->gpu_offset = adev->gmc.vram_start; |
d38ceaf9 AD |
156 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
157 | TTM_MEMTYPE_FLAG_MAPPABLE; | |
158 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
159 | man->default_caching = TTM_PL_FLAG_WC; | |
160 | break; | |
161 | case AMDGPU_PL_GDS: | |
162 | case AMDGPU_PL_GWS: | |
163 | case AMDGPU_PL_OA: | |
164 | /* On-chip GDS memory*/ | |
165 | man->func = &ttm_bo_manager_func; | |
166 | man->gpu_offset = 0; | |
167 | man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; | |
168 | man->available_caching = TTM_PL_FLAG_UNCACHED; | |
169 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
170 | break; | |
171 | default: | |
172 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
173 | return -EINVAL; | |
174 | } | |
175 | return 0; | |
176 | } | |
177 | ||
50da5174 TSD |
178 | /** |
179 | * amdgpu_evict_flags - Compute placement flags | |
180 | * | |
181 | * @bo: The buffer object to evict | |
182 | * @placement: Possible destination(s) for evicted BO | |
183 | * | |
184 | * Fill in placement data when ttm_bo_evict() is called | |
185 | */ | |
d38ceaf9 AD |
186 | static void amdgpu_evict_flags(struct ttm_buffer_object *bo, |
187 | struct ttm_placement *placement) | |
188 | { | |
a7d64de6 | 189 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); |
765e7fbf | 190 | struct amdgpu_bo *abo; |
1aaa5602 | 191 | static const struct ttm_place placements = { |
d38ceaf9 AD |
192 | .fpfn = 0, |
193 | .lpfn = 0, | |
194 | .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | |
195 | }; | |
196 | ||
50da5174 | 197 | /* Don't handle scatter gather BOs */ |
82dee241 CK |
198 | if (bo->type == ttm_bo_type_sg) { |
199 | placement->num_placement = 0; | |
200 | placement->num_busy_placement = 0; | |
201 | return; | |
202 | } | |
203 | ||
50da5174 | 204 | /* Object isn't an AMDGPU object so ignore */ |
c704ab18 | 205 | if (!amdgpu_bo_is_amdgpu_bo(bo)) { |
d38ceaf9 AD |
206 | placement->placement = &placements; |
207 | placement->busy_placement = &placements; | |
208 | placement->num_placement = 1; | |
209 | placement->num_busy_placement = 1; | |
210 | return; | |
211 | } | |
50da5174 | 212 | |
b82485fd | 213 | abo = ttm_to_amdgpu_bo(bo); |
d38ceaf9 | 214 | switch (bo->mem.mem_type) { |
3b2de699 CK |
215 | case AMDGPU_PL_GDS: |
216 | case AMDGPU_PL_GWS: | |
217 | case AMDGPU_PL_OA: | |
218 | placement->num_placement = 0; | |
219 | placement->num_busy_placement = 0; | |
220 | return; | |
221 | ||
d38ceaf9 | 222 | case TTM_PL_VRAM: |
81988f9c | 223 | if (!adev->mman.buffer_funcs_enabled) { |
50da5174 | 224 | /* Move to system memory */ |
c704ab18 | 225 | amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); |
c8c5e569 | 226 | } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && |
5422a28f CK |
227 | !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && |
228 | amdgpu_bo_in_cpu_visible_vram(abo)) { | |
cb2dd1a6 MD |
229 | |
230 | /* Try evicting to the CPU inaccessible part of VRAM | |
231 | * first, but only set GTT as busy placement, so this | |
232 | * BO will be evicted to GTT rather than causing other | |
233 | * BOs to be evicted from VRAM | |
234 | */ | |
c704ab18 | 235 | amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | |
cb2dd1a6 | 236 | AMDGPU_GEM_DOMAIN_GTT); |
5422a28f | 237 | abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; |
cb2dd1a6 MD |
238 | abo->placements[0].lpfn = 0; |
239 | abo->placement.busy_placement = &abo->placements[1]; | |
240 | abo->placement.num_busy_placement = 1; | |
08291c5c | 241 | } else { |
50da5174 | 242 | /* Move to GTT memory */ |
c704ab18 | 243 | amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); |
08291c5c | 244 | } |
d38ceaf9 AD |
245 | break; |
246 | case TTM_PL_TT: | |
247 | default: | |
c704ab18 | 248 | amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); |
3b2de699 | 249 | break; |
d38ceaf9 | 250 | } |
765e7fbf | 251 | *placement = abo->placement; |
d38ceaf9 AD |
252 | } |
253 | ||
50da5174 TSD |
254 | /** |
255 | * amdgpu_verify_access - Verify access for a mmap call | |
256 | * | |
2e603d04 HR |
257 | * @bo: The buffer object to map |
258 | * @filp: The file pointer from the process performing the mmap | |
50da5174 TSD |
259 | * |
260 | * This is called by ttm_bo_mmap() to verify whether a process | |
261 | * has the right to mmap a BO to their process space. | |
262 | */ | |
d38ceaf9 AD |
263 | static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) |
264 | { | |
b82485fd | 265 | struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); |
d38ceaf9 | 266 | |
a46a2cd1 FK |
267 | /* |
268 | * Don't verify access for KFD BOs. They don't have a GEM | |
269 | * object associated with them. | |
270 | */ | |
271 | if (abo->kfd_bo) | |
272 | return 0; | |
273 | ||
054892ed JG |
274 | if (amdgpu_ttm_tt_get_usermm(bo->ttm)) |
275 | return -EPERM; | |
28a39654 | 276 | return drm_vma_node_verify_access(&abo->gem_base.vma_node, |
d9a1f0b4 | 277 | filp->private_data); |
d38ceaf9 AD |
278 | } |
279 | ||
50da5174 TSD |
280 | /** |
281 | * amdgpu_move_null - Register memory for a buffer object | |
282 | * | |
2e603d04 HR |
283 | * @bo: The bo to assign the memory to |
284 | * @new_mem: The memory to be assigned. | |
50da5174 | 285 | * |
2e603d04 | 286 | * Assign the memory from new_mem to the memory of the buffer object bo. |
50da5174 | 287 | */ |
d38ceaf9 AD |
288 | static void amdgpu_move_null(struct ttm_buffer_object *bo, |
289 | struct ttm_mem_reg *new_mem) | |
290 | { | |
291 | struct ttm_mem_reg *old_mem = &bo->mem; | |
292 | ||
293 | BUG_ON(old_mem->mm_node != NULL); | |
294 | *old_mem = *new_mem; | |
295 | new_mem->mm_node = NULL; | |
296 | } | |
297 | ||
50da5174 | 298 | /** |
2e603d04 HR |
299 | * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer. |
300 | * | |
301 | * @bo: The bo to assign the memory to. | |
302 | * @mm_node: Memory manager node for drm allocator. | |
303 | * @mem: The region where the bo resides. | |
304 | * | |
50da5174 | 305 | */ |
92c60d9c CK |
306 | static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, |
307 | struct drm_mm_node *mm_node, | |
308 | struct ttm_mem_reg *mem) | |
d38ceaf9 | 309 | { |
abca90f1 | 310 | uint64_t addr = 0; |
c855e250 | 311 | |
0e33495d | 312 | if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) { |
abca90f1 CK |
313 | addr = mm_node->start << PAGE_SHIFT; |
314 | addr += bo->bdev->man[mem->mem_type].gpu_offset; | |
315 | } | |
92c60d9c | 316 | return addr; |
8892f153 CK |
317 | } |
318 | ||
1eca5a53 | 319 | /** |
2e603d04 HR |
320 | * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to |
321 | * @offset. It also modifies the offset to be within the drm_mm_node returned | |
322 | * | |
323 | * @mem: The region where the bo resides. | |
324 | * @offset: The offset that drm_mm_node is used for finding. | |
325 | * | |
e1d51505 HK |
326 | */ |
327 | static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem, | |
328 | unsigned long *offset) | |
8892f153 | 329 | { |
e1d51505 | 330 | struct drm_mm_node *mm_node = mem->mm_node; |
8892f153 | 331 | |
e1d51505 HK |
332 | while (*offset >= (mm_node->size << PAGE_SHIFT)) { |
333 | *offset -= (mm_node->size << PAGE_SHIFT); | |
334 | ++mm_node; | |
335 | } | |
336 | return mm_node; | |
337 | } | |
8892f153 | 338 | |
e1d51505 HK |
339 | /** |
340 | * amdgpu_copy_ttm_mem_to_mem - Helper function for copy | |
1eca5a53 HK |
341 | * |
342 | * The function copies @size bytes from {src->mem + src->offset} to | |
343 | * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a | |
344 | * move and different for a BO to BO copy. | |
345 | * | |
346 | * @f: Returns the last fence if multiple jobs are submitted. | |
347 | */ | |
348 | int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, | |
349 | struct amdgpu_copy_mem *src, | |
350 | struct amdgpu_copy_mem *dst, | |
351 | uint64_t size, | |
352 | struct reservation_object *resv, | |
353 | struct dma_fence **f) | |
8892f153 | 354 | { |
8892f153 | 355 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; |
1eca5a53 HK |
356 | struct drm_mm_node *src_mm, *dst_mm; |
357 | uint64_t src_node_start, dst_node_start, src_node_size, | |
358 | dst_node_size, src_page_offset, dst_page_offset; | |
220196b3 | 359 | struct dma_fence *fence = NULL; |
1eca5a53 HK |
360 | int r = 0; |
361 | const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * | |
362 | AMDGPU_GPU_PAGE_SIZE); | |
8892f153 | 363 | |
81988f9c | 364 | if (!adev->mman.buffer_funcs_enabled) { |
d38ceaf9 AD |
365 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
366 | return -EINVAL; | |
367 | } | |
368 | ||
e1d51505 | 369 | src_mm = amdgpu_find_mm_node(src->mem, &src->offset); |
1eca5a53 HK |
370 | src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) + |
371 | src->offset; | |
372 | src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset; | |
373 | src_page_offset = src_node_start & (PAGE_SIZE - 1); | |
8892f153 | 374 | |
e1d51505 | 375 | dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset); |
1eca5a53 HK |
376 | dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) + |
377 | dst->offset; | |
378 | dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset; | |
379 | dst_page_offset = dst_node_start & (PAGE_SIZE - 1); | |
8892f153 | 380 | |
abca90f1 | 381 | mutex_lock(&adev->mman.gtt_window_lock); |
1eca5a53 HK |
382 | |
383 | while (size) { | |
384 | unsigned long cur_size; | |
385 | uint64_t from = src_node_start, to = dst_node_start; | |
220196b3 | 386 | struct dma_fence *next; |
8892f153 | 387 | |
1eca5a53 HK |
388 | /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst |
389 | * begins at an offset, then adjust the size accordingly | |
390 | */ | |
391 | cur_size = min3(min(src_node_size, dst_node_size), size, | |
392 | GTT_MAX_BYTES); | |
393 | if (cur_size + src_page_offset > GTT_MAX_BYTES || | |
394 | cur_size + dst_page_offset > GTT_MAX_BYTES) | |
395 | cur_size -= max(src_page_offset, dst_page_offset); | |
396 | ||
397 | /* Map only what needs to be accessed. Map src to window 0 and | |
398 | * dst to window 1 | |
399 | */ | |
0e33495d | 400 | if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) { |
1eca5a53 HK |
401 | r = amdgpu_map_buffer(src->bo, src->mem, |
402 | PFN_UP(cur_size + src_page_offset), | |
403 | src_node_start, 0, ring, | |
404 | &from); | |
abca90f1 CK |
405 | if (r) |
406 | goto error; | |
1eca5a53 HK |
407 | /* Adjust the offset because amdgpu_map_buffer returns |
408 | * start of mapped page | |
409 | */ | |
410 | from += src_page_offset; | |
abca90f1 CK |
411 | } |
412 | ||
0e33495d | 413 | if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) { |
1eca5a53 HK |
414 | r = amdgpu_map_buffer(dst->bo, dst->mem, |
415 | PFN_UP(cur_size + dst_page_offset), | |
416 | dst_node_start, 1, ring, | |
417 | &to); | |
abca90f1 CK |
418 | if (r) |
419 | goto error; | |
1eca5a53 | 420 | to += dst_page_offset; |
abca90f1 CK |
421 | } |
422 | ||
1eca5a53 HK |
423 | r = amdgpu_copy_buffer(ring, from, to, cur_size, |
424 | resv, &next, false, true); | |
8892f153 CK |
425 | if (r) |
426 | goto error; | |
427 | ||
220196b3 | 428 | dma_fence_put(fence); |
8892f153 CK |
429 | fence = next; |
430 | ||
1eca5a53 HK |
431 | size -= cur_size; |
432 | if (!size) | |
8892f153 CK |
433 | break; |
434 | ||
1eca5a53 HK |
435 | src_node_size -= cur_size; |
436 | if (!src_node_size) { | |
437 | src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm, | |
438 | src->mem); | |
439 | src_node_size = (src_mm->size << PAGE_SHIFT); | |
8892f153 | 440 | } else { |
1eca5a53 HK |
441 | src_node_start += cur_size; |
442 | src_page_offset = src_node_start & (PAGE_SIZE - 1); | |
8892f153 | 443 | } |
1eca5a53 HK |
444 | dst_node_size -= cur_size; |
445 | if (!dst_node_size) { | |
446 | dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm, | |
447 | dst->mem); | |
448 | dst_node_size = (dst_mm->size << PAGE_SHIFT); | |
8892f153 | 449 | } else { |
1eca5a53 HK |
450 | dst_node_start += cur_size; |
451 | dst_page_offset = dst_node_start & (PAGE_SIZE - 1); | |
8892f153 CK |
452 | } |
453 | } | |
1eca5a53 | 454 | error: |
abca90f1 | 455 | mutex_unlock(&adev->mman.gtt_window_lock); |
1eca5a53 HK |
456 | if (f) |
457 | *f = dma_fence_get(fence); | |
458 | dma_fence_put(fence); | |
459 | return r; | |
460 | } | |
461 | ||
50da5174 TSD |
462 | /** |
463 | * amdgpu_move_blit - Copy an entire buffer to another buffer | |
464 | * | |
2e603d04 HR |
465 | * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to |
466 | * help move buffers to and from VRAM. | |
50da5174 | 467 | */ |
1eca5a53 HK |
468 | static int amdgpu_move_blit(struct ttm_buffer_object *bo, |
469 | bool evict, bool no_wait_gpu, | |
470 | struct ttm_mem_reg *new_mem, | |
471 | struct ttm_mem_reg *old_mem) | |
472 | { | |
473 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); | |
474 | struct amdgpu_copy_mem src, dst; | |
475 | struct dma_fence *fence = NULL; | |
476 | int r; | |
477 | ||
478 | src.bo = bo; | |
479 | dst.bo = bo; | |
480 | src.mem = old_mem; | |
481 | dst.mem = new_mem; | |
482 | src.offset = 0; | |
483 | dst.offset = 0; | |
484 | ||
485 | r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, | |
486 | new_mem->num_pages << PAGE_SHIFT, | |
487 | bo->resv, &fence); | |
488 | if (r) | |
489 | goto error; | |
ce64bc25 | 490 | |
4947b2f2 CK |
491 | /* Always block for VM page tables before committing the new location */ |
492 | if (bo->type == ttm_bo_type_kernel) | |
493 | r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem); | |
494 | else | |
495 | r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); | |
f54d1867 | 496 | dma_fence_put(fence); |
d38ceaf9 | 497 | return r; |
8892f153 CK |
498 | |
499 | error: | |
500 | if (fence) | |
220196b3 DA |
501 | dma_fence_wait(fence, false); |
502 | dma_fence_put(fence); | |
8892f153 | 503 | return r; |
d38ceaf9 AD |
504 | } |
505 | ||
50da5174 TSD |
506 | /** |
507 | * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer | |
508 | * | |
509 | * Called by amdgpu_bo_move(). | |
510 | */ | |
dfb8fa98 CK |
511 | static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, |
512 | struct ttm_operation_ctx *ctx, | |
d38ceaf9 AD |
513 | struct ttm_mem_reg *new_mem) |
514 | { | |
515 | struct amdgpu_device *adev; | |
516 | struct ttm_mem_reg *old_mem = &bo->mem; | |
517 | struct ttm_mem_reg tmp_mem; | |
518 | struct ttm_place placements; | |
519 | struct ttm_placement placement; | |
520 | int r; | |
521 | ||
a7d64de6 | 522 | adev = amdgpu_ttm_adev(bo->bdev); |
50da5174 TSD |
523 | |
524 | /* create space/pages for new_mem in GTT space */ | |
d38ceaf9 AD |
525 | tmp_mem = *new_mem; |
526 | tmp_mem.mm_node = NULL; | |
527 | placement.num_placement = 1; | |
528 | placement.placement = &placements; | |
529 | placement.num_busy_placement = 1; | |
530 | placement.busy_placement = &placements; | |
531 | placements.fpfn = 0; | |
5e7e8396 | 532 | placements.lpfn = 0; |
d38ceaf9 | 533 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
dfb8fa98 | 534 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); |
d38ceaf9 AD |
535 | if (unlikely(r)) { |
536 | return r; | |
537 | } | |
538 | ||
50da5174 | 539 | /* set caching flags */ |
d38ceaf9 AD |
540 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); |
541 | if (unlikely(r)) { | |
542 | goto out_cleanup; | |
543 | } | |
544 | ||
50da5174 | 545 | /* Bind the memory to the GTT space */ |
993baf15 | 546 | r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx); |
d38ceaf9 AD |
547 | if (unlikely(r)) { |
548 | goto out_cleanup; | |
549 | } | |
50da5174 TSD |
550 | |
551 | /* blit VRAM to GTT */ | |
204029e1 | 552 | r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem); |
d38ceaf9 AD |
553 | if (unlikely(r)) { |
554 | goto out_cleanup; | |
555 | } | |
50da5174 TSD |
556 | |
557 | /* move BO (in tmp_mem) to new_mem */ | |
3e98d829 | 558 | r = ttm_bo_move_ttm(bo, ctx, new_mem); |
d38ceaf9 AD |
559 | out_cleanup: |
560 | ttm_bo_mem_put(bo, &tmp_mem); | |
561 | return r; | |
562 | } | |
563 | ||
50da5174 TSD |
564 | /** |
565 | * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM | |
566 | * | |
567 | * Called by amdgpu_bo_move(). | |
568 | */ | |
dfb8fa98 CK |
569 | static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, |
570 | struct ttm_operation_ctx *ctx, | |
d38ceaf9 AD |
571 | struct ttm_mem_reg *new_mem) |
572 | { | |
573 | struct amdgpu_device *adev; | |
574 | struct ttm_mem_reg *old_mem = &bo->mem; | |
575 | struct ttm_mem_reg tmp_mem; | |
576 | struct ttm_placement placement; | |
577 | struct ttm_place placements; | |
578 | int r; | |
579 | ||
a7d64de6 | 580 | adev = amdgpu_ttm_adev(bo->bdev); |
50da5174 TSD |
581 | |
582 | /* make space in GTT for old_mem buffer */ | |
d38ceaf9 AD |
583 | tmp_mem = *new_mem; |
584 | tmp_mem.mm_node = NULL; | |
585 | placement.num_placement = 1; | |
586 | placement.placement = &placements; | |
587 | placement.num_busy_placement = 1; | |
588 | placement.busy_placement = &placements; | |
589 | placements.fpfn = 0; | |
5e7e8396 | 590 | placements.lpfn = 0; |
d38ceaf9 | 591 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
dfb8fa98 | 592 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); |
d38ceaf9 AD |
593 | if (unlikely(r)) { |
594 | return r; | |
595 | } | |
50da5174 TSD |
596 | |
597 | /* move/bind old memory to GTT space */ | |
3e98d829 | 598 | r = ttm_bo_move_ttm(bo, ctx, &tmp_mem); |
d38ceaf9 AD |
599 | if (unlikely(r)) { |
600 | goto out_cleanup; | |
601 | } | |
50da5174 TSD |
602 | |
603 | /* copy to VRAM */ | |
204029e1 | 604 | r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem); |
d38ceaf9 AD |
605 | if (unlikely(r)) { |
606 | goto out_cleanup; | |
607 | } | |
608 | out_cleanup: | |
609 | ttm_bo_mem_put(bo, &tmp_mem); | |
610 | return r; | |
611 | } | |
612 | ||
50da5174 TSD |
613 | /** |
614 | * amdgpu_bo_move - Move a buffer object to a new memory location | |
615 | * | |
616 | * Called by ttm_bo_handle_move_mem() | |
617 | */ | |
2823f4f0 CK |
618 | static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, |
619 | struct ttm_operation_ctx *ctx, | |
620 | struct ttm_mem_reg *new_mem) | |
d38ceaf9 AD |
621 | { |
622 | struct amdgpu_device *adev; | |
104ece97 | 623 | struct amdgpu_bo *abo; |
d38ceaf9 AD |
624 | struct ttm_mem_reg *old_mem = &bo->mem; |
625 | int r; | |
626 | ||
104ece97 | 627 | /* Can't move a pinned BO */ |
b82485fd | 628 | abo = ttm_to_amdgpu_bo(bo); |
104ece97 MD |
629 | if (WARN_ON_ONCE(abo->pin_count > 0)) |
630 | return -EINVAL; | |
631 | ||
a7d64de6 | 632 | adev = amdgpu_ttm_adev(bo->bdev); |
dbd5ed60 | 633 | |
d38ceaf9 AD |
634 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { |
635 | amdgpu_move_null(bo, new_mem); | |
636 | return 0; | |
637 | } | |
638 | if ((old_mem->mem_type == TTM_PL_TT && | |
639 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
640 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
641 | new_mem->mem_type == TTM_PL_TT)) { | |
642 | /* bind is enough */ | |
643 | amdgpu_move_null(bo, new_mem); | |
644 | return 0; | |
645 | } | |
3b2de699 CK |
646 | if (old_mem->mem_type == AMDGPU_PL_GDS || |
647 | old_mem->mem_type == AMDGPU_PL_GWS || | |
648 | old_mem->mem_type == AMDGPU_PL_OA || | |
649 | new_mem->mem_type == AMDGPU_PL_GDS || | |
650 | new_mem->mem_type == AMDGPU_PL_GWS || | |
651 | new_mem->mem_type == AMDGPU_PL_OA) { | |
652 | /* Nothing to save here */ | |
653 | amdgpu_move_null(bo, new_mem); | |
654 | return 0; | |
655 | } | |
81988f9c CK |
656 | |
657 | if (!adev->mman.buffer_funcs_enabled) | |
d38ceaf9 | 658 | goto memcpy; |
d38ceaf9 AD |
659 | |
660 | if (old_mem->mem_type == TTM_PL_VRAM && | |
661 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
dfb8fa98 | 662 | r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); |
d38ceaf9 AD |
663 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
664 | new_mem->mem_type == TTM_PL_VRAM) { | |
dfb8fa98 | 665 | r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); |
d38ceaf9 | 666 | } else { |
2823f4f0 CK |
667 | r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, |
668 | new_mem, old_mem); | |
d38ceaf9 AD |
669 | } |
670 | ||
671 | if (r) { | |
672 | memcpy: | |
3e98d829 | 673 | r = ttm_bo_move_memcpy(bo, ctx, new_mem); |
d38ceaf9 AD |
674 | if (r) { |
675 | return r; | |
676 | } | |
677 | } | |
678 | ||
96cf8271 JB |
679 | if (bo->type == ttm_bo_type_device && |
680 | new_mem->mem_type == TTM_PL_VRAM && | |
681 | old_mem->mem_type != TTM_PL_VRAM) { | |
682 | /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU | |
683 | * accesses the BO after it's moved. | |
684 | */ | |
685 | abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
686 | } | |
687 | ||
d38ceaf9 AD |
688 | /* update statistics */ |
689 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); | |
690 | return 0; | |
691 | } | |
692 | ||
50da5174 TSD |
693 | /** |
694 | * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault | |
695 | * | |
696 | * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() | |
697 | */ | |
d38ceaf9 AD |
698 | static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
699 | { | |
700 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
a7d64de6 | 701 | struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); |
f8f4b9a6 | 702 | struct drm_mm_node *mm_node = mem->mm_node; |
d38ceaf9 AD |
703 | |
704 | mem->bus.addr = NULL; | |
705 | mem->bus.offset = 0; | |
706 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
707 | mem->bus.base = 0; | |
708 | mem->bus.is_iomem = false; | |
709 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
710 | return -EINVAL; | |
711 | switch (mem->mem_type) { | |
712 | case TTM_PL_SYSTEM: | |
713 | /* system memory */ | |
714 | return 0; | |
715 | case TTM_PL_TT: | |
716 | break; | |
717 | case TTM_PL_VRAM: | |
718 | mem->bus.offset = mem->start << PAGE_SHIFT; | |
719 | /* check if it's visible */ | |
770d13b1 | 720 | if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size) |
d38ceaf9 | 721 | return -EINVAL; |
f8f4b9a6 AL |
722 | /* Only physically contiguous buffers apply. In a contiguous |
723 | * buffer, size of the first mm_node would match the number of | |
724 | * pages in ttm_mem_reg. | |
725 | */ | |
726 | if (adev->mman.aper_base_kaddr && | |
727 | (mm_node->size == mem->num_pages)) | |
728 | mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + | |
729 | mem->bus.offset; | |
730 | ||
770d13b1 | 731 | mem->bus.base = adev->gmc.aper_base; |
d38ceaf9 | 732 | mem->bus.is_iomem = true; |
d38ceaf9 AD |
733 | break; |
734 | default: | |
735 | return -EINVAL; | |
736 | } | |
737 | return 0; | |
738 | } | |
739 | ||
740 | static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
741 | { | |
742 | } | |
743 | ||
9bbdcc0f CK |
744 | static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, |
745 | unsigned long page_offset) | |
746 | { | |
e1d51505 HK |
747 | struct drm_mm_node *mm; |
748 | unsigned long offset = (page_offset << PAGE_SHIFT); | |
9bbdcc0f | 749 | |
e1d51505 HK |
750 | mm = amdgpu_find_mm_node(&bo->mem, &offset); |
751 | return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + | |
752 | (offset >> PAGE_SHIFT); | |
9bbdcc0f CK |
753 | } |
754 | ||
d38ceaf9 AD |
755 | /* |
756 | * TTM backend functions. | |
757 | */ | |
637dd3b5 CK |
758 | struct amdgpu_ttm_gup_task_list { |
759 | struct list_head list; | |
760 | struct task_struct *task; | |
761 | }; | |
762 | ||
d38ceaf9 | 763 | struct amdgpu_ttm_tt { |
637dd3b5 | 764 | struct ttm_dma_tt ttm; |
637dd3b5 CK |
765 | u64 offset; |
766 | uint64_t userptr; | |
0919195f | 767 | struct task_struct *usertask; |
637dd3b5 CK |
768 | uint32_t userflags; |
769 | spinlock_t guptasklock; | |
770 | struct list_head guptasks; | |
2f568dbd | 771 | atomic_t mmu_invalidations; |
ca666a3c | 772 | uint32_t last_set_pages; |
d38ceaf9 AD |
773 | }; |
774 | ||
50da5174 | 775 | /** |
2e603d04 HR |
776 | * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR |
777 | * pointer to memory | |
50da5174 TSD |
778 | * |
779 | * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos(). | |
780 | * This provides a wrapper around the get_user_pages() call to provide | |
781 | * device accessible pages that back user memory. | |
782 | */ | |
2f568dbd | 783 | int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) |
d38ceaf9 | 784 | { |
d38ceaf9 | 785 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
0919195f | 786 | struct mm_struct *mm = gtt->usertask->mm; |
768ae309 | 787 | unsigned int flags = 0; |
2f568dbd CK |
788 | unsigned pinned = 0; |
789 | int r; | |
d38ceaf9 | 790 | |
0919195f FK |
791 | if (!mm) /* Happens during process shutdown */ |
792 | return -ESRCH; | |
793 | ||
768ae309 LS |
794 | if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) |
795 | flags |= FOLL_WRITE; | |
796 | ||
0919195f | 797 | down_read(&mm->mmap_sem); |
b72cf4fc | 798 | |
d38ceaf9 | 799 | if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { |
2e603d04 HR |
800 | /* |
801 | * check that we only use anonymous memory to prevent problems | |
802 | * with writeback | |
803 | */ | |
d38ceaf9 AD |
804 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; |
805 | struct vm_area_struct *vma; | |
806 | ||
0919195f | 807 | vma = find_vma(mm, gtt->userptr); |
b72cf4fc | 808 | if (!vma || vma->vm_file || vma->vm_end < end) { |
0919195f | 809 | up_read(&mm->mmap_sem); |
d38ceaf9 | 810 | return -EPERM; |
b72cf4fc | 811 | } |
d38ceaf9 AD |
812 | } |
813 | ||
50da5174 | 814 | /* loop enough times using contiguous pages of memory */ |
d38ceaf9 AD |
815 | do { |
816 | unsigned num_pages = ttm->num_pages - pinned; | |
817 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
2f568dbd | 818 | struct page **p = pages + pinned; |
637dd3b5 CK |
819 | struct amdgpu_ttm_gup_task_list guptask; |
820 | ||
821 | guptask.task = current; | |
822 | spin_lock(>t->guptasklock); | |
823 | list_add(&guptask.list, >t->guptasks); | |
824 | spin_unlock(>t->guptasklock); | |
d38ceaf9 | 825 | |
0919195f FK |
826 | if (mm == current->mm) |
827 | r = get_user_pages(userptr, num_pages, flags, p, NULL); | |
828 | else | |
829 | r = get_user_pages_remote(gtt->usertask, | |
830 | mm, userptr, num_pages, | |
831 | flags, p, NULL, NULL); | |
637dd3b5 CK |
832 | |
833 | spin_lock(>t->guptasklock); | |
834 | list_del(&guptask.list); | |
835 | spin_unlock(>t->guptasklock); | |
d38ceaf9 | 836 | |
d38ceaf9 AD |
837 | if (r < 0) |
838 | goto release_pages; | |
839 | ||
840 | pinned += r; | |
841 | ||
842 | } while (pinned < ttm->num_pages); | |
843 | ||
0919195f | 844 | up_read(&mm->mmap_sem); |
2f568dbd CK |
845 | return 0; |
846 | ||
847 | release_pages: | |
c6f92f9f | 848 | release_pages(pages, pinned); |
0919195f | 849 | up_read(&mm->mmap_sem); |
2f568dbd CK |
850 | return r; |
851 | } | |
852 | ||
50da5174 | 853 | /** |
2e603d04 | 854 | * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. |
50da5174 | 855 | * |
2e603d04 | 856 | * Called by amdgpu_cs_list_validate(). This creates the page list |
50da5174 TSD |
857 | * that backs user memory and will ultimately be mapped into the device |
858 | * address space. | |
859 | */ | |
a216ab09 | 860 | void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) |
aca81718 | 861 | { |
aca81718 TSD |
862 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
863 | unsigned i; | |
864 | ||
ca666a3c | 865 | gtt->last_set_pages = atomic_read(>t->mmu_invalidations); |
a216ab09 CK |
866 | for (i = 0; i < ttm->num_pages; ++i) { |
867 | if (ttm->pages[i]) | |
868 | put_page(ttm->pages[i]); | |
869 | ||
870 | ttm->pages[i] = pages ? pages[i] : NULL; | |
aca81718 TSD |
871 | } |
872 | } | |
873 | ||
50da5174 TSD |
874 | /** |
875 | * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty | |
876 | * | |
877 | * Called while unpinning userptr pages | |
878 | */ | |
1b0c0f9d | 879 | void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm) |
aca81718 | 880 | { |
aca81718 TSD |
881 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
882 | unsigned i; | |
883 | ||
1b0c0f9d CK |
884 | for (i = 0; i < ttm->num_pages; ++i) { |
885 | struct page *page = ttm->pages[i]; | |
886 | ||
887 | if (!page) | |
888 | continue; | |
889 | ||
890 | if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) | |
891 | set_page_dirty(page); | |
892 | ||
893 | mark_page_accessed(page); | |
aca81718 TSD |
894 | } |
895 | } | |
896 | ||
50da5174 | 897 | /** |
2e603d04 | 898 | * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages |
50da5174 TSD |
899 | * |
900 | * Called by amdgpu_ttm_backend_bind() | |
901 | **/ | |
2f568dbd CK |
902 | static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) |
903 | { | |
a7d64de6 | 904 | struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); |
2f568dbd CK |
905 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
906 | unsigned nents; | |
907 | int r; | |
908 | ||
909 | int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); | |
910 | enum dma_data_direction direction = write ? | |
911 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
912 | ||
50da5174 | 913 | /* Allocate an SG array and squash pages into it */ |
d38ceaf9 AD |
914 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, |
915 | ttm->num_pages << PAGE_SHIFT, | |
916 | GFP_KERNEL); | |
917 | if (r) | |
918 | goto release_sg; | |
919 | ||
50da5174 | 920 | /* Map SG to device */ |
d38ceaf9 AD |
921 | r = -ENOMEM; |
922 | nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
923 | if (nents != ttm->sg->nents) | |
924 | goto release_sg; | |
925 | ||
50da5174 | 926 | /* convert SG to linear array of pages and dma addresses */ |
d38ceaf9 AD |
927 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, |
928 | gtt->ttm.dma_address, ttm->num_pages); | |
929 | ||
930 | return 0; | |
931 | ||
932 | release_sg: | |
933 | kfree(ttm->sg); | |
d38ceaf9 AD |
934 | return r; |
935 | } | |
936 | ||
50da5174 TSD |
937 | /** |
938 | * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages | |
939 | */ | |
d38ceaf9 AD |
940 | static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) |
941 | { | |
a7d64de6 | 942 | struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); |
d38ceaf9 | 943 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
d38ceaf9 AD |
944 | |
945 | int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); | |
946 | enum dma_data_direction direction = write ? | |
947 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
948 | ||
949 | /* double check that we don't free the table twice */ | |
950 | if (!ttm->sg->sgl) | |
951 | return; | |
952 | ||
50da5174 | 953 | /* unmap the pages mapped to the device */ |
d38ceaf9 AD |
954 | dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); |
955 | ||
50da5174 | 956 | /* mark the pages as dirty */ |
1b0c0f9d | 957 | amdgpu_ttm_tt_mark_user_pages(ttm); |
aca81718 | 958 | |
d38ceaf9 AD |
959 | sg_free_table(ttm->sg); |
960 | } | |
961 | ||
959a2091 YZ |
962 | int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, |
963 | struct ttm_buffer_object *tbo, | |
964 | uint64_t flags) | |
965 | { | |
966 | struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); | |
967 | struct ttm_tt *ttm = tbo->ttm; | |
968 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
969 | int r; | |
970 | ||
971 | if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) { | |
972 | uint64_t page_idx = 1; | |
973 | ||
974 | r = amdgpu_gart_bind(adev, gtt->offset, page_idx, | |
975 | ttm->pages, gtt->ttm.dma_address, flags); | |
976 | if (r) | |
977 | goto gart_bind_fail; | |
978 | ||
979 | /* Patch mtype of the second part BO */ | |
980 | flags &= ~AMDGPU_PTE_MTYPE_MASK; | |
981 | flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC); | |
982 | ||
983 | r = amdgpu_gart_bind(adev, | |
984 | gtt->offset + (page_idx << PAGE_SHIFT), | |
985 | ttm->num_pages - page_idx, | |
986 | &ttm->pages[page_idx], | |
987 | &(gtt->ttm.dma_address[page_idx]), flags); | |
988 | } else { | |
989 | r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, | |
990 | ttm->pages, gtt->ttm.dma_address, flags); | |
991 | } | |
992 | ||
993 | gart_bind_fail: | |
994 | if (r) | |
995 | DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", | |
996 | ttm->num_pages, gtt->offset); | |
997 | ||
998 | return r; | |
999 | } | |
1000 | ||
50da5174 TSD |
1001 | /** |
1002 | * amdgpu_ttm_backend_bind - Bind GTT memory | |
1003 | * | |
1004 | * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). | |
1005 | * This handles binding GTT memory to the device address space. | |
1006 | */ | |
d38ceaf9 AD |
1007 | static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, |
1008 | struct ttm_mem_reg *bo_mem) | |
1009 | { | |
d9a13766 | 1010 | struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); |
d38ceaf9 | 1011 | struct amdgpu_ttm_tt *gtt = (void*)ttm; |
ac7afe6b | 1012 | uint64_t flags; |
2ce3f5dc | 1013 | int r = 0; |
d38ceaf9 | 1014 | |
e2f784fa CZ |
1015 | if (gtt->userptr) { |
1016 | r = amdgpu_ttm_tt_pin_userptr(ttm); | |
1017 | if (r) { | |
1018 | DRM_ERROR("failed to pin userptr\n"); | |
1019 | return r; | |
1020 | } | |
1021 | } | |
d38ceaf9 AD |
1022 | if (!ttm->num_pages) { |
1023 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
1024 | ttm->num_pages, bo_mem, ttm); | |
1025 | } | |
1026 | ||
1027 | if (bo_mem->mem_type == AMDGPU_PL_GDS || | |
1028 | bo_mem->mem_type == AMDGPU_PL_GWS || | |
1029 | bo_mem->mem_type == AMDGPU_PL_OA) | |
1030 | return -EINVAL; | |
1031 | ||
3da917b6 CK |
1032 | if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { |
1033 | gtt->offset = AMDGPU_BO_INVALID_OFFSET; | |
ac7afe6b | 1034 | return 0; |
3da917b6 | 1035 | } |
ac7afe6b | 1036 | |
50da5174 | 1037 | /* compute PTE flags relevant to this BO memory */ |
d9a13766 | 1038 | flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); |
50da5174 TSD |
1039 | |
1040 | /* bind pages into GART page tables */ | |
0957dc70 | 1041 | gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; |
d9a13766 | 1042 | r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, |
ac7afe6b CK |
1043 | ttm->pages, gtt->ttm.dma_address, flags); |
1044 | ||
c1c7ce8f | 1045 | if (r) |
ac7afe6b CK |
1046 | DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", |
1047 | ttm->num_pages, gtt->offset); | |
98a7f88c | 1048 | return r; |
c855e250 CK |
1049 | } |
1050 | ||
50da5174 TSD |
1051 | /** |
1052 | * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object | |
1053 | */ | |
c5835bbb | 1054 | int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) |
c855e250 | 1055 | { |
1d00402b | 1056 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); |
c13c55d6 | 1057 | struct ttm_operation_ctx ctx = { false, false }; |
40575732 | 1058 | struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; |
1d00402b | 1059 | struct ttm_mem_reg tmp; |
1d00402b CK |
1060 | struct ttm_placement placement; |
1061 | struct ttm_place placements; | |
485fc361 | 1062 | uint64_t addr, flags; |
c855e250 CK |
1063 | int r; |
1064 | ||
0e33495d | 1065 | if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) |
c855e250 CK |
1066 | return 0; |
1067 | ||
485fc361 CK |
1068 | addr = amdgpu_gmc_agp_addr(bo); |
1069 | if (addr != AMDGPU_BO_INVALID_OFFSET) { | |
1070 | bo->mem.start = addr >> PAGE_SHIFT; | |
1071 | } else { | |
1d00402b | 1072 | |
485fc361 CK |
1073 | /* allocate GART space */ |
1074 | tmp = bo->mem; | |
1075 | tmp.mm_node = NULL; | |
1076 | placement.num_placement = 1; | |
1077 | placement.placement = &placements; | |
1078 | placement.num_busy_placement = 1; | |
1079 | placement.busy_placement = &placements; | |
1080 | placements.fpfn = 0; | |
1081 | placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; | |
1082 | placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | | |
1083 | TTM_PL_FLAG_TT; | |
1084 | ||
1085 | r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); | |
1086 | if (unlikely(r)) | |
1087 | return r; | |
bb990bb0 | 1088 | |
485fc361 CK |
1089 | /* compute PTE flags for this buffer object */ |
1090 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); | |
50da5174 | 1091 | |
485fc361 | 1092 | /* Bind pages */ |
0957dc70 | 1093 | gtt->offset = (u64)tmp.start << PAGE_SHIFT; |
485fc361 CK |
1094 | r = amdgpu_ttm_gart_bind(adev, bo, flags); |
1095 | if (unlikely(r)) { | |
1096 | ttm_bo_mem_put(bo, &tmp); | |
1097 | return r; | |
1098 | } | |
1099 | ||
1100 | ttm_bo_mem_put(bo, &bo->mem); | |
1101 | bo->mem = tmp; | |
40575732 | 1102 | } |
1d00402b | 1103 | |
40575732 CK |
1104 | bo->offset = (bo->mem.start << PAGE_SHIFT) + |
1105 | bo->bdev->man[bo->mem.mem_type].gpu_offset; | |
1106 | ||
1107 | return 0; | |
d38ceaf9 AD |
1108 | } |
1109 | ||
50da5174 TSD |
1110 | /** |
1111 | * amdgpu_ttm_recover_gart - Rebind GTT pages | |
1112 | * | |
1113 | * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to | |
1114 | * rebind GTT pages during a GPU reset. | |
1115 | */ | |
c1c7ce8f | 1116 | int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) |
2c0d7318 | 1117 | { |
c1c7ce8f | 1118 | struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); |
1d1a2cd5 | 1119 | uint64_t flags; |
2c0d7318 CZ |
1120 | int r; |
1121 | ||
959a2091 | 1122 | if (!tbo->ttm) |
c1c7ce8f CK |
1123 | return 0; |
1124 | ||
959a2091 YZ |
1125 | flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem); |
1126 | r = amdgpu_ttm_gart_bind(adev, tbo, flags); | |
1127 | ||
c1c7ce8f | 1128 | return r; |
2c0d7318 CZ |
1129 | } |
1130 | ||
50da5174 TSD |
1131 | /** |
1132 | * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages | |
1133 | * | |
1134 | * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and | |
1135 | * ttm_tt_destroy(). | |
1136 | */ | |
d38ceaf9 AD |
1137 | static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) |
1138 | { | |
d9a13766 | 1139 | struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); |
d38ceaf9 | 1140 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
738f64cc | 1141 | int r; |
d38ceaf9 | 1142 | |
50da5174 | 1143 | /* if the pages have userptr pinning then clear that first */ |
85a4b579 CK |
1144 | if (gtt->userptr) |
1145 | amdgpu_ttm_tt_unpin_userptr(ttm); | |
1146 | ||
3da917b6 | 1147 | if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) |
78ab0a38 CK |
1148 | return 0; |
1149 | ||
d38ceaf9 | 1150 | /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ |
d9a13766 | 1151 | r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); |
c1c7ce8f | 1152 | if (r) |
738f64cc RH |
1153 | DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", |
1154 | gtt->ttm.ttm.num_pages, gtt->offset); | |
738f64cc | 1155 | return r; |
d38ceaf9 AD |
1156 | } |
1157 | ||
1158 | static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) | |
1159 | { | |
1160 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
1161 | ||
0919195f FK |
1162 | if (gtt->usertask) |
1163 | put_task_struct(gtt->usertask); | |
1164 | ||
d38ceaf9 AD |
1165 | ttm_dma_tt_fini(>t->ttm); |
1166 | kfree(gtt); | |
1167 | } | |
1168 | ||
1169 | static struct ttm_backend_func amdgpu_backend_func = { | |
1170 | .bind = &amdgpu_ttm_backend_bind, | |
1171 | .unbind = &amdgpu_ttm_backend_unbind, | |
1172 | .destroy = &amdgpu_ttm_backend_destroy, | |
1173 | }; | |
1174 | ||
50da5174 TSD |
1175 | /** |
1176 | * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO | |
1177 | * | |
1178 | * @bo: The buffer object to create a GTT ttm_tt object around | |
1179 | * | |
1180 | * Called by ttm_tt_create(). | |
1181 | */ | |
dde5da23 CK |
1182 | static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, |
1183 | uint32_t page_flags) | |
d38ceaf9 AD |
1184 | { |
1185 | struct amdgpu_device *adev; | |
1186 | struct amdgpu_ttm_tt *gtt; | |
1187 | ||
dde5da23 | 1188 | adev = amdgpu_ttm_adev(bo->bdev); |
d38ceaf9 AD |
1189 | |
1190 | gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); | |
1191 | if (gtt == NULL) { | |
1192 | return NULL; | |
1193 | } | |
1194 | gtt->ttm.ttm.func = &amdgpu_backend_func; | |
50da5174 TSD |
1195 | |
1196 | /* allocate space for the uninitialized page entries */ | |
dde5da23 | 1197 | if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) { |
d38ceaf9 AD |
1198 | kfree(gtt); |
1199 | return NULL; | |
1200 | } | |
1201 | return >t->ttm.ttm; | |
1202 | } | |
1203 | ||
50da5174 TSD |
1204 | /** |
1205 | * amdgpu_ttm_tt_populate - Map GTT pages visible to the device | |
1206 | * | |
1207 | * Map the pages of a ttm_tt object to an address space visible | |
1208 | * to the underlying device. | |
1209 | */ | |
d0cef9fa RH |
1210 | static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm, |
1211 | struct ttm_operation_ctx *ctx) | |
d38ceaf9 | 1212 | { |
aca81718 | 1213 | struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); |
d38ceaf9 | 1214 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
d38ceaf9 AD |
1215 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
1216 | ||
50da5174 | 1217 | /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ |
d38ceaf9 | 1218 | if (gtt && gtt->userptr) { |
5f0b34cc | 1219 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
d38ceaf9 AD |
1220 | if (!ttm->sg) |
1221 | return -ENOMEM; | |
1222 | ||
1223 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
1224 | ttm->state = tt_unbound; | |
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | if (slave && ttm->sg) { | |
1229 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
e89d0d33 CK |
1230 | gtt->ttm.dma_address, |
1231 | ttm->num_pages); | |
d38ceaf9 | 1232 | ttm->state = tt_unbound; |
79ba2800 | 1233 | return 0; |
d38ceaf9 AD |
1234 | } |
1235 | ||
d38ceaf9 | 1236 | #ifdef CONFIG_SWIOTLB |
fd5fd480 | 1237 | if (adev->need_swiotlb && swiotlb_nr_tbl()) { |
d0cef9fa | 1238 | return ttm_dma_populate(>t->ttm, adev->dev, ctx); |
d38ceaf9 AD |
1239 | } |
1240 | #endif | |
1241 | ||
50da5174 TSD |
1242 | /* fall back to generic helper to populate the page array |
1243 | * and map them to the device */ | |
d0cef9fa | 1244 | return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx); |
d38ceaf9 AD |
1245 | } |
1246 | ||
50da5174 TSD |
1247 | /** |
1248 | * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays | |
1249 | * | |
1250 | * Unmaps pages of a ttm_tt object from the device address space and | |
1251 | * unpopulates the page array backing it. | |
1252 | */ | |
d38ceaf9 AD |
1253 | static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) |
1254 | { | |
1255 | struct amdgpu_device *adev; | |
1256 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
d38ceaf9 AD |
1257 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
1258 | ||
1259 | if (gtt && gtt->userptr) { | |
a216ab09 | 1260 | amdgpu_ttm_tt_set_user_pages(ttm, NULL); |
d38ceaf9 AD |
1261 | kfree(ttm->sg); |
1262 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
1263 | return; | |
1264 | } | |
1265 | ||
1266 | if (slave) | |
1267 | return; | |
1268 | ||
a7d64de6 | 1269 | adev = amdgpu_ttm_adev(ttm->bdev); |
d38ceaf9 AD |
1270 | |
1271 | #ifdef CONFIG_SWIOTLB | |
fd5fd480 | 1272 | if (adev->need_swiotlb && swiotlb_nr_tbl()) { |
d38ceaf9 AD |
1273 | ttm_dma_unpopulate(>t->ttm, adev->dev); |
1274 | return; | |
1275 | } | |
1276 | #endif | |
1277 | ||
50da5174 | 1278 | /* fall back to generic helper to unmap and unpopulate array */ |
7405e0da | 1279 | ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm); |
d38ceaf9 AD |
1280 | } |
1281 | ||
50da5174 | 1282 | /** |
2e603d04 HR |
1283 | * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current |
1284 | * task | |
50da5174 TSD |
1285 | * |
1286 | * @ttm: The ttm_tt object to bind this userptr object to | |
1287 | * @addr: The address in the current tasks VM space to use | |
1288 | * @flags: Requirements of userptr object. | |
1289 | * | |
1290 | * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages | |
1291 | * to current task | |
1292 | */ | |
d38ceaf9 AD |
1293 | int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
1294 | uint32_t flags) | |
1295 | { | |
1296 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
1297 | ||
1298 | if (gtt == NULL) | |
1299 | return -EINVAL; | |
1300 | ||
1301 | gtt->userptr = addr; | |
d38ceaf9 | 1302 | gtt->userflags = flags; |
0919195f FK |
1303 | |
1304 | if (gtt->usertask) | |
1305 | put_task_struct(gtt->usertask); | |
1306 | gtt->usertask = current->group_leader; | |
1307 | get_task_struct(gtt->usertask); | |
1308 | ||
637dd3b5 CK |
1309 | spin_lock_init(>t->guptasklock); |
1310 | INIT_LIST_HEAD(>t->guptasks); | |
2f568dbd | 1311 | atomic_set(>t->mmu_invalidations, 0); |
ca666a3c | 1312 | gtt->last_set_pages = 0; |
637dd3b5 | 1313 | |
d38ceaf9 AD |
1314 | return 0; |
1315 | } | |
1316 | ||
50da5174 TSD |
1317 | /** |
1318 | * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object | |
1319 | */ | |
cc325d19 | 1320 | struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) |
d38ceaf9 AD |
1321 | { |
1322 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
1323 | ||
1324 | if (gtt == NULL) | |
cc325d19 | 1325 | return NULL; |
d38ceaf9 | 1326 | |
0919195f FK |
1327 | if (gtt->usertask == NULL) |
1328 | return NULL; | |
1329 | ||
1330 | return gtt->usertask->mm; | |
d38ceaf9 AD |
1331 | } |
1332 | ||
50da5174 | 1333 | /** |
2e603d04 HR |
1334 | * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an |
1335 | * address range for the current task. | |
50da5174 TSD |
1336 | * |
1337 | */ | |
cc1de6e8 CK |
1338 | bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, |
1339 | unsigned long end) | |
1340 | { | |
1341 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
637dd3b5 | 1342 | struct amdgpu_ttm_gup_task_list *entry; |
cc1de6e8 CK |
1343 | unsigned long size; |
1344 | ||
637dd3b5 | 1345 | if (gtt == NULL || !gtt->userptr) |
cc1de6e8 CK |
1346 | return false; |
1347 | ||
50da5174 TSD |
1348 | /* Return false if no part of the ttm_tt object lies within |
1349 | * the range | |
1350 | */ | |
cc1de6e8 CK |
1351 | size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; |
1352 | if (gtt->userptr > end || gtt->userptr + size <= start) | |
1353 | return false; | |
1354 | ||
50da5174 TSD |
1355 | /* Search the lists of tasks that hold this mapping and see |
1356 | * if current is one of them. If it is return false. | |
1357 | */ | |
637dd3b5 CK |
1358 | spin_lock(>t->guptasklock); |
1359 | list_for_each_entry(entry, >t->guptasks, list) { | |
1360 | if (entry->task == current) { | |
1361 | spin_unlock(>t->guptasklock); | |
1362 | return false; | |
1363 | } | |
1364 | } | |
1365 | spin_unlock(>t->guptasklock); | |
1366 | ||
2f568dbd CK |
1367 | atomic_inc(>t->mmu_invalidations); |
1368 | ||
cc1de6e8 CK |
1369 | return true; |
1370 | } | |
1371 | ||
50da5174 | 1372 | /** |
2e603d04 | 1373 | * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated? |
50da5174 | 1374 | */ |
2f568dbd CK |
1375 | bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, |
1376 | int *last_invalidated) | |
1377 | { | |
1378 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
1379 | int prev_invalidated = *last_invalidated; | |
1380 | ||
1381 | *last_invalidated = atomic_read(>t->mmu_invalidations); | |
1382 | return prev_invalidated != *last_invalidated; | |
1383 | } | |
1384 | ||
50da5174 | 1385 | /** |
2e603d04 HR |
1386 | * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object |
1387 | * been invalidated since the last time they've been set? | |
50da5174 | 1388 | */ |
ca666a3c CK |
1389 | bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm) |
1390 | { | |
1391 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
1392 | ||
1393 | if (gtt == NULL || !gtt->userptr) | |
1394 | return false; | |
1395 | ||
1396 | return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages; | |
1397 | } | |
1398 | ||
50da5174 TSD |
1399 | /** |
1400 | * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? | |
1401 | */ | |
d38ceaf9 AD |
1402 | bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) |
1403 | { | |
1404 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
1405 | ||
1406 | if (gtt == NULL) | |
1407 | return false; | |
1408 | ||
1409 | return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); | |
1410 | } | |
1411 | ||
50da5174 | 1412 | /** |
24a8d289 | 1413 | * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object |
50da5174 TSD |
1414 | * |
1415 | * @ttm: The ttm_tt object to compute the flags for | |
1416 | * @mem: The memory registry backing this ttm_tt object | |
24a8d289 CK |
1417 | * |
1418 | * Figure out the flags to use for a VM PDE (Page Directory Entry). | |
50da5174 | 1419 | */ |
24a8d289 | 1420 | uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem) |
d38ceaf9 | 1421 | { |
6b777607 | 1422 | uint64_t flags = 0; |
d38ceaf9 AD |
1423 | |
1424 | if (mem && mem->mem_type != TTM_PL_SYSTEM) | |
1425 | flags |= AMDGPU_PTE_VALID; | |
1426 | ||
6d99905a | 1427 | if (mem && mem->mem_type == TTM_PL_TT) { |
d38ceaf9 AD |
1428 | flags |= AMDGPU_PTE_SYSTEM; |
1429 | ||
6d99905a CK |
1430 | if (ttm->caching_state == tt_cached) |
1431 | flags |= AMDGPU_PTE_SNOOPED; | |
1432 | } | |
d38ceaf9 | 1433 | |
24a8d289 CK |
1434 | return flags; |
1435 | } | |
1436 | ||
1437 | /** | |
1438 | * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object | |
1439 | * | |
1440 | * @ttm: The ttm_tt object to compute the flags for | |
1441 | * @mem: The memory registry backing this ttm_tt object | |
1442 | ||
1443 | * Figure out the flags to use for a VM PTE (Page Table Entry). | |
1444 | */ | |
1445 | uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, | |
1446 | struct ttm_mem_reg *mem) | |
1447 | { | |
1448 | uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); | |
1449 | ||
4b98e0c4 | 1450 | flags |= adev->gart.gart_pte_flags; |
d38ceaf9 AD |
1451 | flags |= AMDGPU_PTE_READABLE; |
1452 | ||
1453 | if (!amdgpu_ttm_tt_is_readonly(ttm)) | |
1454 | flags |= AMDGPU_PTE_WRITEABLE; | |
1455 | ||
1456 | return flags; | |
1457 | } | |
1458 | ||
50da5174 | 1459 | /** |
2e603d04 HR |
1460 | * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer |
1461 | * object. | |
50da5174 | 1462 | * |
2e603d04 HR |
1463 | * Return true if eviction is sensible. Called by ttm_mem_evict_first() on |
1464 | * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until | |
1465 | * it can find space for a new object and by ttm_bo_force_list_clean() which is | |
50da5174 TSD |
1466 | * used to clean out a memory space. |
1467 | */ | |
9982ca68 CK |
1468 | static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, |
1469 | const struct ttm_place *place) | |
1470 | { | |
4fcae787 CK |
1471 | unsigned long num_pages = bo->mem.num_pages; |
1472 | struct drm_mm_node *node = bo->mem.mm_node; | |
d8d019cc FK |
1473 | struct reservation_object_list *flist; |
1474 | struct dma_fence *f; | |
1475 | int i; | |
1476 | ||
1477 | /* If bo is a KFD BO, check if the bo belongs to the current process. | |
1478 | * If true, then return false as any KFD process needs all its BOs to | |
1479 | * be resident to run successfully | |
1480 | */ | |
1481 | flist = reservation_object_get_list(bo->resv); | |
1482 | if (flist) { | |
1483 | for (i = 0; i < flist->shared_count; ++i) { | |
1484 | f = rcu_dereference_protected(flist->shared[i], | |
1485 | reservation_object_held(bo->resv)); | |
1486 | if (amdkfd_fence_check_mm(f, current->mm)) | |
1487 | return false; | |
1488 | } | |
1489 | } | |
9982ca68 | 1490 | |
4fcae787 CK |
1491 | switch (bo->mem.mem_type) { |
1492 | case TTM_PL_TT: | |
1493 | return true; | |
9982ca68 | 1494 | |
4fcae787 | 1495 | case TTM_PL_VRAM: |
9982ca68 CK |
1496 | /* Check each drm MM node individually */ |
1497 | while (num_pages) { | |
1498 | if (place->fpfn < (node->start + node->size) && | |
1499 | !(place->lpfn && place->lpfn <= node->start)) | |
1500 | return true; | |
1501 | ||
1502 | num_pages -= node->size; | |
1503 | ++node; | |
1504 | } | |
7da2e3e0 | 1505 | return false; |
9982ca68 | 1506 | |
4fcae787 CK |
1507 | default: |
1508 | break; | |
9982ca68 CK |
1509 | } |
1510 | ||
1511 | return ttm_bo_eviction_valuable(bo, place); | |
1512 | } | |
1513 | ||
50da5174 | 1514 | /** |
2e603d04 | 1515 | * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. |
50da5174 TSD |
1516 | * |
1517 | * @bo: The buffer object to read/write | |
1518 | * @offset: Offset into buffer object | |
1519 | * @buf: Secondary buffer to write/read from | |
1520 | * @len: Length in bytes of access | |
1521 | * @write: true if writing | |
1522 | * | |
1523 | * This is used to access VRAM that backs a buffer object via MMIO | |
1524 | * access for debugging purposes. | |
1525 | */ | |
e342610c FK |
1526 | static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, |
1527 | unsigned long offset, | |
1528 | void *buf, int len, int write) | |
1529 | { | |
b82485fd | 1530 | struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); |
e342610c | 1531 | struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); |
e1d51505 | 1532 | struct drm_mm_node *nodes; |
e342610c FK |
1533 | uint32_t value = 0; |
1534 | int ret = 0; | |
1535 | uint64_t pos; | |
1536 | unsigned long flags; | |
1537 | ||
1538 | if (bo->mem.mem_type != TTM_PL_VRAM) | |
1539 | return -EIO; | |
1540 | ||
e1d51505 | 1541 | nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset); |
e342610c FK |
1542 | pos = (nodes->start << PAGE_SHIFT) + offset; |
1543 | ||
770d13b1 | 1544 | while (len && pos < adev->gmc.mc_vram_size) { |
e342610c FK |
1545 | uint64_t aligned_pos = pos & ~(uint64_t)3; |
1546 | uint32_t bytes = 4 - (pos & 3); | |
1547 | uint32_t shift = (pos & 3) * 8; | |
1548 | uint32_t mask = 0xffffffff << shift; | |
1549 | ||
1550 | if (len < bytes) { | |
1551 | mask &= 0xffffffff >> (bytes - len) * 8; | |
1552 | bytes = len; | |
1553 | } | |
1554 | ||
1555 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
97bae49c TSD |
1556 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); |
1557 | WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); | |
e342610c | 1558 | if (!write || mask != 0xffffffff) |
97bae49c | 1559 | value = RREG32_NO_KIQ(mmMM_DATA); |
e342610c FK |
1560 | if (write) { |
1561 | value &= ~mask; | |
1562 | value |= (*(uint32_t *)buf << shift) & mask; | |
97bae49c | 1563 | WREG32_NO_KIQ(mmMM_DATA, value); |
e342610c FK |
1564 | } |
1565 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
1566 | if (!write) { | |
1567 | value = (value & mask) >> shift; | |
1568 | memcpy(buf, &value, bytes); | |
1569 | } | |
1570 | ||
1571 | ret += bytes; | |
1572 | buf = (uint8_t *)buf + bytes; | |
1573 | pos += bytes; | |
1574 | len -= bytes; | |
1575 | if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) { | |
1576 | ++nodes; | |
1577 | pos = (nodes->start << PAGE_SHIFT); | |
1578 | } | |
1579 | } | |
1580 | ||
1581 | return ret; | |
1582 | } | |
1583 | ||
d38ceaf9 AD |
1584 | static struct ttm_bo_driver amdgpu_bo_driver = { |
1585 | .ttm_tt_create = &amdgpu_ttm_tt_create, | |
1586 | .ttm_tt_populate = &amdgpu_ttm_tt_populate, | |
1587 | .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, | |
1588 | .invalidate_caches = &amdgpu_invalidate_caches, | |
1589 | .init_mem_type = &amdgpu_init_mem_type, | |
9982ca68 | 1590 | .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, |
d38ceaf9 AD |
1591 | .evict_flags = &amdgpu_evict_flags, |
1592 | .move = &amdgpu_bo_move, | |
1593 | .verify_access = &amdgpu_verify_access, | |
1594 | .move_notify = &amdgpu_bo_move_notify, | |
1595 | .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, | |
1596 | .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, | |
1597 | .io_mem_free = &amdgpu_ttm_io_mem_free, | |
9bbdcc0f | 1598 | .io_mem_pfn = amdgpu_ttm_io_mem_pfn, |
e342610c | 1599 | .access_memory = &amdgpu_ttm_access_memory |
d38ceaf9 AD |
1600 | }; |
1601 | ||
f5ec697e AD |
1602 | /* |
1603 | * Firmware Reservation functions | |
1604 | */ | |
1605 | /** | |
1606 | * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram | |
1607 | * | |
1608 | * @adev: amdgpu_device pointer | |
1609 | * | |
1610 | * free fw reserved vram if it has been reserved. | |
1611 | */ | |
1612 | static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) | |
1613 | { | |
1614 | amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo, | |
1615 | NULL, &adev->fw_vram_usage.va); | |
1616 | } | |
1617 | ||
1618 | /** | |
1619 | * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw | |
1620 | * | |
1621 | * @adev: amdgpu_device pointer | |
1622 | * | |
1623 | * create bo vram reservation from fw. | |
1624 | */ | |
1625 | static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) | |
1626 | { | |
1627 | struct ttm_operation_ctx ctx = { false, false }; | |
3216c6b7 | 1628 | struct amdgpu_bo_param bp; |
f5ec697e AD |
1629 | int r = 0; |
1630 | int i; | |
770d13b1 | 1631 | u64 vram_size = adev->gmc.visible_vram_size; |
f5ec697e AD |
1632 | u64 offset = adev->fw_vram_usage.start_offset; |
1633 | u64 size = adev->fw_vram_usage.size; | |
1634 | struct amdgpu_bo *bo; | |
1635 | ||
3216c6b7 CZ |
1636 | memset(&bp, 0, sizeof(bp)); |
1637 | bp.size = adev->fw_vram_usage.size; | |
1638 | bp.byte_align = PAGE_SIZE; | |
1639 | bp.domain = AMDGPU_GEM_DOMAIN_VRAM; | |
1640 | bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | | |
1641 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; | |
1642 | bp.type = ttm_bo_type_kernel; | |
1643 | bp.resv = NULL; | |
f5ec697e AD |
1644 | adev->fw_vram_usage.va = NULL; |
1645 | adev->fw_vram_usage.reserved_bo = NULL; | |
1646 | ||
1647 | if (adev->fw_vram_usage.size > 0 && | |
1648 | adev->fw_vram_usage.size <= vram_size) { | |
1649 | ||
3216c6b7 | 1650 | r = amdgpu_bo_create(adev, &bp, |
eab3de23 | 1651 | &adev->fw_vram_usage.reserved_bo); |
f5ec697e AD |
1652 | if (r) |
1653 | goto error_create; | |
1654 | ||
1655 | r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); | |
1656 | if (r) | |
1657 | goto error_reserve; | |
1658 | ||
1659 | /* remove the original mem node and create a new one at the | |
1660 | * request position | |
1661 | */ | |
1662 | bo = adev->fw_vram_usage.reserved_bo; | |
1663 | offset = ALIGN(offset, PAGE_SIZE); | |
1664 | for (i = 0; i < bo->placement.num_placement; ++i) { | |
1665 | bo->placements[i].fpfn = offset >> PAGE_SHIFT; | |
1666 | bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; | |
1667 | } | |
1668 | ||
1669 | ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); | |
1670 | r = ttm_bo_mem_space(&bo->tbo, &bo->placement, | |
1671 | &bo->tbo.mem, &ctx); | |
1672 | if (r) | |
1673 | goto error_pin; | |
1674 | ||
1675 | r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, | |
1676 | AMDGPU_GEM_DOMAIN_VRAM, | |
1677 | adev->fw_vram_usage.start_offset, | |
1678 | (adev->fw_vram_usage.start_offset + | |
7b7c6c81 | 1679 | adev->fw_vram_usage.size)); |
f5ec697e AD |
1680 | if (r) |
1681 | goto error_pin; | |
1682 | r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, | |
1683 | &adev->fw_vram_usage.va); | |
1684 | if (r) | |
1685 | goto error_kmap; | |
1686 | ||
1687 | amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); | |
1688 | } | |
1689 | return r; | |
1690 | ||
1691 | error_kmap: | |
1692 | amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo); | |
1693 | error_pin: | |
1694 | amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo); | |
1695 | error_reserve: | |
1696 | amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo); | |
1697 | error_create: | |
1698 | adev->fw_vram_usage.va = NULL; | |
1699 | adev->fw_vram_usage.reserved_bo = NULL; | |
1700 | return r; | |
1701 | } | |
50da5174 | 1702 | /** |
2e603d04 HR |
1703 | * amdgpu_ttm_init - Init the memory management (ttm) as well as various |
1704 | * gtt/vram related fields. | |
50da5174 TSD |
1705 | * |
1706 | * This initializes all of the memory space pools that the TTM layer | |
1707 | * will need such as the GTT space (system memory mapped to the device), | |
1708 | * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which | |
1709 | * can be mapped per VMID. | |
1710 | */ | |
d38ceaf9 AD |
1711 | int amdgpu_ttm_init(struct amdgpu_device *adev) |
1712 | { | |
36d38372 | 1713 | uint64_t gtt_size; |
d38ceaf9 | 1714 | int r; |
218b5dcd | 1715 | u64 vis_vram_limit; |
d38ceaf9 | 1716 | |
50da5174 | 1717 | /* initialize global references for vram/gtt */ |
70b5c5aa AD |
1718 | r = amdgpu_ttm_global_init(adev); |
1719 | if (r) { | |
1720 | return r; | |
1721 | } | |
d38ceaf9 AD |
1722 | /* No others user of address space so set it to 0 */ |
1723 | r = ttm_bo_device_init(&adev->mman.bdev, | |
1724 | adev->mman.bo_global_ref.ref.object, | |
1725 | &amdgpu_bo_driver, | |
1726 | adev->ddev->anon_inode->i_mapping, | |
1727 | DRM_FILE_PAGE_OFFSET, | |
1728 | adev->need_dma32); | |
1729 | if (r) { | |
1730 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
1731 | return r; | |
1732 | } | |
1733 | adev->mman.initialized = true; | |
7cce9584 AG |
1734 | |
1735 | /* We opt to avoid OOM on system pages allocations */ | |
1736 | adev->mman.bdev.no_retry = true; | |
1737 | ||
50da5174 | 1738 | /* Initialize VRAM pool with all of VRAM divided into pages */ |
d38ceaf9 | 1739 | r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, |
770d13b1 | 1740 | adev->gmc.real_vram_size >> PAGE_SHIFT); |
d38ceaf9 AD |
1741 | if (r) { |
1742 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
1743 | return r; | |
1744 | } | |
218b5dcd JB |
1745 | |
1746 | /* Reduce size of CPU-visible VRAM if requested */ | |
1747 | vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; | |
1748 | if (amdgpu_vis_vram_limit > 0 && | |
770d13b1 CK |
1749 | vis_vram_limit <= adev->gmc.visible_vram_size) |
1750 | adev->gmc.visible_vram_size = vis_vram_limit; | |
218b5dcd | 1751 | |
d38ceaf9 | 1752 | /* Change the size here instead of the init above so only lpfn is affected */ |
57adc4ce | 1753 | amdgpu_ttm_set_buffer_funcs_status(adev, false); |
f8f4b9a6 AL |
1754 | #ifdef CONFIG_64BIT |
1755 | adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, | |
1756 | adev->gmc.visible_vram_size); | |
1757 | #endif | |
d38ceaf9 | 1758 | |
a05502e5 HC |
1759 | /* |
1760 | *The reserved vram for firmware must be pinned to the specified | |
1761 | *place on the VRAM, so reserve it early. | |
1762 | */ | |
f5ec697e | 1763 | r = amdgpu_ttm_fw_reserve_vram_init(adev); |
a05502e5 HC |
1764 | if (r) { |
1765 | return r; | |
1766 | } | |
1767 | ||
50da5174 TSD |
1768 | /* allocate memory as required for VGA |
1769 | * This is used for VGA emulation and pre-OS scanout buffers to | |
1770 | * avoid display artifacts while transitioning between pre-OS | |
1771 | * and driver. */ | |
52975728 CK |
1772 | r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, |
1773 | AMDGPU_GEM_DOMAIN_VRAM, | |
1774 | &adev->stolen_vga_memory, | |
1775 | NULL, NULL); | |
1776 | if (r) | |
1777 | return r; | |
d38ceaf9 | 1778 | DRM_INFO("amdgpu: %uM of VRAM memory ready\n", |
770d13b1 | 1779 | (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); |
36d38372 | 1780 | |
50da5174 TSD |
1781 | /* Compute GTT size, either bsaed on 3/4th the size of RAM size |
1782 | * or whatever the user passed on module init */ | |
424e2c85 RH |
1783 | if (amdgpu_gtt_size == -1) { |
1784 | struct sysinfo si; | |
1785 | ||
1786 | si_meminfo(&si); | |
24562523 | 1787 | gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), |
770d13b1 | 1788 | adev->gmc.mc_vram_size), |
24562523 AG |
1789 | ((uint64_t)si.totalram * si.mem_unit * 3/4)); |
1790 | } | |
1791 | else | |
36d38372 | 1792 | gtt_size = (uint64_t)amdgpu_gtt_size << 20; |
50da5174 TSD |
1793 | |
1794 | /* Initialize GTT memory pool */ | |
36d38372 | 1795 | r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); |
d38ceaf9 AD |
1796 | if (r) { |
1797 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
1798 | return r; | |
1799 | } | |
1800 | DRM_INFO("amdgpu: %uM of GTT memory ready.\n", | |
36d38372 | 1801 | (unsigned)(gtt_size / (1024 * 1024))); |
d38ceaf9 | 1802 | |
50da5174 | 1803 | /* Initialize various on-chip memory pools */ |
c832c346 CK |
1804 | r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, |
1805 | adev->gds.mem.total_size); | |
1806 | if (r) { | |
1807 | DRM_ERROR("Failed initializing GDS heap.\n"); | |
1808 | return r; | |
d38ceaf9 AD |
1809 | } |
1810 | ||
fd395547 CK |
1811 | r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, |
1812 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, | |
1813 | &adev->gds.gds_gfx_bo, NULL, NULL); | |
1814 | if (r) | |
1815 | return r; | |
1816 | ||
c832c346 CK |
1817 | r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, |
1818 | adev->gds.gws.total_size); | |
1819 | if (r) { | |
1820 | DRM_ERROR("Failed initializing gws heap.\n"); | |
1821 | return r; | |
d38ceaf9 AD |
1822 | } |
1823 | ||
fd395547 CK |
1824 | r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, |
1825 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, | |
1826 | &adev->gds.gws_gfx_bo, NULL, NULL); | |
1827 | if (r) | |
1828 | return r; | |
1829 | ||
c832c346 CK |
1830 | r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, |
1831 | adev->gds.oa.total_size); | |
1832 | if (r) { | |
1833 | DRM_ERROR("Failed initializing oa heap.\n"); | |
1834 | return r; | |
d38ceaf9 AD |
1835 | } |
1836 | ||
fd395547 CK |
1837 | r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, |
1838 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, | |
1839 | &adev->gds.oa_gfx_bo, NULL, NULL); | |
1840 | if (r) | |
1841 | return r; | |
1842 | ||
50da5174 | 1843 | /* Register debugfs entries for amdgpu_ttm */ |
d38ceaf9 AD |
1844 | r = amdgpu_ttm_debugfs_init(adev); |
1845 | if (r) { | |
1846 | DRM_ERROR("Failed to init debugfs\n"); | |
1847 | return r; | |
1848 | } | |
1849 | return 0; | |
1850 | } | |
1851 | ||
50da5174 | 1852 | /** |
2e603d04 | 1853 | * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm |
50da5174 | 1854 | */ |
6f752ec2 AG |
1855 | void amdgpu_ttm_late_init(struct amdgpu_device *adev) |
1856 | { | |
50da5174 | 1857 | /* return the VGA stolen memory (if any) back to VRAM */ |
6f752ec2 AG |
1858 | amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); |
1859 | } | |
1860 | ||
50da5174 TSD |
1861 | /** |
1862 | * amdgpu_ttm_fini - De-initialize the TTM memory pools | |
1863 | */ | |
d38ceaf9 AD |
1864 | void amdgpu_ttm_fini(struct amdgpu_device *adev) |
1865 | { | |
d38ceaf9 AD |
1866 | if (!adev->mman.initialized) |
1867 | return; | |
11c6b82a | 1868 | |
d38ceaf9 | 1869 | amdgpu_ttm_debugfs_fini(adev); |
f5ec697e | 1870 | amdgpu_ttm_fw_reserve_vram_fini(adev); |
f8f4b9a6 AL |
1871 | if (adev->mman.aper_base_kaddr) |
1872 | iounmap(adev->mman.aper_base_kaddr); | |
1873 | adev->mman.aper_base_kaddr = NULL; | |
11c6b82a | 1874 | |
d38ceaf9 AD |
1875 | ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); |
1876 | ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); | |
c832c346 CK |
1877 | ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); |
1878 | ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); | |
1879 | ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); | |
d38ceaf9 | 1880 | ttm_bo_device_release(&adev->mman.bdev); |
d38ceaf9 AD |
1881 | amdgpu_ttm_global_fini(adev); |
1882 | adev->mman.initialized = false; | |
1883 | DRM_INFO("amdgpu: ttm finalized\n"); | |
1884 | } | |
1885 | ||
57adc4ce CK |
1886 | /** |
1887 | * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions | |
1888 | * | |
1889 | * @adev: amdgpu_device pointer | |
1890 | * @enable: true when we can use buffer functions. | |
1891 | * | |
1892 | * Enable/disable use of buffer functions during suspend/resume. This should | |
1893 | * only be called at bootup or when userspace isn't running. | |
1894 | */ | |
1895 | void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) | |
d38ceaf9 | 1896 | { |
57adc4ce CK |
1897 | struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM]; |
1898 | uint64_t size; | |
b7d85e1d | 1899 | int r; |
d38ceaf9 | 1900 | |
b7d85e1d CK |
1901 | if (!adev->mman.initialized || adev->in_gpu_reset || |
1902 | adev->mman.buffer_funcs_enabled == enable) | |
d38ceaf9 AD |
1903 | return; |
1904 | ||
b7d85e1d CK |
1905 | if (enable) { |
1906 | struct amdgpu_ring *ring; | |
1907 | struct drm_sched_rq *rq; | |
1908 | ||
1909 | ring = adev->mman.buffer_funcs_ring; | |
1910 | rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL]; | |
aa16b6c6 | 1911 | r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL); |
b7d85e1d CK |
1912 | if (r) { |
1913 | DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", | |
1914 | r); | |
1915 | return; | |
1916 | } | |
1917 | } else { | |
cdc50176 | 1918 | drm_sched_entity_destroy(&adev->mman.entity); |
7766484b AG |
1919 | dma_fence_put(man->move); |
1920 | man->move = NULL; | |
b7d85e1d CK |
1921 | } |
1922 | ||
d38ceaf9 | 1923 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ |
57adc4ce CK |
1924 | if (enable) |
1925 | size = adev->gmc.real_vram_size; | |
1926 | else | |
1927 | size = adev->gmc.visible_vram_size; | |
d38ceaf9 | 1928 | man->size = size >> PAGE_SHIFT; |
81988f9c | 1929 | adev->mman.buffer_funcs_enabled = enable; |
d38ceaf9 AD |
1930 | } |
1931 | ||
d38ceaf9 AD |
1932 | int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) |
1933 | { | |
1934 | struct drm_file *file_priv; | |
1935 | struct amdgpu_device *adev; | |
d38ceaf9 | 1936 | |
e176fe17 | 1937 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) |
d38ceaf9 | 1938 | return -EINVAL; |
d38ceaf9 AD |
1939 | |
1940 | file_priv = filp->private_data; | |
1941 | adev = file_priv->minor->dev->dev_private; | |
e176fe17 | 1942 | if (adev == NULL) |
d38ceaf9 | 1943 | return -EINVAL; |
e176fe17 CK |
1944 | |
1945 | return ttm_bo_mmap(filp, vma, &adev->mman.bdev); | |
d38ceaf9 AD |
1946 | } |
1947 | ||
abca90f1 CK |
1948 | static int amdgpu_map_buffer(struct ttm_buffer_object *bo, |
1949 | struct ttm_mem_reg *mem, unsigned num_pages, | |
1950 | uint64_t offset, unsigned window, | |
1951 | struct amdgpu_ring *ring, | |
1952 | uint64_t *addr) | |
1953 | { | |
1954 | struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; | |
1955 | struct amdgpu_device *adev = ring->adev; | |
1956 | struct ttm_tt *ttm = bo->ttm; | |
1957 | struct amdgpu_job *job; | |
1958 | unsigned num_dw, num_bytes; | |
1959 | dma_addr_t *dma_address; | |
1960 | struct dma_fence *fence; | |
1961 | uint64_t src_addr, dst_addr; | |
1962 | uint64_t flags; | |
1963 | int r; | |
1964 | ||
1965 | BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < | |
1966 | AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); | |
1967 | ||
770d13b1 | 1968 | *addr = adev->gmc.gart_start; |
abca90f1 CK |
1969 | *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * |
1970 | AMDGPU_GPU_PAGE_SIZE; | |
1971 | ||
1972 | num_dw = adev->mman.buffer_funcs->copy_num_dw; | |
1973 | while (num_dw & 0x7) | |
1974 | num_dw++; | |
1975 | ||
1976 | num_bytes = num_pages * 8; | |
1977 | ||
1978 | r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job); | |
1979 | if (r) | |
1980 | return r; | |
1981 | ||
1982 | src_addr = num_dw * 4; | |
1983 | src_addr += job->ibs[0].gpu_addr; | |
1984 | ||
4e830fb1 | 1985 | dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); |
abca90f1 CK |
1986 | dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; |
1987 | amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, | |
1988 | dst_addr, num_bytes); | |
1989 | ||
1990 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
1991 | WARN_ON(job->ibs[0].length_dw > num_dw); | |
1992 | ||
1993 | dma_address = >t->ttm.dma_address[offset >> PAGE_SHIFT]; | |
1994 | flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem); | |
1995 | r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags, | |
1996 | &job->ibs[0].ptr[num_dw]); | |
1997 | if (r) | |
1998 | goto error_free; | |
1999 | ||
0e28b10f | 2000 | r = amdgpu_job_submit(job, &adev->mman.entity, |
abca90f1 CK |
2001 | AMDGPU_FENCE_OWNER_UNDEFINED, &fence); |
2002 | if (r) | |
2003 | goto error_free; | |
2004 | ||
2005 | dma_fence_put(fence); | |
2006 | ||
2007 | return r; | |
2008 | ||
2009 | error_free: | |
2010 | amdgpu_job_free(job); | |
2011 | return r; | |
2012 | } | |
2013 | ||
fc9c8f54 CK |
2014 | int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, |
2015 | uint64_t dst_offset, uint32_t byte_count, | |
d38ceaf9 | 2016 | struct reservation_object *resv, |
fc9c8f54 CK |
2017 | struct dma_fence **fence, bool direct_submit, |
2018 | bool vm_needs_flush) | |
d38ceaf9 AD |
2019 | { |
2020 | struct amdgpu_device *adev = ring->adev; | |
d71518b5 CK |
2021 | struct amdgpu_job *job; |
2022 | ||
d38ceaf9 AD |
2023 | uint32_t max_bytes; |
2024 | unsigned num_loops, num_dw; | |
2025 | unsigned i; | |
2026 | int r; | |
2027 | ||
81988f9c CK |
2028 | if (direct_submit && !ring->ready) { |
2029 | DRM_ERROR("Trying to move memory with ring turned off.\n"); | |
2030 | return -EINVAL; | |
2031 | } | |
2032 | ||
d38ceaf9 AD |
2033 | max_bytes = adev->mman.buffer_funcs->copy_max_bytes; |
2034 | num_loops = DIV_ROUND_UP(byte_count, max_bytes); | |
2035 | num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; | |
2036 | ||
c7ae72c0 CZ |
2037 | /* for IB padding */ |
2038 | while (num_dw & 0x7) | |
2039 | num_dw++; | |
2040 | ||
d71518b5 CK |
2041 | r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); |
2042 | if (r) | |
9066b0c3 | 2043 | return r; |
c7ae72c0 | 2044 | |
cbd52851 | 2045 | if (vm_needs_flush) { |
11c3a249 | 2046 | job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); |
cbd52851 CK |
2047 | job->vm_needs_flush = true; |
2048 | } | |
c7ae72c0 | 2049 | if (resv) { |
e86f9cee | 2050 | r = amdgpu_sync_resv(adev, &job->sync, resv, |
177ae09b AR |
2051 | AMDGPU_FENCE_OWNER_UNDEFINED, |
2052 | false); | |
c7ae72c0 CZ |
2053 | if (r) { |
2054 | DRM_ERROR("sync failed (%d).\n", r); | |
2055 | goto error_free; | |
2056 | } | |
d38ceaf9 | 2057 | } |
d38ceaf9 AD |
2058 | |
2059 | for (i = 0; i < num_loops; i++) { | |
2060 | uint32_t cur_size_in_bytes = min(byte_count, max_bytes); | |
2061 | ||
d71518b5 CK |
2062 | amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, |
2063 | dst_offset, cur_size_in_bytes); | |
d38ceaf9 AD |
2064 | |
2065 | src_offset += cur_size_in_bytes; | |
2066 | dst_offset += cur_size_in_bytes; | |
2067 | byte_count -= cur_size_in_bytes; | |
2068 | } | |
2069 | ||
d71518b5 CK |
2070 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
2071 | WARN_ON(job->ibs[0].length_dw > num_dw); | |
ee913fd9 CK |
2072 | if (direct_submit) |
2073 | r = amdgpu_job_submit_direct(job, ring, fence); | |
2074 | else | |
0e28b10f | 2075 | r = amdgpu_job_submit(job, &adev->mman.entity, |
e24db985 | 2076 | AMDGPU_FENCE_OWNER_UNDEFINED, fence); |
ee913fd9 CK |
2077 | if (r) |
2078 | goto error_free; | |
d38ceaf9 | 2079 | |
e24db985 | 2080 | return r; |
d71518b5 | 2081 | |
c7ae72c0 | 2082 | error_free: |
d71518b5 | 2083 | amdgpu_job_free(job); |
ee913fd9 | 2084 | DRM_ERROR("Error scheduling IBs (%d)\n", r); |
c7ae72c0 | 2085 | return r; |
d38ceaf9 AD |
2086 | } |
2087 | ||
59b4a977 | 2088 | int amdgpu_fill_buffer(struct amdgpu_bo *bo, |
44e1baeb | 2089 | uint32_t src_data, |
f29224a6 CK |
2090 | struct reservation_object *resv, |
2091 | struct dma_fence **fence) | |
59b4a977 | 2092 | { |
a7d64de6 | 2093 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
44e1baeb | 2094 | uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; |
59b4a977 FC |
2095 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; |
2096 | ||
f29224a6 CK |
2097 | struct drm_mm_node *mm_node; |
2098 | unsigned long num_pages; | |
59b4a977 | 2099 | unsigned int num_loops, num_dw; |
f29224a6 CK |
2100 | |
2101 | struct amdgpu_job *job; | |
59b4a977 FC |
2102 | int r; |
2103 | ||
81988f9c | 2104 | if (!adev->mman.buffer_funcs_enabled) { |
f29224a6 CK |
2105 | DRM_ERROR("Trying to clear memory with ring turned off.\n"); |
2106 | return -EINVAL; | |
2107 | } | |
2108 | ||
92c60d9c | 2109 | if (bo->tbo.mem.mem_type == TTM_PL_TT) { |
c5835bbb | 2110 | r = amdgpu_ttm_alloc_gart(&bo->tbo); |
92c60d9c CK |
2111 | if (r) |
2112 | return r; | |
2113 | } | |
2114 | ||
f29224a6 CK |
2115 | num_pages = bo->tbo.num_pages; |
2116 | mm_node = bo->tbo.mem.mm_node; | |
2117 | num_loops = 0; | |
2118 | while (num_pages) { | |
2119 | uint32_t byte_count = mm_node->size << PAGE_SHIFT; | |
2120 | ||
2121 | num_loops += DIV_ROUND_UP(byte_count, max_bytes); | |
2122 | num_pages -= mm_node->size; | |
2123 | ++mm_node; | |
2124 | } | |
44e1baeb | 2125 | num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; |
59b4a977 FC |
2126 | |
2127 | /* for IB padding */ | |
f29224a6 | 2128 | num_dw += 64; |
59b4a977 FC |
2129 | |
2130 | r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); | |
2131 | if (r) | |
2132 | return r; | |
2133 | ||
2134 | if (resv) { | |
2135 | r = amdgpu_sync_resv(adev, &job->sync, resv, | |
177ae09b | 2136 | AMDGPU_FENCE_OWNER_UNDEFINED, false); |
59b4a977 FC |
2137 | if (r) { |
2138 | DRM_ERROR("sync failed (%d).\n", r); | |
2139 | goto error_free; | |
2140 | } | |
2141 | } | |
2142 | ||
f29224a6 CK |
2143 | num_pages = bo->tbo.num_pages; |
2144 | mm_node = bo->tbo.mem.mm_node; | |
59b4a977 | 2145 | |
f29224a6 CK |
2146 | while (num_pages) { |
2147 | uint32_t byte_count = mm_node->size << PAGE_SHIFT; | |
2148 | uint64_t dst_addr; | |
59b4a977 | 2149 | |
92c60d9c | 2150 | dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); |
f29224a6 CK |
2151 | while (byte_count) { |
2152 | uint32_t cur_size_in_bytes = min(byte_count, max_bytes); | |
2153 | ||
44e1baeb CK |
2154 | amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, |
2155 | dst_addr, cur_size_in_bytes); | |
f29224a6 CK |
2156 | |
2157 | dst_addr += cur_size_in_bytes; | |
2158 | byte_count -= cur_size_in_bytes; | |
2159 | } | |
2160 | ||
2161 | num_pages -= mm_node->size; | |
2162 | ++mm_node; | |
59b4a977 FC |
2163 | } |
2164 | ||
2165 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
2166 | WARN_ON(job->ibs[0].length_dw > num_dw); | |
0e28b10f | 2167 | r = amdgpu_job_submit(job, &adev->mman.entity, |
f29224a6 | 2168 | AMDGPU_FENCE_OWNER_UNDEFINED, fence); |
59b4a977 FC |
2169 | if (r) |
2170 | goto error_free; | |
2171 | ||
2172 | return 0; | |
2173 | ||
2174 | error_free: | |
2175 | amdgpu_job_free(job); | |
2176 | return r; | |
2177 | } | |
2178 | ||
d38ceaf9 AD |
2179 | #if defined(CONFIG_DEBUG_FS) |
2180 | ||
2181 | static int amdgpu_mm_dump_table(struct seq_file *m, void *data) | |
2182 | { | |
2183 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
0ee86853 | 2184 | unsigned ttm_pl = (uintptr_t)node->info_ent->data; |
d38ceaf9 AD |
2185 | struct drm_device *dev = node->minor->dev; |
2186 | struct amdgpu_device *adev = dev->dev_private; | |
12d4ac58 | 2187 | struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl]; |
b5c3714f | 2188 | struct drm_printer p = drm_seq_file_printer(m); |
d38ceaf9 | 2189 | |
12d4ac58 | 2190 | man->func->debug(man, &p); |
b5c3714f | 2191 | return 0; |
d38ceaf9 AD |
2192 | } |
2193 | ||
06ab6832 | 2194 | static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { |
0ee86853 CK |
2195 | {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM}, |
2196 | {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT}, | |
2197 | {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS}, | |
2198 | {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS}, | |
2199 | {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA}, | |
d38ceaf9 AD |
2200 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, |
2201 | #ifdef CONFIG_SWIOTLB | |
2202 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
2203 | #endif | |
2204 | }; | |
2205 | ||
50da5174 TSD |
2206 | /** |
2207 | * amdgpu_ttm_vram_read - Linear read access to VRAM | |
2208 | * | |
2209 | * Accesses VRAM via MMIO for debugging purposes. | |
2210 | */ | |
d38ceaf9 AD |
2211 | static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, |
2212 | size_t size, loff_t *pos) | |
2213 | { | |
45063097 | 2214 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
2215 | ssize_t result = 0; |
2216 | int r; | |
2217 | ||
2218 | if (size & 0x3 || *pos & 0x3) | |
2219 | return -EINVAL; | |
2220 | ||
770d13b1 | 2221 | if (*pos >= adev->gmc.mc_vram_size) |
9156e723 TSD |
2222 | return -ENXIO; |
2223 | ||
d38ceaf9 AD |
2224 | while (size) { |
2225 | unsigned long flags; | |
2226 | uint32_t value; | |
2227 | ||
770d13b1 | 2228 | if (*pos >= adev->gmc.mc_vram_size) |
d38ceaf9 AD |
2229 | return result; |
2230 | ||
2231 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
c3057281 TSD |
2232 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); |
2233 | WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); | |
2234 | value = RREG32_NO_KIQ(mmMM_DATA); | |
d38ceaf9 AD |
2235 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); |
2236 | ||
2237 | r = put_user(value, (uint32_t *)buf); | |
2238 | if (r) | |
2239 | return r; | |
2240 | ||
2241 | result += 4; | |
2242 | buf += 4; | |
2243 | *pos += 4; | |
2244 | size -= 4; | |
2245 | } | |
2246 | ||
2247 | return result; | |
2248 | } | |
2249 | ||
50da5174 TSD |
2250 | /** |
2251 | * amdgpu_ttm_vram_write - Linear write access to VRAM | |
2252 | * | |
2253 | * Accesses VRAM via MMIO for debugging purposes. | |
2254 | */ | |
08cab989 TSD |
2255 | static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, |
2256 | size_t size, loff_t *pos) | |
2257 | { | |
2258 | struct amdgpu_device *adev = file_inode(f)->i_private; | |
2259 | ssize_t result = 0; | |
2260 | int r; | |
2261 | ||
2262 | if (size & 0x3 || *pos & 0x3) | |
2263 | return -EINVAL; | |
2264 | ||
770d13b1 | 2265 | if (*pos >= adev->gmc.mc_vram_size) |
08cab989 TSD |
2266 | return -ENXIO; |
2267 | ||
2268 | while (size) { | |
2269 | unsigned long flags; | |
2270 | uint32_t value; | |
2271 | ||
770d13b1 | 2272 | if (*pos >= adev->gmc.mc_vram_size) |
08cab989 TSD |
2273 | return result; |
2274 | ||
2275 | r = get_user(value, (uint32_t *)buf); | |
2276 | if (r) | |
2277 | return r; | |
2278 | ||
2279 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
c3057281 TSD |
2280 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); |
2281 | WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); | |
2282 | WREG32_NO_KIQ(mmMM_DATA, value); | |
08cab989 TSD |
2283 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); |
2284 | ||
2285 | result += 4; | |
2286 | buf += 4; | |
2287 | *pos += 4; | |
2288 | size -= 4; | |
2289 | } | |
2290 | ||
2291 | return result; | |
2292 | } | |
2293 | ||
d38ceaf9 AD |
2294 | static const struct file_operations amdgpu_ttm_vram_fops = { |
2295 | .owner = THIS_MODULE, | |
2296 | .read = amdgpu_ttm_vram_read, | |
08cab989 TSD |
2297 | .write = amdgpu_ttm_vram_write, |
2298 | .llseek = default_llseek, | |
d38ceaf9 AD |
2299 | }; |
2300 | ||
a1d29476 CK |
2301 | #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS |
2302 | ||
50da5174 TSD |
2303 | /** |
2304 | * amdgpu_ttm_gtt_read - Linear read access to GTT memory | |
2305 | */ | |
d38ceaf9 AD |
2306 | static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, |
2307 | size_t size, loff_t *pos) | |
2308 | { | |
45063097 | 2309 | struct amdgpu_device *adev = file_inode(f)->i_private; |
d38ceaf9 AD |
2310 | ssize_t result = 0; |
2311 | int r; | |
2312 | ||
2313 | while (size) { | |
2314 | loff_t p = *pos / PAGE_SIZE; | |
2315 | unsigned off = *pos & ~PAGE_MASK; | |
2316 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); | |
2317 | struct page *page; | |
2318 | void *ptr; | |
2319 | ||
2320 | if (p >= adev->gart.num_cpu_pages) | |
2321 | return result; | |
2322 | ||
2323 | page = adev->gart.pages[p]; | |
2324 | if (page) { | |
2325 | ptr = kmap(page); | |
2326 | ptr += off; | |
2327 | ||
2328 | r = copy_to_user(buf, ptr, cur_size); | |
2329 | kunmap(adev->gart.pages[p]); | |
2330 | } else | |
2331 | r = clear_user(buf, cur_size); | |
2332 | ||
2333 | if (r) | |
2334 | return -EFAULT; | |
2335 | ||
2336 | result += cur_size; | |
2337 | buf += cur_size; | |
2338 | *pos += cur_size; | |
2339 | size -= cur_size; | |
2340 | } | |
2341 | ||
2342 | return result; | |
2343 | } | |
2344 | ||
2345 | static const struct file_operations amdgpu_ttm_gtt_fops = { | |
2346 | .owner = THIS_MODULE, | |
2347 | .read = amdgpu_ttm_gtt_read, | |
2348 | .llseek = default_llseek | |
2349 | }; | |
2350 | ||
2351 | #endif | |
2352 | ||
50da5174 TSD |
2353 | /** |
2354 | * amdgpu_iomem_read - Virtual read access to GPU mapped memory | |
2355 | * | |
2356 | * This function is used to read memory that has been mapped to the | |
2357 | * GPU and the known addresses are not physical addresses but instead | |
2358 | * bus addresses (e.g., what you'd put in an IB or ring buffer). | |
2359 | */ | |
ebb043f2 TSD |
2360 | static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, |
2361 | size_t size, loff_t *pos) | |
38290b2c TSD |
2362 | { |
2363 | struct amdgpu_device *adev = file_inode(f)->i_private; | |
38290b2c | 2364 | struct iommu_domain *dom; |
ebb043f2 TSD |
2365 | ssize_t result = 0; |
2366 | int r; | |
38290b2c | 2367 | |
50da5174 | 2368 | /* retrieve the IOMMU domain if any for this device */ |
ebb043f2 | 2369 | dom = iommu_get_domain_for_dev(adev->dev); |
38290b2c | 2370 | |
ebb043f2 TSD |
2371 | while (size) { |
2372 | phys_addr_t addr = *pos & PAGE_MASK; | |
2373 | loff_t off = *pos & ~PAGE_MASK; | |
2374 | size_t bytes = PAGE_SIZE - off; | |
2375 | unsigned long pfn; | |
2376 | struct page *p; | |
2377 | void *ptr; | |
2378 | ||
2379 | bytes = bytes < size ? bytes : size; | |
2380 | ||
50da5174 TSD |
2381 | /* Translate the bus address to a physical address. If |
2382 | * the domain is NULL it means there is no IOMMU active | |
2383 | * and the address translation is the identity | |
2384 | */ | |
ebb043f2 TSD |
2385 | addr = dom ? iommu_iova_to_phys(dom, addr) : addr; |
2386 | ||
2387 | pfn = addr >> PAGE_SHIFT; | |
2388 | if (!pfn_valid(pfn)) | |
2389 | return -EPERM; | |
2390 | ||
2391 | p = pfn_to_page(pfn); | |
2392 | if (p->mapping != adev->mman.bdev.dev_mapping) | |
2393 | return -EPERM; | |
2394 | ||
2395 | ptr = kmap(p); | |
864917a3 | 2396 | r = copy_to_user(buf, ptr + off, bytes); |
ebb043f2 TSD |
2397 | kunmap(p); |
2398 | if (r) | |
2399 | return -EFAULT; | |
2400 | ||
2401 | size -= bytes; | |
2402 | *pos += bytes; | |
2403 | result += bytes; | |
2404 | } | |
2405 | ||
2406 | return result; | |
2407 | } | |
2408 | ||
50da5174 TSD |
2409 | /** |
2410 | * amdgpu_iomem_write - Virtual write access to GPU mapped memory | |
2411 | * | |
2412 | * This function is used to write memory that has been mapped to the | |
2413 | * GPU and the known addresses are not physical addresses but instead | |
2414 | * bus addresses (e.g., what you'd put in an IB or ring buffer). | |
2415 | */ | |
ebb043f2 TSD |
2416 | static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, |
2417 | size_t size, loff_t *pos) | |
2418 | { | |
2419 | struct amdgpu_device *adev = file_inode(f)->i_private; | |
2420 | struct iommu_domain *dom; | |
2421 | ssize_t result = 0; | |
2422 | int r; | |
38290b2c TSD |
2423 | |
2424 | dom = iommu_get_domain_for_dev(adev->dev); | |
a40cfa0b | 2425 | |
ebb043f2 TSD |
2426 | while (size) { |
2427 | phys_addr_t addr = *pos & PAGE_MASK; | |
2428 | loff_t off = *pos & ~PAGE_MASK; | |
2429 | size_t bytes = PAGE_SIZE - off; | |
2430 | unsigned long pfn; | |
2431 | struct page *p; | |
2432 | void *ptr; | |
2433 | ||
2434 | bytes = bytes < size ? bytes : size; | |
38290b2c | 2435 | |
ebb043f2 TSD |
2436 | addr = dom ? iommu_iova_to_phys(dom, addr) : addr; |
2437 | ||
2438 | pfn = addr >> PAGE_SHIFT; | |
2439 | if (!pfn_valid(pfn)) | |
2440 | return -EPERM; | |
2441 | ||
2442 | p = pfn_to_page(pfn); | |
2443 | if (p->mapping != adev->mman.bdev.dev_mapping) | |
2444 | return -EPERM; | |
2445 | ||
2446 | ptr = kmap(p); | |
864917a3 | 2447 | r = copy_from_user(ptr + off, buf, bytes); |
ebb043f2 TSD |
2448 | kunmap(p); |
2449 | if (r) | |
2450 | return -EFAULT; | |
2451 | ||
2452 | size -= bytes; | |
2453 | *pos += bytes; | |
2454 | result += bytes; | |
2455 | } | |
2456 | ||
2457 | return result; | |
38290b2c TSD |
2458 | } |
2459 | ||
ebb043f2 | 2460 | static const struct file_operations amdgpu_ttm_iomem_fops = { |
38290b2c | 2461 | .owner = THIS_MODULE, |
ebb043f2 TSD |
2462 | .read = amdgpu_iomem_read, |
2463 | .write = amdgpu_iomem_write, | |
38290b2c TSD |
2464 | .llseek = default_llseek |
2465 | }; | |
a40cfa0b TSD |
2466 | |
2467 | static const struct { | |
2468 | char *name; | |
2469 | const struct file_operations *fops; | |
2470 | int domain; | |
2471 | } ttm_debugfs_entries[] = { | |
2472 | { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM }, | |
2473 | #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS | |
2474 | { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT }, | |
2475 | #endif | |
ebb043f2 | 2476 | { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM }, |
a40cfa0b TSD |
2477 | }; |
2478 | ||
a1d29476 CK |
2479 | #endif |
2480 | ||
d38ceaf9 AD |
2481 | static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) |
2482 | { | |
2483 | #if defined(CONFIG_DEBUG_FS) | |
2484 | unsigned count; | |
2485 | ||
2486 | struct drm_minor *minor = adev->ddev->primary; | |
2487 | struct dentry *ent, *root = minor->debugfs_root; | |
2488 | ||
a40cfa0b TSD |
2489 | for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) { |
2490 | ent = debugfs_create_file( | |
2491 | ttm_debugfs_entries[count].name, | |
2492 | S_IFREG | S_IRUGO, root, | |
2493 | adev, | |
2494 | ttm_debugfs_entries[count].fops); | |
2495 | if (IS_ERR(ent)) | |
2496 | return PTR_ERR(ent); | |
2497 | if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) | |
770d13b1 | 2498 | i_size_write(ent->d_inode, adev->gmc.mc_vram_size); |
a40cfa0b | 2499 | else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) |
770d13b1 | 2500 | i_size_write(ent->d_inode, adev->gmc.gart_size); |
a40cfa0b TSD |
2501 | adev->mman.debugfs_entries[count] = ent; |
2502 | } | |
d38ceaf9 AD |
2503 | |
2504 | count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); | |
2505 | ||
2506 | #ifdef CONFIG_SWIOTLB | |
fd5fd480 | 2507 | if (!(adev->need_swiotlb && swiotlb_nr_tbl())) |
d38ceaf9 AD |
2508 | --count; |
2509 | #endif | |
2510 | ||
2511 | return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); | |
2512 | #else | |
d38ceaf9 AD |
2513 | return 0; |
2514 | #endif | |
2515 | } | |
2516 | ||
2517 | static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) | |
2518 | { | |
2519 | #if defined(CONFIG_DEBUG_FS) | |
a40cfa0b | 2520 | unsigned i; |
d38ceaf9 | 2521 | |
a40cfa0b TSD |
2522 | for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++) |
2523 | debugfs_remove(adev->mman.debugfs_entries[i]); | |
a1d29476 | 2524 | #endif |
d38ceaf9 | 2525 | } |